HI-5002PCI [HOLTIC]

1Mbps CAN Transceiver with Low Power Standby Mode; 1Mbps的CAN与低功耗待机模式收发器


型号：	HI-5002PCI
厂家：	HOLT INTEGRATED CIRCUITS
描述：	1Mbps CAN Transceiver with Low Power Standby Mode 1Mbps的CAN与低功耗待机模式收发器
文件：	总13页 (文件大小：83K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI-5000, HI-5001, HI-5002

1Mbps CAN Transceiver with

Low Power Standby Mode

September 2011

PIN CONFIGURATIONS (Top Views)

GENERALDESCRIPTION

TXD - 1

GND - 2

VDD - 3

RXD - 4

8 - STB

The HI-5000 is a 1 Mbps Controller Area Network (CAN)

transceiver. It interfaces between a CAN protocol con-

troller and the physical wires of the bus in a CAN network.

Differential output amplitude and current drive capability

are specifically enhanced to meet the needs of long cable

runs typical in many applications such as industrial auto-

mation.

7 - CANH

6 - CANL

5 - SPLIT

HI-5000PSI

TXD - 1

GND - 2

VDD - 3

RXD - 4

8 - STB

7 - CANH

6 - CANL

5 - VIO

HI-5001PSI

The HI-5000 supports two modes of operation: Normal

Mode and Standby Mode. The Standby Mode is a very

low-current mode which continues to monitor bus activity

and allows an external controller to manage wake-up.

8 - PIN PLASTIC NARROW BODY SOIC

Superior common-mode receiver performance makes

the device especially suitable for applications where

ground reference voltages may vary from point to point

over long distances along the CAN bus. In addition, the

HI-5000 provides a SPLIT pin to give an output reference

voltage of VDD/2 which can be used for stabilizing the re-

cessive bus level when the split termination technique is

used to terminate the bus.

GND

VDD

12 CANH

11 CANH

10 CANL

HI-5002PCI

CANL

A TXD dominant time-out feature also protects the bus

from being driven into a permanent dominant state (so-

called “babbling idiot”) if pin TXD becomes permanently

low due to application failure.

16 - PIN PLASTIC 4 x 4mm QFN

The device also has short circuit protection to +/-58V on

CANH, CANL and SPLIT pins and ESD protection to

+/- 6kV on all pins.

FEATURES

The HI-5001 is identical to the HI-5000 except the SPLIT

pin is substituted with a VIO supply voltage pin. This al-

lows the HI-5001 to interface directly with controllers with

2.5V or 3.3V supply voltages.

· Compatible with ISO 11898-5 standard.

· Signaling rates up to 1Mbit/s.

· Internal VDD/2 voltage source available to stabilize the

recessive bus level if split termination is used (HI-5000

SPLIT pin).

· VIO input on HI-5001 allows for direct interfacing with 2.5V

or 3.3V controllers.

· Detection of permanent dominant on TXD pin (babbling

idiot protection).

The HI-5002 provides both the SPLIT and VIO supply

voltage pins in a compact 16-pin QFN.

All three devices are available in industrial -40^oC to +85^oC

temperature ranges. “RoHS compliant” lead-free options

are also available.

· High impedance allows connection of up to 120 nodes.

· CANH, CANLand SPLITpins short-circuit proof to +/-58V.

· Will not disturb the bus if unpowered.

HOLT INTEGRATED CIRCUITS

www.holtic.com

(DS5000 Rev. B)

09/11

HI-5000, HI-5001, HI-5002

PIN DESCRIPTIONS

SIGNAL

TXD

FUNCTION

INPUT

DESCRIPTION

100kOhm internal pull-up. Transmit Data Input.

Chip 0V supply

GND

POWER

OUTPUT

BUS I/O

INPUT

VDD

Positive supply, 5V +/-5%. Bypass with 0.1uF ceramic capacitor.

Receive Data Output.

RXD

CANL

CANH

STB

CAN Bus Line Low.

CAN Bus Line High.

100kOhm internal pull-up. Standby Mode selection input. Drive STB low or connect to GND

for Normal operation. Drive STB high to select low-current Standby Mode.

Supplies a VDD/2 output to provide recessive bus level stabilization when a split termination

is used to terminate the bus.

SPLIT

(HI-5000)

VIO

INPUT

Connect to a 2.5V or 3.3V supply to allow compatibility of all digital I/O (RXD, TXD, STB)

with a low voltage controller input.

(HI-5001)

BLOCK DIAGRAM

VDD

SPLIT

V Split

(HI-5000)

CANH

TXD

Dominant

Detect

CANL

TXD

STB

Driver

Standby

Control

VIO

(HI-5001)

Main

Receiver

RXD

GND

MUX

Low power

Standby Rx

Figure 1. HI-5000 Functional Block Diagram

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

FUNCTIONAL DESCRIPTION

due to an unpowered node with high leakage from the bus

lines to ground), the split circuit will force the recessive

voltage to VDD/2.

OPERATING MODES

The HI-5000 provides two modes of operation which are

selectable via the STB pin. Table 1 summarizes the modes.

INTERNAL PROTECTION FEATURES

Table 1 - Operating Modes

Short-circuit protection

MODE

STB pin

Short-circuit protection is provided on the CANH, CANL and

SPLIT pins. These pins are protected from ESD to over 6KV

(HBM) and from shorts between -58V and +58V continuous,

as specified in ISO 11898-5. The short circuit current is limited

to less than 200mAtypical.

Normal

LOW

HIGH

Standby

TXD permanent dominant time-out

Normal Mode

A timer circuit prevents the bus lines being driven into a

permanent dominant state, which would result in a situation

blocking all bus traffic. This could happen in the case of the

TXD pin becoming permanently low due to a hardware or

application failure. The timer is triggered by a negative edge

on the TXD pin (start of dominant state). If the TXD pin is not

set high (recessive state) after a typical time of 2ms, the

transmitter outputs will be disabled, putting the bus lines into

the recessive state. The timer is reset by a positive edge on

the TXD pin. Note that the minimum TXD dominant time-out

time, tdom = 300μs, defines the minimum possible bit rate of

40kbit/s (the CAN protocol specifies a maximum of 11

successive dominant bits − 5 successive dominant bits

immediately followed by an error frame).

Normal mode is selected by setting the STB pin to a LOW

logic level (GND). In this mode, the transceiver transmits and

receives data in the usual way from the CANH and CANLbus

lines. The differential receiver converts the analog bus data

to digital data which is output on the RXD pin (Note: the RXD

output on HI-5001 is compatible with 2.5V or 3.3V controllers

if the VIO pin is connected to a 2.5V or 3.3V supply).

Standby Mode

Standby Mode is selected by setting the STB pin to a HIGH

logic level. In this mode, the transmitter is switched off and a

low power differential receiver monitors the bus lines for

activity. A dominant signal of more than 3ms will be reflected

on the RXD pin as a logic LOW, where it may be detected by

the host as a wake-up request. The device will not leave

standby mode until the host forces the STB pin to a logic low.

Fail-safe features

Pin TXD has a pull up in order to set a recessive level if pin

TXD is left open.

Pins TXD and STB will become floating if power is lost. This

will prevent reverse currents via these pins.

SPLIT Circuit

The SPLIT pin provides a stable VDD/2 DC voltage. This

pin can be used to stabilize the recessive common mode

voltage by connecting the SPLIT pin to the center tap of the

split termination (see figure 7). In the case of a recessive

bus voltage dropping below the ideal value of VDD/2 (e.g.

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

TIMING DIAGRAMS

Timing Delays

HIGH

LOW

TXD

CANH

CANL

Dominant

Recessive

0.9V

DIFF(BUS) =

CANH - VCANL

0.5V

HIGH

LOW

RXD

50%

tdr(TXD)

tdf(TXD)

tdr(RXD)

tdf(RXD)

tProp1

tProp2

TXD dominant time-out feature

transmitter

enabled

tRdom

tdom(TXD)

recessive

HIGH

LOW

TXD

dominant

transmitter disabled

CANH

CANL

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND = 0V)

Supply Voltage, VDD, VIO : .....................................................................7V Operating Temperature Range:(Industrial).........................-40°C to +85°C

Current at Input pins ......................................................-100mA to +100mA

Maximum Junction Temperature²......................................................175°C

DC Voltages at TXD, RXD and STB ..............................-0.5V to VDD +0.5V

DC Voltages at CANH, CANL and SPLIT: ...............................-58V to +58V

Internal Power Dissipation: ..............................................................900mW

Storage Temperature Range: -65°C to +150°C

Soldering Temperature:

(Ceramic)......................60 sec. at +300°C

(Plastic - leads).............10 sec. at +280°C

(Plastic - body) .....................+260°C Max.

Electrostatic Discharge (ESD)¹, All pins ..........................................+/- 6kV

NOTES:

1. Human Body Model (HBM).

2. Junction Temperature TJ is defined as TJ = TAMB + P × Rth, where TAMB is the ambient or operating temperature, P is the power dissipation and Rth is

a fixed thermal resistance value which depends on the package and circuit board mounting conditions.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

VDD = 5V±5%, Operating temperature range (unless otherwise noted). Positive currents flow into the IC.

LIMITS

PARAMETER

SUPPLY CURRENT

SYMBOL

CONDITIONS

UNIT

MIN

TYP

MAX

VDD Supply Current

IDD

IIO

Recessive: VTXD = VDD

Dominant: VTXD = 0 V

Standby Mode: VTXD = VDD

100

μA

VIO Supply Current

μA

DIGITAL INPUTS (Pins TXD, STB)

HIGH-level input voltage (see Note 1)

LOW-level input voltage

VIH

VIL

70%VDD

− 0.5

VDD + 0.5

30%VDD

HIGH-level input current

LOW-level input current

IIH

IIL

VTXD = VDD or VIO

VTXD = 0 V

− 5

− 50

+ 5

− 150

μA

DIGITAL OUTPUTS

HIGH-level output voltage (RXD Pin) (see Note 1)

LOW-level output voltage (RXD Pin)

VOH

VOL

IOH = 1mA

IOL = 1mA

90%VDD

0.1

10%VDD

Output voltage (SPLIT Pin)

Standby leakage current (SPLIT Pin)

VSPLIT

ISTB

− 100 μA < ISPLIT < 100 μA

0.45VDD 0.5VDD 0.55VDD

μA

-5

DRIVER

CANH dominant output voltage

CANL dominant output voltage

VO(CANH)

VO(CANL)

VTXD = 0 V

VTXD = 0 V (See Fig. 2)

0.5

3.6

1.4

4.25

1.75

Recessive output voltage

VCANH(r),

VCANL(r)

VTXD = VDD, RL = 0 (See Fig. 2)

0.5VDD

Bus output voltage in standby

VSTB

-0.1

0.1

Dominant differential output voltage

Recessive differential output voltage

VDIFF(d)(o)

VDIFF(r)(o)

VTXD = 0 V, 45 Ω < RL < 65 Ω

VTXD = VDD, no load (See Fig. 2)

1.5

− 50

1.8

Matching of dominant output voltage,

VDD − VO(CANH) − VO(CANL)

VOM

(See Fig. 4)

− 100

-40

150

Steady state common mode output voltage

VOC(ss)

VSTB = 0V, RL = 60 Ω (See Fig. 5)

0.5VDD

NOTE:

1. When VIO is connected (HI-5001 or HI-5002), limits are referenced wrt VIO rather than VDD.

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

DC ELECTRICAL CHARACTERISTICS (cont.)

VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC.

LIMITS

TYP

PARAMETER

SYMBOL

CONDITIONS

UNIT

MIN

MAX

Short-circuit steady-state output current

IOS(ss)

VCANH = +58V, VCANL open

VCANH = -58V, VCANL openV

VCANL = +58V, VCANH open

-20

-200

100

-20

100

200

VCANL = -58V, VCANH open (See Fig. 6)

RECEIVER

Differential receiver threshold voltage

Differential hysteresis voltage

Differential hysteresis voltage in Standby mode

VTh(Rx)(diff)

VHys(Rx)(diff)

VHys(Stb)(diff)

− 12 V < VCANH, VCANL < + 12 V

500

700

120

900

200

1150

Input leakage current, unpowered node

Differential input resistance

ICANH, ICANL

RIN(DIFF)

VDD = VIO 0 V

VCANH = VCANL = 5V

− 200

+ 200

μA

kΩ

VTXD = VDD

− 12 V < VCANH, VCANL < + 12 V

Common mode input resistance

RIN(CM)

VTXD = VDD

− 12 V < VCANH, VCANL < + 12 V

kΩ

Deviation between common mode input resistance

between CANH and CANL

RIN(CM)(m)

VCANH = VCANL

− 3

+ 3

AC ELECTRICAL CHARACTERISTICS

VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC.

LIMITS

TYP

PARAMETER

SYMBOL

CONDITIONS

UNIT

MIN

MAX

Bit time

Bit rate

tBit

fBit

1000

μs

kHz

Common mode input capacitance³

Differential input capacitance³

CIN(CM)

CDIFF(CM)

VTXD = VDD, 1Mbit/s data rate

Delay TXD to bus active

Delay TXD to bus inactive

Delay bus active to RXD

Delay bus inactive to RXD

tdr(TXD)

tdf(TXD)

tdf(RXD)

tdr(RXD)

150

See Timing Diagrans

Propagation delay TXD to RXD (recessive to dominant)

Propagation delay TXD to RXD (dominant to recessive)

tProp1

tProp2

110

160

240

TXD permanent dominant time-out

TXD permanent dominant timer reset time

tdom

tRdom

VTXD = 0 V

Rising edge on TXD while in

permanent dominant state

0.3

0.5

μs

Dominant time required on bus for standby receiver

detection

t_wake

μs

NOTES:

1. All currents into the device pins are positive; all currents out of the device pins are negative.

2. All typicals are given for VDD = 5V, TA = 25°C.

3. Guaranteed by design but not tested.

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

Application and Test Information

Transceiver

TXD

V_DIFF(d)(o)

R_L

V_O(CANH)

V_O(CANL)

STB

Dominant

~3.5V: V_O(CANH)

~2.5V

Recessive

~1.5V: V_O(CANL)

Figure 2. CAN Bus Driver Circuit

300 W +/- 1%

Transceiver

TXD

CANH

V_DIFF(d)(o)

R_L

-12V <= V_TEST<= +12V

CANL

300 W +/- 1%

STB

Figure 3. CAN Bus Driver (Dominant) Test Circuit

Transceiver

TXD

V_DIFF(d)(o)

R_L

V_O(CANH)

V₁

V_O(CANL)

V_OM= V_DD- V_O(CANH)+ V_O(CANL)

STB

Figure 4. Driver Output Symmetry Test.

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

Application and Test Information

Transceiver

TXD

V_DIFF(d)(o)

R_L

V₁

V_O(CANH)

V_O(CANL)

V_OC(ss)= V_O(CANH)+ V_O(CANL)

STB

Figure 5. Common Mode Output Voltage Test.

Transceiver

CANH

TXD

-58V or +58V

CANL

V₁

Figure 6. CAN Bus Driver Short-Circuit Test. (Note: V1 is a pulse from 0V to VDD with duty cycle

of 99% such that permanent dominant time-out is avoided).

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

Application and Test Information

VBAT

Regulator

VDD

TXD

RXD

CANH

SPLIT

VDD

TXD

RXD

RL/2

HI-5000

Controller

GND

(optional)

STB

CANL

GND

VBAT

3.3V

Regulator

VDD

VIO

TXD

RXD

CANH

VDD

TXD

RXD

HI-5001

Controller

STB

CANL

GND

Figure 7. Typical Application Connections

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

ORDERING INFORMATION

HI - 500x xxx x

LEAD

PART

NUMBER

FINISH

Tin / Lead (Sn / Pb) Solder

Blank

100% Matte Tin (Pb-free, RoHS compliant)

PART

NUMBER

PACKAGE

DESCRIPTION

PSI

PCI

CRI

8 PIN PLASTIC NARROW BODY SOIC (8HN) (HI-5000 or HI-5001 only)

16 PIN PLASTIC 4 x 4 mm QFN (16PCS) (HI-5002 only)

8 PIN CERDIP (8D) not available Pb-free (HI-5000 or HI-5001 only)

PART

NUMBER

DESCRIPTION

SPLIT pin option

VIO pin option

5000

5001

Both SPLIT and VIO pins available

5002

HOLT INTEGRATED CIRCUITS

HI-5000, HI-5001, HI-5002

REVISION HISTORY

P/N

Rev

Date

Description of Change

DS5000 NEW 04/01/11 Initial Release

04/29/11 Corrected heat-sink note on QFN package drawing.

09/16/11 Update pad and heat-sink dimensions for 16-lead QFN package (16PCS)

HOLT INTEGRATED CIRCUITS

PACKAGE DIMENSIONS

8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB

(Narrow Body)

inches (millimeters)

Package Type: 8HN

.194 .004

(4.92 .09)

.0085 .0015

(.216 .038)

.236 .008

(5.99 .21)

.154 .004

(3.90 .09)

PIN 1

See Detail A

.0165 .003

(.419 .089)

.055 .005

(1.397 .127)

0° to 8°

.0069 .003

(.1753 .074)

.050

(1.27)

.033 .017

(.838 .432)

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

BSC

Detail A

16-PIN PLASTIC CHIP-SCALE PACKAGE

millimeters

Package Type: 16PCS

Electrically isolated metal

heat sink on bottom of

package

Connect to any ground or

power plane for optimum

thermal dissipation

2.80 .10

4.00 BSC

0.65 BSC

Bottom

View

Top View

4.00 BSC

2.80 .10

0.30 .05

0.40 .05

1.00 max

0.20 typ

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS

PACKAGE DIMENSIONS

inches (millimeters)

8-PIN CERDIP

Package Type: 8D

.380 ±.004

(9.652 ±.102)

.005 min

(.127 min)

.248 ±.003

(6.299 ±.076)

.039 ±.006

(.991 ±.154)

.100

(2.54)

BSC

.314 ±.003

(7.976 ±.076)

.015 min

(.381min)

.200 max

(5.080 max)

Base Plane

.010 ±.006

(.254 ±.152)

Seating Plane

.018 ±.006

(.457 ±.152)

.163 ±.037

(4.140 ±.940)

.350 ±.030

(8.890 ±.762)

.056 ±.006

(1.422 ±.152)

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS

HI-5002PCI [HOLTIC]

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