HI-6130 [HOLTIC]
3.3V BC / MT / RT Multi-Terminal Device; 3.3V BC / MT / RT多终端设备
| 型号： | HI-6130 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | 3.3V BC / MT / RT Multi-Terminal Device |
| 文件： | 总290页 (文件大小：6306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-6130 / HI-6131 / HI-6132
MIL-STD-1553 / MIL-STD-1760
3.3V BC / MT / RT Multi-Terminal Device
December, 2012
•
Fully programmable Bus Controller with 28 op
code instruction set.
GENERAL DESCPIPTION
The 3.3V CMOS HI-613x device provides a complete
single- or multi-function interface between a host
processor and MIL-STD-1553B bus. Each IC contains
a Bus Controller (BC), a Bus Monitor Terminal (MT)
and two independent Remote Terminals (RTs). Any
combination of the contained 1553 functions can
be enabled for concurrent operation. The enabled
terminals communicate with the MIL-STD-1553 buses
through a shared on-chip dual bus transceiver and
external transformer. The user allocates 64K bytes of
on-chip static RAM between devices to suit application
requirements.
•
Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
•
•
IRIG Monitor Terminal (IMT) Mode supports IRIG-
106 Chapter 10 packet format.
IMT Monitor Mode can optionally generate
complete IRIG-106 data packets, including full
packet headers and trailers.
•
•
Independent 16-bit time tag counters and clock
sources for all terminals. The Bus Controller
and Monitor also have 32- and 48-bit time count
options, respectively.
Two options are offered for host access to internal
registers and static RAM: The HI-6130 uses a 16-bit
parallel bus; the HI-6131 communicates with the host
via a 4-wire serial peripheral interface (SPI). The HI-
6132 combines both 16-bit parallel bus and SPI in a
single 15 x 15mm hermetically sealed ceramic package.
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
•
•
Built-in self-test for protocol logic, digital signal
paths and internal RAM.
Optional self-initialization at reset uses external
serial EEPROM.
Device
Host Interface Packages
•
•
±8kV ESD Protection (HBM, all pins).
HI-6130
HI-6131
16-bit parallel 100-pin PQFP
Two temperature ranges: -40oC to +85oC, or
4-wire SPI
64-pin QFN
-55oC to +125oC with optional burn-in.
64-pin PQFP
•
RoHS compliant.
HI-6132
16-bit parallel 121 ceramic PGA
or 4-wire SPI or LGA
PIN CONFIGURATION (TOP)
Programmable interrupts provide terminal status
to the host processor. Circular data buffers in RAM
have interrupts for rollover and programmable “level
attained”. The HI-613x can be configured for automatic
self-initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM for any subset of one to four terminal
devices.
75 - D1
74 - D0
VCC - 1
GND - 2
BCTRIG - 3
D12 - 4
D13 - 5
D14 - 6
D15 - 7
RAMEDC - 8
CE - 9
MODE - 10
STR / OE - 11
73 - WPOL
72 - BTYPE
71 - BENDI
70 - TEST
69 - RT1LOCK
68 - MTSTOFF
67 - BCENA
66 - BUSA
65 - VCCP
64 - BUSA
63 - BUSB
62 - VCCP
61 - BUSB
60 - RT2ENA
59 - RT2A_0
58 - RT2A_1
57 - RT2A_2
56 - RT2A_3
55 - BWID
54 - A15
VCC - 12
MCLK - 13
HI-6130PQxF
FEATURES
GND - 14
WAIT / WAIT - 15
R/W / WE - 16
RT1A_0 - 17
RT1A_1 - 18
RT1A_2 - 19
MR - 20
•
Concurrent multi-terminal operation for one to
four MIL-STD-1553B functions: BC, MT and two
independent RTs.
RT1A_3 - 21
RT1A_4 - 22
A0 - 23
53 - A14
52 - A12
51 - A13
•
•
•
64K bytes internal static RAM with RAM Error
Detection/Correction option.
A1 - 24
A2 - 25
TOP VIEW
Autonomous terminal operation requires minimal
host intervention.
Shared MIL-STD-1553 bus interface reduces
circuit complexity and circuit board area.
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DS6130 Rev. F
12/12
HI-6130, HI-6131
NOTES:
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HI-6130, HI-6131
Table of Contents
1. BLOCK DIAGRAM ........................................................................................... 14
2. FEATURE OVERVIEW ................................................................................... 15
2.1.
2.2.
2.3.
2.4.
2.5.
Bus Controller Operation ..........................................................................................15
Remote Terminal Operation......................................................................................15
Monitor Terminal Operation.......................................................................................15
Interrupts...................................................................................................................15
Reset and Initialization..............................................................................................15
3. PIN DESCRIPTIONS ....................................................................................... 16
4. MEMORY MAP................................................................................................. 21
5. RAM STRUCTURES ....................................................................................... 22
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
Interrupt Log Data Buffer ..........................................................................................22
Bus Controller (BC) Instruction List...........................................................................22
Bus Controller (BC) Msg Control / Status Stack .......................................................22
Bus Controller (BC) Call Stack..................................................................................22
Bus Controller (BC) General Purpose Queue...........................................................22
Monitor Terminal Temporary Buffers A & B ...............................................................22
Monitor Terminal (MT) Address List ..........................................................................22
Monitor Terminal (MT) Message Filter Table.............................................................22
Monitor Terminal (MT) Data Buffers..........................................................................22
5.10. RT1 and RT2 Command Illegalization Tables...........................................................22
5.11. RT1 and RT2 Descriptor Tables................................................................................23
5.12. RT1 and RT2 Temporary Receive Buffers ................................................................23
5.13. RT Message Data Buffers.........................................................................................23
5.14. RT Storage for Mode Code Commands....................................................................23
6. HARDWARE FEATURES ................................................................................ 23
6.1.
6.2.
6.3.
6.4.
6.5.
Remote Terminal Address Inputs..............................................................................23
Dual Transceivers for MIL-STD-1553 Bus ................................................................23
Encoder and Decoders .............................................................................................23
Auto-Initialization Serial EEPROM Interface.............................................................23
Selection of Host Interface (HI-6132 only)................................................................24
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7. REGISTER & MEMORY ADDRESSING.......................................................... 24
7.1.
8-bit Bus Operation: (HI-6130 Only) .........................................................................24
8. REGISTER DEFINITIONS ............................................................................... 24
9. REGISTERS USED BY ALL DEVICE FUNCTIONS ........................................ 29
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
Master Configuration Register (0x0000)...................................................................29
Master Status and Reset Register (0x0001) ............................................................33
Overview of Interrupts...............................................................................................36
Hardware Interrupt Behavior.....................................................................................36
Interrupt Count & Log Address Register (0x000A) ...................................................37
Interrupt Log Buffer...................................................................................................38
Hardware Interrupt Registers....................................................................................40
9.7.1.
9.7.2.
9.7.3.
Hardware Interrupt Enable Register (0x000F) ......................................................40
Hardware Pending Interrupt Register (0x0006) ....................................................40
Hardware Interrupt Output Enable Register (0x0013) ..........................................40
9.8.
9.9.
Time Tag Counter Configuration ...............................................................................44
Time Tag Counter Configuration Register (0x0039)..................................................45
9.10. Memory Address Pointer Registers (HI-6131 only)...................................................49
10. BUS CONTROLLER − CONFIGURATION AND OPERATION........................ 51
10.1. Bus Controller Condition Codes................................................................................52
10.2. Bus Controller Instruction Op Codes ........................................................................55
10.3. Bus Controller General Purpose Queue ...................................................................63
10.4. Bus Controller Message Control / Status Blocks ......................................................63
10.4.1. BC Control Word ...................................................................................................64
10.4.2. Time to Next Message Word .................................................................................68
10.4.3. Data Block Pointer.................................................................................................68
10.4.4. BC Block Status Word...........................................................................................69
11. BUS CONTROLLER REGISTER DESCRIPTION .......................................... 73
11.1. BC (Bus Controller) Configuration Register (0x0032)...............................................73
11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033) .................82
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)...............................................82
11.4. Bus Controller (BC) Frame Time Remaining Register (0x0035)...............................83
11.5. Bus Controller (BC) Time To Next Message Register (0x0036)................................83
11.6. Bus Controller (BC) Condition Code Register (Read 0x0037)..................................83
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11.7. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)........................86
11.8. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038).................86
11.9. Bus Controller (BC) Time Tag Counter (0x0043) ......................................................87
11.10. Bus Controller (BC) Time Tag Counter High (0x0044)..............................................87
11.11. Bus Controller (BC) Time Tag Utility Register (0x0045) ...........................................88
11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046) ..................................88
11.13. Bus Controller (BC) Time Tag Match Register (0x0047) ..........................................88
11.14. Bus Controller (BC) Time Tag Match High Register (0x0048) .................................88
11.15. Bus Controller Interrupt Registers and Their Use.....................................................89
11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ......................................90
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007) ....................................90
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) ..........................90
12. SIMPLE MONITOR TERMINAL (SMT) ............................................................ 93
12.1. Overview...................................................................................................................93
12.2. SMT Block Status Word (BSW) Description .............................................................98
12.3. SMT Message Filter Table ......................................................................................101
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION ............. 103
13.1. SMT Configuration Register (0x0029) ....................................................................103
13.2. SMT Bus Monitor Address List Start Address Register (0x002F) ...........................106
13.3. SMT Next Message Command Buffer Address (0x0030) .......................................106
13.4. SMT Last Message Command Buffer Address (0x0031)........................................107
13.5. SMT Bus Monitor Time Tag Count Register (0x003A) ............................................107
13.6. SMT Bus Monitor Time Tag Count Mid Register (0x003B) .....................................107
13.7. SMT Bus Monitor Time Tag Count High Register (0x003C)....................................107
13.8. SMT Bus Monitor Time Tag Utility Register (0x003D).............................................108
13.9. SMT Bus Monitor Time Tag Utility Mid Register (0x003E) ......................................108
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F).....................................108
13.11. SMT Bus Monitor Time Tag Match Register (0x0040) ............................................109
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041) .....................................109
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042) ...................................109
13.14. SMT Bus Monitor Interrupt Registers and Their Use .............................................. 110
13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011)..........................................111
13.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008)........................................111
13.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015)..............................111
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14. IRIG-106 MONITOR TERMINAL (IMT) .......................................................... 113
14.1. Overview................................................................................................................. 113
14.2. IRIG-106 Bus Monitor - Data Packet Format.......................................................... 114
14.3. IRIG-106 Packet Header Description...................................................................... 116
14.3.1. Packet Sync Pattern. .......................................................................................... 116
14.3.2. Channel ID. ......................................................................................................... 116
14.3.3. Packet Length. .................................................................................................... 116
14.3.4. Data Length. ....................................................................................................... 116
14.3.5. Data Type Version. ............................................................................................. 116
14.3.6. Sequence Number. ............................................................................................. 116
14.3.7. Packet Flags. ...................................................................................................... 116
14.3.8. Data Type. .......................................................................................................... 117
14.3.9. Relative Time Counter. ....................................................................................... 117
14.3.10. Header Checksum. ............................................................................................. 117
14.4. IRIG-106 Packet Trailer Description ....................................................................... 117
14.5. IRIG-106 Data Packet Trailer Description............................................................... 117
14.5.1. Channel Specific Data. ....................................................................................... 118
14.5.2. IRIG-106 Intra-Packet Time Stamp. ................................................................... 118
14.5.3. IRIG-106 Intra-Packet Data Header. .................................................................. 118
14.5.4. IRIG-106 Message Data. .................................................................................... 118
14.6. IMT Block Status Word (BSW) Description............................................................. 119
14.7. IMT Message Filter Table........................................................................................122
15. IRIG-106 BUS MONITOR (IMT) CONFIGURATION AND OPERATION........ 125
15.1. Generating complete IRIG-106 Data Packets.........................................................125
15.2. Generating only IRIG-106 Packet Body (no header or trailer)................................125
16. REGISTERS USED BY THE IMT BUS MONITOR ........................................ 128
16.1. IMT Bus Monitor MT Configuration Register (0x0029)............................................128
16.2. IMT Bus Monitor Address List Start Address Register (0x002F).............................132
16.3. IMT Bus Monitor Next Message Storage Pointer (0x0030) ....................................132
16.4. IMT Bus Monitor Last Message Buffer Address (0x0031).......................................132
16.5. IMT Packet Maximum Message Count Register (0x002A).....................................133
16.5.1. Practical IRIG-106 packet message count considerations..................................133
16.6. IMT Packet Maximum 1553 Word Count Register (0x002B) ..................................133
16.6.1. Practical IRIG-106 packet word count considerations.........................................134
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HI-6130, HI-6131
16.7. IMT Maximum Packet Time Register (0x002C) ......................................................134
16.7.1. Practical IRIG-106 packet time considerations....................................................134
16.8. IMT Packet Maximum Gap Time Register (0x002D) ..............................................134
16.8.1. Practical IRIG-106 maximum gap time considerations........................................135
16.9. IMT Packet Header Channel ID Register (0x002E)................................................135
16.10. IMT Monitor Time Tag Count Low Register (0x003A) .............................................136
16.11. IMT Monitor Time Tag Count Mid Register (0x003B)..............................................136
16.12. IMT Monitor Time Tag Count High Register (0x003C) ............................................136
16.13. IMT Time Tag Utility Low Register (0x003D)...........................................................136
16.14. IMT Time Tag Utility Mid Register (0x003E)............................................................137
16.15. IMT Time Tag Utility High Register (0x003F) ..........................................................137
16.15.1. Loading a 48-bit value into the three 16-bit SMT Time Tag Count Registers .....137
16.15.2. Capturing a 48-bit value from the three 16-bit SMT Time Tag Count Registers .137
16.16. IMT Time Tag Match Low Register (0x0040) ..........................................................137
16.17. IMT Time Tag Match Mid Register (0x0041) ...........................................................137
16.18. IMT Time Tag Match High Register (0x0042)..........................................................138
16.19. IMT Bus Monitor Interrupt Registers and Their Use................................................139
16.19.1. IMT Bus Monitor Interrupt Enable Register (0x0011) ..........................................140
16.19.2. IMT Bus Monitor Pending Interrupt Register (0x0008)........................................140
16.19.3. IMT Bus Monitor Interrupt Output Enable Register (0x0015) ..............................140
17. SINGLE OR DUAL REMOTE TERMINAL(S) − OVERVIEW ......................... 143
18. REGISTERS USED BY REMOTE TERMINALS RT1 AND RT2.................... 144
18.1. Remote Terminal 1 (RT1) Configuration Register (0x0017)
Remote Terminal 2 (RT2) Configuration Register (0x0020)....................................144
18.2. Remote Terminal 1 (RT1) Operational Status Register (0x0018)
Remote Terminal 2 (RT2) Operational Status Register (0x0021) ...........................148
18.3. Remote Terminal 1 (RT1) Current Command Register (0x0002)
Remote Terminal 2 (RT2) Current Command Register (0x0004)............................150
18.4. Remote Terminal 1 (RT1) Current Control Word Address Register (0x0003)
Remote Terminal 2 (RT2) Current Control Word Address Register (0x0005).........150
18.5. Remote Terminal 1 (RT1) Descriptor Table Base Address Register (0x0019)
Remote Terminal 2 (RT2) Descriptor Table Base Address Register (0x0022)........150
18.6. Remote Terminal 1 (RT1) MIL-STD-1553 Status Word Bits Register (0x001A)
Remote Terminal 2 (RT2) MIL-STD-1553 Status Word Bits Register (0x0023)......151
18.7. Remote Terminal 1 (RT1) Current Message Information Word Register (0x001B)
Remote Terminal 2 (RT2) Current Message Information Word Register (0x0024).152
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18.8. Remote Terminal 1 (RT1) Bus A Select Register (0x001C)
Remote Terminal 2 (RT2) Bus A Select Register (0x0025).....................................153
18.9. Remote Terminal 1 (RT1) Bus B Select Register (0x001D)
Remote Terminal 2 (RT2) Bus B Select Register (0x0026).....................................153
18.10. Remote Terminal 1 (RT1) Built-In Test (BIT) Word Register (0x001E)
Remote Terminal 2 (RT2) Built-In Test (BIT) Word Register (0x0027)....................154
18.11. Remote Terminal 1 (RT1) Alternate Built-In Test (BIT) Word Register (0x001F)
Remote Terminal 2 (RT2) Alternate Built-In Test (BIT) Word Register (0x0028).....155
18.12. Remote Terminal 1 (RT1) Time Tag Counter Register (0x0049)
Remote Terminal 2 (RT2) Time Tag Counter Register (0x004B) ............................155
18.13. Remote Terminal 1 (RT1) Time Tag Utility Register (0x004A)
Remote Terminal 2 (RT2) Time Tag Utility Register (0x004C) ................................156
18.13.1. RT Time Tag Counter Loading ............................................................................156
18.13.2. RT Time Tag Count Match Interrupts ..................................................................156
18.14. RT1 and RT2 Remote Terminal Interrupt Registers and Their Use ........................157
18.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012).................................158
18.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009)...............................158
18.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016) .....................158
19. REMOTE TERMINAL RT1 AND RT2 CONFIGURATION AND OPERATION 161
19.1. Command Responses ............................................................................................161
19.1.1. RT to RT Commands. .........................................................................................163
19.2. Command Illegalization Table.................................................................................163
19.3. Temporary Receive Data Buffer..............................................................................168
19.4. Descriptor Table......................................................................................................168
19.4.1. Receive Subaddress Control Word .....................................................................171
19.4.2. Transmit Subaddress Control Word ....................................................................174
19.4.3. Data Buffer Options for Mode Code Commands.................................................176
19.4.4. Receive Mode Control Word ...............................................................................177
19.4.5. Transmit Mode Control Word...............................................................................179
20. REMOTE TERMINAL RT1 AND RT2 MESSAGE DATA BUFFERS............... 183
20.1. Subaddress Message Information Words ..............................................................184
20.1.1. Receive Subaddress Command .........................................................................184
20.1.2. Transmit Subaddress Command ........................................................................186
20.2. Mode Command Message Information Words .......................................................187
20.2.1. Receive Mode Command ...................................................................................188
20.2.2. Transmit Mode Command ..................................................................................189
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20.3. Ping-Pong Data Buffering .......................................................................................191
20.3.1. Double Buffered (Ping-Pong) Mode ....................................................................191
20.3.2. Ping-Pong Enable / Disable Handshake .............................................................192
20.3.3. Broadcast Message Handling in Ping-Pong Mode..............................................194
20.4. Indexed Data Buffer Mode......................................................................................196
20.4.1. Single Message Mode.........................................................................................196
20.4.2. Broadcast Message Handling in Index Mode......................................................196
20.5. Circular Buffer Mode 1............................................................................................200
20.6. Circular Buffer Mode 2............................................................................................204
21. REMOTE TERMINAL RT1 AND RT2 MODE COMMAND PROCESSING .... 209
21.1. General Considerations ..........................................................................................209
21.2. Mode Command Interrupts .....................................................................................209
21.3. Mode Command Data Words .................................................................................210
21.4. Standard Mode Command Processing...................................................................212
21.5. Simplified Mode Command Processing..................................................................212
22. SERIAL EEPROM PROGRAMMING UTILITY............................................... 214
22.1. Writing the Auto-Initialization EEPROM..................................................................214
22.2. Overall 32K Word Checksum Used by Auto-Initialization .......................................216
23. RESET AND INITIALIZATION........................................................................ 218
23.1. Hardware Master Reset and Optional Auto-Initialization ........................................218
23.2. Memory Test Fail Address Register (0x0024).......................................................221
23.3. Software Reset .......................................................................................................222
23.3.1. Remote Terminal 1 (RT1) ....................................................................................222
23.3.2. Remote Terminal 2 (RT2) ....................................................................................223
23.3.3. Bus Monitor SMT / IMT........................................................................................224
24. SELF-TEST.................................................................................................... 226
24.1. Optional RAM Self-Test after Hardware Master Reset ...........................................226
24.2. Host-Directed Self-Test...........................................................................................226
24.2.1. Self-Test Control Register (0x0028) .................................................................226
24.2.2. Loopback Test Transmit Data Register (0x001F) ..............................................230
24.2.3. Loopback Test Receive Data Register (0x0002) ...............................................230
24.2.4. RAM Self-Test Fail Address Register (0x001B).................................................230
24.2.5. Host-Directed RAM Self-Test...............................................................................231
24.2.6. Host-Directed RT-Mode Loopback Testing (On-Line Analog or Off-Line Digital) 231
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24.2.7. Programmed BC-Mode Digital Loopback Testing (Off-Line) ..............................232
24.2.8. Continuous BC-Mode Analog Loopback Testing (On-Line) ................................232
25. HOST INTERFACE ........................................................................................ 233
25.1. HI-6130 Host Bus Interface.....................................................................................233
25.1.1. Bus Wait States and Data Prefetch.....................................................................233
25.2. HI-6131 Serial Peripheral Interface.........................................................................234
25.2.1. Serial Peripheral Interface (SPI) Basics .............................................................234
25.2.2. HI-6131 SPI Commands......................................................................................235
25.2.3. Fast-Access Commands for Registers 0-15 .......................................................235
25.2.4. Fast-Access Write Commands for Registers 0-63 .............................................235
25.2.5. Indirect Addressing of RAM and Registers .........................................................236
25.2.6. Data Prefetch for SPI Read Cycles ....................................................................238
25.2.7. Special Purpose Commands ..............................................................................239
25.2.8. RT Descriptor Table Prefetch Exceptions ...........................................................241
26. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS ... 245
27. ELECTRICAL CHARACTERISTICS .............................................................. 272
27.1. Absolute Maximum Ratings ....................................................................................272
27.2. Recommended Operating Conditions.....................................................................272
27.3. DC Electrical Characteristics ..................................................................................272
27.4. AC Electrical Characteristics ― HI-6131 Host Bus Interface Timing......................274
27.5. AC Electrical Characteristics ― HI-6130 Host Bus Interface Timing......................275
28. MIL-STD-1553 BUS INTERFACE .................................................................. 280
29. THERMAL CHARACTERISTICS ................................................................... 281
30. ADDITIONAL PIN / PACKAGE CONFIGURATIONS ..................................... 281
30.1. HI-6131PCx (64-pin QFN) ......................................................................................281
30.2. HI-6131PQx (64-pin PQFP)....................................................................................282
30.3. HI-6132Cxx (121BGA, 121LGA or 121PGA) ..........................................................283
31. ORDERING INFORMATION.......................................................................... 284
32. REVISION HISTORY ..................................................................................... 286
33. PACKAGE DIMENSIONS .............................................................................. 288
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List of Figures
Figure 1. Block Diagram.............................................................................................................. 14
Figure 2. Address Mapping for Registers and RAM .................................................................... 21
Figure 3. Fixed Address Mapping for Interrupt Log Buffer........................................................... 39
Figure 4. Bus Controller Message Sequence Structures............................................................. 52
Figure 5. Bus Controller Flag Operation...................................................................................... 62
Figure 6. Structure of Bus Controller Message Control / Status Blocks in RAM ......................... 64
Figure 7. Simple Monitor Terminal (SMT) Data Storage.............................................................. 97
Figure 8. Deriving the Monitor Filter Table Address from the Received Command Word ......... 101
Figure 9. IRIG-106 Data Packet and Message Storage Summary.............................................115
Figure 10. Deriving the Monitor Filter Table Address from the Received Command Word ....... 123
Figure 11. IRIG-106 Data Fields and Message Storage............................................................ 124
Figure 12. MIL-STD-1553 Command Word Structure ............................................................... 161
Figure 13. Deriving the Illegalization Table Address From the Received Command Word ....... 165
Figure 14. Address Mapping for Illegalization Table ................................................................. 166
Figure 15. Summary of RT1 Illegalization Table Addresses for Mode Code Commands ......... 167
Figure 16. Address Mapping for RT1 Descriptor Table ............................................................. 170
Figure 17. Deriving a Descriptor Table Control Word Address From Command Word ............. 171
Figure 18. Illustration of Ping-Pong Buffer Mode ...................................................................... 193
Figure 19. Ping-Pong Buffer Mode Example for a Receive Subaddress .................................. 195
Figure 20. Illustration of Indexed Buffer Mode .......................................................................... 198
Figure 21. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled) .... 199
Figure 22. Illustration of Circular Buffer Mode 1 ........................................................................ 202
Figure 23. Circular Buffer Mode 1 Example for a Receive Subaddress ................................... 203
Figure 24. Illustration of Circular Buffer Mode 2 ........................................................................ 207
Figure 25. Circular Buffer Mode 2 Example for a Receive Subaddress ................................... 208
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Figure 26. Generalized Single-Byte Transfer Using SPI Protocol.
SCK is Shown for SPI Modes 0 and 3 ..................................................................... 235
Figure 27. Single-Word (2-Byte) Read From RAM or a Register .............................................. 237
Figure 28. Single-Word (2-Byte) Write To RAM or a Register .................................................. 237
Figure 29. HI-6131 Host Bus Interface Timing Diagram............................................................ 274
Figure 30. Register and RAM Write Operations for BTYPE = 1................................................ 276
Figure 31. Register and RAM Write Operations for BTYPE = 0................................................ 277
Figure 32. Register and RAM Read Operations for BTYPE = 1................................................ 278
Figure 33. Register and RAM Read Operations for BTYPE = 0................................................ 279
Figure 34. MIL-STD-1553 Direct Coupled Test Circuits............................................................. 280
Figure 35. MIL-STD-1553 Transformer Coupled Test Circuits................................................... 280
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List of Tables
Table 1. Common pins (Apply to all devices)............................................................................... 16
Table 2. Pins that apply to HI-6130 or HI-6132 only (Host parallel bus interface)....................... 19
Table 3. Pins that apply to HI-6131 or HI-6132 only (Host SPI bus interface)............................. 20
Table 4. Pins that apply to HI-6132 only (Selectable 16-bit parallel bus or SPI host interface)... 20
Table 5. Register Summary ......................................................................................................... 25
Table 6. Bus Controller Condition Code Table............................................................................. 53
Table 7. Bus Controller Instruction Op Codes.............................................................................. 56
Table 8. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition ..... 82
Table 9. Message Block in Circular Command Buffer for SMT Monitor using 16-bit Time Tag ... 93
Table 10. Message Block in Circular Command Buffer for SMT Monitor using 48-bit Time Tag . 94
Table 11. Monitor Address List for SMT Mode............................................................................. 95
Table 12. SMT Message Filter Table ......................................................................................... 102
Table 13. IMT Message Filter Table........................................................................................... 123
Table 14. Monitor Address List for IMT Mode ............................................................................ 126
Table 15. Summary of Data Buffer Modes. ............................................................................... 184
Table 16. Circular Buffer Mode 2 (Initialization factors based on message block size)............. 205
Table 17. Mode Code Command Summary............................................................................... 210
Table 18. Terminal Unlock Word Encoding................................................................................ 215
Table 19. Registers are not written using EEPROM data.......................................................... 216
Table 20. READY delay times: from MR input pin rising edge to READY output pin rising edge....
218
Table 21. RT1 Soft Reset Summary .......................................................................................... 222
Table 22. RT2 Soft Reset Summary .......................................................................................... 223
Table 23. SMT / IMT Soft Reset Summary ................................................................................ 224
Table 24. Fast-Access SPI Commands for Lower Registers .................................................... 243
Table 25. SPI Commands using Memory Address Pointer........................................................ 244
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HI-6130, HI-6131
1. BLOCK DIAGRAM
HI-6130 MIL-STD-1553 Terminal with Host Parallel Bus Interface
HI-6131 MIL-STD-1553 Terminal with Host SPI Interface
RT1A4 - 0
RT1AP
IRQ
MTPKRDY
READY
RT2A4 - 0
RT2AP
Discrete
Signal
Outputs
Configuration
Option
Logic
BENDI
ACTIVE
RT1LOCK
RT2LOCK
MTSTOFF
RAMEDC
RT1MC8
RT2MC8
Static RAM
and
Registers
BWID
BTYPE
WPOL
MCLK
INTERNAL
CLOCKS
TTCLK
MTTCLK
Host Bus
Interface
BC
Message
Processor
CE
R / W or WE
STR or OE
A0 / LB
TXINHA
HI-6130
Only
Address
Bus A
BUSA
WAIT or WAIT
A15:1
Data
Manchester
Encoder
Control
BUS
Memory
and
Register
Access
Control
D15:0
Bus A
Manchester
Decoder
MT
Message
Processor
BUSA
Address
Data
Host
Interface
SPI
CE
SCK
SI
Control
TXINHB
HI-6131
Only
RT1
Message
Processor
Bus B
Manchester
Encoder
SO
BUSB
BUS
Bus B
Manchester
Decoder
AUTOEN
EECOPY
MR
BUSB
Reset &
Initialization
Logic
RT2
Message
Processor
TRANSCEIVER
VCCP
BUS/SPI
(HI-6132 only)
POWER
GND
VCC
BCENA
BCTRIG
MTRUN
RT1ENA
RT2ENA
ACKIRQ
RT1SSF
RT2SSF
LOGIC POWER
Discrete
Signal
Input
Serial
Peripheral
Interface
(SPI) to
TEST
Test
Logic
MODE
EEPROM
OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
Figure 1. Block Diagram
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HI-6130, HI-6131
rollover occurs, or when a user-programmed buffer level
2. FEATURE OVERVIEW
has been reached. The IMT stores message records
in the assigned buffer using IRIG 106 “packet body”
format. The device can optionally generate complete
IRIG 106 packets, including full packet headers and
trailers meeting IRIG 106 Chapter 10 requirements.
2.1. Bus Controller Operation
TheHI-613xisconfigurabletooperateasaBusController
(BC). The BC is a programmable message-sequencing
device for control in MIL-STD-1553B applications.
Programmed using a set of 28 instruction op codes,
the BC greatly reduces the host’s processing workload.
The BC can optionally use a 16- or a 32-bit time base,
clocked from a choice of six internally generated clocks,
or an external time base clock. Special BC op codes
manage all 32-bit time base functions.
2.4. Interrupts
Host interrupts can originate from device hardware or
any of the enabled terminal devices (up to 4 devices).
A circular 64-word Interrupt Log Buffer retains interrupt
information from the last 32 interrupts, while the
hardware maintains a count of occurring interrupts since
the previous host buffer service.
TheprogrammableHI-613xBusControllerautonomously
supports multi-frame message scheduling, message
retry schemes, storage of message data, asynchronous
message insertion and status /error reporting to the host
processor.
Hardware-assisted interrupt decoding provides quick
identification of the interrupt source by terminal device:
BC, MT, RT1, RT2 or hardware. When a hardware
interrupt occurs (e.g., Bus A Loopback Failure), a
Pending Hardware Interrupt register bit explicitly
identifies the interrupt source. For interrupts from BC,
MT or RT, the three low-order bits in the same register
identify the specific interrupt register (or registers) with
pending interrupts: that is, the BC, MT or RT Pending
Interrupt registers.
2.2. Remote Terminal Operation
The HI-613x is configurable to operate one as or two
RemoteTerminals.TheRTsaremodeledafterthepopular
Holt HI-6120/21 Remote Terminal. The two Remote
Terminals operate with independent characteristics,
each RT having fully separate RAM structures (e.g.,
descriptor and illegal command tables) and independent
configuration and status registers. RAM buffer options
include single, double and 2 circular buffer choices. The
two RTs can be reset and reinitialized independently.
The full benefit of two autonomous RTs is achieved
while using the same complexity and circuit board area
as a single Remote Terminal.
2.5. Reset and Initialization
After hardware Master Reset, there are two HI-
613x initialization methods: host initialization or self-
initialization from external serial EEPROM. For host
initialization, the host processor uses its bus interface
or 4-wire SPI to load HI-613x registers and initialize
tables, data buffers, etc. in internal static RAM. For self-
initialization, the device uses setup information contained
within an external serial EEPROM. A dedicated 4-wire
SPI port reads data from the serial EEPROM and writes
it to registers and RAM. Error checking is performed,
looking for data mismatch or an EEPROM checksum
error.
2.3. Monitor Terminal Operation
Message commands, terminal responses and message
data are stored in internal RAM, using one of two
possible modes. Simple Monitor Terminal (SMT) and
IRIG Monitor Terminal (IMT) Modes are targeted for
different applications. When operating in SMT mode, the
MT records commands and data separately. The SMT
can utilize 16- or 48-bit time tags with a range of clocking
options.
Individual 1553 terminal devices (BC, MT, RT1 or RT2)
can be re-initialized from the serial EEPROM by writing
to the Reset Initialization Register.
The IMT mode operation is designed to meet data
recording requirements of Telemetry Standard RCC
Document 106-07, Chapter 10. This “IRIG 106 Chapter
10” data recorder uses 48-bit relative time stamping,
having 10MHz (100ns) resolution. Message time stamps
occur at one of three selectable message progress
points. Several error handling schemes are available.
Bus Monitor interrupts notify the host when circular buffer
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HI-6130, HI-6131
3. PIN DESCRIPTIONS
Table 1. Common pins (Apply to all devices)
Pin
Function
Description
Input
50KΩ pull-down
MCLK
Master clock input, 50.0MHz +/-100 ppm.
TTCLK
Inputs
Optional clock input for BC time base and RT time tag counters.
MTTCLK
50KΩ pull-down Optional clock input for the MT time tag counter.
Each function (BC, MT, RT1, RT2) has an independent time tag counter. The BC
and RT counters share a common clock, selectable from internally generated
frequencies, or an external clock input. The MT time tag counter has its own
external or internal clock source.
Input
50KΩ pull-up
Master reset, active low. The host can also assert software reset by setting bits
in the Master Status & Reset register.
MR
Transmit inhibit inputs for Bus A and Bus B, active high. These two inputs are
TXINHA
TXINHB
Inputs
logically ORed with the pair of corresponding bits in the Master Configuration
50KΩ pull-down Register to enable or inhibit transmit on Bus A or Bus B, affecting behavior for
all enabled 1553 devices.
Memory test disable, active high. When this pin is low, the device performs a
Input
memory test on the entire RAM after rising edge on the MR reset pin. When
MTSTOFF
AUTOEN
50KΩ pull-down this pin is high, RAM testing is skipped, resulting in a faster reset process. For
further information, refer to Section 23.
Auto-Initialize Enable, active high. If this pin is high at rising edge on MR reset
pin, self-initialization proceeds, copying configuration data to registers and RAM
Input
50KΩ pull-down from an external serial EEPROM via a dedicated EEPROM SPl port. Refer to
Section 23.
This pin is low when auto-initialization or built-in test is in process. The host
cannot read or write device RAM or registers when pin state is low; reads to
READY
ACTIVE
Output
Output
any address return the value in the Master Status & Reset register. When the
AUTOEN pin is low at Master Reset, the host can configure device RAM and
registers after READY goes high.
This pin is high while an enabled BC or RT in the device is processing a 1553
message. The IMTA bit 1 in Master Configuration Register 0x0000 logically-
ORs bus monitor (MT) activity as well.
ECS
Output
ESCK
MOSI
MISO
Output
Output
Input
Dedicated 4-wire Serial Peripheral Interface (SPI) for connection to an optional
external EEPROM used for automatic self-initialization when AUTOEN is high
at Master Reset.
50KΩ pull-down
Input
EEPROM Copy, active high. Asserting this input initiates RAM and register copy
EECOPY
BCENA
50KΩ pull-down into serial EEPROM used for auto-initialization. Refer to Section 23.
Input
50KΩ pull-down
Bus Controller Enable input, active high.
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HI-6130, HI-6131
Pin
Function
Description
Input
50KΩ pull-down
BCTRIG
BC Trigger input, active high. Used in conjunction with certain BC instructions.
Input
Monitor Run / Stop input, active high. This input starts/stops MT data recording.
MTRUN
50KΩ pull-down Upon going low, the MT stops when the current message is completed.
RT1 and RT2 enable input pins, active high. These inputs are logically ANDed
with the corresponding RT1ENA and RT2ENA bits in Master Configuration
Register 0x0000. TheANDed result must be high before initializing RTDescriptor
Tables, and must be high when the Master Configuration Register RT1STEX or
RT1ENA
RT2ENA
Inputs
50KΩ pull-down
RT2STEX start execution bits are asserted to begin RT1 or RT2 operation.
Pin states are latched to the Lock bit in the RTx Operational Status register
when rising edge occurs on the MR pin. If status register Lock bit is high, the
host cannot overwrite the terminal address in the same register. If status register
Lock bit is low, the host can overwrite the terminal address and parity (and the
RT1LOCK
RT2LOCK
Inputs
50KΩ pull-down
Lock bit) in the RTx Operational Status register.
Remote Terminal “Reset RT” mode command (MC8) received. This active low
output is asserted at Status Word completion when RT1 or RT2 received a
“Reset Remote Terminal” mode code command. The minimum output pulse
width is 100ns, unaffected by MR assertion.
RT1MC8
RT2MC8
Outputs
RT Subsystem Fail input, active high. When this input is high, the selected RT1
RT1SSF
RT2SSF
Inputs
or RT2 sets the SUBSYS flag in its transmit status word. This input is logically-
50KΩ pull-down ORed with the same bit in the terminal’s RT1 or RT2 1553 Status Word Bits
register.
Monitor Packet Ready output, active high. This pin is asserted when a message
data packet is complete, as defined by the various MT configuration registers
(maximum word or message count, maximum packet time, etc.) Assertion of
this bit indicates the MT has stopped.
MTPKRDY
IRQ
Output
Interrupt request, active low. This pin is asserted each time an enabled interrupt
event occurs. This signal is programmed as a brief low-going pulse output or
as a level output by the INTSEL bit in the Master Configuration Register. If level
output is selected, IRQ stays low until the host acknowledges IRQ by pulsing a
rising edge at the ACKIRQ pin.
Output
Input
Interrupt Acknowledge, active high. This input is only used when the INTSEL bit
in the RT Configuration Register is high, enabling level interrupt assertion for the
50KΩ pull-down IRQ pin. When interrupt assertion causes the IRQ pin to go low, a high-going
ACKIRQ
pulse on ACKIRQ (250ns minimum duration) clears the IRQ output to logic 1.
Remote terminal address bits 4 - 0, and parity bit for RT1 and RT2. The RTAP
pin provides odd parity for the address on pins RTA4:0.
RT1A4:0
RT1AP
The terminal address and parity pin levels are latched into the respective RT
Inputs
Operational Status Registers when rising edge occurs on the MR pin. The RT
50KΩ pull-ups
RT2A4:0
RT2AP
Operational Status Register value (not these pins) reflects the active terminal
address. The host can overwrite the RT Operational Status register address
value only when the register Lock bit is reset.
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HI-6130, HI-6131
Pin
Function
Description
Big Endian configuration pin for selecting “endianness” or byte order, when
using byte transfers. Endianness is the system attribute that indicates whether
integers are represented with the most significant byte stored at the lowest
address (big endian) or at the highest address (little endian). Internal register /
RAM storage is “big endian.”
When using the HI-6130, this pin only applies when the host parallel bus is
configured for 8-bit width, that is, when BWID equals 0. When the HI-6130 is
configured for 16-bit bus width, the BENDI input pin is “don’t care.”
Input
50KΩ pull-up
BENDI
When using the HI-6131, this pin controls the byte order of transferred 16-bit
data following the SPI command. When BENDI is low, “little endian” is chosen;
the low order byte (bits 7:0) is transacted on the SPI before the high order byte
(bits 15:8). When BENDI is high, “big endian” is chosen and the high order byte
is transacted on the SPI before the low order byte.
RAM EDC (Error Detection / Correction) enable.
When pin is low, device operates with 32K word RAM address space, EDC
disabled. When pin is high, device operates with 24K word RAM address space
with EDC enabled. All single-bit RAM read errors are automatically corrected.
The corrected errors and uncorrectable multi-bit RAM read errors can generate
separate, optional interrupts.
Input
50KΩ pull-down
RAMEDC
Input
Test enable input. The host asserts this pin to perform RAM self-test and loop-
TEST
50KΩ pull-down back tests.
Input
50KΩ pull-up
MODE
Pin used for factory test. Do not connect.
VCC
VCCP
GND
Power Supply
3.3VDC power supply for logic and bus transceiver.
BUSA
BUSA
Bi-directional Bus A interface to external MIL-STD-1553 isolation transformer.
Observe positive / negative polarity.
Analog
Analog
BUSB
BUSB
Bi-directional Bus B interface to external MIL-STD-1553 isolation transformer.
Observe positive / negative polarity.
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HI-6130, HI-6131
Table 2. Pins that apply to HI-6130 or HI-6132 only (Host parallel bus interface)
Pin
Function
Description
Chip Enable, active low. When asserted, this pin enables host read or write
accesses to device RAM or registers using the host’s parallel bus interface. This
pin is normally connected to a Chip Select output from the host’s bus interface.
Input
50KΩ pull-up
CE
Tri-state data bus for host read/write operations upon registers and shared
RAM. All bus read/write operations transact 16 bit words, but bus width can be
configured for 8 or 16 bits. For 8-bit bus width, pins D15:8 are not connected.
Sixteen-bit words are transacted over an 8-bit bus as a pair of byte operations,
In / Out
D15:0
50KΩ pull-down with data presented sequentially on pins D7:0. For compatibility with different
host processors when 8-bit bus width is enabled, the BENDI input determines
whether the low order byte is transferred before the high order byte, or vice
versa.
Address bus for host read/write operations upon registers and shared RAM.
A15:1
Input
50KΩ pull-up
When using 16-bit bus width, address bit A0 / (LB) from the host is not used. For
8-bit bus width, output A0 equals 0 during the first byte read/write access; and
equals 1 during the second byte access.
A0 / LB
Input
50KΩ pull-up
Configuration pin for host bus width. High selects 16-bit bus width, low selects
8-bit bus width.
BWID
Configuration pin for host bus read/write control signal style. High selects “Intel
style” using separate read strobe OE (output enable) and write strobe WE. Low
selects “Motorola style” using single active-low read/write strobe STR and read/
write select signal, R/W.
Input
50KΩ pull-up
BTYPE
Read/write direction signal R/W when BTYPE pin is low.
Active-low Write Enable WE when BTYPE pin is high.
Input
50KΩ pull-up
R/W / WE
Used for host read or write accesses to device RAM or registers. This pin or the
CE pin should be high during all address transitions.
Active-low common read/write strobe STR when BTYPE pin is low.
Active-low Output Enable OE when BTYPE pin is high.
Input
50KΩ pull-up
STR / OE
WPOL
Used for host read or write accesses to device RAM or registers.
Configuration pin for WAIT output polarity. When the WPOL pin is low, the “wait”
output is active low (WAIT). When WPOL is high, the “wait” output is active high
(WAIT).
Input
50KΩ pull-up
HOLT INTEGRATED CIRCUITS
19
HI-6130, HI-6131
Pin
Function
Description
Host bus read cycle WAIT or WAIT output. The HI-6130 WPOL input pin sets the
active level for this “wait” output.
Read cycles are slower than write cycles, but prefetching speeds data availability
for multi-word sequential address read cycles. For every new bus read cycle,
the HI-6130 asserts WAIT. Connected to the processor WAIT or WAIT input, this
action inserts one or more processor wait states (depending on processor clock
frequency) while the HI-6130 fetches the first word. After reading each HI-6130
register or RAM address, the device prefetches and retains data from the next
address. If the next bus access reads that sequential address, the data is ready
without WAIT assertion, even if that read cycle occurs some time later. While
the prefetch “chain” is broken by any write cycle, each read cycle prefetches
and retains data from the next address, whether or not it is needed. Thus WAIT
assertion only occurs for the first word read.
WAIT / WAIT Output
The WAIT output is useful when the host processor runs at high clock rates and/
or when processor read wait states do not provide adequate timing margin for
worst case (slowest) read cycle timing for the HI-6130. Using the WAIT output
for the slow, first read cycle means the processor bus interface can be optimized
to use faster no-wait cycles for write operations, and for reading words 2 through
N in successive address, N-word read operations. Processors lacking a WAIT
or WAIT input pin are typically configured to insert a fixed number of wait states
for every read/write cycle.
Table 3. Pins that apply to HI-6131 or HI-6132 only (Host SPI bus interface)
Pin
Function
Description
Chip Enable, active low. When asserted, this pin enables host read or write
accesses to device RAM or registers via host SPI port. The HI-6131 SPI port
operates in Slave mode. This pin is connected to the Slave Select output on
the host SPI port.
Input
50KΩ pull-up
CE
SO
Serial Peripheral Interface (SPI) Serial Output pin. This pin is connected to
MISO (Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated
when not transmitting serial data to the host.
Output
Input
Serial Peripheral Interface (SPI) Serial Input pin. This pin is connected to
50KΩ pull-down MOSI (Master Out - Slave In) pin on host SPI port.
SI
Input
Serial Peripheral Interface (SPI) Serial Clock pin. This pin is connected to SCK
SCK
50KΩ pull-down output pin on host SPI port.
Table 4. Pins that apply to HI-6132 only (Selectable 16-bit parallel bus or SPI host interface)
Pin
Function
Input
Description
BUS / SPI
Selects 16-bit wide parallel bus or SPI operation
50KΩ pull-up
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20
HI-6130, HI-6131
4. MEMORY MAP
0x7FFF
0x01FF
RT2 Temporary Receive Buffer.
32 Words
0x01E0
0x01DF
Host-Allocated
Static RAM.
Comprising 94% of the memory
address space, this RAM is
allocated for use by the
RT1 Temporary Receive Buffer.
32 Words
0x01C0
0x01BF
enabled terminal devices.
Interrupt Log Data Buffer.
64 Words
0x0800
0x07FF
RT2 Descriptor Table.
Defines terminal behavior
for valid commands:
how data is stored,
host interrupts, etc.
512 words
0x0180
0x017F
MT Message Filter Table.
Multiple Descriptor Tables can be
used for fast context switching.
The active Descriptor Table is
defined by the Descriptor Table
Base Address Register.
128 Words
0x0600
0x05FF
RT1 Descriptor Table.
Defines terminal behavior
for valid commands:
how data is stored,
host interrupts, etc.
512 words
0x0100
0x00FF
BC General Purpose Queue.
64 Words
Multiple Descriptor Tables can be
used for fast context switching.
The active Descriptor Table is
defined by the Descriptor Table
Base Address Register.
0x00C0
0x00BF
0x00B8
0x00B7
0x00B0
MT Address List B. 8 Words
MT Address List A. 8 Words
0x0400
0x03FF
RT2 Illegalization Table.
Initialized by the host, this table
identifies illegal commands.
256 Words
0x00AF
MT Temporary Buffer B.
42 Words
0x0300
0x02FF
0x0086
0x0085
MT Temporary Buffer A.
RT1 Illegalization Table.
Initialized by the host, this table
identifies illegal commands.
256 Words
42 Words
0x005C
0x005B
0x0054
0x0053
0x0050
BC Call Stack. 8 Words
Reserved. 4 Words
0x0200
0x01FF
Expanded
at Right
0x004F
Registers (listed in Table 4)
80 Locations
0x0000
0x0000
Figure 2. Address Mapping for Registers and RAM
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HI-6130, HI-6131
5.5. Bus Controller (BC) General
5. RAM STRUCTURES
Purpose Queue
Figure 2 shows a memory map for HI-613x memory and
registers. Application requirements dictate the specific
RAM structures needed. These structures listed here
are explained later.
The Bus Controller General Purpose Queue provides a
convenient way for the BC to convey information to the
external host. Numerous BC op codes push various data
onto the queue, including time tag count, data values,
message Block Status Word or the data at specific RAM
address locations.
5.1. Interrupt Log Data Buffer
The device maintains information from the last 32
interrupts in a 64-word circular buffer in RAM known as
the Interrupt Log. Two 16-bit words characterize each
interrupt; one word identifies the interrupt type (Interrupt
Identification Word) and one word identifies the
command that generated the interrupt (InterruptAddress
Word). After reset, the Interrupt Log Address Register
contains the fixed buffer start address of 0x0180. After
each occurring interrupt, the device updates the register
to point to the log address used for the next occurring
interrupt.
5.6. Monitor Terminal Temporary Buffers
A & B
The HI-613x Monitor Terminal (MT) has one 42 word
receive buffer for each bus. Received command words,
status words and data words are temporarily stored in
these buffers. At message completion, the recorded
data is copied to Monitor Terminal buffer(s).
5.7. Monitor Terminal (MT) Address List
5.2. Bus Controller (BC) Instruction List
The monitor Address List contains user-written RAM
addresses assigning buffer start and end addresses,
and buffer utilization interrupt addresses. It also has
device-maintained data buffer pointer(s).
BC message sequencing uses an instruction list,
comprised of multiple 2-word entries. Each entry
consists of an instruction word (op code plus execution
condition code) followed by a parameter word. Some op
codes execute unconditionally, but most are conditional,
and execute only if the condition code specified in the
instruction word tests true. This architecture provides
flexibility for message frame scheduling and autonomous
BC program execution, based on various conditions.
5.8. Monitor Terminal (MT) Message
Filter Table
This 128-word table is optionally used to selectively
monitor MIL-STD-1553 messages based on each
command’s RT address and subaddress, and the
transmit/receive bit status.
5.3. Bus Controller (BC) Msg Control /
Status Stack
5.9. Monitor Terminal (MT) Data Buffers
Referenced when a BC Instruction List parameter is
an address pointer, the Message Control Status Stack
consists of 8- or 16-word control blocks for individual
MIL-STD-1553 messages. Within the message control/
status block, execution parameters are provided
including inter-message gap, message format, active
bus, message command word(s), then address pointer
to a message data block in RAM (when the command
includes data) and the expected RT status response.
For bus monitor applications, there are two operating
modes: The SMT simple monitor stores command and
data words in separate RAM buffers. The IMT IRIG-
106 monitor stores all information in a single RAM data
buffer, with or without formatted packet header and
trailer. For both, the monitor Address List assigns RAM
buffer boundaries.
5.10. RT1 and RT2 Command Illegalization
Tables
5.4. Bus Controller (BC) Call Stack
For each RT, optional illegal command detection utilizes
this table in RAM. The table can illegalize any logical
combination of 11 command word bits comprising
subaddress, the transmit/receive bit and word count (or
mode code), plus broadcast vs non-broadcast status,
When the Bus Controller executes a “subroutine call”
op code, the BC Subroutine Call Stack stores the list
address for the next op code, to be executed upon
return from subroutine. The BC call stack allows 8 levels
of nesting.
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HI-6130, HI-6131
resulting in a total of 4,096 possible combinations.
6. HARDWARE FEATURES
Terminal response to an illegal command sets “Message
Error” status and transmits Status Word only. If illegal
command detection is not used (that is, no “illegal”
entries in Illegalization Table), the terminal responds “in
form” to all valid commands.
6.1. Remote Terminal Address Inputs
The 5-bit Remote Terminal address is set using pins
RTA4:0. The RTAP input pin should be set or reset to
present matching odd parity. The state of the RT address
and parity pins is latched into the RT Operational Status
register upon rising edge on the MR master reset
input. The state of the LOCK input is latched into the
RT Operational Status register at the same time, and
controls whether or not the active terminal address
and parity in the RT Operational Status register can
be overwritten by host writes into the register. When
the LOCK input pin is high, autoinitialization cannot
overwrite the RT address value latched from the input
pins. Between Master Reset assertions, the state of the
RTA and RTAP input pins is “don’t care”. If the value
of RT address and parity in the RT Operational Status
register has parity error, terminal operation is disabled.
5.11. RT1 and RT2 Descriptor Tables
For each RT, a host-initialized Descriptor Table in RAM
defines how the terminal responds to valid commands.
The table is comprised of 128 four-word descriptor
blocks. Each of 32 subaddresses and 32 mode code
values has one descriptor block for transmit and another
for receive. The descriptor table defines message
options (interrupt selections, data buffer mode, etc.) and
contains pointers to allocated data storage in RAM.
5.12. RT1 and RT2 Temporary Receive
Buffers
Remote Terminals RT1 and RT2 temporarily store
command and data words during message transaction.
At successful message completion, all data is transferred
to assigned subaddress buffers. This strategy prevents
valid data from being overwritten by incomplete or bad
data from a later message ending in error.
6.2. Dual Transceivers for MIL-STD-1553
Bus
Built-in bus transceivers provide direct interface
between the device and MIL-STD-1553 bus isolation
transformers. The transceivers convert digital data to
and from differential Manchester II encoded bus signals.
A pair of “transmit inhibit” input pins exercises direct
control over transmission for both buses.
5.13. RT Message Data Buffers
Ordinary transmit and receive commands transact from
1 to 32 data words. The host allocates space in RAM
for storing transacted message data words as well as
message information words.
6.3. Encoder and Decoders
The device uses separate Manchester II encoders and
decoders for each bus. Decoders check for proper
sync pulse and Manchester waveform, edge skew,
correct number of bits and parity. Encoders are used
for transmission. During transmit, each encoded word is
looped back through the bus decoder for error checking.
Receiver bus sampling is clocked at 50 MHz, providing
excellent tolerance to zero-crossing distortion.
5.14. RT Storage for Mode Code
Commands
In addition to commands used for data transmit and
receive, MIL-STD-1553 also defines “mode code
commands” for command and control. These “mode
commands” transfer a single data word, or no data word
at all. The user has the option for storing mode command
data in RAM buffers assigned in the Descriptor Table, or
stored within the RT Descriptor Table itself. The second
option is often preferred for its simplicity.
6.4. Auto-Initialization Serial EEPROM
Interface
The device has an automatic self-initialization feature.
If self-initialization is enabled after MR master reset,
the device reads configuration settings from an external
serialEEPROMtoinitializeregistersandRAMstructures.
A method is provided to initially program or later modify
the external serial EEPROM by copying host-loaded
tables and register values to the serial EEPROM.
HOLT INTEGRATED CIRCUITS
23
HI-6130, HI-6131
whether the first or second byte in the word is being
6.5. Selection of Host Interface (HI-6132
only)
addressed, whileA15-A1 indicate the word address. This
difference must be considered when assigning HI-6130
pointer values or accessing RAM or registers. From the
microprocessor’s standpoint, any host-assigned RAM
buffer address will be double the value of the buffer’s
pointer stored in RAM. This paragraph only applies to
HI-6130 using 8-bit bus width. From this point on, all
register and memory addresses presented in this data
sheet are 15-bit word addresses.
The HI-6132 (hermetic ceramic BGA package) provides
the option of a selectable host interface using the SPI/
BUS pin.
•
BUS/SPI pin set to logic “1”: Selects 16-bit parallel
bus host interface
•
BUS/SPI pin reset to logic “0”: Selects SPI host
interface
From the host standpoint, register operations and RAM
operations are performed identically. Depending on
function, individual registers may be read-only, read-
write, or a combination of read-only and read-write bit
fields. Read-only registers and read-only register bit
fields, are protected against accidental host overwrite
by device logic.
7. REGISTER & MEMORY
ADDRESSING
The HI-613x has an internal address space of 32K
16-bit words. Registers occupy the low 80 locations in
this address space. In this data sheet, register / RAM
addresses are expressed as hexadecimal numbers,
using the C programming convention where the prefix
“0x” denotes a hexadecimal value; e.g., 0x00FF
represents 00FF hex.
Addresses in the range 0x004C to 0x7FFF apply to
static RAM memory. All RAM is read-write and can be
written or read by either the host or the internal device
logic. Both host and the device update certain RAM
locations (e.g., RT Descriptor Table Control Words).
These locations are protected against accidental data
collision by arbitration logic which acts when concurrent
writes by both host and device occur.
Figure 2 shows address mapping for registers and
RAM. All registers and some RAM structures have fixed
addresses. Other RAM structures shown are relocatable;
Each relocatable structure has a base address register.
Figure 2 shows the default locations for relocatable
structures. RAM allocations for unused MIL-STD-1553
functions can be reassigned as needed. For example,
an application using just a Bus Monitor can reassign all
BC and RT RAM for monitor needs.
8. REGISTER DEFINITIONS
Residing at the start of the memory address space, 80
addresses are reserved for HI-613x registers. Register
addresses overlay the shared RAM address space.
Register bits are active high and bit 15 is the most
significant.
Device RAM and register address mapping is word
oriented, rather than byte oriented. Register and memory
addresses throughout this document reflect word
addressing. For all parallel bus-interface applications
(HI-6130) and most SPI interface applications (HI-
6131), word oriented addressing applies. Word oriented
addressing uses address inputs A15 to A1; address
input A0 is not used. Fifteen bits are sufficient for a 32K
address range.
Table 5 lists all device registers.
7.1. 8-bit Bus Operation: (HI-6130 Only)
When required by the application, parallel bus
interface HI-6130 devices can use byte transfers. All
8-bit microprocessors (and some 16-bit and 32-bit
microprocessors) use (or can use) byte-oriented memory
accesses. To provide byte capability, the HI-6130 uses
the sixteenth bus address input, A0. Thus 16 address
pins A15:0 address 64K bytes. The A0 input denotes
HOLT INTEGRATED CIRCUITS
24
HI-6130, HI-6131
Table 5. Register Summary
Hard
Reset
Default
Register
Number
Hex
Address
Used By Register Name
0
1
2
3
4
5
6
7
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
All
All
Master Configuration Register (page 29)
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Master Status and Reset Register (page 33)
RT1 Current Command Register (page 150)
RT1 Current Control Word Address Register (page 150)
RT2 Current Command Register (page 150)
RT2 Current Control Word Address Register (page 150)
Hardware Pending Interrupt Register (page 40)
BC Pending Interrupt Register (page 90)
RT1
RT1
RT2
RT2
All
BC
SMT Pending Interrupt Register (page 111)
IMT Pending Interrupt Register (page 140)
8
0x0008
MT
0x0000
9
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
RT1/RT2 RT1 & RT2 Pending Interrupt Register (page 158)
0x0000
0x0180
0x0000
0x0000
0x0000
0x0000
0x6000
0x6000
10
11
12
13
14
15
16
All
All
All
All
All
All
BC
Interrupt Count & Log Address Register (page 37)
Memory Address Pointer 1 (HI-6131 only) (page 49)
Memory Address Pointer 2 (HI-6131 only) (page 49)
Memory Address Pointer 3 (HI-6131 only) (page 49)
Memory Address Pointer 4 (HI-6131 only) (page 49)
Hardware Interrupt Enable Register (page 40)
BC Interrupt Enable Register (page 90)
SMT Interrupt Enable Register (page 111)
IMT Interrupt Enable Register (page 140)
17
0x0011
MT
0x6000
18
19
20
0x0012
0x0013
0x0014
RT/RT2 RT1 & RT2 Interrupt Enable Register (page 158)
0x6000
0x6000
0x0000
All
Hardware Interrupt Output Enable Register (page 40)
BC Interrupt Output Enable Register (page 90)
BC
SMT Interrupt Output Enable Register (page 111)
IMT Interrupt Output Enable Register (page 140)
21
0x0015
MT
0x0000
22
23
24
25
26
0x0016
0x0017
0x0018
0x0019
0x001A
RT1/RT2 RT1 & RT2 Interrupt Output Enable Register (page 158)
0x0000
0x0000
0x0000
0x0400
0x0000
RT1
RT1
RT1
RT1
RT1 Configuration Register (page 144)
RT1 Operational Status Register (page 148)
RT1 Descriptor Table Base Address Register (page 150)
RT1 1553 Status Word Bits Register (page 151)
HOLT INTEGRATED CIRCUITS
25
HI-6130, HI-6131
Hard
Reset
Default
Register
Number
Hex
Address
Used By Register Name
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
RT1
RT1
RT1
RT1
RT1
RT2
RT2
RT2
RT2
RT2
RT2
RT2
RT2
RT2
RT1 Current Message Info Word Register (page 152)
RT1 Bus A Select Register (page 153)
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0600
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
RT1 Bus B Select Register (page 153)
RT1 Built-In Test (BIT) Word Register (page 154)
RT1 Alternate BIT Word Register (page 155)
RT2 Configuration Register (page 144)
RT2 Operational Status Register (page 148)
RT2 Descriptor Table Base Address Register (page 150)
RT2 1553 Status Word Bits Register (page 151)
RT2 Current Message Info Word Register (page 152)
RT2 Bus A Select Register (page 153)
RT2 Bus B Select Register (page 153)
RT2 Built-In Test (BIT) Word Register (page 154)
RT2 Alt. BIT Word Register (page 155)
SMT (Bus Monitor) Configuration Register (page 103)
IMT (Bus Monitor) Configuration Register (page 128)
41
0x0029
MT
0x0800
42
43
44
45
46
0x002A
0x002B
0x002C
0x002D
0x002E
MT
MT
MT
MT
MT
IMT Packet Maximum Message Count (page 133)
IMT Packet Maximum 1553 Word Count (page 133)
IMT Packet Maximum Time (page 134)
0x0000
0x0000
0x0000
0x0000
0x0000
IMT Packet Maximum Gap Time (page 134)
IMT Channel ID Register (page 135)
SMT Address List Start Address Register (page 106)
IMT Address List Start Address Register (page 132)
47
48
49
0x002F
0x0030
0x0031
MT
MT
MT
0x0060
0x0000
0x0000
SMT Next Message Buffer Address Pointer (page 106)
IMT Next Message Buffer Address Pointer (page 132)
SMT Last Message Buffer Address Register (page 107)
IMT Last Message Buffer Address Register (page 132)
50
51
52
53
54
0x0032
0x0033
0x0034
0x0035
0x0036
BC
BC
BC
BC
BC
BC Configuration Register (page 73)
0x0000
0x0000
0x0000
0x0000
0x0000
Start Address Register for BC Instruction List (page 82)
BC Instruction List Pointer (page 82)
BC Frame Time Remaining Register (page 83)
BC Time to Next Message Register (page 83)
HOLT INTEGRATED CIRCUITS
26
HI-6130, HI-6131
Hard
Reset
Default
Register
Number
Hex
Address
Used By Register Name
BC Condition Code (page 83)
55
0x0037
BC
0x0000
BC General Purpose Flag Register (page 86)
56
57
0x0038
0x0039
BC
All
BC General Purpose Queue Pointer Register (page 86)
0x00C0
0x0000
Time Tag Counter Configuration Register (page 45)
SMT Time Tag Counter Low (page 107)
IMT Time Tag Counter Low (page 136)
58
59
60
61
62
63
64
65
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
0x0040
0x0041
MT
MT
MT
MT
MT
MT
MT
MT
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
SMT Time Tag Counter Mid (page 107)
IMT Time Tag Counter Mid (page 136)
SMT Time Tag Counter High (page 107)
IMT Time Tag Counter High (page 136)
SMTTimeTag Utility Register Low (count load or capture) (page 108)
IMT Time Tag Utility Register Low (count load or capture) (page 136)
SMTTime Tag Utility Register Mid (count load or capture) (page 108)
IMT Time Tag Utility Register Mid (count load or capture) (page 137)
SMTTimeTagUtilityRegisterHigh(countloadorcapture)(page108)
IMTTime Tag Utility Register High (count load or capture) (page 137)
SMTTimeTagMatchRegisterLow(countmatchinterrupt)(page109)
IMTTimeTag Match Register Low (count match interrupt) (page 137)
SMTTimeTagMatchRegisterMid(countmatchinterrupt)(page109)
IMTTime Tag Match Register Mid (count match interrupt) (page 137)
SMT Time Tag Match Register High (count match interrupt) (page
109)
66
0x0042
MT
0x0000
IMTTimeTagMatchRegisterHigh(countmatchinterrupt)(page138)
67
68
69
70
71
72
73
0x0043
0x0044
0x0045
0x0046
0x0047
0x0048
0x0049
BC
BC
BC
BC
BC
BC
RT1
BC Time Tag Counter Low (page 87)
0x0000
0x0000
BC Time Tag Counter High (page 87)
BC Time Tag Utility Register Low (count load or capture) (page 88) 0x0000
BC Time Tag Utility Register High (count load or capture) (page 88) 0x0000
BC Time Tag Match Register Low (count match interrupt) (page 88) 0x0000
BC Time Tag Match Register High (count match interrupt) (page 88) 0x0000
RT1 Time Tag Counter (page 155)
0x0000
0x0000
0x0000
RT1 Time Tag Utility Register (count load / count match interrupt)
(page 156)
74
75
0x004A
0x004B
RT1
RT2
RT2 Time Tag Counter (page 155)
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27
HI-6130, HI-6131
Hard
Reset
Default
Register
Number
Hex
Address
Used By Register Name
RT2 Time Tag Utility Register (count load / count match interrupt)
(page 156)
76
0x004C
RT2
0x0000
77
78
79
80
0x004D
0x004E
0x004F
0x0050
Test
----
Factory Test Control Register
0x0000
0x0000
0x0000
0x0000
Checksum Fail Address & EEPROM Lock/Unlock
BC Last Message Block Address
BC
BC
Default location for BC WMI address pointer
Self-Test Control Register (when TEST input pin is logic 1) (see
40*
31*
2*
0x0028
0x001F
0x0002
0x001B
Self-Test page 226). When TEST pin is logic 0, this address is an RT2
register.
0x0000
Loopback Test Transmit Data Register (when TEST input pin is
Self-Test logic 1) (see page 230). When TEST pin is logic 0, this address is 0x0000
an RT1 register.
Loopback Test Receive Data Register (when TEST input pin is
Self-Test logic 1) (see page 230). When TEST pin is logic 0, this address is 0x0000
an RT1 register.
RAM Self-Test Fail Address Register (when TEST input pin is logic
Self-Test 1) (see “RAM Self-Test Fail Address Register (0x001B)” on page 0x0000
230). When TEST pin is logic 0, this address is an RT2 register.
27*
Memory Test Fail Address Register (when AUTOEN input pin is
logic 1) (see page 221). This is the first RAM / register address
with data mismatch (see Section 23.1 on page 218). Once
execution starts, register address 0x0024 is an RT2 register.
36**
0x0024
Auto-Init.
0x0000
* Alternate function for these registers when TEST pin is logic 1.
** Alternate function after reset when AUTOEN pin is logic .
Register descriptions are grouped by function: Bus Controller, Bus Monitor, Remote Terminal. Here is the presentation
order:
1. Registers used by all device functions (configuration, status and time tag registers),
2. Bus Controller registers,
3. Bus Controller configuration and operation,
4. Bus Monitor registers,
5. Bus Monitor configuration and operation,
6. Remote Terminal registers,
7. Remote Terminal configuration and operation
HOLT INTEGRATED CIRCUITS
28
HI-6130, HI-6131
9. REGISTERS USED BY ALL DEVICE FUNCTIONS
9.1. Master Configuration Register (0x0000)
TXINH
T
A
XINH
B
B
CSTBRCTENMAAPSMEALP1SSESLR08 RT2ENRAT1ERNTA2SRTETX1SBTESXDTIXNOTSEIML TAReserved
MTENA
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
All bits in this 16-bit register are read-write and are fully maintained by the host. This register is cleared after MR pin
master reset, and is unaffected by assertion of the MTRESET, RT1RESET or RT2RESET bits in the Master Status
and Reset Register (0x0001).
Bit No. Mnemonic
R/W Reset Function
Transmit Inhibit Bus A.
This bit is logically ORed with the TXINHA input pin. This register bit and
the corresponding TXINHA pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus A.
15
14
TXINHA
TXINHB
R/W
0
Transmit Inhibit Bus B.
This bit is logically ORed with the TXINHB input pin. This register bit and
the corresponding TXINHB pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus B.
R/W
0
Bus Controller Start.
If the BCENA input pin and BCENA register bit are both logic 1, a host
write which sets this bit to 1 begins Bus Controller operation. When
written to 1, this bit self-resets to 0. This bit always reads back at logic 0
state.
13
BCSTRT
R/W
0
Bus Controller Enable.
This bit is logically ANDed with the BCENA input pin. If either the input
pin or this register bit is logic 0, Bus Controller operation is disabled. The
BCENA input pin should be connected to ground in applications not using
BC mode. This bit cannot be set if BCENA input pin = 0.
12
BCENA
R/W
0
When the BCENA pin and BCENA register bit are both logic 1, the Bus
Controller device is enabled, but BC operation does not begin until
BCSTRT bit 13 is set. If this register bit or the BCENA input pin becomes
logic 0 while BC operation is underway, BC operation is immediately
terminated without waiting for message completion.
HOLT INTEGRATED CIRCUITS
29
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
MAP (Memory Address Pointer) Select.
This 2-bit field only applies to the HI-6131 with SPI host interface. The
host SPI relies on a hardware memory address pointer for many SPI
register or RAM accesses. This 2-bit field specifies which MAP is active
for SPI transactions:
Register Bit
11-10
Active Map
MAP Register
Address
Enabling SPI
Op Code
0-0
0-1
1-0
1-1
MAP1
MAP2
MAP3
MAP4
0x000B
0x000C
0x000D
0x000E
0xD8
0xD9
0xDA
0xDB
MAPSEL1:0
(HI-6131
11 − 10
R/W
0
The full 16-bit register can be directly written by the host using SPI op
code 0x10, followed by 16-bit data word. An alternative method uses SPI
op codes 0xD8 – 0xDA that write just the 2-bit MAPSEL field, without
affecting other register data. These four SPI op codes only require
transmission of an 8-bit instruction, without accompanying data.
only)
Note: “Fast access” SPI op codes contain embedded register addresses
and use a separate memory address pointer. This preserves values
contained in MAP1 through MAP4. The “fast access MAP” cannot be
read by the host but is written each time a “fast access” op code is
processed. Fast Access op codes are provided for these SPI operations:
•
•
SPI reads to register addresses 0 through 0x000F (decimal 15)
SPI writes to register addresses 0 through 0x003F (decimal 63)
Single-Strobe Read for 8-Bit Parallel Bus.
This option only applies to HI-6130 devices with host parallel bus
interface configured for 8-bit bus width. When performing 2-byte memory
read accesses, some microprocessors with 8-bit bus assert separate
Read_Enable (or STROBE) pulses for high and low bytes. Other
microprocessors assert a single, wider Read_Enable (or STROBE)
pulse, while simply changing the low address bit (A0 / LB) to access the
two bytes. For this last case, the SSRD8 bit should be set when writing
device configuration, before the first register or RAM read access is
performed.
SSR8
(HI-6130
only)
9
R/W
0
Bus Monitor Enable.
This bit is logically ANDed with the MTRUN input pin. If input pin or
register bit equals logic 0, Bus Monitor operation is disabled. The
MTRUN input pin should be connected to ground in applications not
using monitor mode.
When the MTRUN pin and MTENA register bit are both logic 1, the
Bus Monitor is enabled, Operation commences when the receiver
first decodes MIL-STD-1553 activity meeting the “start record” criteria
selected by bits 6:5 in the MT Configuration Register. If monitor operation
is underway when the MTENA register bit or MTRUN input pin becomes
logic 0, monitor operation stops after completion of any message already
underway; monitor resumes when the MTENA register bit and MTRUN
input pin are both logic 1.
8
MTENA
R/W
0
HOLT INTEGRATED CIRCUITS
30
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Remote Terminal 2 Enable.
This bit is logically ANDed with the RT2ENA input pin. If input pin or
register bit equals logic 0, RT2 operation is disabled. The RT2ENA input
pin should be connected to ground in applications not using Remote
Terminal 2. This bit cannot be set if RT2ENA input pin = 0.
7
RT2ENA
R/W
0
When the register bit and RT2ENA input pin are both logic 1, Remote
Terminal 2 is enabled, but operation is controlled by the state of the
RT2STEX register bit.
Remote Terminal 1 Enable.
This bit is logically ANDed with the RT1ENA input pin. If input pin or
register bit equals logic 0, RT1 operation is disabled. The RT1ENA input
pin should be connected to ground in applications not using Remote
Terminal 1. This bit cannot be set if RT1ENA input pin = 0.
6
RT1ENA
R/W
0
When the register bit and RT1ENA input pin are both logic 1, Remote
Terminal 1 is enabled, but operation is controlled by the state of the
RT1STEX register bit.
Remote Terminal 2 Start Execution.
If register bit 7 and the RT2ENA input pin are both logic 1, setting this bit
begins Remote Terminal 2 operation. Once running, resetting this bit (or
the RT2ENA register bit or RT2ENA input pin) immediately stops RT2
operation.
5
4
RT2STEX
RT1STEX
R/W
R/W
0
0
Remote Terminal 1 Start Execution.
If register bit 6 and the RT1ENA input pin are both logic 1, setting this bit
begins Remote Terminal 1 operation. Once running, resetting this bit (or
the RT1ENA register bit or RT1ENA input pin) immediately stops RT1
operation.
HOLT INTEGRATED CIRCUITS
31
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Bus Shutdown Transmit Only.
The bit only applies when Remote Terminal RT1 and/or RT2 is enabled.
The BSDTXO bit determines how a 1553 bus inhibit works when (a) the
RTxINHA or RTxINHB bit is set in the RT Configuration Register, or (b)
the RT receives a valid “bus shutdown” mode code command, either
MC4 or MC21:
•
When the BSDTXO bit is reset, logic 1 for an RTxINHAor RTxINHB bit
in a RT Configuration Register (or a “bus shutdown” mode command
with auto shutdown enabled) inhibits both transmit and receive on
the selected bus.
•
When the BSDTXO bit is set, logic 1 for an RTxINHA or RTxINHB bit
in a RT Configuration Register (or a “bus shutdown” mode command
with auto shutdown enabled) inhibits transmit only on the selected
bus; but receive functions are unaffected. Valid commands are
heeded, but the RT transmits no responses. NOT RECOMMENDED.
The HI-613x RT1 and RT2 automatically fulfill unconditional MC4 “bus
shutdown” in accordance with the BSDTXO setting, as well as MC5
“override bus shutdown.”
3
BSDTXO
R/W
0
The AUTOBSD bit in the RT Configuration Register determines whether
conditional MC20 “selected bus shutdown” and MC21 “override selected
bus shutdown” are fulfilled automatically, or by host writes to the
RTxINHA or RTxINHB bits in the appropriate RT Configuration Register:
•
•
When the AUTOBSD bit is logic 0 in the RT1 or RT2 Configuration
Register, automatic fulfillment is disabled for MC20 “selected
bus shutdown” and MC21 “override selected bus shutdown” mode
commands. The host fulfills bus shutdown and override by writing
the RTxINHA and RTxINHB bits in the appropriate RT Configuration
Register.
When the AUTOBSD bit is logic 1 in the RT1 or RT2 Configuration
Register, automatic fulfillment is enabled for MC20 “selected
bus shutdown” and MC21 “override selected bus shutdown” mode
commands. When the received mode data word matches the value
stored in the RT “Bus A (or B) Select” register, the RT automatically
fulfills MC20 “selected bus shutdown” in accordance with the
BSDTXO setting, as well as MC21 “override selected bus shutdown”.
Auto-shutdown bypasses the RTxINHA and RTxINHB bits in the RT
Configuration Register, but the upper 4 bits in the RT’s BIT Word
register indicate Tx and Rx bus shutdown status.
IRQ Output Type Select.
When this bit is 0, the IRQ (interrupt request) output generates a 1µs
negative pulse when enabled interrupt events occur. When this bit is
logic 1, the IRQ output consists of a continuous low level output requiring
host action to negate IRQ to the high state. When level interrupts are
enabled, the host negates IRQ by asserting the ACKIRQ input pin for at
least 250ns.
2
INTSEL
R/W
0
HOLT INTEGRATED CIRCUITS
32
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Indicate MT Activity.
When this bit equals 0, the ACTIVE status output is not asserted for Bus
Monitor activity, unless the monitored message involves another on-
chip terminal). When this bit equals 1, enabled Bus Monitor activity is
logically-ORed with the activity of the other on-chip devices to determine
ACTIVE status; the ACTIVE output is asserted during such Bus Monitor
activity, whether or not the monitored message involves another on-chip
terminal.
1
0
IMTA
R/W
0
-
Reserved
-
This bit is not used and reads logic 0.
9.2. Master Status and Reset Register (0x0001)
ReserAveUdTOMETNRERSTE2TRRETS1ERTBECSMETIPBCACMTTIVMEIMPTPIPRT1MRIPT1MRIPT2INRHT1INEHECKREAMIF
READY
0
0
0
0
0
0
0
0
0
0
0
R
5
0
0
0
0
0
MR Reset
Host Access
Bit
R
RW
15 14 13 12 11 10
9
8
7
6
4
3
2
1
0
This 16-bit register has a combination of read only and read-write bits. This register is cleared after MR pin master
reset, but is unaffected by assertion of MTRESET, RT1RESET or RT2RESET register bits.
Bit No. Mnemonic
R/W
Reset Function
The READY output pin reflects the state of this register bit. READY
is low when auto-initialization, a soft reset caused by bit 12~10
assertion, or built-in test is underway. Host access to device registers
or RAM is locked out while READY is low. While READY = 0, any host
read access returns the value in this register, regardless of address
provided. When READY goes high, the host may access registers and
RAM.
15
READY
R
0
14
13
Reserved
AUTOEN
R
R
0
0
This bit is not used.
Auto-Initialization Enable Status.
This bit reflects the state of the AUTOEN input pin that applied at the
rising edge on the MR Master Reset input pin. If the register bit is high,
auto-initialization was performed following MR reset.
Bus Monitor Reset.
When written to logic 1, this bit initiates Bus Monitor reset. This bit
remains high until reset is complete. While this bit remains high, the
READY output pin and register bit 15 are held low, host RAM and
register access is suspended. While READY = 0, any host read access
returns the value in this register, regardless of address provided. Upon
reset completion, this bit self-clears to logic 0, the READY pin goes
high and host read/write access is restored.
12
MTRESET
R/W
0
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HI-6130, HI-6131
Bit No. Mnemonic
R/W
Reset Function
Remote Terminal 2 Reset.
When written to logic 1, this bit initiates RT2 reset by clearing the STEX
Start Execution bit in the RT2 Configuration Register, then performing
the RT soft reset actions described in Section 23. This bit remains high
until reset is complete. While this bit remains high, the READY output
pin and register bit 15 are held low, host RAM and register access is
suspended. While READY = 0, any host read access returns the value
in this register, regardless of address provided. Upon reset completion,
this bit self-clears to logic 0, the READY pin goes high and host read/
write access is restored.
11
RT2RESET R/W
0
Remote Terminal 1 Reset.
When written to logic 1, this bit initiates RT1 reset by clearing the STEX
Start Execution bit in the RT1 Configuration Register, then performing
the RT soft reset actions described in Section 23. This bit remains high
until reset is complete. While this bit remains high, the READY output
pin and register bit 15 are held low, host RAM and register access is
suspended. While READY = 0, any host read access returns the value
in this register, regardless of address provided. Upon reset completion,
this bit self-clears to logic 0, the READY pin goes high and host read/
write access is restored.
10
RT1RESET R/W
0
BC Message in Process.
This bit is high when the BC is processing a MIL-STD-1553 message.
Falling edge occurs at message completion, after register and RAM
buffer updates.
9
8
BCMIP
R
R
0
0
BC Active.
This bit is high when the BC is enabled and running. It will read logic
1 during MIL-STD-1553 message processing and during programmed
delays.
BCACTIVE
Bus Monitor Message in Process.
7
6
5
4
MTMIP
MTPIP
R
R
R
R
0
0
0
0
This bit is set when a valid MIL-STD-1553 command is decoded, and is
reset upon monitored message completion.
Bus Monitor Packet in Process.
This bit is set at start of a data packet and is reset when the packet is
deemed complete.
Remote Terminal 2 Message in Process.
RT2MIP
RT1MIP
This bit is set when a valid MIL-STD-1553 command is decoded for
RT2, and is reset upon message completion.
Remote Terminal 1 Message in Process.
This bit is set when a valid MIL-STD-1553 command is decoded for
RT1, and is reset upon message completion.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W
Reset Function
Remote Terminal 2 Bus Inhibited.
This bit is high when one bus is inhibited for RT2 due to execution of a
“bus shutdown” mode code command. The shut-down bus is identified
in the RT2 BIT (built-in test) Word Register. Shut-down can be ended
by “bus shutdown override” mode code command, MR reset or setting
the RT2RESET bit in this register.
3
2
RT2INH
RT1INH
R
0
0
Remote Terminal 1 Bus Inhibited.
This bit is high when one bus is inhibited for RT1 due to execution of a
“bus shutdown” mode code command. The shut-down bus is identified
in the RT1 BIT (built-in test) Word Register. Shut-down can be ended
by “bus shutdown override” mode code command, MR reset or setting
the RT1RESET bit in this register.
R
EEPROM Checksum Error.
This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as RT or MT soft reset with auto-initialization.
The EECKE bit is set (as well as bit 14 in the Hardware Pending
Interrupt Register, 0x0006) when a serial EEPROM checksum failure
occurs. Such failure may occur during full auto-initialization after MR
master reset, or during execution of a partial, terminal-specific reset
after assertion of the RT1RESET, RT2RESET or MTRESET bits in this
register.
1
EECKE
R
0
RAM Initialization Fail Interrupt.
This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as terminal-specific partial auto-initialization
during RT or MT soft reset.
The RAMIF bit is set (as well as bit 13 in the Hardware Pending
Interrupt Register, 0x0006) when one or more initialized RAM locations
do not match their two corresponding serial EEPROM byte locations.
Such failure may occur during full auto-initialization after MR master
reset, or during execution of a partial, terminal-specific reset after
assertion of the RT1RESET, RT2RESET or MTRESET bits in this
register.
0
RAMIF
R
0
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
9.3. Overview of Interrupts
For interrupt management, the host accesses up to thirteen HI-613x registers and a 64-word circular Interrupt Log
Buffer in RAM. The log buffer and the Interrupt Count & Log Address Register are utilized in any system design
involving interrupts. In addition, there are four 3-register groups, identified by terminal function. One 3-register group
is for Hardware interrupts; this register triplet is active in every HI-613x design. Other 3-register groups are only active
when the corresponding terminal functions are enabled; these are the interrupt register triplets used for Bus Controller,
Bus Monitor and Remote Terminal interrupts. The Remote Terminal interrupt register triplet is shared by RT1 and RT2.
Each interrupt register triplet for BC, SMT or IMT, RT or Hardware consists of
•
•
•
An Interrupt Enable Register to enable and disable interrupt recognition
A Pending Interrupt Register to capture the occurrence of enabled interrupts
An Interrupt Output Enable Register selectively enables IRQ output to host when enabled interrupts occur
Within each register triplet, corresponding register bits are mapped to the same interrupt-causing event. Initialize the
Interrupt Enable Register to select interrupt-causing events heeded by the HI-613x; most applications utilize just a
subset of the available interrupt options. Interrupt-causing events are ignored if their corresponding bits are reset in
the Interrupt Enable Register. Setting an Interrupt Enable register bit from 0 to 1 does not trigger interrupt recognition
for events that occurred while the bit was zero.
The next datasheet sections describes interrupt features active in all HI-613x projects, namely the Interrupt Log Buffer,
the Interrupt Count & Log Address Register and the Hardware Interrupt register triplet.
9.4. Hardware Interrupt Behavior
Behavior described here for Hardware Interrupts closely resembles the behavior for the BC, RT and SMT or IMT
interrupt register triplets, described later in the four corresponding sections of this datasheet.
When an enabled hardware interrupt event occurs, the Interrupt Log Buffer is updated and a bit is set in the Hardware
Pending Interrupt Register. This action takes place only if the bit for the interrupt-causing event was already set in the
Hardware Interrupt Enable Register. The host can poll the Hardware Pending Interrupt Register to detect occurrence
of hardware interrupts, indicated by non-zero value. When the host reads the Hardware Pending Interrupt Register,
it automatically clears to 0x0000.
When an enabled hardware interrupt event occurs, if the corresponding bit is also set in the Hardware Interrupt Output
Enable Register, the IRQ output is asserted to alert the host. Thus, the Hardware Interrupt Output Enable Register
establishes two interrupt priority levels for hardware events: high priority interrupts generate an IRQ signal output,
while low priority interrupts do not. The host detects low priority interrupts by polling the Hardware Pending Interrupt
Register.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the Hardware,
BC, RT or MT Interrupt Output Enable registers. Multiple interrupt-causing events can occur simultaneously, so each
IRQ output assertion can result from one or more interrupt conditions.
When the host receives an IRQ signal from the device, it identifies the event (or events) that triggered the interrupt.
The host has two options: (a) go to the Interrupt Log Buffer (using the method described in sections 9.5 and 9.6), or (b)
use a hardware-assisted scheme using the three low order bits in the Hardware Pending Interrupt Register to identify
new interrupt(s).
For the second method, the host reads the Hardware Pending Interrupt Register. While bits 15-3 in this register identify
hardware interrupt conditions, the three low-order register bits indicate zero vs. non-zero status for the BC, RT and
MT Pending Interrupt Registers. If any of these bits is logic 1, the corresponding Pending Interrupt Register has one or
more interrupt flags set. Any combination of these three bits may be set, or all three bits may be zero, if only hardware
interrupt(s) occurred. When the host reads any of the four Pending Interrupt registers, the read access self-resets the
register to 0x0000. Thus, the host should retain the read value from the Hardware Pending Interrupt Register when
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
1 or more bits are non-zero in the bit 2-0 range. These bits indicate zero vs. non-zero status for the BC, RT and MT
Pending Interrupt Registers:
•
When bits 2-0 in the Hardware Pending Interrupt Register read 000, there are no new interrupts in the BC, RT
and MT Pending Interrupt Registers.
•
When BCIP (BC Interrupt Pending) bit 0 is set in the Hardware Pending Interrupt Register, the BC Pending In-
terrupt Register contains a nonzero value. The host can read the BC Pending Interrupt Register to identify the
specific bus controller interrupt event(s).
•
•
When MTIP (MT Interrupt Pending) bit 1 is set in the Hardware Pending Interrupt Register, the MT Pending Inter-
rupt Register contains a nonzero value. The host can read the MT Pending Interrupt Register (shared by SMT or
IMT) to identify the specific bus monitor interrupt event(s).
When RTIP (RT Interrupt Pending) bit 1 is set in the Hardware Pending Interrupt Register, the RT Pending Inter-
rupt Register contains a nonzero value. The host can read the RT Pending Interrupt Register to identify specific
RT1 or RT2 interrupt event(s).
When polling the Pending Interrupt registers to identify low priority interrupts that do not assert the IRQ output, the
same decoding method can be applied. A single read of the Hardware Pending Interrupt Register reveals zero vs.
Non-zero status of all four Pending Interrupt registers.
Alternately, the host can poll the Interrupt Count & Log Address Register to identify low priority interrupts that do not
assert the IRQ output. Bits 15:9 in this register contain a 7-bit count value indicating the number of interrupts logged
(0 - 127) since the Interrupt Count & Log Address Register was last read. Although the Interrupt Log Buffer only holds
data from the last 32 interrupts, register bits 15:9 count beyond 32 for buffer overrun detection. Counting stops at 127.
Register bits 15:9 are reset automatically when the host reads the Interrupt Count & Log Address Register.
9.5. Interrupt Count & Log Address Register (0x000A)
MSB Interrupt Count
MSB Interrupt Log Address
0
0
0
0
0
0
0
9
1
1
0
0
0
0
0
0
1
0
0
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
8
7
6
5
4
3
2
This 16-bit register is read-only and is fully maintained by HI-613x logic. The register contains 0x0180 after MR pin
master reset. It is not affected by assertion of MTRESET, RT1RESET or RT2RESET bits in the Master Status and
Reset Register (0x0001).
The value in Interrupt Log Address register bits 8:0 is a 9-bit address pointer to the circular 64-word Interrupt Log
Buffer, located in RAM. Register bits 8:6 are always 1-1-0 so the 9-bit address pointer ranges from 0x0180 to 0x019E.
This pointer indicates the storage address for two information words that will be stored for the next-occurring interrupt.
The value is always even since two words are stored for each interrupt.
Upper register bits 15:9 contain a 7-bit count value for the number of interrupts logged (0 - 127) since the Interrupt
Count & Log Address Register was last read. Although the circular Interrupt Log Buffer only retains data from the last
32 interrupts, counting continues beyond 32 so the host can detect circular buffer overrun. Bits 15:9 stop incrementing
at full count (127 interrupts) and automatically reset to zero when the host reads this register.
After MR master reset, the HI-613x initializes this register to 0x0180, an interrupt count of zero and Interrupt Log Buffer
address of 0x180. After reset, the first interrupt stores words at buffer addresses 0x0180 and 0x0181. Subsequent
interrupts store word pairs at sequential addresses. Information words for the 32nd interrupt are stored in last two
buffer addresses 0x01BE and 0x01BF, and the Interrupt Log Address “rolls over” to read 0x0180, where interrupt
information for the 33rd post-reset interrupt will be stored.
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HI-6130, HI-6131
9.6. Interrupt Log Buffer
Shown in Figure 15, the Interrupt Log Buffer is a circular 64-word buffer in RAM, residing at address range 0x0180 to
0x01BF. Device logic stores two information words in the buffer for each enabled interrupt that occurs, so buffer size
dictates storage for up to 32 interrupt events. After the 32nd, 64th, 96th,... interrupt occurs, the buffer address pointer
(bits 8:0 in register 0x000A) “wraps around” to buffer start address 0x0180 and subsequent interrupts overwrite previ-
ously stored interrupt information.
HI-613x interrupt logic stores two words in the Interrupt Log Buffer for each enabled interrupt that occurs: an Interrupt
Identification Word and an Interrupt Address Word. The Interrupt Identification Word (IIW) identifies the occurring inter-
rupt type using a word format identical to the applicable Pending Interrupt Register. More than one bit may be asserted
in an Interrupt Identification Word. For example, IBR (interrupt broadcast received) and MERR (interrupt message
error) can occur for the same RT message. One assertion of the INT output pin alerts the host when concurrent mes-
sage interrupts occur.
The log buffer Interrupt Address Word varies, depending on the interrupt type. Hardware interrupts are not directly
linked with command or message processing. Hardware interrupts write an Interrupt Address Word value of 0x0000.
For BC, SMT or IMT interrupts, the Interrupt Address Word (IAW) identifies the message in which the interrupt oc-
curred. For RT interrupts, the Interrupt Address Word (IAW) identifies the Command Word for the message in which
the interrupt occurred:
Interrupt Type
Interrupt Identification Word (IIW)
Interrupt Address Word (IAW)
Matches format of Hardware Pending
Interrupt Register 0x0006 on page 40
Hardware
Always 0x0000
A BC Control/Status Block address, points to the
Block Status Word of the message in which interrupt
occurred
Bus Controller
(BC)
Matches format of the BC Pending
Interrupt Register 0x0007 on page 90
An SMT Command Buffer address, points to the
Block Status Word of the message in which interrupt
occurred
Simple Bus
Monitor (SMT)
Matches the format of the SMT Pending
Interrupt Register 0x0008 on page 111
An IMT integrated Data Buffer address, points to the
Block Status Word of the message in which interrupt
occurred
IRIG-106 Bus
Monitor (IMT)
Matches the format of the IMT Pending
Interrupt Register 0x0008 on page 140
RT1 or RT2 Descriptor Table address pointing to the
Command Word of the message in which interrupt
occurred
Remote Terminal Matches format of RT1 / RT2 Pending
RT1 and/or RT2 Interrupt Register 0x0009 on page 158
For a given terminal (BC, SMT, IMT or RT1/RT2) multiple interrupts can be enabled, and two or more interrupts can
occur in a single message. There will be a single 2-word Log Buffer update and the Interrupt Information Word will have
one bit set for each occurring interrupt. Simultaneous interrupts for one terminal (having interrupt output enabled) are
logically-ORed, resulting in a single assertion of the IRQ output to the host.
When operating with two or more enabled terminal devices (BC, SMT, IMT or RT1/RT2), simultaneous interrupts
can occur in the same message for multiple terminals. Each terminal device with occurring interrupt(s) will have its
own 2-word Log Buffer update. Simultaneous interrupts for multiple terminals (having interrupt output enabled) are
logically-ORed, resulting in a single assertion of the IRQ output to the host.
In later data sheet sections, definitions are provided for interrupt register triplets used by the BC (bus controller), SMT
(simple monitor terminal), IMT (IRIG-106 monitor terminal) and RT (remote terminal).
HOLT INTEGRATED CIRCUITS
38
HI-6130, HI-6131
INTERRUPT 32
INTERRUPT 32
Interrupt Address Word
0x01BF
0x01BE
0x01BD
0x01BC
0x01BB
0x01BA
0x01B9
0x01B8
0x01B7
0x01B6
0x01B5
0x01B4
The Interrupt Log Address Register
points to this address after Interrupt
31 event occurs. Upon Interrupt 32
completion, device logic reinitializes
the log address pointer to 0x0180
before Interrupt 33 is processed.
Interrupt Information Word
Interrupt Address Word
INTERRUPT 31
INTERRUPT 31
INTERRUPT 30
INTERRUPT 30
INTERRUPT 29
INTERRUPT 29
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
INTERRUPT 28
INTERRUPT 28
INTERRUPT 27
INTERRUPT 27
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
.
.
.
.
.
.
.
.
INTERRUPT 6
INTERRUPT 6
INTERRUPT 5
INTERRUPT 5
INTERRUPT 4
INTERRUPT 4
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
0x018B
0x018A
0x0189
0x0188
0x0187
0x0186
0x0185
0x0184
0x0183
0x0182
0x0181
0x0180
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
INTERRUPT 3
INTERRUPT 3
INTERRUPT 2
INTERRUPT 2
INTERRUPT 1
INTERRUPT 1
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Log Address Register
is initialized by device logic to
point to this address after
Interrupt Information Word
hardware reset (MR) or software reset
Figure 3. Fixed Address Mapping for Interrupt Log Buffer
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
9.7. Hardware Interrupt Registers
9.7.1. Hardware Interrupt Enable Register (0x000F)
EECKREA/MRIAFM/ EURNRCRE RT2APRFT1APF
HSPIINT LBFA
LBFBMTTTBRCOTTRTO2TRTMT1TTMMTTTBMCTT ReserRveedserRveedserved
M
MR Reset
Host Access
Bit
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
RW
9
R
2
* Bits 4 - 0 are read-only and cannot be modified by host.
15 14 13 12 11 10
8
7
6
5
4
3
1
0
9.7.2. Hardware Pending Interrupt Register (0x0006)
EECKREA/MRIAFM/ EURNRCRE
HSPIINT LBFA RT2APRFT1APF
LBFBMTTTBRCOTTRTO2TRTMT1TTMMTTTBMCTT RTIP MTIP BCIP
M
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
9
R *
1
* Bits 2 - 0 are set for pending interrupts
from RT (RT1 or RT2), MT or BC
15 14 13 12 11 10
8
7
6
5
4
3
2
0
9.7.3. Hardware Interrupt Output Enable Register (0x0013)
EECKREA/MRIAFM/ EURNRCRE RT2APRFT1APF
HSPIINT LBFA
LBFBMTTTBRCOTTRTO2TRTMT1TTMMTTTBMCTT ReserRveedserRveedserved
M
MR Reset
Host Access
Bit
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
RW
9
R
1
* Bits 2 - 0 are read-only and cannot be set by host.
15 14 13 12 11 10
8
7
6
5
4
3
2
0
These three registers govern hardware interrupt behavior.As explained on the preceding page, bits 2-0 in the Hardware
Pending Interrupt Register are set whenever interrupt bits are set in the other three pending interrupt registers (RT,
MT and BC). The table below first describes the common bits 15-3 in all three registers and then describes register-
to-register differences for bits 2-0.
Bit No. Mnemonic
R/W Reset Function
Host SPI Interrupt.
This bit only applies to HI-6131 with SPI host interface, which operates
in SPI Slave mode. An unexpected number of SCK clock pulses
occured during a SPI transaction.
15
HSPIINT
R/W
0
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
EEPROM Checksum Error Interrupt.
This function only applies when the RAMEDC input pin is logic 0 and
the AUTOEN input pin is logic 1 at rising edge of MR Master Reset. This
enables auto-initialization from serial EEPROM, as well as RT or MT soft
reset with auto-initialization. This bit is logic 1 in the Hardware Interrupt
Enable Register and in the Hardware Interrupt Output Enable Register
after MR master reset.
The EECKE bit is set in the Hardware Pending Interrupt Register (as
well as bit 1 in the Master Status and Reset Register, 0x0001) when
a serial EEPROM checksum failure occurs during auto initialization,
or execution of a partial reset caused by assertion of the RT1RESET,
RT2RESET or MTRESET bits in the Master Status and Reset Register,
0x0001.
EECKE
Register bit 14 has a secondary function when input pin RAMEDC is
connected to logic 1. When the RAMEDC pin is high, the available
RAM address space is reduced from 32K words to 24K words, but error
detection and correction (EDC) is performed after every RAM address
read cycle.
14
R/W
1
Detected and Corrected 24K RAM Error.
This function only applies when the device RAMEDC input pin is
connected high, configuring the device for 24K RAM with EDC enabled.
Single-bit errors are automatically corrected by the device, but multiple-
bit errors are not correctable.
When a single-bit RAM data error is detected and corrected, register bit
14 is set to logic 1. The EECKE bit 1 in register 0x0001 is also cleared.
RAMERR
When bit 14 is asserted in the Hardware Pending Interrupt Register
0x0009, the host can distinguish an EECKE interrupt from a RAMERR
interrupt by reading the Master Status and Reset Register 0x0001.
EECKE bit 1 in that register will be logic 1 for EECKE interrupt, logic 0
for CRAMERR interrupt.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
RAM Initialization Fail Interrupt.
This function only applies when the RAMEDC input pin is logic 0 and
the AUTOEN input pin is logic 1 at rising edge of MR Master Reset. This
enables auto-initialization from serial EEPROM, as well as RT or MT soft
reset with auto-initialization. This bit is logic 1 in the Hardware Interrupt
Enable Register and in the Hardware Interrupt Output Enable Register
after MR master reset.
The RAMIF bit is set in the Hardware Pending Interrupt Register (as well
as bit 0 in the Master Status and Reset Register, 0x0001) when one or
more initialized RAM locations do not match their two corresponding
serial EEPROM byte locations. Such failure occurs during auto
initialization, or execution of a partial reset caused by assertion of the
RT1RESET, RT2RESET or MTRESET bits in the Master Status and
Reset Register, 0x0001.
RAMIF
Register bit 14 has a secondary function when input pin RAMEDC is
connected to logic 1. When the RAMEDC pin is high, the available
RAM address space is reduced from 32K words to 24K words, but error
detection and correction (EDC) is performed after every RAM address
read cycle.
13
R/W
1
Uncorrected 24K RAM Error.
This function only applies when the device RAMEDC input pin is
connected high, configuring the device for 24K RAM with EDC enabled.
The device automatically corrects single-bit errors, but multiple-bit errors
are not correctable.
When an uncorrectable RAM data error is detected, register bit 13 is set
to logic 1. The RAMIF bit 1 in register 0x0001 is also cleared.
UNCRE
When bit 13 is asserted in the Hardware Pending Interrupt Register
0x0009, the host can distinguish a RAMIF interrupt from a UNCRE
interrupt by reading the Master Status and Reset Register 0x0001.
RAMIF bit 1 in that register will be logic 1 for RAMIF interrupt, logic 0 for
UNCRE interrupt.
Loopback Fail Bus A Interrupt (LBFA)
Loopback Fail Bus B Interrupt (LBFB)
For all transmitted words, the device checks MIL-STD-1553 word validity
for the subsequently received/decoded word detected on the bus. This
includes sync, encoding, bit count and parity checking. The last word
in each message transmitted by the device is also checked for data
matching.
12
11
LBFA
LBFB
R/W
0
The LBFA bit is set each time loop-back detects an invalid or
mismatched word on Bus A. The LBFB bit is set each time loop-back
detects an invalid or mismatched word on Bus B.
MT Time Tag Counter Rollover.
The Bus Monitor time tag counter rolled over from full count to zero.
Depending on options selected in the Time Tag Configuration Register,
the MT time count may be either 16 or 48 bits.
10
MTTTRO
R/W
0
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
BC Time Tag Counter Rollover.
The Bus Controller time tag counter rolled over from full count to zero.
Depending on options selected in the Time Tag Configuration Register,
the BC time count may be either 16 or 32 bits.
9
8
7
BCTTRO
RT2TTM
RT1TTM
R/W
R/W
R/W
0
0
0
RT2 Time Tag Match.
The 16-bit Remote Terminal 2 time tag counter incremented to a count
matching the contained value in the RT2 Time Tag Reload / Match
Register.
RT1 Time Tag Match.
The 16-bit Remote Terminal 1 time tag counter incremented to a count
matching the contained value in the RT1 Time Tag Reload / Match
Register.
MT Time Tag Match.
6
5
MTTTM
BCTTM
R/W
R/W
0
0
The Bus Monitor time tag counter incremented to a count matching the
contained value in the MT Time Tag Match Registers.
BC Time Tag Match.
The Bus Controller time tag counter incremented to a count matching
the contained value in the BC Time Tag Match Register(s).
RT2 Terminal Address Parity Fail Interrupt.
The Remote Terminal address and parity bits (latched into the RT2
Operational Status Register at rising edge of MR) do not exhibit odd par-
ity (do not have an odd number of bits having logic 1 state). Note: RT2
address parity is only checked if the RT2ENA pin is logic 1 at rising edge
of MR.
4
3
RT2APF
RT1APF
R/W
R/W
1
1
RT1 Terminal Address Parity Fail Interrupt.
The Remote Terminal address and parity bits (latched into the RT1
Operational Status Register at rising edge of MR) do not exhibit odd
parity (do not have an odd number of bits having logic 1 state). Note:
RT1 address parity is only checked if the RT1ENA pin is logic 1 at rising
edge of MR.
For the Hardware Interrupt Enable Register and the Hardware Interrupt Output Enable Register only
2 − 0
Reserved
Bits 2-0 cannot be written and read back 000.
For the Hardware Pending Interrupt Register only
RT Interrupt Pending.
When this bit is high, one or more bits are set in the RT Pending
0
2
1
RTIP
R
R
Interrupt Register. The host can read that register (0x0009) to determine
the RT1 or RT2 interrupt event(s).
MT Interrupt Pending.
When this bit is high, one or more bits are set in the MT Pending
0
MTIP
Interrupt Register. The host can read that register (0x0008) to determine
the MT interrupt event(s).
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Bit No. Mnemonic
R/W Reset Function
BC Interrupt Pending.
When this bit is high, one or more bits are set in the BC Pending
Interrupt Register. The host can read that register (0x0007) to determine
the BC interrupt event(s).
0
BCIP
R
0
9.8. Time Tag Counter Configuration
Each device (RT1, RT2, BC or MT) has an independent time tag counter used for time-stamping messages. The
two remote terminals RT1 and RT2 have independent 16-bit time tag counters because each RT needs independent
count reset and “synchronization” loading. In the Time Tag Counter Configuration Register, bits 2-0 select the clock
source for both of the RT1 and RT2 time tag counters. The same clock source is shared by the Bus Controller. The
host controls the free-running RT1 and RT2 time tag counters using bit pairs 11-10 (RT2) or 9-8 (RT1) in the Time Tag
Counter Configuration Register. Here is a summary of host-initiated operations involving the RT time tag counters:
a. Clearing the 16-bit RT1 or RT2 time tag count to 0x0000.
b. Copying the RT1 or RT2 TT16 Time Tag Utility Register value into the 16-bit RT1 or RT2 time tag counter.
c. Copying the current 16-bit RT1 or RT2 time tag count value into the RT1 or RT2 TT16 Time Tag Utility Register.
The bus controller (BC) can operate using either a 16- or 32-bit time tag counter, selected using register bit 3, BCTT32,
in the Time Tag Counter Configuration Register. The BC time tag counter clock source is selected using register bits
2-0. This common clock source is shared by the BC, RT1 and RT2. Bit pair 13-12 is used for clearing BC time tag
counter, loading the counter with a 16- or 32-bit value contained in the BC Time Tag Reload Register, or writing the
current 16- or 32-bit BC time tag counter value to the BCMT Time Tag Utility Register set (shared by the BC and MT.)
The free-running BC time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be
captured. In 32-bit time tag mode, the full count is captured by simultaneously loading two utility registers. Writing bits
13-12 in the Time Tag Counter Configuration Register initiates these operations. Here is a summary of host-initiated
operations involving the BC time tag counter:
a. Clearing a 16- or 32-bit BC time tag count, whichever is enabled.
b. When 16-bit BC time tag count is enabled,
•
loading the 16-bit BC time tag counter with the 16-bit value contained in the BC TT16 Time Tag Utility
Register
•
capturing the current 16-bit BC time tag counter value to the BC TT16 Time Tag Utility Register
c. When 32-bit BC time tag count is enabled,
•
loading the 32-bit BC time tag counter with the 32-bit value contained in the BC TT32 Time Tag Utility
Register pair
•
capturing the current 32-bit BC time tag counter value to the BC TT32 Time Tag Utility Register pair
The bus monitor (MT) can operate using either a 16- or 48-bit time tag counter, selected using MT Configuration
Register bits 1-0. When using 16-bit resolution, one register is adequate for holding time tag values. When using 48-bit
time tag count resolution, three 16-bit registers are needed for each stored time tag count. The MT time tag counter
clock source is selected using bits 7-5 in the Time Tag Counter Configuration Register, 0x0039. The MT time tag clock
source is separate from the source shared by the BC, RT1 and RT2.
The free-running MT time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be
captured. In 48-bit time tag mode, the full count is captured by simultaneously loading three utility registers. Writing
bits 15-14 in the Time Tag Counter Configuration Register 0x0039 initiates these operations.
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Here is a summary of host-initiated operations involving the MT time tag counter:
a. Clearing a 16- or 48-bit MT time tag count, whichever is enabled.
b. When 16-bit MT time tag count is enabled,
•
loading the 16-bit MT time tag counter with the 16-bit value contained in the MT TT16 Time Tag Utility
Register
•
capturing the current 16-bit MT time tag counter value to the MT TT16 Time Tag Utility Register
c. When 48-bit MT time tag count is enabled,
•
loading the 48-bit MT time tag counter with the 48-bit value contained in the MT TT48 Time Tag Utility
Register triplet
•
capturing the current 48-bit MT time tag counter value to the MT TT48 Time Tag Utility Register triplet when
48-bit MT time tag count is enabled
Host interrupts can be generated when any of the four time tag counters in the device reach preset values contained
in Time Tag Match registers. Refer to the Section 9.3.
9.9. Time Tag Counter Configuration Register (0x0039)
MTTCK3
M BAC1TTRA0T1TRTAT1TTRAT01TRTAT1TTA0 MTTCMKT2TCMKT1TCBKC0TTT3T2CKT2TCKT1TCK0
MTTTA1TTTBAC0TT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
This 16-bit read-write register is cleared after MR pin master reset, but is unaffected by assertion of MTRESET,
RT1RESET or RT2RESET register bits.
When written, register bits 15-8 work in pairs to initiate a particular action, such as clearing or loading one of these
counters. When written, register bits 15-8 self reset to zero after initiating the assigned action. Thus, bits 15-8 always
read logic 0. Register bits 7-0 are used for configuring the various time tag counters in the HI-613x device. These
bits will read back the last value written by the host.
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Bit No. Mnemonic
R/W Reset Function
MT Time Tag Action Bits 1-0.
After performing the action below, these host-written bits self reset to
00:
Bits 15-14 Action
00
01
Do Nothing.
Reset 16- or 48-bit MT Time Tag count to zero.
Load the 16- or 48-bit value from BCMT Time Tag Utility
Register(s) into the MT Time Tag Count register(s).
10
11
15
14
MTTTA1
MTTTA0
R/W
0
Capture current 16- or 48-bit value in the MT Time
Tag Count Register(s) into the BCMT Time Tag Utility
Register(s).
If the MT is using 16-bit time tag, the MT Time Tag Counter uses a
single register address, 0x003A. The BCMT Time Tag Utility Register
used for the load and capture operations is register address 0x003D.
If the MT is using 48-bit time tag, the MT Time Tag Counter uses three
register addresses. The High-Mid-Low words are found at 0x003C,
0x003B and 0x003A. The triplet of BCMT Time Tag Utility Registers
used for the load and capture operations is located at register
addresses 0x003F (High), 0x003E (Mid) and 0x003D (Low).
Bit No. Mnemonic
R/W Reset Function
Bits 1-0 in the MT Configuration Register, 0x0029 select IRIG-106
monitor, IMT (always 48-bit time tag counting), or simple monitor, SMT,
(choice of 16-bit or 48-bit time tag counting):
MT Configuration
Register, bits 1-0
MT Operation
Time Tag Mode
48-bit time tag
16-bit time tag
48-bit time tag
IMT (IRIG-106)
monitor mode
00 or 10
15
14
MTTTA1
MTTTA0
R/W
0
SMT (simple)
monitor mode
01
11
(continued)
SMT (simple)
monitor mode
When the MT is operating in Simple mode with 48-bit time tag, the
recorded Command Buffer entry for each 1553 message has eight 16-
bit words. When operating with 16-bit time tag, the recorded Command
Buffer entry for each 1553 message has four 16-bit words.
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Bit No. Mnemonic
R/W Reset Function
BC Time Tag Action Bits 1-0.
After performing the action below, these host-written bits self reset to
00:
Bits 13-12 Action
00 or 11
01
Do Nothing.
Reset 16- or 32-bit BC Time Tag count to zero.
Load the 16- or 32-bit value from BCMT Time Tag Utility
Register(s) into the BC Time Tag Count register(s).
10
13
12
BCTTA1
BCTTA0
R/W
0
If BCTT32 register bit 3 equals 0, the BC is using 16-bit time tag. The
BC Time Tag Counter uses a single register address, 0x0043. The
BCMT Time Tag Utility Register used for these operations is register
address 0x003D.
If BCTT32 register bit 3 equals 1 the BC is using 32-bit time tagging,
so the BC Time Tag Counter requires two 16-bit register addresses.
The High and Low BC time tag counter words are found at 0x0044 and
0x0043. The pair of BCMT Time Tag Utility Registers used for timer
operations is located at register addresses 0x003E (High word) and
0x003D (Low word).
RT2 Time Tag Action Bits 1-0.
After performing the RT2 time tag counter action below, these host-
written bits self reset to 00:
Bits 11-10 Action
11
10
RT2TTA1
RT2TTA0
R/W
0
00 or 11
01
Do Nothing.
Reset 16-bit RT2 Time Tag count to zero.
Load the 16-bit value from the RT2 Time Tag Utility
Register(s) into the RT2 Time Tag Counter.
10
RT1 Time Tag Action Bits 1-0.
After performing the RT1 time tag counter action below, these host-
written bits self reset to 00:
Bits 9-8
00 or 11
01
Action
9
8
RT1TTA1
RT1TTA0
R/W
0
Do Nothing.
Reset 16-bit RT1 Time Tag count to zero.
Load the 16-bit value from the RT1 Time Tag Utility
Register(s) into the RT1 Time Tag Counter.
10
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
MT Time Tag Clock Selection Bits 3-0.
These three bits select the clock source for the BC, RT1 and RT2 Time
Tag Counters from the following options:
Bits 3-2-1-0
MT Time Tag Counter Clock Source
7
6
5
4
MTTCK3
MTTCK2
MTTCK1
MTTCK0
0-0-0-0
0-0-0-1
0-0-1-0
0-0-1-1
0-1-0-0
0-1-0-1
0-1-1-0
0-1-1-1
1-x-x-x
Time Tag Counter Disabled.
External clock provided at the MTTCLK input pin.
Internally generated 2μs clock.
Internally generated 4μs clock.
Internally generated 8μs clock.
Internally generated 16μs clock.
Internally generated 32μs clock.
Internally generated 64μs clock.
Internally generated 100μs clock.
R/W
0
BC Time Tag 32-Bit Count Enable.
3
BCTT32
R/W
0
When the BCTT32 bit equals 0, the BC time tag counter is 16 bits.
When the BCTT32 bit equals 1, the BC time tag counter is 32 bits.
BC and RT Time Tag Clock Selection Bits 2-0.
These three bits select the clock source for the BC, RT1 and RT2 Time
Tag Counters from the following options:
Bits 2-1-0
Time Tag Counter Clock Source
2
1
0
TTCK2
TTCK1
TTCK0
0-0-0
0-0-1
0-1-0
0-1-1
1-0-0
1-0-1
1-1-0
1-1-1
Time Tag Counter Disabled.
R/W
0
External clock provided at TTCLK input pin.
Internally generated 2μs clock.
Internally generated 4μs clock.
Internally generated 8μs clock.
Internally generated 16μs clock.
Internally generated 32μs clock.
Internally generated 64μs clock.
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9.10. Memory Address Pointer Registers (HI-6131 only)
This section only applies for the HI-6131 with SPI host interface. It does not apply to the HI-6130 with parallel bus
interface.
The HI-6131 SPI uses predefined 8-bit instruction op codes to perform a variety of predetermined actions. Some op
codes must be followed by two or more operand bytes, while other SPI codes perform their desired action without
additional operands. Examples of self-contained SPI op codes include the “Fast access” op codes used for reading or
writing registers at the low end of the address space.
“Fast access” op codes used for direct addressing contain embedded register addresses, but only work over a limited
address range.
•
SPI reads to register addresses 0 through 0x000F (decimal 15) use an 8-bit op code of the form
0x00 + (Reg_Addr << 2) where Reg_Addr = 0 to 0xF before left-shifting two bits.
•
SPI writes to register addresses 0 through 0x003F (decimal 63) use an 8-bit op code of the form
0x80 + Reg_Addr where Reg_Addr equals 0 to 0x3F.
The two “fast access” op codes use a dedicated memory address pointer to perform their duties without affecting val-
ues contained in other Memory Address Pointer registers. The “fast access” Memory Address Pointer cannot be read
by the host, but is written each time a “fast access” op code is processed.
The HI-6131 uses a Memory Address Pointer for SPI reads to register addresses over 0x000F, or for SPI writes
to register addresses over 0x003F. For most SPI read and write operations, the starting memory address for the
requested operation is written to the Memory Address Pointer (or MAP) before the op code (using the MAP) is invoked.
In the case of a multiword data transfer involving a range of sequential addresses, the memory address pointer is
initialized with the starting (lowest) address. After the SPI transfers data from the first address, the memory address
pointer automatically increments to the next address. When read access occurs, the device prefetches the data stored
at the next address to support the fastest possible data rates. As long as the chip select stays low (asserted) and the
SPI master continues to provide serial clocks, data read/write transfers for sequential addresses continue until the
chip select is negated. Please refer to Section 25.2, describing SPI host access and the SPI op codes used for data
transfer.
For flexibility in configuring the HI-6131device, four independent Memory Address Pointers are available. These can
be assigned in any manner that supports application requirements. For example:
•
•
To simplify data access while supporting concurrent terminal devices (BC, MT, RT1 and RT2), some devices may
need a dedicated Memory Address Pointer (MAP) while other devices may be able to share a MAP.
Consider using a dedicated Memory Address Pointer for interrupt service routines. Many SPI operations are mul-
tiword transfers that utilize the Memory Address Pointer auto-increment feature. If interrupts are enabled during
multiword transfers, a dedicated Memory Address Pointer for the interrupt service routine avoids corruption of the
MAP used by the interrupted routine.
Residing in the lower register address space, the four Memory Address Pointers can be read or written with a single
8-bit “fast access” op code (plus the desired 16-bit data value, when writing).
Just one of the four MAP registers is enabled at any time. Each of the four Memory Address Pointers has a dedicated
8-bit “MAP Select” op code that enables it by writing the Master Configuration Register. Or the host can directly write
the MAPSEL (Memory Address Pointer select) bits 11-10 in the Master Configuration Register to enable the desired
MAP register. Full descriptions of SPI data transfer methods are provided later in this document.
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HI-6130, HI-6131
The four memory address pointer registers are:
MAP1 Memory Address Pointer Register
MAP2 Memory Address Pointer Register
MAP3 Memory Address Pointer Register
MAP4 Memory Address Pointer Register
0x000B
0x000C
0x000D
0x000E
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
0
0
0
5
0
4
0
3
0
2
0
1
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
0
These 16-bit registers are read-write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RT1RESET, RT2RESET or MTRESET bits in the Master Status and
Reset Register (0x0001).
Each of these registers has a unique SPI op code that reads the MAP value in the register, and another op code that
writes a new MAP value into the register. See SPI op code table. The host selects the active MAP register by writing
the MAPSEL (memory address pointer select) bits 11-10 in the Master Configuration Register (see Section 9.1), or by
using the four defined “MAP Select” SPI op codes, described in Section 25.2. The active MAP register contains the
memory address used for SPI read write access to registers and RAM.
Please refer to Section 25.2 for a full description of the interface and the SPI instruction op codes.
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10. BUS CONTROLLER − CONFIGURATION AND OPERATION
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Controller (BC), requiring minimal host processor
support. All MIL-STD-1553B error-checking is automatically performed, including RT response time, Manchester II
encoding, sync type, bit count, word parity, word count, responding RT address, and detection of the full range of pos-
sible error conditions encountered during BC operation. The device implements all MIL-STD-1553B message formats.
Message format is configurable on a message by message basis. Each message is individually programmable for
command type. Individual messages can be programmed for automatic retries on either bus, and interrupt requests
may be enabled or disabled.
The HI-613x Bus Controller provides a flexible means for scheduling major and minor frames, allowing insertion of
asynchronous messages during frame execution. Upon error, individual messages can be programmed for one or two
automatic retries, and the BC can switch buses before retry occurs. Message data is separated from control and status
data, to serve the needs for double buffering in RAM and bulk data transfers.
Before Bus Controller operation can begin, the BCENA input pin must be connected to logic 1 to allow BC operation. All
Bus Controller operational registers (see Section 11) must be properly configured. The BC Instruction List in RAM must
be initialized to define message sequencing and conditional execution, and finally the host must assert BCSTRT bit
13 in the Master Configuration Register 0x0000 to initiate execution of Instruction List op codes. The following pages
provide the necessary details for successful Bus Controller operation.
Figure 3 shows the registers and RAM resources utilized by the Bus Controller. All Bus Controller registers are fully
described in Section 11.
Initial control of BC message sequencing involves the BC Instruction List Pointer in register 0x0034. Before BC
execution begins, the instruction list starting address is copied from the BC Instruction List Start Address Register,
0x0033. Once message sequencing is underway, the BC Instruction List Pointer in register 0x0034 is updated by the
BC control logic.
The BC Instruction List in RAM comprises a series of 2-word entries, an instruction op code followed by a parameter
word. While processing messages, the BC control logic fetches and executes the instruction op code referenced by
the BC Instruction List Pointer from the BC Instruction List. The pointer parameter, referencing the first word in the
Message Control/Status Block, must have the form 0xHHH8 or 0xHHH0, where each H represents a hex character,
0-9 or A-F. If the individual message is RT-to-RT, the address must have the form 0xHHH0.
Each op code word in the BC Instruction List has the format:
Odd
Parity
X
P
X
X
X
X
X
0
9
1
0
1
0
X
X
X
X
X
Op Code Field
Validation Field
Condition Code
15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
Bit
Bus Controller execution stops immediately if the BC logic fetches an op code word having one or more of these error
conditions:
•
•
•
Bit 15 contains even parity
Bits 14-10 contain an undefined op code
Validation field bits 9-5 do not equal 01010
If enabled in the BC Interrupt Enable Register 0x0010, a BCTRAP interrupt occurs when execution stops because of
an illegal op code.
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6 Unused Addresses
GPQ Word 63
GPQ Words 1 - 62
GPQ Word 63
RT-RT Message Only
2nd RT Status Word
Tx Command Word
RT Status Word
BC General Purpose
Queue Pointer
reg 0x0038
Time Tag Bits 31-16
if BC Uses 32-Bit
Time Base
Loopback Word
Block Status Word
Time Tag Word
BC GP Queue
in RAM
Data Word N
Data Word(s)
Data Word 1
Time to Next Msg
Data Block Pointer
Command Word *
BC Control Word
Increasing
Memory
Address
Parameter
Op Code
Parameter (pointer)
Op Code
Message Data
Block in RAM
BC Instruction
List Pointer
reg 0x0034
Parameter
Message
Control / Status
Block in RAM
BC Instruction
List Start Address
reg 0x0033
Op Code
* Rx Command Word
if RT-RT Message
HI-613x
Register
Space
Bus Controller
Instruction List
in RAM
Figure 4. Bus Controller Message Sequence Structures
10.1. Bus Controller Condition Codes
For most op codes, execution is conditional, depending on evaluation of the Condition Code field. Condition Code bits
3-0 define the specific condition. Condition Code bit 4 identifies the required outcome for op code execution, true or
false, following evaluation of Condition Code bits 3-0. The host has read-only access to the BC condition codes by
reading the BC Condition Code Register 0x0037.
Eight of the condition codes (1000 through 1111) are set or cleared based on the outcome of the most recent message.
The remaining eight codes are General Purpose Condition Codes, GP0 through GP7. Three processes affect values
of the General Purpose Condition Code bits: (a) they may be toggled, set or cleared when the BC logic executes a FLG
(GP Flags Bits) op code. (b) they may be toggled, set or cleared when the host writes the BC General Purpose Flag
Register 0x0037. (c) only GP0 and GP1 may be set or cleared when the BC logic executes a CMT (Compare Mes-
sage Timer) op code, or a CFT (Compare Frame Timer) op code. The sixteen BC Condition Codes are summarized
in Table 6.
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Table 6. Bus Controller Condition Code Table
Code
Bit 3-0
Condition Code
Inverse
Function
Bit 4 = 1
Bit 4 = 0
Less Than or GP0 Flag.
This flag may be toggled, set or cleared when the BC logic
executes a FLG (General Purpose Flags Bits) op code, or
when the host writes the BC General Purpose Flag Register
0x0037.
LT / GP0
GT-EQ / GP0
This flag is also set or cleared based on the evaluation of a
CMT (Compare Message Timer) or CFT (Compare Frame
Timer) instruction op code:
If CMT parameter < BC Time to Next Message Reg
If CFT parameter < BC Frame Time Remaining Reg
LT / GP0 = 1
LT / GP0 = 0
LT / GP0 = 0
GT-EQ / GP0 = 0
GT-EQ / GP0 = 1
GT-EQ / GP0 = 1
0x0
If CMT parameter = BC Time to Next Message Reg
If CFT parameter = BC Frame Time Remaining Reg
If CMT parameter > BC Time to Next Message Reg
If CFT parameter > BC Frame Time Remaining Reg
LT / GP0 = 1
or 0 based on
compared values
GT-EQ / GP0 =
0 or 1 based on
compared values
If CMT parameter ≠ BC Time to Next Message Reg
If CFT parameter ≠ BC Frame Time Remaining Reg
Equal To or GP1 Flag.
This flag may be toggled, set or cleared when the BC logic
executes a FLG (General Purpose Flags Bits) op code, or
when the host writes the BC General Purpose Flag Register
0x0037.
EQ / GP1
NE / GP1
This flag is also set or cleared based on the evaluation of a
CMT (Compare Message Timer) or CFT (Compare Frame
Timer) instruction op code:
If CMT parameter < BC Time to Next Message Reg
If CFT parameter < BC Frame Time Remaining Reg
0x1
EQ / GP1 = 0
EQ / GP1 = 1
EQ / GP1 = 0
EQ / GP1 = 0
NE / GP1 = 1
NE / GP1 = 0
NE / GP1 = 1
NE / GP1 = 1
If CMT parameter = BC Time to Next Message Reg
If CFT parameter = BC Frame Time Remaining Reg
If CMT parameter > BC Time to Next Message Reg
If CFT parameter > BC Frame Time Remaining Reg
If CMT parameter ≠ BC Time to Next Message Reg
If CFT parameter ≠ BC Frame Time Remaining Reg
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Code
Bit 3-0
Condition Code
Inverse
Bit 4 = 1
Function
Bit 4 = 0
0x2
0x3
0x4
0x5
0x6
0x7
GP2
GP3
GP4
GP5
GP6
GP7
GP2
GP3
GP4
GP5
GP6
GP7
General Purpose Flag Bits 2-7.
These flags may be toggled, set or cleared when the BC logic
executes a FLG (General Purpose Flags Bits) op code, or
when the host writes the BC General Purpose Flag Register
0x0037.
No Response Flag.
This flag is set when an RT failed to respond to a command,
or responded later than the BC No Response Timeout
programmed using bits 15-14 in the BC Configuration Register
0x0032.
0x8
NORESP
RESP
Format Error Flag.
This flag is set when the received response to the last
message had one or more violations to MIL-STD-1553B
validation criteria, including problems with sync, encoding, bit
count, parity, or word count.
0x9
FMTERR
FMTERR
This flag is also set when the received RT Status Word
response from the last message contained an incorrect RT
address field.
Good Data Block Transfer.
Reflecting status for the last 1553 message, this flag is set
after completion of error-free RT-to-BC transfers, RT-to-RT
transfers, or transmit mode code commands with data. This
flag is reset after invalid messages, or after completion of BC-
to-RT transfers, receive mode code commands with data, or
mode code commands without data. This flag may be used to
determine when the transmit aspect of an RT-to-RT transfer is
error-free.
0xA
GOODBLOCK
GOODBLOCK
Masked Status Set.
Reflecting status for the last 1553 message, this flag is set
when one or both of the following conditions occurred:
•
In the message BC Control Word, at least one of the Sta-
tus Mask bits 14-9 are logic 0, but the corresponding bit
or bits are set in the received RT Status Word. When the
Reserved Bits Mask (message BC Control Word bit 9) is
logic 0, this flag is set when any or all of the three reserved
bits are set in the received RT Status Word.
0xB
MSKSTATSET
MSKSTATSET
•
In the BC Configuration Register 0x0032, the BCR (broad-
cast command received) Mask Enable bit 0 is logic 1. the
Mask Broadcast bit 5 in the message BC Control Word is
logic 0, and the BCR (Broadcast Command Received) bit
4 is logic 1 in the received RT Status Word.
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Code
Bit 3-0
Condition Code
Inverse
Bit 4 = 1
Function
Bit 4 = 0
Bad Message.
Reflecting status for the last 1553 message, the Bad Message
flag is set for Format Error, No Response error, or Loopback
error. See Sections 24.2.6 through 24.2.8.
0xC
BADMSG
GOODMSG
A Status Set condition has no effect on the Bad Message
condition code.
1 Retry.
If Condition Code bits 3:0 = 0xD and bit 4 = 0, one or two
message retries is indicated.
0xD
0xE
0xF
1RETRY
2RETRY
ALWAYS
1RETRY
Undefined
NEVER
If Condition Code bits 3:0 = 0xD and bit 4 = 1, zero message
retries is indicated.
2 Retries.
If Condition Code bits 3:0 = 0xE and bit 4 = 0, two message
retries is indicated.
Condition Code bits 3:0 = 0xE and bit 4 = 1 is undefined.
Always.
The ALWAYS bit is set (Condition Code bit 4 = 0) to designate
an instruction op code as unconditional.
The NEVER bit is set (Condition Code bit 4 = 1) to designate
an instruction op code as NOP (no op).
10.2. Bus Controller Instruction Op Codes
In the BC Instruction List, each op code word contains a 5-bit instruction field that spans bits 14-10. The instruction op
codes are described in Table 7. Four instructions execute unconditionally, without evaluating the condition code test.
For these instructions, the Condition Code field is “don’t care”.
The four unconditional instruction op codes are:
1. CMT (Compare Message Timer)
2. CFT (Compare Frame Timer)
3. FLG (General Purpose Flag Bits)
4. XQF (execute and Flip)
All other instruction op codes execute conditionally. They execute only if evaluation of the Condition Code tests true,
logic 1. If the Condition Code field tests false, the BC Instruction List Pointer skips to the next instruction op code in
the BC Instruction List.
Many instruction op codes utilize the following parameter word in the BC Instruction List. Depending on the op code,
the parameter may be a RAM address, a time value, an interrupt bit pattern, an argument that sets or clears General
Purpose Flag bits, or an immediate value. For some op codes, the parameter word is not used and is therefore “don’t
care.” For an XEQ (execute message) instruction, the parameter is a RAM address pointer referencing the start of
the message Control/Status Block.
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HI-6130, HI-6131
These instructions control program execution: Halt, Jump, Subroutine Call and Subroutine Return. Subroutine calls
can be nested 8 levels deep. If BC Call Stack overflow or underflow occurs, device logic generates a CSTKERR (Call
Stack Pointer Error) interrupt, if enabled. Other host interrupts are generated under program control using the Interrupt
Request instruction. In this case, a 4-bit user-defined interrupt code is written to the BC Interrupt Request Bits 3-0 in
the BC Pending Interrupt Register.
Other instructions are formed various duties: set, reset or toggle General Purpose Flag bits; load the Time Tag counter;
load the Frame Time counter; begin a new BC frame; wait for external trigger, then start a new BC frame; evaluate
remaining Frame Time; or evaluate time to next message.
Table 7. Bus Controller Instruction Op Codes
Op
Code
Name Instruction
Parameter
Function
If the Condition Code evaluates True, execute the message
at the parameter-specified Message Control Status Block
address. Otherwise (Condition Code Evaluates False),
continue execution at the next op code in the BC Instruction
List.
At the start of XEQ message execution, if the fourth word in
the Message Control/Status Block is nonzero, it is copied to
the BC Time to Next Message Register, and message timer
begins decrementing. The BC message sequencer does not
fetch the next instruction op code until the message timer
reaches zero.
Execute
Message
RAM Address for
Message Control/
Status Block
Regarding Condition Codes used with XEQ:
XEQ
0x01
•
If using LT, GT-EQ, EQ and NE (which are only
modified by the device upon completion of CMT or CFT
op codes) the host must not change the value of the
shared function GP0 or GP1 flag bit during execution of
the contingent message.
Conditional
•
•
If using GP Flag Bit status (GP0 through GP7) to enable
a message, host must not alter the tested GP Flag bit
during execution of a contingent message.
The ALWAYS and NEVER Condition Codes may be
used with XEQ. The following Condition Codes must
not be used with XEQ: BADMSG, RETRY1 or RETRY2,
NORESP, MSKSTATSET, FMTERR or GOODBLOCK.
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Op
Code
Name Instruction
Parameter
Function
If the Condition Code evaluates True, execute the message
at the parameter-specified Message Control Status Block
address. Otherwise (Condition Code Evaluates False),
continue execution at the next op code in the BC Instruction
List.
Regarding Condition Codes used with XQG:
•
If using LT, GT-EQ, EQ and NE (which are only
modified by the device upon completion of CMT or CFT
op codes) the host must not change the value of the
shared function GP0 or GP1 flag bit during execution of
the contingent message.
•
•
If using GP Flag Bit status (GP0 through GP7) to enable
a message, host must not alter the tested GP Flag bit
during execution of a contingent message.
Execute
Message and
Go
The ALWAYS and NEVER Condition Codes may be
used with XQG. The following Condition Codes must
not be used with XQG: BADMSG, RETRY1 or RETRY2,
NORESP, MSKSTATSET, FMTERR or GOODBLOCK.
RAM Address for
Message Control/
Status Block
XQG
0x16
Conditional
At the start of XQG message execution, if the fourth (Time
to Next Message) word in the Message Control/Status
Block is nonzero, it is copied to the BC Time to Next
Message Register 0x0036, and this message timer begins
countdown. Completion of an XQG message may occur
while message timer countdown continues.
Unlike XEQ, the XQG op code does not wait for the
decrementing message timer to hit 0 before fetching the
next instruction op code. As long as op codes following
XQG do not execute a 1553 message, each op code
is performed after fetch. Upon reaching a following
XEQ, XQG, XQF or XFG execute-message instruction,
transaction of its 1553 message does not begin until Time
to Next Message count reaches 0. Thus, programmed 1553
message timing is maintained, while allowing execution of
non-message instruction op codes.
If the Condition Code evaluates True, jump to the
parameter-specified instruction op code in the BC
Instruction List. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
Jump
RAM Address
within the BC
Instruction List
JMP
CAL
0x02
0x03
Conditional
If the Condition Code evaluates True, push address of the
next instruction op code onto the 8-level BC Call Stack, then
jump to the parameter-specified instruction op code in the
BC Instruction List. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
Call
Subroutine
RAM Address
within the BC
Instruction List
Conditional
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Op
Code
Name Instruction
Parameter
Function
If the Condition Code evaluates True, pop the top address
Return from
Subroutine
from the BC Call Stack, then jump to the popped instruction
op code address in the BC Instruction List. Otherwise
(Condition Code Evaluates False), continue execution at the
next op code in the BC Instruction List.
Not Used
RTN
0x04
(Don’t Care)
Conditional
If the Condition Code evaluates True, generate a host
interrupt by writing the parameter-specified 4-bit value N to
bits 8-5 in the BC Pending Interrupt Register. Otherwise,
continue execution at the next op code in the BC Instruction
List.
Interrupt
Request
4-Bit Interrupt
Pattern, 0x000N
IRQ
0x06
0x07
Conditional
Note: no interrupt is generated if N = 0
If the Condition Code evaluates True, stop execution of the
BC Instruction List until a new BC Start is issued by the
host. Otherwise (Condition Code Evaluates False), continue
execution at the next op code in the BC Instruction List.
Halt
HLT
Not Used
(Don’t Care)
Conditional
If the Condition Code evaluates True, initiate a delay equal
to the parameter-specified value. Otherwise (Condition
Code Evaluates False), continue execution at the next op
code in the BC Instruction List.
Delay
DLY
Delay Time Value
(1 μs per LSB
resolution)
0x08
Conditional
If the Time-to-Next Message counter is in use, the DLY
parameter has higher priority than the count for an
unfinished Message Timer delay.
Wait until
Frame Timer
Equals 0
If the Condition Code evaluates True, stop BC Instruction
List execution until the BC Frame Time Counter decrements
to 0. Otherwise (Condition Code Evaluates False), continue
execution at the next op code in the BC Instruction List.
Not Used
WFT
CFT
0x09
0x0A
(Don’t Care)
Conditional
Compare to
Frame Timer
Compare the parameter-specified Time Value to the BC
Frame Time Remaining Register 0x0035. Set and clear
LT and EQ bits 1 and 0 in the BC General Purpose Flag
Register (Section 11.7).
Time Value
(100 µs / LSB
resolution)
Conditional
Compare the parameter-specified Time Value to the BC
Time to Next Message Register 0x0036. Set and clear
LT and EQ bits 1 and 0 in the BC General Purpose Flag
Register (Section 11.7).
When CMT is preceded by an XEQ or XQF instruction, the
BC Time to Next Message Register 0x0036 value used
for comparison is always 0x0000 because the message
timer (initiated by XEQ or XQF) decrements to zero before
fetching the CMP instruction. In this case, a CMT with
non-zero parameter word always sets GT-EQ and NE and
always resets LT and EQ flags. When CMT is preceded by
an XEQ or XQF instruction, a CMT with parameter word
0x0000 always sets GT-EQ and EQ and always resets LT
and NE flags. Further, the CMT op code will never set LT
and NE, while clearing GT-EQ and EQ flags.
Compare
to Message
Timer
Time Value
CMT
0x0B
(1 µs per LSB
resolution)
Unconditional
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HI-6130, HI-6131
Op
Code
Name Instruction
Parameter
Function
Time Value
If the Condition Code evaluates True, load the BC Time Tag
Count Register 0x0043 with the parameter-specified Time
Value. This represents bits 15-0 when the BC operates
with 32-bit time tag. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
(Resolution is
programmed by
bits 2-0 in the
Time Tag Counter
Configuration
Load Time
Tag Counter
LTT
0x0D
Conditional
Register 0x0039) Read LTH regarding LTT-LTH sequences.
If the Condition Code evaluates True, load the BC Time Tag
Count High Register 0x0044 with the parameter-specified
Time Value. This represents bits 31-16 when BC operates
with 32-bit time tag.
Load Time
Tag Counter
High
Otherwise (Condition Code Evaluates False), continue
execution at the next op code in the BC Instruction List.
Time Value
(Resolution is
programmed by
bits 2-0 in the
If LTH immediately follows an LTT instruction, all 32 counter
bits are loaded simultaneously. If LTH is not preceded by
an LTT instruction, time count bits 15-0 in 0x0043 will be
Conditional
LTH
0x18
LTH only
applies
Time Tag Counter cleared to 0x0000 when bits 31-16 are written to register
Configuration
0x0044.
when 32-bit
time base is
enabled
Register 0x0039)
This instruction is only allowed when BCTT32 bit 3 is logic
1 in the Time Tag Counter Configuration register 0x0039,
selecting 32-bit time base operation for the BC and RT(s).
If BCTT32 is logic 0, this instruction stops instruction list
execution, and generates an illegal instruction BCTRAP
interrupt, if enabled.
If the Condition Code evaluates True, load the BC Frame
Time Remaining Register 0x0035 with the parameter-
specified Time Value. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
Load Frame
Timer
Time Value
LFT
0x0E
0x0F
0x10
(100 µs / LSB
resolution)
Conditional
Start Frame
Timer
If the Condition Code evaluates True, start decrementing
the BC Frame Time Remaining Register 0x0035. Otherwise
(Condition Code Evaluates False), continue execution at the
next op code in the BC Instruction List.
Not Used
SFT
(Don’t Care)
Conditional
If the Condition Code evaluates True, push the value in the
BC Time Tag Count Register 0x0043 onto the BC General
Purpose Queue. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
Push Time
Tag Count
Not Used
PTT
(Don’t Care)
Conditional
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Op
Code
Name Instruction
Parameter
Function
If the Condition Code evaluates True, push the value in
Push Time
Tag Count
High
the BC Time Tag Count High Register 0x0044 onto the BC
General Purpose Queue. This represents bits 31-16 when
BC operates with 32-bit time tag. Otherwise (Condition
Code Evaluates False), continue execution at the next op
code in the BC Instruction List.
Conditional
PTH
Not Used
0x19
(Don’t Care)
This instruction is only allowed when BCTT32 bit 3 is logic
1 in the Time Tag Counter Configuration register 0x0039,
selecting 32-bit time base operation for the BC and RT(s).
If BCTT32 is logic 0, this instruction stops instruction list
execution, and generates an illegal instruction BCTRAP
interrupt, if enabled.
PTH only
applies
when 32-bit
time base is
enabled
If the Condition Code evaluates True, push the value in
the BC Time Tag Count High Register 0x0044 and then
push the value in the BC Time Tag Count (Low) Register
0x0043 onto the BC General Purpose Queue. (Both words
are fetched simultaneously but pushed serially.) Otherwise
(Condition Code Evaluates False), continue execution at the
next op code in the BC Instruction List.
Push Time
Tag Count
Both
Conditional
PTB
Not Used
0x1A
(Don’t Care)
PTB only
applies
when 32-bit
time base is
enabled
This instruction is only allowed when BCTT32 bit 3 is logic
1 in the Time Tag Counter Configuration register 0x0039,
selecting 32-bit time base operation for the BC and RT(s).
If BCTT32 is logic 0, this instruction stops instruction list
execution, and generates an illegal instruction BCTRAP
interrupt, if enabled.
If the Condition Code evaluates True, push the value of the
Block Status Word from the most recent message onto the
BC General Purpose Queue. Otherwise (Condition Code
Evaluates False), continue execution at the next op code in
the BC Instruction List.
Push Block
Status Word
Not Used
PBS
0x11
0x12
0x13
0x14
(Don’t Care)
Conditional
Push
Immediate
Value
If the Condition Code evaluates True, push the parameter-
specified immediate value onto the BC General Purpose
Immediate Value Queue. Otherwise (Condition Code Evaluates False),
PSI
continue execution at the next op code in the BC Instruction
List.
Conditional
If the Condition Code evaluates True, push the value stored
at the parameter-specified address onto the BC General
Memory Address Purpose Queue. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Instruction List.
Push Indirect
PSM
Conditional
Wait for
External
WTG Trigger
If the Condition Code evaluates True, wait for a rising edge
(logic 0 to 1 transition) on the BCTRIG pin before continuing
execution at the next op code in the BC Instruction List
Otherwise (Condition Code Evaluates False), continue
Not Used
(Don’t Care)
Conditional
execution at the next op code in the BC Instruction List.
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Op
Code
Name Instruction
Parameter
Function
Unconditionally execute the message at the parameter-
specified Message Control/Status Block Address. At
message completion, if the Condition Code evaluates
True, then toggle bit 4 of the Message Control/Status Block
Address, and store the new Message Control/Status Block
Address as the updated value of the parameter following
the XQF instruction op code. As a result, the next time
this address in the BC Instruction List is executed, the
processed Message Control/ Status Block resides at the
updated address (old address XOR 0x0010) instead of the
old address. Otherwise (Condition Code Evaluates False)
the value of the Message Control/Status Block Address
parameter is not changed.
Execute and
Flip
RAM Address for
Message Control/
Status Block
XQF
0x15
Unconditional
At the start of XQF message execution, if the fourth word in
the Message Control/Status Block is nonzero, it is copied to
the BC Time to Next Message Register, and message timer
begins decrementing. The BC message sequencer does not
fetch the next instruction op code until this message timer
reaches zero.
Unconditionally execute the message at the parameter-
specified Message Control/Status Block Address. At
message completion, if the Condition Code evaluates
True, then toggle bit 4 of the Message Control/Status Block
Address, and store the new Message Control/Status Block
Address as the updated value of the parameter following
the XFG instruction op code. As a result, the next time
this address in the BC Instruction List is executed, the
processed Message Control/ Status Block resides at the
updated address (old address XOR 0x0010) instead of the
old address. Otherwise (Condition Code Evaluates False)
the value of the Message Control/Status Block Address
parameter is not changed.
Execute, Flip
and Go
RAM Address for At the start of XQG message execution, if the fourth (Time
Message Control/ to Next Message) word in the Message Control/Status
XFG
0x1A
Status Block
Block is nonzero, it is copied to the BC Time to Next
Message Register 0x0036, and this message timer begins
countdown. Completion of an XQG message may occur
while message timer countdown continues.
Unconditional
Unlike XQF, the XFG op code does not wait for the
decrementing message timer to hit 0 before fetching the
next instruction op code. As long as op codes following XFG
do not execute a 1553 message, each op code is performed
after fetch. Upon reaching a following XEQ, XQG, XQF
or XFG execute-message instruction, transaction of its
1553 message does not begin until Time to Next Message
count reaches 0. Thus, programmed 1553 message timing
is maintained, while allowing execution of non-message
instruction op codes.
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Op
Code
Name Instruction
Parameter
Function
If the Condition Code evaluates True, write the parameter-
Write
Immediate
Value to WMI
WMP Memory
Pointer
specified immediate value to the dedicated WMI memory
pointer (a register not accessible by the host). Otherwise
(Condition Code Evaluates False), continue execution at the
next op code in the BC Instruction List.
0x1B
0x1C
Immediate Value
Immediate value must exceed 0x4F or WMP instruction has
no effect. After reset, the default WMI memory pointer value
is 0x0050.
Conditional
Write
Immediate
Value to
Memory
If the Condition Code evaluates True, write the parameter-
specified immediate value to 0x0050 or the memory
Immediate Value address specified by the last WMP instruction performed.
Otherwise (Condition Code Evaluates False), continue
WMI
execution at the next op code in the BC Instruction List.
Conditional
Decrement
RAM
Specified
by Memory
Address,
Skip the Next
If the Condition Code evaluates True, the memory address
specified by the parameter word is decremented. If the new
value is non-zero, the next instruction is executed. If the
decremented value is zero, the next instruction is skipped.
Otherwise (Condition Code Evaluates False), continue
execution at the next op code in the BC Instruction List.
DSZ
0x1D
0x0C
Memory Address
Instruction if
Zero
The primary purpose of DSZ is N-iteration repeating
execution loops. N is initialized with a WMI op code, and the
instruction following DSZ is a JMP to top-of-loop.
Conditional
General
Purpose Flag
Bits
The parameter word value is used to set, clear, or toggle
the lower byte in the BC General Purpose Flag Register
0x0037. The upper and lower bytes in the parameter word
provide 2-bit arguments that modify each of the eight GP
flag bits, as illustrated below.
Word value sets,
clears or toggles
General Purpose
Flag Bits
FLG
Unconditional
GP7
GP0
H7 H6 H5 H4 H3 H2 H1 H0
High Byte: Clear GP Bits 7-0
Hx =
Lx =
0
0
1
1
Parameter
Word Bit
No
Set
Clear Toggle
GPx
Change GPx
GPx
15 14 13 12 11 10
9
8
L7 L6 L5 L4 L3 L2 L1 L0
Low Byte: Set GP Bits 7-0
0
1
0
1
H-L Bit Combinations Modify GP Flag Bits
Parameter
Word Bit
7
6
5
4
3
2
1
0
Figure 5. Bus Controller Flag Operation
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10.3. Bus Controller General Purpose Queue
The HI-613x BC architecture includes a General Purpose Queue, a 64-word circular buffer which the BC can use to
convey information to the external BC host. Various BC instruction op codes push data values onto the queue, such
as the Block Status Word for the last message, Time Tag Counter values, immediate data values, or values stored in
specific RAM addresses.
The BC General Purpose Queue Pointer 0x0038 (see Section 11.8) is initialized with the default starting address
0x00C0 after reset. The queue is relocatable, so the host may overwrite the default base address. Updated by the BC
logic each time a data word is pushed onto the queue, the pointer in register 0x0038 always points to the next storage
address in the queue to be written. The address pointer rolls over every 64th word written. If the BCGPQ bit 13 is logic
1 In the BC Interrupt Enable Register, a BC interrupt is generated when the General Purpose Queue Pointer rolls over
from its ending address to its base address.
10.4. Bus Controller Message Control / Status Blocks
In the BC Instruction List, each occurrence of the “execute message” instructions, XEQ, XQG, XQF and XFG, refer-
ences a MIL-STD-1553B message. The op code word is followed by the parameter word, a memory pointer indicating
the RAM start address for a corresponding Message Control/Status Block. The pointer address indicates the first word
in the Message Control/Status Block, the BC Control Word. Figure 6 illustrates this relationship.
The HI-613x is fully compatible with all MIL-STD-1553B message formats. For most MIL-STD-1553 messages, the
corresponding Message Control/Status Block contains 8 words:
•
BC Control Word. This word contains flags that select message format, choose the active bus, enable message
retry and end-of-message interrupt, indicate expected RT status word flags, etc.
•
•
MIL-STD-1553 Command Word. When message is RT-to-RT, this is the Receive Command Word.
Data Address Pointer. For subaddress commands and mode code commands with data, this word identifies
the start address of the Message Data Block in RAM. For mode commands without data, this word is not used.
•
•
Time-to-Next Message. The time count loaded here begins decrementing at start of message. When value ex-
ceeds message execution time, it paces delivery of the next message.
Time Tag Word. The current value of the internal time tag count is written to the Time Tag Word at Start-of-Mes-
sage and again at the End-of-Message. When the BC uses a 16-bit time base, this location contains the complete
time count. When the BC uses 32-bit time base, this word contains time bits 15-0 and block word 7 contains time
bits 31-16 (instead of Loopback Word).
•
•
Block Status Word. This word contains various message result flags.
Loopback Word, containing the last word transmitted by the BC (16-bit time base only) or
Time Tag Bits 31-16 (32-bit time base only)
•
RT Status Word received.
This is the Transmit RT Status Word when message is RT-to-RT.
When the message is RT-to-RT, the Message Control/Status Block contains 8 additional words:
•
•
•
Transmit Command Word.
Receive RT Status Word.
Six unused word locations, to maintain 8 or 16 words per Message Control/Status Block.
Figure 6 shows the range of Message Control/Status Block variations. Selected words in the Message Control/Status
Block are described next.
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6 Unused Addresses
6 Unused Addresses
Rx RT Status Word
Tx Command Word
Increasing
Memory
Address
Rx RT Status Word
Tx Command Word
Tx RT Status Word
Loopback Word
RT Status Word
Loopback Word
Block Status Word
Time Tag Word
RT Status Word
High Time Tag Word
Block Status Word
Low Time Tag Word
Tx RT Status Word
High Time Tag Word
Block Status Word
Time Tag Word
Block Status Word
Time Tag Word
Time to Next Msg
Data Block Pointer
Rx Command Word
BC Control Word
Time to Next Msg
Data Block Pointer
Command Word
BC Control Word
Time to Next Msg
Data Block Pointer
Rx Command Word
BC Control Word
Time to Next Msg
Data Block Pointer
Command Word
BC Control Word
Message
Message
Message
Message
Control / Status Block Control / Status Block
Control / Status Block Control / Status Block
for all messages
except RT-to-RT
for RT-to-RT
messages only
for all messages
except RT-to-RT
for RT-to-RT
messages only
Bus Controller Configured for 16-Bit Time Base
Bus Controller Configured for 32-Bit Time Base
Figure 6. Structure of Bus Controller Message Control / Status Blocks in RAM
10.4.1. BC Control Word
RTRYENA RTRTFMT
USA
STMFAMSAKRSSKVMASK USEBSELFTMSATSKEBOCMRIRNeTserMveCdODBFCMSTTFMT
TXTTMCE1M7A
S
S
R
K
QMBASSYKM
S
A
S
S
Y
K
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
RW
Host Access
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
The BC Control Word is the first word in each Message Control / Status Block. The BC Control Word is not transmitted
on the MIL-STD-1553 bus. This word is initialized and maintained by the host to specify message attributes: message
format, which bus to use, bit masks for the received RT Status Word, enabling interrupt at end-of-message, and
enabling self test:
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Bit No. Mnemonic
R/W Reset Function
Transmit Time Tag for Synchronize Mode Code Command MC17.
This option bit only applies when BC Configuration Register TTSYNEN bit
3 is logic 1. See page 26. This bit affects only the “synchronize with data”
mode code command, (mode code 0x11 or decimal 17).
•
•
If this Control Word bit is logic 0 (or if BC Configuration Register
TTSYNEN bit 3 is logic 0) the BC transmits the value contained in
the Message Data Block as the data word for a “synchronize” mode
code command MC17. The transmitted word is fetched from the RAM
address referenced by the Data Address Pointer.
If this Control Word bit and BC Configuration Register TTSYNEN bit
3 are both logic 1, the “synchronize” mode data word value originates
from the 16-bit BC time base counter (low order 16 bits when using the
32-bit BC time base option).
15
TXTTMC17 R/W
0
•
If BC Configuration Register ETTSYN bit 2 is also logic 1, the
transmitted time tag data word is always an even value; the least
significant bit is always 0.
•
When ETTSYN bit 2 is logic 0, the data word least significant bit
may be 0 or 1. See page 26.
The transmitted data value is saved in the message data block, at the
address indicated by the Data Address Pointer word.
Message Error Bit Mask.
If this BC Control Word bit is logic 0 and the Message Error bit 10 is logic 1
in the received RT Status Word, a “Status Set” condition will result.
If this BC Control Word bit is logic 1, the Message Error bit 10 in the
received RT Status Word has no effect on the outcome for a “Status Set”
condition.
Note: A “Status Set” condition results if one or more of these events occurs:
•
one or more of the mask bits 14-9 in the BC Control Word is logic 0 and
the corresponding bit is logic 1 in the received RT Status Word,
14
MEMASK
R/W
0
•
the BCRME bit 0 is logic 1 in the BC Configuration Register 0x0032 and
the MASKBCR bit in the BC Control Word is logic 0 and the Broadcast
Command Received bit 4 is logic 1 in the RT Status Word
•
•
the BCRME bit 0 is logic 0 in the BC Configuration Register 0x0032 and
the MASKBCR bit in the BC Control Word differs from the Broadcast
Command Received bit 4 in the RT Status Word
The received RT Status Word contains an RT Address field different
from the RT Address field in the transmitted Command Word
Service Request Bit Mask.
If this BC Control Word bit is logic 0 and the Service Request bit 8 is logic 1
in the received RT Status Word, a “Status Set” condition will result.
13
SRQMASK
R/W
0
If this BC Control Word bit is logic 1, the Service Request bit 8 in the
received RT Status Word has no effect on the outcome for a “Status Set”
condition.
See “Note” at end of MEMASK bit description above.
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Bit No. Mnemonic
R/W Reset Function
Busy Bit Mask.
If this BC Control Word bit is logic 0 and the Busy bit 3 is logic 1 in the
received RT Status Word, a “Status Set” condition will result.
12
11
10
BSYMASK
R/W
0
0
0
If this BC Control Word bit is logic 1, the Busy bit 3 in the received RT
Status Word has no effect on the outcome for a “Status Set” condition.
See “Note” at end of MEMASK bit description above.
Subsystem Flag Bit Mask.
If this BC Control Word bit is logic 0 and the Subsystem Flag bit 2 is logic 1
in the received RT Status Word, a “Status Set” condition will result.
SSYSMASK R/W
If this BC Control Word bit is logic 1, the Subsystem Flag bit 2 in the
received RT Status Word has no effect on the outcome for a “Status Set”
condition.
See “Note” at end of MEMASK bit description above.
Terminal Flag Bit Mask.
If this BC Control Word bit is logic 0 and the Terminal Flag bit 0 is logic 1 in
the received RT Status Word, a “Status Set” condition will result.
TFMASK
R/W
If this BC Control Word bit is logic 1, the Terminal Flag bit 0 in the received
RT Status Word has no effect on the outcome for a “Status Set” condition.
See “Note” at end of MEMASK bit description above.
Reserved Bits Mask.
If this BC Control Word bit is logic 0 and one or more of the three Reserved
bits 7-5 is logic 1 in the received RT Status Word, a “Status Set” condition
will result.
9
RSVMASK
R/W
0
If this BC Control Word bit is logic 1, the three Reserved bits 7-5 in the
received RT Status Word have no effect on the outcome for a “Status Set”
condition.
See “Note” at end of MEMASK bit description above.
Retry Enabled.
If this Control Word bit is logic 1 and BCRE (BC Retry Enable) bit 12 is logic
1 in the BC Configuration Register 0x0032, the BC will retry a message if
RT response timeout or Format Error occurs.
8
7
RTRYENA
USEBUSA
R/W
R/W
0
0
If this Control Word bit is logic 1 and BCRE (BC Retry Enable) bit 12 is
logic 1 and BCRSB (BC Retry If Status Word Bits Set) bit 8 is also logic
1 in the BC Configuration Register 0x0032, the BC will retry a message
when a “Status Set” condition occurs. See “Note” at end of MEMASK bit 14
description above.
Use Bus A / Use Bus B.
If this Control Word bit is logic 1, the BC transmits the command on Bus A.
If this Control Word bit is logic 0, the BC transmits the command on Bus B.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Self-Test Message Off-Line.
If this Control Word bit is logic 1, transmission of this message onto the
1553 bus is inhibited. Instead the digitally-encoded Command Word is
looped back into the receive decoder for the selected bus. This tests both
the encoding and decoding signal paths. Upon message completion, Loop
Test Fail bit 8 in the Block Status Word indicates the self-test result.
6
SELFTST
R/W
0
If BC is configured for 16-bit time base, the received Loopback Word is
stored in the Message Control/Status Block. If the BC is configured for 32-
bit time base, time tag bits 31-16 are stored in the Loopback Word location.
See Section “24.2.7. Programmed BC-Mode Digital Loopback Testing (Off-
Line)” on page 232.
Mask Broadcast Command Received Bit.
If the BCRME bit 0 is logic 1 in the BC Configuration Register 0x0032,
then this Control Word bit is a “mask bit” like bits 14-9, acting upon the BCR
Broadcast Command Received bit 4 in the received RT Status Word:
•
If this MASKBCR Control Word bit is logic 0 and the Broadcast
Command Received bit 4 is logic 1 in the received RT Status Word, a
“Status Set” condition will result.
•
If this MASKBCR Control Word bit is logic 1, the Broadcast Command
Received bit 4 in the received RT Status Word has no effect on the
outcome for a “Status Set” condition.
5
MASKBCR
R/W
0
If the BCRME bit 0 is logic 0 in the BC Configuration Register 0x0032,
then this MASKBCR Control Word bit reflects the expected state of the
Broadcast Command Received bit 4 in the received RT Status Word:
•
If this MASKBCR Control Word bit does not match the logic state
of the Broadcast Command Received bit 4 in the received RT Status
Word, a “Status Set” condition will result.
•
If this MASKBCR Control Word bit matches the logic state of the
Broadcast Command Received bit 4 in the received RT Status Word,
then the Broadcast Command Received bit 4 in the received RT Status
Word has no effect on the outcome for a “Status Set” condition.
See Table 8.
End of Message Interrupt.
If the BCEOM bit 3 is logic 1 in the BC Interrupt Enable Register 0x0010, an
EOM interrupt will occur upon message completion, if this Control Word bit
is logic 1.
4
3
EOMINT
R/W
R/W
0
0
Reserved
This bit is not used.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
2
1
0
MCODFMT
BCSTFMT
RTRTFMT
Mode Code Message Format.
Broadcast Message Format.
RT to RT Message Format.
The combination of these three Message Format bits selects the MIL-STD-
1553B message type:
Mode
Code Bit 2
Broadcast RT-RT
Message Type
Bit 1
Bit 0
0
0
0
BC-to-RT if the T/R bit * equals logic 0
RT-to-BC if the T/R bit * equals logic 1
R/W
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
RT-to-RT
Broadcast BC-to-RT
Broadcast RT-to-RT
Mode Code Command
Do Not Use
Broadcast Mode Code Command
Do Not Use
* Transmit / Receive bit in Command Word
Note: Bit 0 must be logic 1 for RT-RT messages. This is the single control
point enabling the 16-word Control Block that configures RT-RT messages.
10.4.2. Time to Next Message Word
The HI-613x Bus Controller provides a programmable delay for Time to Next Message. This word in the Message
Control / Status Block specifies the delay from the start of this message, to the start of the next message. The delay is
programmable with 1 µs per LSB resolution, and has a maximum value of 65.535 milliseconds.
When the specified Time to Next Message value is less than the actual time required to transact the current message,
the next message starts immediately upon completion current message, after the minimum inter-message gap time of
4µs. This gap corresponds to a bus “dead time” of 2µs.
10.4.3. Data Block Pointer
The Data Block Pointer in the Message Control / Status Block provides the starting address in RAM for storage of
message data words or mode code data. For BC-to-RT (receive) commands, this pointer contains the RAM location
for the first data word transmitted by the BC.
For RT-to-BC (transmit) commands or RT-to-RT commands, this pointer contains the RAM location for storing the first
data word transmitted by the RT (and received by the BC).
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HI-6130, HI-6131
10.4.4. BC Block Status Word
1
0
Y
R
Y
G
R
A
T
T
EOM SOM BID MBCESTATFSET TM LBE MSTA
R
TSETR
GDB W
LE SE IWE
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
4
3
2
1
0
The Block Status Word in the Message Control / Status Block provides information regarding message status (in-
process or completed), the bus it was transmitted on, whether errors occurred during the message, and the type of
occurring errors. This word is written into RAM by the device after message completion. Because it resides in RAM,
the host has read-write access, although this word is usually treated as read-only by the host.
Bit No. Mnemonic
R/W Reset Function
End of Message.
This bit is set upon completion of a BC message, whether or not errors
occurred. When EOM is set, the current value of the Time Tag Word(s) is
(are) written to the corresponding Time Tag Word(s) in the BC Message
Control/Status Block.
15
EOM
R/W
0
Start of Message.
This bit is set at the start of a BC message and cleared at the end of the
message. When SOM is set (and reset), the current value of the Time Tag
Word(s) is (are) written to the corresponding Time Tag Word(s) in the BC
Message Control/Status Block.
14
13
SOM
BID
R/W
R/W
0
0
Bus ID (Bus B / Bus A).
This bit is logic 1 if the BC message was transacted on Bus B.
This bIt is logic 0 if the BC message was transacted on Bus A.
Message Block Coding Error.
A programming test aid, this bit only applies when CHKFMT bit 13 is logic
1 in the BC Configuration Register. Each message BC Control Word has
flags that indicate format: mode code command (bit 2), RT-RT message
(bit 1) and broadcast message (bit 0). When CHKFMT is 1, these flags
are compared to the message Command Word(s) that follow the Control
Word in the Message Block. When message format mismatch occurs (a
BC programming error), this MBCE bit is set in the message Block Status
Word. See CHKFMT description in “BC (Bus Controller) Configuration
Register (0x0032)” on page 73.
12
MBCE
R/W
0
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Status Set.
This bit is not affected by the values of mask bits 14-9 in the BC Control
Word for the message.
This bit is logic 1 when the received RT Status Word contains an
unexpected bit value in the bit 10-0 range. The expected value is usually
logic 0 for bits 10-0 in the received RT Status Word.
11
STATSET
R/W
0
Exception: the expected value for Broadcast Command Received bit 4 in
the received RT Status Word is logic 1 when BCRME bit 0 is logic 1 in the
BC Configuration Register 0x0032, and MASKBCR bit in the BC Control
Word bit is logic 0
Format Error.
This bit is logic 1 when a received RT response violates MIL-STD-1553
message validation criteria. This includes sync, word count, encoding, bit
count or parity errors. Word bits 2-0 provide additional information. This
flag is also set when the received RT Status Word response from the last
message contained an incorrect RT address field.
10
FE
R/W
R/W
0
0
No Response Timeout Error.
This bit is logic 1 when an RT fails to respond, or responds later than
the BC No Response Timeout interval specified by bits 15-14 in the BC
Configuration Register 0x0032.
9
TM
Loopback Error.
The HI-613x BC evaluates its own 1553 message transmissions. The
received version of each word transmitted by the BC is checked for 1553
validity (sync, encoding, bit count and/or parity error). In addition, for each
message transacted, the received image for the last word transmitted by
the BC is evaluated for data match.
8
LBE
R/W
0
This bit is logic 1 when the received version for one or more words
transmitted by the BC fails 1553 “word validity” criteria, and/or the
received version for the last word transmitted by the BC does not match
the Manchester II word transmitted by the BC.
Masked Status Set.
This bit is logic 1 when any of the following conditions occurs:
•
One or more of the mask bits 14-9 in the BC Control Word is logic 0
and the corresponding bit is logic 1 in the received RT Status Word.
•
Or the BCRME bit 0 is logic 1 in the BC Configuration Register 0x0032
and the MASKBCR bit in the BC Control Word is logic 0 and the
Broadcast Command Received bit 4 is logic 1 in the RT Status Word.
7
MSTATSET R/W
0
•
•
Or the BCRME bit 0 is logic 0 in the BC Configuration Register
0x0032 and the MASKBCR bit in the BC Control Word differs from
the Broadcast Command Received bit 4 in the RT Status Word.
Or the received RT Status Word contains an RTAddress field different
from the RT Address field in the transmitted Command Word.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Retry Count 1 and Retry Count 0
If BCRE (BC Retry Enable) bit 12 is logic 1 in the BC Configuration
Register 0x0032 and RTRYENA bit 8 is logic 1 in the BC Control Word
for this message, the BC will retry the message if RT response timeout or
Format Error occurs.
Also, if BCRE (BC Retry Enable) bit 12 is logic 1 and BCRSB (BC Retry
if Status Word Bits Set) bit 8 is logic 1 in the BC Configuration Register
0x0032 and RTRYENA bit 8 is logic 1 in the BC Control Word for this
message, the BC will retry the message when a “Status Set” condition
occurs. See “MSTATSET” bit 7 description above.
6
5
RTRY1
RTRY0
R/W
0
The combination of these two bits indicates the number of times this
message was retried:
RTRY1 Bit 6
RTRY0 Bit 5
Number of Retries
0
0
1
1
0
1
0
1
0
1
2
Not Used
Good Transmit Data Block Transfer.
This bit is set to logic 1 upon successful completion of an error-free RT-to-
BC message, RT-to-RT message, or transmit mode code message with
data. This bit always resets to logic 0 for any BC-to-RT message, mode
code message without data, or any incomplete or invalid message.
4
GDB
R/W
0
This bit may be used for determining when the transmit portion of an
RT-to-RT message is error-free. If this bit and Error Flag bit 12 are both
set to logic 1 in the Block Status Word for an RT-to-RT message, the
transmitting RT responded correctly but error occurred in the receiving RT
portion of the message.
Wrong RT Address and/or No Gap.
This bit is logic 1 when one or both of the following conditions occur
•
the RT address field within a received RT Status Word does not match
the RT address field in the Command Word transmitted by the BC
3
WAG
R/W
0
•
the BCGCE BC Gap Check Enable bit 1 in the BC Configuration
Register 0x0032 and the RT responds with response time less than
4 µs per MIL-STD-1553B, mid-parity bit to mid-sync, (2 µs bus “dead
time”).
Word Count (Length) Error.
This bit is logic 1 when an RT-to-BC message, RT-to-RT message, or
transmit mode code message with data is transacted with the wrong
number of data words.
2
1
LE
SE
R/W
R/W
0
0
This bit always resets to logic 0 for BC-to-RT messages, receive mode
code messages, or transmit mode code messages without data.
Sync Error.
This bit is logic 1 when an RT responds with Data Sync in its Status Word,
or with Command/Status Sync in a Data Word.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Invalid Word Error.
This bit is logic 1 when an RT response in one or more words having
at least one of the following errors: sync encoding error, Manchester II
encoding error, bit count error, parity error.
0
IWE
R/W
0
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HI-6130, HI-6131
11. BUS CONTROLLER REGISTER DESCRIPTION
In addition to the registers described here, a HI-6131 Bus Controller also utilizes one or more Memory Address Pointer
registers (described in Section 9.10) for managing SPI read/write operations. This comment does not apply for parallel
bus interface HI-6130 designs.
11.1. BC (Bus Controller) Configuration Register (0x0032)
BCTOC0HKFBMCTREBC2RBECR1BACR2BACRSMBENDBVSYNBDCVGTBECWDTTESYENTETNSYBNCGCBECRME
BCTO1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit No. Mnemonic
R/W Reset Function
BC Time Out Select.
This 2-bit field selects the BC “no response” time-out delay from four
available selections. Excluding RT-RT commands, response delay is
measured from command word mid-parity bit to status word mid-sync:
Bit 11:10
Bus Dead Time
Time Out (excludes RT-RT)
00
01
10
11
15μs
20μs
58μs
138μs
17μs
22μs
60μs
140μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This
adds 42µs for the embedded parity half-bit, transmit command word,
transmit-RT status word and data half-sync within this interval:
15 − 14 BCTO1:0
R/W
0
TxRT Bus Dead
Bit 11:10
RT-RT Time Out*
Time
00
01
10
11
18μs
23μs
58μs
138μs
60μs
65μs
100μs
180μs
*Note: per RT Validation Test Plan, Fig. 8.
All time out select values have –100ns / +500ns tolerance.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Check Message Format.
When this bit equals logic 1, BC Control Word message format bits
2-0 (mode command, RT-RT message and broadcast flags) are
compared to values for the message Command Word(s) that follow the
Control Word in the Message Block. This is provided as a BC program
development aid.
When the CHKFMT bit is logic 1 and message format mismatch
occurs, the MBCE Message Block Coding Error bit 12 is set in the
message Block Status Word (see Section “10.4.4. BC Block Status
Word” on page 69). If enabled, BC Trap interrupt is generated (see
Section “11.15.3. Bus Controller (BC) Interrupt Output Enable Register
(0x0014)” on page 90).
13
CHKFMT
R/W
0
When the CHKFMT bit is logic 0, no format checking occurs between
BC Control Word bits 2-0 and the MIL-STD-1553 message Command
Word(s). Even with message format checking disabled, BC Control
Word bit 0 must be logic 1 for RT-RT messages. This is the single
control point enabling the 16-word BC Control Block that configures an
RT-to-RT message.
BC Retry Enable.
If bit 12 equals logic 0, command retries are disabled for all messages.
If bit 12 equals logic 1, command retries can be enabled on an
individual message basis by setting bit 8 in the BC Control Word for all
messages to be retried.
12
11
BCRE
R/W
R/W
0
0
BC Second Retry Enable.
If retries are enabled (register bit 12 equals 1) this bit selects the
number of retries performed, If bit 11 equals logic 0, a single retry is
performed. If bit 11 equals logic 1, up to two retries are performed.
BC2RE
BC First Retry Use Alternate Bus.
If retries are enabled (register bit 12 equals 1) this bit selects the bus
used for the first retry. If bit 10 equals 0, the first retry is performed on
the same bus from which the message was originally transmitted. If bit
10 equals 1, first retry is performed on the alternate bus from which the
message was originally transmitted.
10
BCR1A
BCR2A
R/W
R/W
0
0
BC Second Retry Use Alternate Bus.
If first and second retries are enabled (register bits 12:11 equal 1-1)
this bit selects the bus used for the second retry. If bit 9 equals 0, the
second retry is performed on the same bus where the message was
originally transmitted. If bit 9 equals 1, second retry is performed on the
alternate bus from where the message was originally transmitted.
9
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
BC Retry If Unmasked Status Word Bit Set.
This bit affects operation of BC retries. If bit 8 equals logic 0, the BC
will not retry messages because of status bit(s) set in the RT Status
Word, or Status Word with non-matching RT address field.
If retries are enabled and bit 8 equals logic 1, the BC will retry
messages for these RT status word results:
1. One or more BC Control Word mask bits 14-9 is logic 0 (bits are
not masked) and the corresponding bit is logic 1 in the received RT
Status Word.
8
BCRSB
R/W
0
2. The BCR Mask Enable bit 0 equals 0 in the BC Configuration
Register 0x0032. The Broadcast Command Received (BCR) bit in
the received RT Status Word differs from the Mask BCR bit (bit 5) in
the BC Control Word.
3. Received Status Word RT address does not match Command Word
RT address.
Message Error Status, No Data is Valid
Bit 7 affects BC validation of RT responses to transmit commands
when the Message Error (ME) bit is asserted in the received RT Status
Word.
When the MENDV bit equals logic 0:
•
When an RT responds Message Error status to a transmit
command, the response is valid only if the Status Word is followed
by the commanded number of data words. Message result:
7
MENDV
R/W
0
Condition
Block Status Word
Condition Code Register
Commanded
number of data
words
Good Data Block
(GDB) bit = 1
Good Data Block Transfer
(GDBT) bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If MEMASK =
1 in BC Control
Word
Status Set
(STATSET) bit = 1.
----------
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
•
If the RT responds Message Error status to a transmit command
with the wrong number of data words or no data words, here is the
message result:
Condition
Block Status Word Condition Code Register
Wrong number of (or
no) data words
Format Error (FE)
bit = 1
Format Error (FMTERR)
bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If MEMASK = 1 in
BC Control Word
Word Count Error
(LE) bit = 1.
Bad Message (BADMSG)
bit = 1
Status Set
(STATSET) bit = 1.
----------
MENDV
7
R/W
0
(continued)
When the MENDV bit equals logic 1:
When an RT responds Message Error status to a transmit
•
command, the response is valid with the commanded number of
data words, or ME status with no data words. Here is the message
result:
Condition
Block Status Word Condition Code Register
Commanded # of
data words only,
“Good Data” is not
shown if no data
Good Data Block
(GDB) bit = 1
Good Data Block Transfer
(GDBT) bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If MEMASK = 0 in
BC Control Word
Status Set
(STATSET) bit = 1.
----------
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
•
If the RT responds Message Error status to a transmit command
with the wrong number of data words (not 0), here is the message
result:
Condition
Block Status Word Condition Code Register
Wrong number of
data words
Format Error (FE)
bit = 1
Format Error (FMTERR)
bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If MEMASK = 0 in
BC Control Word
Word Count Error
(LE) bit = 1.
Bad Message (BADMSG)
bit = 1
Status Set
(STATSET) bit = 1.
----------
The only 3 cases when an RT transmits Message Error status onto the
bus:
1. An RT using “illegal command detection” receives an illegal command
that otherwise meets all other validation requirements. The RT
responds with Status Word only, with Message Error bit set. No data
words are sent.
MENDV
7
R/W
0
(continued)
2. An RT receives a “transmit status” mode command (MC2). The
previous valid command for the RT had Message Error status. The
RT responds with Status Word only, with Message Error bit set. No
data words are sent.
3. An RT receives a “transmit last command” mode command (MC18
decimal). The previous valid command for the RT set Message Error
status. The RT responds with Status Word (with Message Error bit
set) and one data word, the previous Command Word.
In summary, Message Error status never occurs with more
than one data word, and only occurs with one data word for the
“transmit last command” mode code.
Besides illegal command detection, there is just one situation where
Message Error status occurs, but Status transmission is suppressed:
The RT detects a valid receive command having correct RT address,
but an invalid word is detected in the accompanying data words, or a
gap occurs between words. In this situation, Message Error status
is set but the RT suppresses its Status Word transmission. This
suppressed ME status is only seen by the BC if retrieved by a following
“transmit status’’ or “transmit last command” mode command.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Busy Status, No Data, is Valid
Bit 6 affects BC validation of RT responses to transmit commands when
the Busy bit is asserted in the received RT Status Word.
When the BSNDV bit equals logic 0:
When an RT responds Busy status to a transmit command, the
response is valid only if the Status Word is followed by the commanded
number of data words. Here is the message result:
Condition
Block Status Word Condition Code Register
Commanded number
of data words
Good Data Block
(GDB) bit = 1
Good Data Block Transfer
(GDBT) bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If BSYMASK = 1 in
BC Control Word
Status Set
(STATSET) bit = 1.
----------
•
If the RT responds Busy status to a transmit command with
the wrong number of data words or no data words, here is the
message result:
Condition
Block Status Word Condition Code Register
Wrong number of (or
no) data words
Format Error (FE)
bit = 1
Format Error (FMTERR)
bit = 1
6
BSYNDV
R/W
0
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If BSYMASK = 1 in
BC Control Word
Word Count Error
(LE) bit = 1.
Bad Message (BADMSG)
bit = 1
Status Set
(STATSET) bit = 1.
----------
When the BSNDV bit equals logic 1:
•
When an RT responds to a transmit command with Busy status,
the response is valid when accompanied by the commanded
number of data words, or accompanied by no data words. Here is
the message result:
Condition
Block Status Word Condition Code Register
Commanded # of
data words only,
“Good Data” is not
shown if no data
Good Data Block
(GDB) bit = 1
Good Data Block Transfer
(GDBT) bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If BSYMASK = 0 in
BC Control Word
Status Set
(STATSET) bit = 1.
----------
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
•
If the RT responds to a transmit command with Busy status and
the wrong number of data words (but not 0), here is the message
result:
Condition
Block Status Word Condition Code Register
Wrong number of
data words
Format Error (FE)
bit = 1
Format Error (FMTERR)
bit = 1
Masked Status Set
(MSTATSET) bit = 1.
Masked Status Set
(MSTATSET) bit = 1.
If BSYMASK = 0 in
BC Control Word
Word Count Error
(LE) bit = 1.
Bad Message (BADMSG)
bit = 1
Status Set
(STATSET) bit = 1.
----------
BSYNDV
6
R/W
0
(continued)
A busy RT is one that is functional, but cannot send or receive data
when commanded by the Bus Controller. An RT that is busy sets
the Busy bit in its Status Word responses. In response to transmit
commands, the busy terminal has no words to transmit, so only the
Status Word is transmitted. In the case of the “transmit vector word” and
transmit BIT word” mode code commands, even if the data is available
to the terminal, it is prohibited to send the data word if the Busy bit is set
in the Status Word.
There is just one defined situation in which an RT transmits Busy
status with one (and only one) data word: An RT receives a “transmit
last command” mode command (MC18 decimal). When the previous
valid command for the RT had Busy status, the RT responds with last
message status condition (with Busy bit set) and one data word, the
previous Command Word.
BC Message Gap Timer Enable.
If bit 5 is logic 0, the BC does not add delay between 1553 messages.
Message timing is paced by the time required for the BC to complete
message post processing. In this case, the minimum inter-message gap
will be used, with a bus “dead time” of approximately 6 to 9µs.
If bit 5 is logic 1, the BC Message Timer is enabled. The “Time to Next
Message” value from the Message Control Block is decremented at
1µs rate. When the count decrements from 1 to 0, the next message
starts. If the specified message gap time is less than the time needed
for the current message, the next message will start immediately after
completion of the current message. In this case, the minimum inter-
message gap will be used, with a bus “dead time” of approximately 6 to
9µs. This allows the BC to implement minor frame cycle times without
host processor intervention.
5
BCGTE
R/W
0
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Bit No. Mnemonic
R/W Reset Function
BC Watchdog Timer (WDT) Enabled.
When this bit is logic 1, if the End of Frame (EOF) interrupt bit is set
in the BC Interrupt Enable register, the BC sets the EOF bit in the BC
Pending Interrupt register when the BC Frame Timer decrements from 1
to 0.
When using this feature, it is necessary to periodically reload the Frame
Time register by means of the LFT Load Frame Time op code in the BC
message sequence control block. The loaded value must allow for the
worst-case frame time (including message retries). The WDT provides
a failsafe recovery from faults such as message sequence stuck in
repetitive loop without LFT reload, or execution jumping to the wrong
sequence.
4
BCWDTE
R/W
0
BC Time Tag Synchronization Enable
This option bit only affects the “synchronize with data” mode code
command, MC17. When this bit is logic 1, the source of the mode
data issued with the “synchronize” mode command is determined by
message BC Control Word TXTTMC17 bit 15 (see Section 10.4.1)
•
If BC Control Word TXTTMC17 bit 15 = logic 0, the “synchronize”
mode data word originates from the message data block, at the
RAM address indicated by the Data Address Pointer word.
•
If BC Control Word TXTTMC17 bit 15 = logic 1, the “synchronize”
mode data word value originates from the 16-bit BC time base
counter (or the low order 16 bits, when using the 32-bit BC time
base option). The transmitted data value is saved in the message
data block, at the address indicated by the Data Address Pointer
word.
3
TTSYNEN
R/W
0
If the TTSYNEN bit is logic 0, regardless of the state of message
Control Word bit 15, the “synchronize with data” mode command
(MC17) is always issued with mode data originating from the message
data block, at the RAM address indicated by the Data Address Pointer
word.
Even Time Tag Sync.
This bit only applies when TTSYNEN bit 3 is logic 1 and BC Control
Word TXTTMC17 bit 15 is also logic 1, selecting “synchronize” mode
data origin as time base counter. In this case, if ETTSYN is logic 1,
the transmitted time tag data word is always even; the low order bit is
always 0. When the ETTSYN bit is logic 0, the data word may be even
or odd; the LSB may be 0 or 1.
2
ETTSYN
R/W
0
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
BC Gap Check Enable.
When this bit is logic 1, the BC verifies that any transmission by a
Remote Terminal on the bus is preceded by an inter-word gap of at
least 4µs. When this minimum gap time is violated, the BC declares
the RT Status Word invalid, and the No Gap error bit is set in the Block
Status Word. Gap detection measures the time span from mid-parity of
last received word, to mid-sync of the following word (defined here as
detection of a properly encoded sync plus two bits). Measured gap time
is adjusted to evaluate just the interval of interest, corresponding to a
bus “dead time” (end-of-parity to start-of-sync) of 2µs minimum.
1
BCGCE
R/W
0
When this bit is logic 0 (strongly recommended) the BC does not
check for minimum bus “dead time” prior to start of transmission by a
device on the MIL-STD-1553 bus.
BCR Mask Enable.
This bit selects the function of BC Control Word bit 5, Mask Broadcast,
when evaluating the BCR (Broadcast Command Received) bit in RT
status words.
If BCR Mask Enable bit 0 is logic 1, then RT status word BCR bit
masking is enabled. The state of the Mask BCR bit in each BC Control
Word selectively allows or disallows BCR status testing by the BC:
•
When “Mask BCR” is logic 1 in a message’s BC Control Word (dis-
abling BCR status bit test), the value of the RT status word BCR bit
is “don’t care” in terms of affecting the occurrence of a “Status Set”
condition.
•
•
When “Mask BCR” is logic 0 in the message’s BC Control Word,
“Status Set” occurs when the BCR bit in the received RT Status
Word is logic 1.
0
BCRME
R/W
0
While broadcast commands never result in transmitted RT status,
the “Mask BCR” bit should be set in BC Control Words for “transmit
status” or “transmit last command” mode commands immediately
following broadcast messages. Setting the “Mask BCR” bit of the
message’s BC Control Word to logic 1 indicates the expected value
of the BCR bit in the received RT Status Word.
If BCR Mask Enable bit 0 is logic 0, the “Mask BCR” bit in a
message’s BC Control Word indicates the expected state of the BCR bit
in the received RT status word. In this situation, whenever the BCR bit
in the received RT status word differs from the state of the “Mask BCR”
bit in the BC Control Word, a “Status Set” condition occurs and the BC
generates a Status Set interrupt, if enabled.
Table 8 summarizes the effects of BC configuration, message Control
Word and RT Status Word on “Status Set” bit in the Block Status Word.
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Table 8. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition
BC Configuration
Register 0x0032
“BCR Mask Enable”
bit 0
Received BCR bit
4 in the Remote
Terminal Status
Word
Message Control
Word “Mask BCR”
bit 5
Resultant Block
Status Word “Status
Set” bit 11
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
0
1
X
0
1
0
11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
This register is initialized with the base address of the re-locatable BC Instruction List in device RAM.
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is Read-Only and is fully maintained by the device. When the bus controller is enabled, setting
BCSTRT bit 13 in the Master Configuration Register begins bus controller operation. The device copies the Instruction
List base address from register 0x0033 into this register. This pointer references pairs of words in the BC instruction
list. Each word pair is comprised of an op code word followed by a parameter word. Pointer update occurs just before
execution of the next BC instruction list op code, after execution of the prior op code, and evaluation of its result-
dependent outcome.
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11.4. Bus Controller (BC) Frame Time Remaining Register (0x0035)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is Read-Write. A value is written to this register upon execution of the BC instruction list op code,
“Load Frame Timer” (LFT). Time remaining value begins decrementing upon execution of the Start Frame Timer (SFT)
instruction op code. The parameter word accompanying the op code word is the desired time value, expressed with a
resolution of 100 µs per LSB, with a maximum value of 6.5535 sec.
11.5. Bus Controller (BC) Time To Next Message Register (0x0036)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is Read-Only. This programmable time-to-next message timer is loaded on a message-by-mes-
sage basis, with values from word 4 in each Message Control / Status Block. The BC time-to-next message is defined
as the time from the start of the current message to the start of the next message, i.e., mid-sync zero crossing to the
next mid-sync zero crossing. This timer provides a 1 µs per LSB resolution, with a maximum value of 65.535 ms.
11.6. Bus Controller (BC) Condition Code Register (Read 0x0037)
1
P
G
/
Q
BCRU
R
N
ETR
R
Y
E
1
TRBYA0DMMSSGTAGTDSBETFMTENRORREGSPPF7GPF6GPF5GPF4GPF3GPF2E
LT / GP0
MR Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Host Access
Bit
R
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Sharing the same register address as the Write-Only General Purpose Flag Register, this 16-bit register is Read-Only.
Bit 15 indicates BC run/stop status. With this exception, the upper 8 bits indicate results from the last message pro-
cessed by the Bus Controller. The lower 8 bits of this register are general purpose flag bits, which may be set, cleared,
or toggled by the host using the BC General Purpose Flag Register (see page 33), or by the device by means of the
General Purpose Flag Bits (FLG) instruction op code. Further, bits 1-0 can be set or cleared by the device BC logic
by execution of two BC instruction op codes: Compare to Frame Timer (CFT) and Compare to Message Timer (CMT).
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Bit No. Mnemonic
R/W Reset Function
BC Run / Stop
This is a status bit, not a condition code. This bit indicates whether the
BC is running or stopped. The bit is set to logic 1 when the BCSTRT
bit 13 in the Master Configuration Register is asserted and the BCENA
input pin and BCENA bit 12 in the Master Configuration Register 0x0000
are both logic 1.
15
BC RUN
R
0
Once set, this bit resets to logic 0 if the BCENA input pin or BCENA
register bit are reset to logic 0 by the host, or if the BC executes the
HLT instruction, or if the BC executes an illegal op code. The “illegal
op code” case will generate a BCTRAP interrupt, if enabled (see
Section “11.15.3. Bus Controller (BC) Interrupt Output Enable Register
(0x0014)” on page 90).
Message Retry Status Bits.
Bits 14-13 indicate the retry status of the most recent message the
number of times message was retried:
14
13
RETRY 1
RETRY 0
Bit 14:13
Number of Message Re-tries
R
R
0
0
0-0
0-1
1-0
1-1
0
1
2
not used
Bad Message.
12
BADMSG
This bit is logic 1 to indicate message format error, loopback test failure,
or no response error for the last message.
Masked Status Set.
This bit is set if one or more of the following conditions occurred during
the last message:
•
One or more of the Status Mask bits 14-9 are logic 0 in the BC
Control Word, and the corresponding bits are logic 1 in the received
RT Status Word. When BC Control Word “Reserved Bits Mask” bit
9 is logic 0, this Masked Status Set bit is set if any of the three
Reserved bits are set in the received RT Status Word.
•
•
The BCR Mask Enable bit 0 is logic 0 in the BC Configuration
Register 0x0032. Opposite logic states occur for the Mask BCR
bit in the message BC Control Word and the Broadcast Command
Received (BCR) bit in the received RT Status Word.
11
MSTATSET
R
0
The BCR Mask Enable bit 0 is logic 1 in the BC Configuration
Register 0x0032. Opposite logic states prevail for the Mask BCR
bit in the message BC Control Word and the Broadcast Command
Received (BCR) bit in the received RT Status Word.
The table on page 27 shows how the Broadcast Command Received
(BCR) bit in the received RT Status Word affects Masked Status Set.
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Bit No. Mnemonic
R/W Reset Function
Good Data Block Transfer.
Indicating status for the last transmit-data message, this bit is set to
logic 1 after completion of an error-free RT-to-BC transfer, RT-to-RT
transfer, or transmit mode command with data. This bit is reset to logic
0 following any message in which error occurs. This bit is always logic
0 after completion of a BC-to-RT transfer, a receive mode command
with data, or any mode command without data. This bit can be used
to determine when the transmit portion of an RT-to-RT message was
error-free: A Block Status Word for an RT-to-RT message having both
the Error Flag and Good Data Block Transfer bits set indicates that
the transmitting RT responded correctly, but an error was detected in
the receiving RT portion of the message. This bit is not affected by the
device loop back function.
10
GDBT
R
0
Format Error.
This bit is logic 1 when the received data from the most recent message
contains one or more violations of the MIL-STD-1553 message
validation criteria, including sync, encoding, parity, bit count or word
count errors.
9
FMTERR
R
0
This bit is also set if the received Status Word from the responding RT
contains incorrect RT address bits 15:10.
No Response Error.
This bit is set to logic 1 when an RT fails to respond to a command,
or responds later then the BC No Response Timeout time. The No
Response Timeout delay is programmed using BC Timeout Select bits
15-14 in the BC Configuration Register 0x0032.
8
7 − 2
1
NORESP
GP7 − GP2
EQ / GP1
R
R
R
0
0
0
General Purpose Flags 7-2.
Interpretation of these flag bits is user defined. These bits are set
cleared or toggled by the host, through use of the BC General Purpose
Flag Register, or by the BC, through use of the FLG instruction op code.
Equal / General Purpose Flag 1.
This flag bit is manipulated using the same methods as General
Purpose Flags 7-2, or may be set or cleared by two BC instruction op
codes, Compare to Frame Time Counter (CFT) or Compare to Message
Time Counter (CMT).
Less Than / General Purpose Flag 0
This flag bit is manipulated using the same methods as General
Purpose Flags 7-2, or may be set or cleared by two BC instruction
op codes, Compare to Frame Time Counter (CFT) or Compared to
Message Time Counter (CMT).
0
LT / GP0
R
0
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11.7. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)
CLR GCPLFR7GCPLFR6GCPLFR5GCPLFR4GCPLFR3GCPLFR2GCPLFR1GSPEFT0GSPEFT7GSPEFT6GSPEFT5GSPEFT4GSPEFT3GSPEFT2GSPEFT1GPF0
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Sharing the same register address as the Read-Only BC Condition Code Register, this 16-bit register is Write-Only.
This register is written by the host to set, clear or toggle any combination of the 8 general-purpose flags 7-0 in the BC
Condition Code Register. When this register is written, general-purpose flags are modified. Reading register address
0x0037 returns the value in the BC Condition Code Register, containing the modified GP flag bits (see Section 11.6).
Each general-purpose flag in the BC Condition Code Register is mirrored twice in the General Purpose Flag Register,
once in the upper byte and once in the lower byte. Bits asserted in the lower byte set the corresponding GP flag bits
in the BC Condition Code Register to 1. Bits asserted in the upper byte clear the corresponding GP flag bits in the BC
Condition Code Register to 0. Bits asserted in both the lower and upper bytes for a specific GP flag toggles (inverts)
the corresponding GP flag bit in the BC Condition Code Register. When both bits are written to logic 0 state for a spe-
cific GP flag bit, no change occurs for that GP flag bit. The FLG instruction op code operates similarly, as shown in the
diagram in Figure 5.
Bit No. Mnemonic
R/W Reset Function
Clear General Purpose Flag 7-0.
CLEAR
15 − 8
W
0
Bits asserted in the upper byte clear the corresponding GP flag bits in
the BC Condition Code Register to 0.
GP7 − GP2
Set General Purpose Flag 7-0.
Bits asserted in the lower byte set the corresponding GP flag bits in the
BC Condition Code Register to 1. Bits asserted in both the lower and
upper bytes for GPx toggles that GP flag bit in the BC Condition Code
Register.
SET
7 − 0
W
0
GP7 − GP2
11.8. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038)
MSB
General Purpose Queue RAM Address
LSB
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
2
0
1
MR Reset
Host Access
Bit
R
RW
R
15 14 13 12 11 10
9
8
7
6
5
4
3
0
This 16-bit register is a combination of Read-Only and Read-Write bits. This register contains 0x00C0 after MR pin
master reset. The initialized value represents the base address for the 64-word BC General Purpose Queue. The host
can overwrite the default 0x00C0 value, but low order bits 5-0 and bit 15 must equal logic 0 for the initialized value.
These bits cannot be set to logic 1 by a host write cycle.
The general purpose queue provides a way for the Bus Controller message sequencer to convey various information
to the external host. The BC instruction set includes op codes that push data values onto this queue, including immedi-
ate data values, the Block Status Word from the most recent message, the Time Tag Register count, or the contents
of a specified memory address.
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The General Purpose Queue is implemented as a 64-word circular buffer. This register always points to the next
queue address to be written, the address following the last queue location written by the Bus Controller. This queue
pointer rolls over from bits 5:0 = 11111 to 00000, every 64th word written. (Bits 15:6 are static.) If enabled in the BC
Interrupt Enable Register, the BCGPQ interrupt will be generated each time queue pointer rollover occurs.
11.9. Bus Controller (BC) Time Tag Counter (0x0043)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
11.10. Bus Controller (BC) Time Tag Counter High (0x0044)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
These registers are read-only and are cleared after MR pin Master Reset. The Bus Controller can be configured for
either 16- or 32-bit time base counting in the Time Tag Counter Configuration Register. When configured for 16-bit time
base operation, register 0x0043 contains the entire 16-bit count. When configured for 32-bit time base operation, count
bits 31-16 reside in register 0x0044 while register 0x0043 contains bits 15-0.
For programmed bus controller action, instruction op codes are provided for loading a time tag count value, or pushing
the current time tag count onto the BC General Purpose Queue. If configured for 32-bit time base operation, separate
op codes are provided for loading the upper or lower words individually, or pushing the individual words or simultane-
ously pushing both words onto the BC General Purpose Queue:
Configuration
Op Code
Description
LTT
LTH
PTT
PTH
PTB
Load Time Tag Count (parameter) into register 0x0043.
Not used for 16-bit time base.
16-Bit Time
Base
Push Time Tag Count from register 0x0043 onto BC GP Queue.
Not used for 16-bit time base.
Not used for 16-bit time base.
LTT
LTH
PTT
PTH
PTB
Load Low Time Tag Count (parameter) into register 0x0043.
Load High Time Tag Count (parameter) into register 0x0044.
Push Low Time Tag Count from register 0x0043 onto BC GP Queue.
Push High Time Tag Count from register 0x0044 onto BC GP Queue.
Push Low and High Time Tag Counts from register 0x0043 and 0x0044 onto BC GP
Queue (simultaneous 32-bit count capture)
32-Bit Time
Base
The host can bypass BC Instruction List execution to exercise direct control over the BC Time Tag counter. By writing
bits 13-12 in the Time Tag Counter Configuration Register 0x0039, the host can clear time tag count to zero, or load
the current value contained in the BC Time Tag Utility Register(s) into the BC Time Tag counter(s). Finally, the BC Time
Tag Match Register(s) provide capability for host interrupts when the time tag count reaches any predetermined 16- or
32-bit value.
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11.11. Bus Controller (BC) Time Tag Utility Register (0x0045)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These registers are read-write and are cleared after MR pin Master Reset. This utility register pair is used for simul-
taneously loading a 16- or 32-bit value into the BC Time Tag Counter. When loading, the value contained in utility reg-
ister 0x003D is copied into BC Time Tag Counter register 0x0043. If the BC is configured for 16-bit time base, register
0x0043 contains the entire 16-bit count. If configured for 32-bit time base operation, count bits 31-16 are simultane-
ously copied from utility register 0x003E into BC Time Tag Counter register 0x0044. Please refer to the description for
bits 13-12 in the “Time Tag Counter Configuration Register (0x0039)” on page 45.
11.13. Bus Controller (BC) Time Tag Match Register (0x0047)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
11.14. Bus Controller (BC) Time Tag Match High Register (0x0048)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These registers are read-write and are cleared after MR pin Master Reset. When the BCTTM bit 5 is logic 1 in the
Hardware Interrupt Enable Register 0x000F, an interrupt occurs when the BC time tag count matches the value stored
in this register pair. If the BC is configured for 16-bit time base, match register 0x0045 is compared to time base count
register 0x0043 for match determination. If configured for 32-bit time base operation, count bits 31-16 in match register
0x0046 is also compared to BC Time Tag Counter register 0x0044 for match determination. Please refer to the descrip-
tion for BCTTM bit 5 in the Hardware Interrupt Registers in Section 9.7.
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11.15. Bus Controller Interrupt Registers and Their Use
Section 9.4 on page 36 through Section 9.6 describe how the host uses three Hardware Interrupt registers, the Interrupt
Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When the Bus Controller is enabled,
three additional registers are dedicated to Bus Controller interrupts. Comparable to the Hardware Interrupt register
triplet, the Bus Controller has
•
•
•
A BC Interrupt Enable Register to enable and disable interrupts
A BC Pending Interrupt Register to capture the occurrence of enabled interrupts
A BC Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding
interrupt condition is enabled. Numerous interrupt options are available for the BC. At initialization, bits are set in the
BC Interrupt Enable register to identify the interrupt-causing events for the BC which are heeded by the HI-613x. Most
Bus Controller applications only use a subset of available BC interrupt options. Interrupt-causing events are ignored
when their corresponding bits are reset in the BC Interrupt Enable Register. Setting an Interrupt Enable register bit
from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever a Bus Controller interrupt event occurs (and the corresponding bit is already set in the BC Interrupt Enable
Register), these actions occur:
•
•
The Interrupt Log Buffer is updated.
A bit corresponding to the interrupt type is set in the BC Pending Interrupt Register. The type bit is logically-ORed
with the preexisting register value, retaining bits for prior, unserviced BC interrupts.
•
BC Interrupt Pending (BCIP) bit 0 is set in the Hardware Pending Interrupt Register. The BCIP bit is logically-
ORed with the preexisting register value, retaining bits for unserviced hardware interrupts and the preexisting
status of the MTIP and RTIP (Bus Monitor and RT) interrupt pending bits.
•
If the matching bit is already set in the BC Interrupt Output Enable Register, an IRQ output occurs.
If the matching bit in the BC Interrupt Output Enable Register was not already set (i.e., low priority polled interrupt), the
host can poll the BC Pending Interrupt Register to detect the occurrence of BC interrupts, indicated by non-zero value.
Reading the BC Pending Interrupt Register automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four
Interrupt Output Enable registers (hardware, BC, RT and SMT or IMT). Multiple interrupt-causing events can occur
simultaneously, so single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.4 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
Hardware Pending Interrupt Register to indicate when BC, RT, SMT and/or IMT interrupts occur. When BCIP (BC
Interrupt Pending) bit 0 is set in the Hardware Pending Interrupt Register, the BC Pending Interrupt Register contains
a nonzero value and may be read next to identify the specific BC interrupt event(s). Or, the host can directly interrogate
the Interrupt Count & Log Address Register, followed by the Interrupt Log Buffer. Data sheet section 9.4 has a detailed
description.
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11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010)
ATSET
SELMBSCGGPBQCRECTSRTYKBECRTRRSATP BCIRQB3CIRQB2CIRQB1CIRQB0CMEBRCREORMeserRveedserRvedserved
BCWDT
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
0
RW
9
R
1
15 14 13 12 11 10
7
6
5
4
3
2
0
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007)
ATSET
BCWDSTELMBSCGGP
BQCRECTSRTYKBECRTRRSATP BCIRQB3CIRQB2CIRQB1CIRQB0CMEBRCREORMeserRveedserRvedserved
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
8
15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014)
ATSET
SELMBSCGGPBQCRECTSRTYKBECRTRRSATP BCIRQB3CIRQB2CIRQB1CIRQB0CMEBRCREORMeserRveedserRvedserved
BCWDT
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
0
RW
9
R
1
15 14 13 12 11 10
7
6
5
4
3
2
0
Three registers govern BC interrupt behavior: the BC Interrupt Enable Register, the BC Pending Interrupt Register
and the BC Interrupt Output Enable Register. When a bit is set in the BC Interrupt Enable Register, the correspond-
ing BC interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally
disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the
bit was zero.
When an enabled BC interrupt event occurs, the corresponding bit is set in the BC Pending Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, BCIP bit 0 in the Hardware Pending Interrupt Register
is also set whenever a message sets at least one bit in the BC Pending Interrupt Register.
If the corresponding bit is set in the BC Interrupt Output Enable Register, the IRQ output is asserted at message
completion. The BC Interrupt Output Enable Register establishes two priority levels: high priority interrupts generate
an IRQ output while low priority interrupts do not. Both priority levels update the Pending Interrupt Register and Inter-
rupt Log Buffer. The host can detect low priority (masked) interrupts by polling Pending Interrupt registers.
The table below first describes the common bits 15-3 in all three BC interrupt registers and then describes register-
to-register differences for bits 2-0.
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Bit No. Mnemonic
Function
BC Watchdog Timer Interrupt.
The BC Frame Timer expired.
15
14
BCWDT
BC Selected Message Interrupt.
SELMSG
The completion of a MIL-STD-1553 message that has bit 4 set (EOM) in the message
block Control Word.
BC General Purpose Queue Rollover Interrupt.
13
12
BCGPQ
The 64-word circular BC General Purpose Queue Pointer rolled over to its base address
value.
BC Retry Interrupt.
The occurrence of a retried message by the BC. If enabled, the interrupt will occur after
the last enabled message retry (one or two) regardless of the outcome, successful or
unsuccessful.
BCRETRY
BC Call Stack Pointer Error Interrupt.
The BC subroutine stack depth was violated due to an overflow or underflow condition.
Call stack level is incremented each time a BC “subroutine call” op code (CAL) is
executed. Call stack level is decremented each time a BC “subroutine return” op code
(RTN) is executed. The allowed range for the call stack level is 0-7. An interrupt occurs
when a CAL op code executes when stack level is 7, An interrupt also occurs when a
RTN op code executes when stack level is 0.
11
CSTKERR
BC Trap Interrupt.
Two conditions can assert this interrupt:
The BC fetched an illegal op code. The BC operation stops when the current 1553
message is complete. An illegal op code is either undefined, fails parity check, and/or
has the wrong value for bits 9-5. When this occurs, BCRUN bit 15 resets to logic 0 in
the BC Condition Code and GP Flag register 0x0037.
When the CHKFMT bit 13 is set in the BC Configuration Register, the BC Control Word
message format bits 2-0 (mode command, RT-RT and broadcast message flags) are
compared to the stored value(s) for the message Command Word(s) following the
Control Word in the Message Block. When mismatch occurs between Control Word
format bits and Command Word(s), the BCTRAP interrupt is asserted, if enabled. BC
instruction list execution continues, so this condition can be differentiated from illegal
op code because BCRUN bit 15 remains high in the BC Condition Code and GP Flag
register, 0x0037. For mode command or broadcast mismatch, the stored message
block Command Word(s) are transmitted. For RT-RT format mismatch, RT-RT bit 1
in the Control Word has priority, determining whether the message block is treated
as an 8- or 16-word entity. For RT-RT format mismatch, message failure is likely
for this message or the next message block, since the message block boundary
is misplaced. The CHKFMT option bit detects BC programming problems in the
development phase. The option is normally disabled in the field.
10
BCTRAP
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Bit No. Mnemonic
Function
BC Status Set Interrupt.
The BC received an RT Status Word containing the wrong RT address field, or having
an unexpected bit value for at least one of the eight non-reserved status bits. The
expected value for these bits (excluding the BCR bit) is usually 0.
9
STATSET
The BCR (broadcast command received) bit can have an expected value of 1 when
BCR Mask Enable bit in the BC Configuration Register is logic 0. In this case, the
Mask Broadcast bit in the message block Control Word shows the expected value
of the Status Word BCR bit. If the Control Word’s Mask Broadcast bit is logic 1, the
expected value of BCR in the RT Status Word is logic 1.
BC Interrupt Request Bits 3-0.
When this 4-bit field is nonzero, the BC executed an IRQ op code. The value of bits 8:5
will equal the value of the 4 LSBs in the parameter associated with the IRQ op code.
The user may define the 4- bit pattern to suit application requirements.
8 − 5
BCIRQ3:0
BCMERR
BC Message Error Interrupt.
4
A non-broadcast message ended with RT Status Word containing the ME Message
Error status bit set.
BC End of Message Interrupt.
3
BCEOM
The successful completion of a message, regardless of validity.
2 − 0
Reserved
Bits 2-0 cannot be written, and read back 000.
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12. SIMPLE MONITOR TERMINAL (SMT)
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Monitor, requiring minimal host support. Two
fundamentally different monitor modes are offered. Each of these modes has a separate data sheet section describing
registers used and operational details. Information regarding the alternative IRIG-106 Monitor Terminal (IMT) begins
in Section 14.
12.1. Overview
Simple Monitor Terminal (SMT) Mode has its own dedicated Time Tag counter, and can use either a 16- or 48-bit
Time Tag scheme. The SMT monitor utilizes two circular buffers in RAM: a Command Buffer and a Data Buffer. Each
recorded MIL-STD-1553 message appends a fixed length entry into the Command Buffer and a variable length entry
into the Data Buffer.
The SMT message records a fixed length “message block” in the Command Buffer for each MIL-STD-1553 message.
The advantage of fixed length Command Buffer message blocks is that the host can quickly jump to the block start
address for any message.
The number of words added to the Data Buffer for each message depends on the MIL-STD-1553 message type,
ranging from zero (broadcast mode command without data) to 35 words (for a 32 data word RT-RT command).
In SMT mode, both circular buffers are fully utilized for recording message data. Unlike IMT mode, there is no option for
generating a data header or data trailer. SMT monitor mode allows selective monitoring of MIL-STD-1553 messages,
based on the address, subaddress and T/R status in each monitored Command Word, or can monitor all messages,
when preferred. The SMT monitor offers flexible interrupt options.
In Master Configuration Register 0x0000, MTENA bit 8 is logically ANDed with the MTRUN input pin to enable the SMT
monitor. If the MTRUN input pin or Master Configuration Register bit 8 equals logic 0, Bus Monitor operation is disabled.
When the pin and Master Configuration Register MTENA bit 8 are both logic 1, the Bus Monitor is enabled. Operation
commences when the receiver first decodes MIL-STD-1553 activity meeting the “start record” criteria selected by bits
6-5 in the MT Configuration Register 0x0029. If monitor operation is underway when Master Configuration Register
MTENA bit 8 or MTRUN input pin becomes logic 0, monitor operation stops after completion of any message already
underway.
The HI-613x is configured for SMT operation by writing bits 1-0 in the MT Configuration Register 0x0029.
When MT Configuration Register bits 1-0 equal 11, the SMT operates with 16-bit Time Tag resolution and each recorded
MIL-STD-1553 message adds a four word entry in the Circular Command Buffer. This is summarized in Table 9.
Table 9. Message Block in Circular Command Buffer for SMT Monitor using 16-bit Time Tag
Message
Word
Block
Word Name Word Function when using 16-bit time tag
Message Command Word.
Message
The MIL-STD-1553 Command Word that initiated the message.
Command
Word 3
Word 2
For an RT-RT message, Receive Command Word 1 is stored here; Transmit Command
Word 2 is the first stored word in the Message Data Block.
Word
Data Block
Pointer
Starting address in the Data Buffer for the corresponding message data block.
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Message
Word
Word Name Word Function when using 16-bit time tag
Block
Message
Time Stamp
Bits 15 ~ 0
Sixteen bit message time stamp.
Word 1
Word 0
Word 0 is the first word in the Command Buffer entry for each message.
Message Block Status Word, defined in Section 12.2.
Block Status
Word
Word 0 is the first word in the Command Buffer entry for each message.
When MT Configuration Register bits 1-0 equal 01, the Simple Message Monitor operates with 48-bit Time Tag
resolution. Each MIL-STD-1553 message adds an 8-word entry in the Circular Command Buffer. This is summarized
in Table 10. The expanded message block accommodates two additional Time Tag words, a Message Length word
and a Response Time word not found when using 16-bit Time tag resolution.
Table 10. Message Block in Circular Command Buffer for SMT Monitor using 48-bit Time Tag
Message
Word
Block
Word Name Word Function when using 16-bit time tag
Message Command Word.
Message
The MIL-STD-1553 Command Word that initiated the message.
Command
Word 7
For an RT-RT message, Receive Command Word 1 is stored here; Transmit Command
Word
Word 2 is the first stored word in the Message Data Block.
Data Block
Pointer
Word 6
Word 5
Starting address in the Data Buffer for the corresponding message data block.
Message
Length Word
(bytes)
The Message Length Word indicates the number of bytes stored in the Message Data
Block. The range is 0 to 70 bytes, corresponding to 0 to 35 16-bit words stored.
The Response Time Word contains two 8-bit fields:
•
•
Bits 15 ~ 8 contains GAP2
Bits 7 ~ 0 contains GAP1
All GAP values are measured from mid-parity zero crossing of the preceding word, to
the mid-sync zero crossing of the Status Word (the gap “dead time” interval plus 2 µs).
Time resolution is 100 ns per LSB, so the maximum indicated gap time for GAP1 or
GAP2 is 25.5 µs.
Response
Time Word
Word 4
For RT-RT messages, the GAP1 byte indicates transmit RT response time, and the
GAP2 byte indicates received RT response time.
For all other messages, the GAP1 byte indicates the only RT response time, and the
GAP2 byte reads 0x00.
Block Status
Word
Word 3
Message Block Status Word, defined in Section 12.2.
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Message
Word
Word Name Word Function when using 16-bit time tag
Block
Message
Word 2
Word 1
Word 0
Time Stamp Upper 16-bit word of message 48-bit time stamp.
Bits 47 ~ 32
Message
Time Stamp Middle 16-bit word of message 48-bit time stamp.
Bits 31 ~ 16
Message
Time Stamp
Bits 15 ~ 0
Lower 16-bit word of message 48-bit time stamp.
Word 0 is the first word in the Command Buffer entry for each message.
The Circular Command Buffer address range is bounded by the values in Address List Words 0 and 2. The Circular
Data Buffer address range is bounded by the values in Address List Words 4 and 6. The “Next Address” Words 1 and
5 must be initialized by the host for the first data written after reset, usually to match the Word 0 and Word 4 values
respectively. Thereafter, these values are maintained by the device each time a new MIL-STD-1553 message is
recorded.
Two optional Buffer address interrupts are offered. When enabled, a Command or Data Buffer Address Interrupt
occurs whenever the matching RAM address in the Buffer is written. The Address List contains the address values for
these optional “buffer utilization” interrupts.
For SMT mode, the 8-word Monitor Address List is defined in Table 11.
Table 11. Monitor Address List for SMT Mode
Address
Word Name Description
List Word
Host initialized with a RAM address value if this interrupt is enabled.
Data Buffer
Word 7
Word 6
Word 5
Interrupt
Address
If enabled, an interrupt occurs when the matching RAM address is written.
Address must occur within the range bounded by Words 4 and 6.
Data Buffer
End Address
Host initialized, defines SMT Data Buffer upper (rollover) address.
Must be host initialized, usually to match SMT Data Buffer Start Address.
Updated by device each time a new MIL-STD-1553 message is recorded.
This value advances through the address range in circular buffer fashion.
Data
Buffer Next
Address
Data
Word 4
Word 3
Buffer Start Host initialized, defines SMT Data Buffer lower address boundary.
Address
Command
Buffer
Interrupt
Address
Host initialized with a RAM address value if this interrupt is enabled.
If enabled, an interrupt occurs when the matching RAM address is written.
Address must occur within the range bounded by Words 0 and 2.
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Address
List Word
Word Name Description
Command
Word 2
Word 1
Word 0
Buffer End
Address
Host initialized, defines SMT Circular Command Buffer upper (rollover) address.
Must be host initialized, usually to match Command Buffer Start Address.
Updated by device each time a new MIL-STD-1553 message is recorded.
This value advances through the address range in circular buffer fashion.
Command
Buffer Next
Address
Command
Buffer Start
Address
Host initialized, defines SMT Circular Command Buffer lower address boundary. Word 0
occurs at the Address List base address in register 0x002F.
For each monitored MIL-STD-1553 command, the written Command Buffer entry is fixed at 4 or 8 words, depending
on selected Time Tag resolution. Depending on MIL-STD-1553 message type, the written Data Buffer entry varies
in length, ranging from zero words (for broadcast mode code commands without data) to 35 words (for an RT-to-RT
message with 32 data words). Simple Monitor Terminal Data Storage is summarized in Figure 7.
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Data
Buffer
Command
Buffer
Non-Broadcast
Message Types
Corresponding
Broadcast
Messages
Data Words
for Message N+1
Command Word
for Message
1-32 Data Words:
Data N
.........
Data 1
Data Words
for Message N
Data Block Pointer
for Message
Transmitting RT
Status Word
Message Time
Stamp, Bits 15-0
RT-to-BC
(Transmit) Command
No Broadcast
Version
Data Words
for Message N-1
Block Status Word
for Message
Receiving RT
Status Word
Data
Buffer
1-32 Data Words:
1-32 Data Words:
Command
Buffer
Data N
Data N
.........
.........
Data Buffer Blocks
for Each Message
Data 1
Data 1
BC-to-RT
(Receive) Command
Broadcast BC-to-RT
(Receive) Command
Command Buffer
Single Message Block
Initialized for 16-bit Time Stamp
Register 0x0029 Bits 1-0 equal 01
Receiving RT
Status Word
1-32 Data Words:
1-32 Data Words:
Data N
Data N
.........
.........
Data
Data 1
Data 1
Command
Buffer
Transmitting RT
Status Word
Transmitting RT
Status Word
Buffer
Command Word 2
to Transmit RT
Command Word 2
to Transmit RT
Data Words
for Message N+1
Command Word
for Message
RT-to-RT
Command
Broadcast RT-to-RT
Command
Data Words
for Message N
Data Block Pointer
for Message
Message Length
Word
Mode Data Word
Data Words
for Message N-1
Transmitting RT
Status Word
Response Time
Word
Data
Buffer
Transmit Mode Code
With Data
No Broadcast
Version
Block Status Word
for Message
Data Buffer Blocks
for Each Message
Receiving RT
Status Word
Message Time
Stamp, Bits 47-32
Mode Data Word
Mode Data Word
Message Time
Stamp, Bits 31-16
Receive Mode Code
With Data
Broadcase Receive
Mode Code With Data
Message Time
Stamp, Bits 15-0
For Broadcast Mode
Codes Without Data
(MC0 - MC15)
No Status or Data
Words Are Recorded
RT Status Word
Command
Buffer
Increasing
Memory
Address
Transmit or Receive
Mode Code Without Data
Command Buffer
Single Message Block
The number of words stored in the Data Buffer varies
from message to message, based on message type.
Initialized for 48-bit Time Stamp
Register 0x0029 Bits 1-0 equal 11
Figure 7. Simple Monitor Terminal (SMT) Data Storage
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12.2. SMT Block Status Word (BSW) Description
The SMT bus monitor stores a Block Status Word in the Circular Command Buffer for each monitored MIL-STD-1553
message. This word provides information regarding message status, the bus on which the message occurred, whether
errors occurred during the message, and the type of occurring errors. The Block Status Word for SMT mode is defined
as follows:
d
EOM SOM BID EO RR IGE TM GDB DSR ReserLvEe SE WE RRGSRARCWC2WCE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SMT Block Status Word
with Extended Status Bits Enabled
(Not IRIG-106 Chapter 10 Compliant)
Bit No. Mnemonic
R/W Reset Function
End of Message.
15
EOM
R/W
0
Bit 15 is set upon completion of a monitored message, whether or not
errors occurred. When EOM is set, SOM bit 14 is concurrently reset.
Start of Message.
Bit 14 is set to logic 1 approximately 3-4 µs after completion of a valid
Command Word, and is reset to logic 0 at the end of the message.
If the monitor uses message filtering, SOM is only set for monitored
messages.
14
SOM
R/W
0
Bus ID (Bus B / Bus A).
Bit 13 indicates the bus ID for the message. This bit is logic 0 for a
message occurring on Bus A. This bit is logic 1 for a message occurring
on Bus B.
13
BID
R/W
0
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Bit No. Mnemonic
R/W Reset Function
Error Occurred Flag.
This bit indicates a message error was encountered. This bit is set when
one or more of the following conditions are true (logical-OR):
•
•
•
•
•
•
•
•
•
an unfinished message is superseded by another valid command
Bit 10 Illegal Gap Error is set
Bit 9 Response Timeout is set
Bit 5 Length (Word Count) Error is set
Bit 4 Sync Type Error is set
Bit 3 Invalid Word Error is set
Bit 2 RT-RT Gap / Sync / Address Error is set
Bit 1 RT-RT Command Word 2 Error is set (except as noted)
Bit 0 Command Word Content Error is set (except as noted)
12
EO
R/W
0
There are three exceptions where register bit 0 or 1 is set without
affecting bit 12 state:
Bit 1 RT-RT Command Word 2 Errors that do not assert bit 12
•
RT-RT Transmit Command Word 2 subaddress field equals 00000
or 11111 (mode code command indicated)
•
RT-RT Transmit Command Word 2 has the same RT Address as
Receive Command Word 1
Bit 0 Command Word Content Error that does not assert bit 12
•
Undefined receive mode code 0~15 decimal.
RT-to-RT Transfer
11
10
RR
R/W
R/W
0
0
When logic 1, bit 11 indicates an RT-to-RT message, beginning with two
contiguous Command Words.
Illegal Gap Error
IGE
When logic 1, bit 10 indicates an illegal gap occurred on the bus, other
than Response Timeout.
Response Timeout
When logic 1, bit 9 indicates a response timeout occurred. This bit is
set if an RT Status Word associated with this message failed to arrive
within the response time interval specified by bits 15-14 in the MT
Configuration Register 0x0029.
9
8
TM
R/W
R/W
0
0
Good Data Block Transfer
Bit 8 is set to logic 1 following completion of a valid, error-free message.
This bit is reset to logic 0 following completion of a message in which
error occurred. If an RT responds to a transmit command with Busy
status and does not transmit the commanded data words, this is not
considered a message error that causes GDB reset.
GDB
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Bit No. Mnemonic
R/W Reset Function
Data Buffer Rollover
Bit 7 is logic 1 to indicate that this message overran the monitor Data
Buffer end address, causing the storage pointer to roll over to the base
address.
7
6
DSR
SFS
R/W
R/W
0
0
Status Flag Set
Bit 6 is logic 1 when a status bit was set in an RT Status Word response.
Word Count (Length) Error
Bit 5 indicates that the number of data words transmitted by the BC or
RT differs from the Word Count specified in the Command Word. An RT
Status Word with the Busy bit set will not cause Word Count Error. A
transmit command with Response Timeout will not cause Word Count
Error.
5
LE
R/W
0
Sync Type Error
Bit 4 is logic 1 to indicate that a BC transmitted data sync with a
Command Word, or a command / status sync occurred with Data Word,
or an RT responded with data sync in its Status Word and/or command/
status sync in a Data Word.
4
3
SE
R/W
R/W
0
0
Invalid Word Error (WE)
Bit 3 is logic 1 indicate on invalid word error occurred. This includes
Manchester decoding errors in the sync pattern or word bits, or the
wrong number of bits in the word, or parity error.
WE
RT-to-RT Gap/Sync/Address Error (RRGSA)
Bit 2 is logic 1 if one or more of the following RT-RT message conditions
occur:
•
MT Gap Check is enabled (bit 12 equals 1 in register 0x0029) and
an RT Status Word is received having a response time less than
4µs, per MIL-STD-1553B (mid-parity to mid-sync). In other words,
the bus “dead time” was less than 2µs.
2
RRGSA
R/W
0
•
•
One of the RTs responds with an invalid Status Word, having a sync
error, a Manchester encoding error, bit count error and/or parity error
One of the RT Status Words contains an RT Address that differs
from the RT Address in the corresponding Command Word.
RT-to-RT Command Word 2 Error (RRCW2)
Bit 1 is logic 1 if an RT-to-RT message occurs (two contiguous
Command Words) with one or more of the following illogical conditions:
•
•
Transmit Command Word 2 T/R bit equals 0 (receive)
1
RRCW2
R/W
0
Transmit Command Word 2 subaddress field equals 00000 or 11111
(mode command indicated)
•
•
Transmit Command Word 2 has the same RT Address as Receive
Command Word 1
Transmit Command Word 2 has sync error
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Bit No. Mnemonic
R/W Reset Function
Command Word Content Error (CWCE)
Bit 0 is logic 1 if a received Command Word violates one or more MIL-
STD-1553B requirements:
•
•
•
A non-mode broadcast transmit Command Word occurred. (non-
mode has 5-bit subaddress field equal to decimal 1~30)
0
CWCE
R/W
0
A receive mode code Command Word was received with mode code
in the range of 0~15 decimal (undefined)
A broadcast transmit mode code command occurred having a mode
code value for which broadcast is not allowed (mode code = decimal
0, 2, 16, 18 or 19)
12.3. SMT Message Filter Table
The Simple Monitor Terminal can select messages for monitoring through the use of a 128-word MT Filter Table,
located at fixed RAM address 0x0100. When the table bit corresponding to a new message Command Word is logic
1, that message is ignored by the monitor. If the table bit is logic 0, that message is recorded.
After MR master reset, 100% of MIL-STD-1553 messages are monitored, since the entire table address range 0x0100
through 0x017F inclusive is 0x0000. The result is that every valid Command Word, received on an idle bus, marks the
start of a new MIL-STD-1553 message recorded by the monitor. The Message Filter Table is addressed using three
fields in the received Command Word: the 5-bit RT Address field, the T/R Transmit/Receive bit, and the MSB of the
5-bit Subaddress field. This is illustrated in Figure 8.
Bit Fields Comprising Each Received Command Word
Terminal
Address
TA4:0
Word Count
(Mode Code)
WC4:0
Subaddress
SA4:0
Command
Sync
T/R
Bit
P
Filter Table
Address
0 0 0 0 0 0 0 1 0
Figure 8. Deriving the Monitor Filter Table Address from the Received Command Word
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Each RT Address from 0 to 31 decimal has four 16-bit table words: two words enable/disable individual Receive
Subaddresses, two more words enable/disable individual Transmit Subaddresses. The first four table words apply to
Subaddress 0 and are illustrated in Table 12. This 4-word pattern repeats for all 32 Subaddresses, 0-31 decimal.
Table 12. SMT Message Filter Table
Filter Table addresses
RT Address 31 Subaddresses (4 words)
0x017C - 0x017F
Filter Table addresses
RT Address 30 Subaddresses (4 words)
0x0178 - 0x017B
.
.
.
.
.
.
Filter Table addresses
RT Address 2 Subaddresses (4 words)
0x0108 - 0x010B
Filter Table addresses
RT Address 1 Subaddresses (4 words)
0x0104 - 0x0107
Filter Table address 0x0103
RT Address 0, Transmit Subaddresses 31 to 16
Word Bit #
Transmit SA
Filter Table address 0x0102
Word Bit #
15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT Address 0, Transmit Subaddresses 15 to 0
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Transmit SA
Filter Table address 0x0101
RT Address 0, Receive Subaddresses 31 to 16
Word Bit #
Receive SA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT Address 0, Receive Subaddresses 15 to 0
Filter Table address 0x0100
Word Bit #
Receive SA
15 14 13 12 11 10
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
A subaddress message is monitored when the corresponding word
bit equals logic 0. The message is not monitored when the bit equals 1.
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HI-6130, HI-6131
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION
In addition to the registers described here, a HI-6131 SMT Bus Monitor also utilizes one or more Memory Address
Pointer registers (described in Section 9.10) for managing SPI read/write operations. This comment does not apply for
parallel bus interface HI-6130 designs.
13.1. SMT Configuration Register (0x0029)
IMT
MTTOM1TTOR0eserGveCdHKReserReserMveTdTTMB1TTTRBe0serMveTdSRMRT1SRMRT0CRRIWeserMveTdXM4F8BTTSMT /
ved
0
0
0
0
0
0
0
0
0
0
RW
6
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
W
15 14 13 12 11 10
9
8
7
5
4
3
2
1
0
Bit No. Mnemonic
R/W Reset Function
MT Time Out Select.
This 2-bit field selects the Monitor “no response” time-out delay from
four available selections. Excluding RT-RT commands, the delay is
measured from command word mid-parity bit to status word mid-sync.
Bus
Dead
Time
Time Out
(excludes RT-
RT)
Bit 15:14
RT-RT Time Out
15 − 14 MTTO1:0
R/W
0
00
01
10
11
16μs
21μs
80μs
138μs
18μs
23μs
82μs
140μs
61μs
66μs
122μs
180μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This adds
40µs for the embedded transmit command word and transmit-RT status
word within this interval.
Bit 13 is not used by the bus monitor operating in SMT mode.
Initialize this bit to logic 0.
13
12
Reserved
W
0
0
0
Gap Check.
When this bit equals 1, the monitor evaluates inter-message gaps and
RT response times for a minimum preceding bus dead time of 2 µs.
This dead time corresponds to an inter-message gap of 4µs, measured
per MIL-STD-1553, from mid-parity zero crossing of the preceding
word, to mid-sync zero crossing of the following word. A minimum gap
time violation results in a Format Error in the Block Status Word for the
message.
GCHK
R/W
R/W
When this bit equals 0 (recommended), the monitor does not check for
short inter-message gap times.
Bits 11-10 are not used by the bus monitor operating in SMT mode.
Initialize these bits to logic 0.
11 − 10 Reserved
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Monitor Time Tag Message Bit Select.
This 2-bit field selects the bit within the MIL-STD-1553 message where
time stamp occurs. Time stamp occurs at mid-bit transition:
Bit 9:8
Time Tag Event
00
01
10
11
Last Bit of Last Word in Message
First Bit of First (Command) Word in Message
Last Bit of First (Command) Word in Message
time tag disabled, stores time tag = 0
9 − 8
MTTTB1:0
R/W
0
For options 00 and 10, the “Last Bit” precedes the word’s parity bit. For
option 01, the “First Bit” occurs 0.5µs after command sync. While “First
Word” generally denotes a command word, message recording can
begin with a data word when register bit 5 equals 1.
Bit 7 is not used by the bus monitor operating in SMT mode.
Initialize this bit to logic 0.
7
Reserved
R/W
0
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
MT Start-Record Requirement 1:0.
When register bits 6-5 equal 00, the MT starts recording a new
MIL-STD-1553 message when a properly encoded, complete
MIL-STD-1553 word with command sync is decoded: The command
sync is followed by 16 properly encoded data bits plus a 17th parity bit
expressing odd parity. No data is recorded until this condition is met.
This is the usual setting. (default setting)
When register bits 6-5 equal 01, the MT starts recording a new
MIL-STD-1553 message when a properly encoded, complete
MIL-STD-1553 word with command sync or data sync is decoded.
The properly encoded command sync (or data sync) is followed by 16
properly encoded data bits plus a 17th parity bit expressing odd parity.
If recording begins with data sync, the Sync Error flag will be set in the
Block Status Word.
When register bits 6-5 equal 10, the MT starts recording a new
MIL-STD-1553 message upon detection of a properly encoded
command sync with two contiguous data bits. If the properly
encoded command sync with two contiguous data bits does not result in
a valid command word, the Invalid Word Error is set in the Block Status
Word. This selection begins recording for complete MIL-STD-1553
command words as well as for command word fragments, or command
words with bad parity. Under some circumstances, this record option
might be helpful for debugging MIL-STD-1553 communication failure.
6 − 5
MTSRR1:0
R/W
0
When register bits 6-5 equal 11, the MT starts recording new bus activity
upon detection of any properly encoded sync (command or data)
with two contiguous data bits. This selection begins recording for
complete MIL-STD-1553 command or data words as well as for word
fragments, or words with bad parity. If the properly encoded sync with
two contiguous data bits does not result in a valid Manchester II word,
the Invalid Word Error is set in the Block Status Word. If recording
begins with data sync, the Sync Error flag will be set in the Block Status
Word. Under some circumstances, this record option might be helpful for
debugging MIL-STD-1553 communication failure.
MT Continue Recording After Invalid Word.
When bit 4 equals 0, the MT stops recording an incomplete message
when an invalid MIL-STD-1553 word is decoded. The invalid word is not
stored, and the MT awaits word detection per register bits 6-5 before the
next MIL-STD-1553 message is recorded. (default)
4
3
MTCRIW
Reserved
R/W
R/W
0
0
When bit 4 equals 1, the MT continues recording an incomplete
message when an invalid MIL-STD-1553 word is decoded. The invalid
word is stored and the MT continues monitoring the message until
completion or time-out occurs.
Bit 3 is not used by the bus monitor operating in SMT mode.
Initialize this bit to logic 0.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Extended Message Flag Enable.
Usually register bit 2 is set to logic 1 to enable expanded status/error
flags, occupying the “reserved” bit positions in the IRIG-106 Block Status
Word.
2
MTXMF
R/W
0
When register bit 2 equals 0, the recorded status/error flags are limited
to the defined bits in the IRIG-106 Block Status Word. This is described
in Section 14.6.
48-Bit Time Tag / 16-Bit Time Tag
When register bit 1 equals 0, the SMT time tag counter operates with 16-
bit resolution and the recorded entry for each MIL-STD-1553 message in
the Command Buffer is four 16-bit words.
1
0
48BTT
R/W
R/W
0
0
When register bit 1 equals 1, the SMT time tag counter operates with
48-bit resolution. To record the 48-bit time count, the entry for each MIL-
STD-1553 message in the Command Buffer is eight 16-bit words. Two
of the words added are used for Response Time and Message Length
words. See Section 13.5.
Select Simple Monitor Terminal (SMT) or IRIG-106 Monitor Terminal
(IMT).
SMT / IMT
For SMT operation, this register bit must be logic 1.
13.2. SMT Bus Monitor Address List Start Address Register (0x002F)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
1
7
0
6
1
5
1
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is Read-Write and is fully maintained by the host. After MR pin master reset, this register is
initialized with 0x00B0, the default base address of the MT Address Table in device RAM. The host can overwrite the
default base address. This register is not affected by MT soft reset, when the MTRESET bit is asserted in the Master
Status and Reset Register, 0x0001. The Address List for SMT mode is summarized in Table 11 on page 95.
13.3. SMT Next Message Command Buffer Address (0x0030)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is read-only and is updated by the MT upon completion of a monitored MIL-STD-1553 message.
This register is cleared after MR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the Master
Status and Reset Register, 0x0001. This register contains the address for the first word to be stored in MT Command
Buffer, for the next MIL-STD-1553 message. After the first post-reset message is logged, this register mirrors the value
contained in SMT Address List word 1 (see Table 11 on page 95).
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HI-6130, HI-6131
The MT logic only updates this “next message address” register after message completion. Therefore, after reset or
after the host has changed the MT Address List Start Address Register 0x002F, this register does not contain a pointer
address until processing for the next message is completed. If the read value equals zero, the “next message address”
is the Command Buffer starting address.
13.4. SMT Last Message Command Buffer Address (0x0031)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is read-only and is updated by the MT upon completion of a monitored MIL-STD-1553 message.
This register is cleared after MR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the Master
Status and Reset Register, 0x0001.
This register contains the RAM address for the first word stored in the Circular Command Buffer for the last completed
MIL-STD-1553 message.
13.5. SMT Bus Monitor Time Tag Count Register (0x003A)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
When MT Configuration Register bits 1-0 equal 11, the Simple Message Monitor operates with 16-bit Time Tag
resolution and register 0x003A contains the full 16-bit Time Tag count.
When MT Configuration Register bits 1-0 equal 01, the Simple Message Monitor operates with 48-bit Time Tag
resolution and the full Time Tag Count requires the above register plus two additional registers:
13.6. SMT Bus Monitor Time Tag Count Mid Register (0x003B)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
13.7. SMT Bus Monitor Time Tag Count High Register (0x003C)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
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HI-6130, HI-6131
When configured for 48-bit time base operation, count bits 47-17 reside in register 0x003C, count bits 31-16 reside in
register 0x003B while register 0x003A contains bits 15-0.
The host cannot directly write these registers but uses other methods to control or read Time Tag count. By writing bits
15-14 in the Time Tag Counter Configuration Register 0x0039, the host can clear time tag count to zero, copy the cur-
rent time count to the SMT Time Tag Utility Register(s), or load the current value contained in the SMT Time Tag Utility
Register(s) into the SMT Time Tag counter(s). Finally, the SMT Time Tag Match Register(s) provide capability for host
interrupts when the time tag count reaches any predetermined 16- or 48-bit value. For further information, refer to the
description of the Time Tag Counter Configuration Register 0x0039.
13.8. SMT Bus Monitor Time Tag Utility Register (0x003D)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
When MT Configuration Register bits 1-0 equal 11, the Simple Message Monitor operates with 16-bit Time Tag
resolution and register 0x003D is the only Time Tag Utility register needed.
When MT Configuration Register bits 1-0 equal 01, the Simple Message Monitor operates with 48-bit Time Tag
resolution and “utility” operations require the above register plus two additional registers:
13.9. SMT Bus Monitor Time Tag Utility Mid Register (0x003E)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These registers are read-write and are cleared after MR pin Master Reset. This utility register triplet is used for
simultaneously loading or reading a 16- or 48-bit value into or from the SMT Time Tag Counter. Please refer to the
description for bits 15-14 in the Time Tag Counter Configuration Register 0x0039 in Section 9.9.
Loading a 16-bit or 48-bit value into the SMT Time Tag Count Register(s)
When loading or clearing Time Tag count, the 16-bit value in Time Tag Utility Register 0x003D is copied into SMT
Time Tag Count register 0x003A. If configured for 48-bit time stamp operation, count bits 47-17 and count bits 31-16
are simultaneously copied from Time Tag Utility Registers 0x003F and 0x003E into SMT Time Tag Count Registers
0x003C and 0x003B respectively.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Capturing a 16-bit or 48-bit value from the SMT Time Tag Count Register(s)
When capturing Time Tag count, the 16-bit value in SMT Time Tag Count register 0x003A is copied into Time Tag Utility
Register 0x003D. If configured for 48-bit time stamp operation, count bits 47-17 and count bits 31-16 in SMT Time Tag
Count Registers 0x003C and 0x003B are simultaneously copied into Time Tag Utility Registers 0x003F and 0x003E
respectively.
13.11. SMT Bus Monitor Time Tag Match Register (0x0040)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
When MT Configuration Register bits 1-0 equal 11, the Simple Message Monitor operates with 16-bit Time Tag resolu-
tion and register 0x0040 is the only Time Tag Utility register needed.
When MT Configuration Register bits 1-0 equal 01, the Simple Message Monitor operates with 48-bit Time Tag resolu-
tion and time tag matching operations require the above register plus two additional registers:
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These registers are read-write and are cleared after MR pin Master Reset. When the MTTTM bit 6 is logic 1 in the
Hardware Interrupt Enable Register 0x000F, an interrupt occurs when the MT time tag count matches the value stored
in this register triplet. If the MT is configured for 16-bit time tag, Time Tag Match Register 0x0040 is compared to Time
Tag Count register 0x003A for match determination.
If configured for 48-bit time tag operation, count bits 47-17 and 31-16 in Time Tag Match Registers 0x0042 and 0x0041
are also compared to MT Time Tag Count Registers 0x003C and 0x003B for 48-bit match determination.
Please refer to the description for MTTTM bit 6 in the Hardware Interrupt Registers described in Section 9.7.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
13.14. SMT Bus Monitor Interrupt Registers and Their Use
Section 9.4 on page 36 through Section 9.6 describe how the host uses three Hardware Interrupt registers, the Interrupt
Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When the SMT is enabled, three
additional registers are dedicated to SMT interrupts. Comparable to the Hardware Interrupt register triplet, the SMT
has
•
•
•
An SMT Interrupt Enable Register to enable and disable interrupts
An SMT Pending Interrupt Register to capture the occurrence of enabled interrupts
An SMT Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available for the SMT. At initialization, bits are set in the SMT
Interrupt Enable register to identify the interrupt-causing events for the SMT which are heeded by the HI-613x. Most
SMT applications only use a subset of available SMT interrupt options. Interrupt-causing events are ignored when their
corresponding bits are reset in the SMT Interrupt Enable Register. Setting an Interrupt Enable register bit from 0 to 1
does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever an SMT interrupt event occurs (and the corresponding bit is already set in the SMT Interrupt Enable
Register), these actions occur:
•
•
The Interrupt Log Buffer is updated.
A bit corresponding to the interrupt type is set in the SMT Pending Interrupt Register. The type bit is logically-
ORed with the preexisting register value, retaining bits for prior, unserviced SMT interrupts.
•
MT Interrupt Pending (MTIP) bit 1 used by SMT or IMT is set in the Hardware Pending Interrupt Register. The
MTIP bit is logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts
and the preexisting status of the BCIP and RTIP (Bus Controller and RT) interrupt pending bits.
•
If the matching bit is already set in the SMT Interrupt Output Enable Register, an IRQ output occurs.
If the matching bit in the SMT Interrupt Output Enable Register was not already set (i.e., low priority polled interrupt),
the host can poll the SMT Pending Interrupt Register to detect the occurrence of SMT interrupts, indicated by non-zero
value. Reading the SMT Pending Interrupt Register automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four
Interrupt Output Enable registers (hardware, BC, RT and SMT or IMT). Multiple interrupt-causing events can occur
simultaneously, so single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.4 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
Hardware Pending Interrupt Register to indicate when BC, RT, SMT and/or IMT interrupts occur. When MT Interrupt
Pending (MTIP) bit 1 used by SMT or IMT is set in the Hardware Pending Interrupt Register, the SMT Pending Interrupt
Register contains a nonzero value and may be read next to identify the specific SMT interrupt event(s). Or, the host
can directly interrogate the Interrupt Count & Log Address Register, followed by the Interrupt Log Buffer. Data sheet
section 9.4 has a detailed description.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
13.14.1.SMT Bus Monitor Interrupt Enable Register (0x0011)
ReserRveedserRveedserRvedserRveedserRveedserCveBdUFDRBOUFCRBOUFDMBAUTFMMTAMTEMRTREORMeserRveedserRvedserved
Reserved
0
0
0
0
0
0
0
RW
9
0
0
0
0
0
0
0
0
R
1
0
MR Reset
Host Access
Bit
15
14 13 12 11 10
8
7
6
5
4
3
2
0
13.14.2.SMT Bus Monitor Pending Interrupt Register (0x0008)
ReserRveedserRveedserRvedserRveedserRveedserCveBdUFDRBOUFCRBOUFDMBAUTFMMTAMTEMRTREORMeserRveedserRvedserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
R
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
13.14.3.SMT Bus Monitor Interrupt Output Enable Register (0x0015)
ReserRveedserRveedserRvedserRveedserRveedserCveBdUFDRBOUFCRBOUFDMBAUTFMMTAMTEMRTREORMeserRveedserRvedserved
Reserved
0
0
0
0
0
0
0
RW
9
0
0
0
0
0
0
0
0
R
1
0
MR Reset
Host Access
Bit
15
14 13 12 11 10
8
7
6
5
4
3
2
0
Three registers govern SMT interrupt behavior: the SMT Interrupt Enable Register, the SMT Pending Interrupt Register
and the SMT Interrupt Output Enable Register. When a bit is set in the SMT Interrupt Enable Register, the corresponding
SMT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally
disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the
bit was zero.
When an enabled SMT interrupt event occurs, the corresponding bit is set in the SMT Pending Interrupt Register
and the Interrupt Log Buffer is updated. To simplify interrupt decoding, MTIP bit 1 in the Hardware Pending Interrupt
Register is also set whenever one or more bits are set in the SMT Pending Interrupt Register.
If the corresponding bit is already set in the SMT Interrupt Output Enable Register, the IRQ output pin is asserted at
Pending Interrupt Register assertion. The SMT Interrupt Output Enable Register establishes two priority levels: high
priority interrupts generate an IRQ output while low priority interrupts do not. Both priority levels update the SMT
Pending Interrupt Register and the Interrupt Log Buffer. The host detects low priority (masked) interrupts by polling
SMT Pending Interrupt Register.
The table below describes the bit descriptions shared by all three SMT interrupt registers.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Bit No. Mnemonic
Function
These bits are not used in SMT monitor mode. They should be initialized logic 0 in the
SMT Interrupt Enable Register. These bits will always read logic 0 in the SMT Pending
Interrupt Register.
15 − 9 Reserved
Command Buffer Rollover Interrupt.
8
7
6
5
4
CBUFRO
DBUFRO
CBUFMAT
DBUFMAT
SMTMERR
The Command Buffer Pointer value (Word 1 in the SMT Address List) has rolled over to
the Command Buffer Start Address (Word 0 in the SMT Address List).
Data Buffer Rollover Interrupt.
The Data Buffer Pointer value (Word 5 in the SMT Address List) has rolled over to the
Data Buffer Start Address (Word 4 in the SMT Address List).
Command Buffer Address Match Interrupt.
The Command Buffer Pointer value (Word 1 in the SMT Address List) has reached the
Command Buffer Address Match value in Word 3 of the SMT Address List.
Data Buffer Address Match Interrupt.
The Data Buffer Pointer value (Word 5 in the SMT Address List) has reached the Data
Buffer Address Match value in Word 7 of the SMT Address List.
SMT Message Error Interrupt.
A non-broadcast MIL-STD-1553 message ended with an RT Status Word containing the
ME Message Error status bit set.
SMT End of Message Interrupt.
3
SMTEOM
Reserved
Successful completion of a MIL-STD-1553 message, regardless of validity.
2 − 0
Bits 2-0 cannot be written, and read back 000.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
14. IRIG-106 MONITOR TERMINAL (IMT)
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Monitor, requiring minimal host support. Two
fundamentally different monitor modes are offered. Each of these modes has a separate data sheet section describing
registers used and operational details. Information regarding the alternative Simple Monitor Terminal (SMT) may be
found in Section 12.
14.1. Overview
IRIG-106 Monitor Terminal (IMT) mode complies with IRIG-106, a comprehensive standard ensuring interoperability of
aeronautical telemetry at United States Military RCC member ranges. The telemetry group of the Range Commanders
Council maintains the IRIG-106 standard. Chapter 10 of the standard defines operation and interfaces for digital flight
data recorders over a range of telemetry protocols, including MIL-STD-1553. Further information on the IRIG-106
standard can be found at http://irig106.org/
The HI-613x is configured for IMT operation when bit 0 in the MT Configuration Register 0x0029 is logic 0. The IMT
always operates with 48-bit Time Tag resolution. In register 0x0000, MTENA bit 8 is logically ANDed with the MTRUN
input pin to enable the Bus Monitor. If the MTRUN input pin or MTENA register bit equals logic 0, Bus Monitor operation
is disabled. When the MTRUN pin and MTENA register bit are both logic 1, the Bus Monitor is enabled. Operation
commences when the receiver first decodes MIL-STD-1553 activity meeting the “start record” criteria selected by bits
6-5 in the MT Configuration Register. If monitor operation is underway when the MTENA register bit or MTRUN input
pin becomes logic 0, monitor operation stops and the open data packet is finalized after completion of any message
already underway.
The Holt IRIG-106 Monitor Terminal (hereafter called IMT) uses a single storage buffer in device RAM. Recorded
message data, message results and characteristics are stored in multiple-message “data packets”. As they occur,
MIL-STD-1553 messages are appended to the end of the open data packet and time stamped with a 48-bit Time Tag
value. By default, the IMT records all MIL-STD-1553 messages, although it optionally records just selected messages,
based on RT address, subaddress and transmit/receive status for each detected Command Word.
The IMT optionally generates a Packet Header and Packet Trailer consistent with IRIG-106 Chapter 10 specifications.
The header contains various data including data packet size, time stamp and header checksum. The trailer is primarily
comprised of a data checksum. While the IRIG-106 standard requires a header and trailer on each data packet, some
applications will require data packet size exceeding the RAM capacity of the HI-613x device. In this case, the IMT
may be configured to disable automatic header and trailer generation, so the entire RAM buffer is used for message
storage. Upon receiving each end-of-packet interrupt, the host offloads the entire block of new message data, which
may be appended to a large packet buffer RAM, accessible to the host microcontroller. At the appropriate time, the
host then generates the required IRIG-106 packet header and packet trailer.
The IMT can be configured to automatically start a new data packet after finalization of each completed data packet,
or the host microcontroller can command the start of the new data packet. In either case, the starting address for the
new packet follows the last storage address of the previous packet (even when the last packet was finalized due to
imminent buffer overrun). The device stores packet data in circular buffer fashion, automatically wrapping around to
the buffer start address after the last buffer address is written. The host microcontroller is responsible for offloading
each data packet in a timely manner to avoid data overwrite by the HI-613x device. One strategy: enable a “packet
ready” interrupt, as well as an “N-word warning before full buffer” interrupt triggered halfway through the IMT RAM
buffer capacity. The host microcontroller uses these alternating interrupts to pace data buffer offloading, reading a half
buffer each time one of the two interrupts occurs.
The HI-613x IMT is highly flexible. According to the IRIG-106 standard, the Block Status Word stored for each MIL-
STD-1553 message contains several reserved status bits which always read logic 0. The HI-613x device optionally
uses these bits to convey additional status information to the host; the host then resets the reserved bits before
including the Block Status Word in the IRIG-106 data packet.
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14.2. IRIG-106 Bus Monitor - Data Packet Format
When the HI-613x Bus Monitor is initialized for IMT operation, recorded bus message information is stored in device
RAM using a “data packet“ format consistent with IRIG-106 Chapter 10. The IRIG-106 data packet is comprised of
three parts: a Packet Header, a Packet Body (containing the monitored MIL-STD-1553 message information) and a
Packet Trailer. The HI-613x IMT may be configured to generate complete data IRIG-106 packets, including Packet
Header and Packet Trailer, or may be configured to generate only the Packet Body, without Packet Header and Packet
Trailer.
The IRIG-106 data packet is shown in Figure 9. When the IMTHTD bit 3 in the IMT Configuration Register 0x0029
is logic 1, the HI-613x stores only the Packet Body. When the IMTHTD bit 3 is logic 0, the HI-613x stores a Packet
Header and Packet Trailer, described on the next pages, in addition to the Packet Body.
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Data Checksum
(16 Bits)
IRIG-106
Packet Trailer
8 Bytes
Packet
Trailer
Filler Bits 15 - 0
always 0x0000
Packet
Trailer
Filler Bits 47 - 32
0x0000 When Needed
Filler Bits 15 - 0
0x0000 When Needed
Data Packet
for
Message N
Message N
See ahead for
additional details
on Data Packets
Message 4
Message 3
Message 2
Increasing
Memory
Address
Packet
Body
Message 1
Data Packet
for
Message 2
Time T Reserved Msg Count
Tag Bits
T
000000 Bits 23-16
Message Count
Bits 15 - 0
Header Checksum
(16-Bit)
Relative Time
Counter, Bits 47-32
Relative Time
Counter, Bits 31-16
Relative Time
Counter, Bits 15-0
Data Packet
for
Message 1
Packet
Flags 0x00
Data Type
0x19
Sequence Data Type
Number Version
Data Length (Bytes)
Bits 31 - 16
Channel Specific
Data, 4 Bytes
Data Length (Bytes)
Bits 15 - 0
Packet Length (Bytes)
Bits 31 - 16
IRIG-106
Packet Header
24 Bytes
Packet Length (Bytes)
Bits 15 - 0
Packet
Header
Packet
Header
Packet
Channel ID
Packet Sync Pattern
always 0xEB25
Bit 15
0
Figure 9. IRIG-106 Data Packet and Message Storage Summary
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14.3. IRIG-106 Packet Header Description
The length of the packet header is fixed at 24 bytes, shown in as twelve 16-bit words. The Packet Header consists of
10 contiguous fields in the following sequence:
14.3.1. Packet Sync Pattern.
A static sync value of 0xEB25 is used for every packet.
14.3.2. Channel ID.
This 2-byte field contains a value representing the Packet Channel ID. The Packet Header is generated using the
value stored in register 0x002E.
14.3.3. Packet Length.
This 32-bit field contains a value representing the length of the entire packet. The value indicates the number of bytes
in the packet, and is always a multiple of four (bits 1-0 are always 0-0). The Packet Length includes the Packet Header,
Channel Specific Data, Intra-Packet Headers, Data, Filler, and Data Checksum. (The HI-613x IMT does not generate
the optional Packet Secondary Header.)
14.3.4. Data Length.
This 32-bit field contains a value representing the valid data length within the packet, expressed in number of bytes.
Valid data length includes Channel Specific Data, Intra-Packet Data Headers, Intra-Packet Time Stamp(s), and Data,
but does not include the Packet Trailer Filler and Data Checksum.
14.3.5. Data Type Version.
This 8-bit field contains a value at or below the release version of the IRIG-106 standard applied to the data types in
the table below. The Packet Header is generated using the value encoded by bits 11-10 in register 0x0029. The Data
Type value is used in the Packet Header as shown below.
Register 0x0029
Bits 11-10
Data
Type
IRIG-106
01
10
11
00
0x01
0x02
0x03
0x04
IRIG-106-04 (original release)
IRIG-106-05 (default
IRIG-106-07
IRIG-106-09
14.3.6. Sequence Number.
This 8-bit field contains a value representing the packet sequence number for each Channel ID. This is simply a
counter that increments to a maximum count of 0xFF, incrementing once for every packet transferred. After master
reset, the Sequence Number starts at 0x00. Upon reaching 0xFF, the Sequence Number rolls over to 0x00 and
continues counting.
14.3.7. Packet Flags.
This 8-bit field equals either 0x00 or 0x02, depending on the checksum type selected by bit 1 in register 0x0029. If Data
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Checksum is disabled, this field equals 0x00. If 16-bit Data Checksum is enabled, this field equals 0x02. Although bits
7-2 in this field always equal logic 0, the encoded significance for all eight Packet Flags is explained here:
•
•
•
•
•
•
Packet Secondary Header is not present (bit 7)
Packet Header 48-bit Relative Time Count used for Intra-Packet Time Stamps (bit 6)
Sync error did not occur for Relative Time Count (bit 5)
Data Overflow error did not occur (bit 4)
Optional IRIG-106 Packet Secondary Header is not used (bits 3-2)
Data Checksum format: bits 1-0 always equal 00 or 10
00 = data checksum disabled (automatic, when register 0x0029 bit 1 = logic 0)
01 = 8-bit data checksum (option not available)
10 = 16-bit data checksum (automatic, when register 0x0029 bit 1 = logic 1)
11 = 32-bit data checksum (option not available)
14.3.8. Data Type.
This 8-bit field contains a value representing the type and format of the data. The HI-613x IMT always generates a
fixed Data Type value of 0x19, which represents a MIL-STD-1553B Format 1 data packet.
14.3.9. Relative Time Counter.
This 48-bit (3-word) field contains a value representing the 10 MHz Relative Time Counter (RTC). The RTC is derived
from an internal clock generator, and remains free running during each data packet recording. The 48-bit value applies
to the first bit of message data in the packet body.
14.3.10.Header Checksum.
This 16-bit (1-word) field contains the 16-bit arithmetic sum of all 16-bit words in the header, excluding the Header
Checksum word itself.
14.4. IRIG-106 Packet Trailer Description
IRIG-106 defines a Packet Trailer consisting of an optional Data Checksum, preceded by “filler words”. The standard
requires the overall packet length to be an even number of 16-bit words. The HI-613x IMT inserts 0x0000 “filler” words
to meet this requirement. Every packet generated by the HI-613x IMT has a Packet Trailer consisting of 2 or 3 filler
words (0x0000) followed by the 16-bit Data Checksum word.
Bit 1 in register 0x0029 enables/disables automatic generation of a 16-bit Data Checksum. When auto checksum
is disabled, the Packet Trailer simply consists of 3 or 4 filler words. When the configuration bit is logic 1, the 16-bit
checksum is written into the last packet word at packet finalization. If an 8- or 32-bit data checksum is needed, the
host must generate it. IRIG-106 defines the Data Checksum as the arithmetic sum of all of the bytes (8-bit checksum),
words (16-bit checksum) or long words (32-bit checksum) in the entire packet, excluding the 24-byte Packet Header
and the Data Checksum itself.
14.5. IRIG-106 Data Packet Trailer Description
The HI-613x IMT Packet Body consists of a 32-bit Channel Specific Data field, followed by one or more message data
blocks, with separate message data blocks for each monitored MIL-STD-1553 message.
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14.5.1. Channel Specific Data.
This 32-bit field occurs once per packet and precedes the packet channel data. The Channel Specific Data is comprised
of the following fields:
Bits 31-30
Bits 29-24
Bits 23-0
Time Tag Bits
Reserved, always 000000
Message Count
Bits 31-30 indicate the MIL-STD-1553 data bit at which Intra-Packet Header time stamp occurs for each message:
00 = time stamp occurs at the last bit of the last word in the message
01 = time stamp occurs at the first bit of the first word in the message
10 = time stamp occurs at the last bit of the first word in the message
11 = reserved, not used
Bits 23-0 indicate the binary count for the number of MIL-STD-1553 messages included in the packet. An integral
number of complete transaction messages will be in each packet
For each monitored MIL-STD-1553 message, three data fields are stored in the Packet Body. These are shown in
Figure 11, and explained here:
14.5.2. IRIG-106 Intra-Packet Time Stamp.
This 64-bit field contains a 48-bit Relative Time Counter value that marks the relative reception time for the MIL-
STD-1553 message. The high order 16 bits always equal 0x0000. Time stamping occurs at the message bit indicated
in the Channel Specific Data.
14.5.3. IRIG-106 Intra-Packet Data Header.
This 48-bit field is comprised of the following sub fields:
Block Status Word (BSW). This 16-bit word indicates status for the following MIL-STD-1553 message and indi-
cates MIL-STD-1553 bus protocol errors.
Response Time Word. This 16-bit word contains two 8-bit fields. For all messages except RT-to-RT, the GAP1
byte indicates the RT response time. For RT-to-RT messages, the GAP1 byte indicates the Transmit RT response
time, and the GAP2 byte indicates the Receive RT response time:
Bits 15-8
Bits 7-0
GAP2
GAP1
For both gap measurements, response time is measured consistently with MIL-STD-1553 definition, from the
mid-parity zero crossing of the preceding word, to the mid-sync zero crossing of the RT Status Word. For both,
the resolution is 100 ns per LSB, with a maximum time value of 25.5 µs.
Message Length Word. This 16-bit word indicates the number of bytes in the following message data block,
ranging from 2 to 72 bytes, for 1 to 36 stored 16-bit words.
14.5.4. IRIG-106 Message Data.
This variable length block stores all MIL-STD-1553 message words in the order received. The number of words stored
depends on the MIL-STD-1553 message type, ranging from 1 word stored (for a broadcast mode code command
without data), to 36 words stored for an RT-to-RT message. Refer to Figure 11. An IRIG-106 packet typically contains
numerous MIL-STD-1553 messages, although the standard states the packet must contain at least one message (no
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empty packets).
14.6. IMT Block Status Word (BSW) Description
The IRIG-106 standard describes a Block Status Word stored within the Intra-Packet Data Header for each monitored
MIL-STD-1553 message. This word provides information regarding message status, the bus on which the message
occurred, whether errors occurred during the message, and the type of occurring errors. The IRIG-106 Chapter 10
compliant Block Status Word contains eight reserved bits, which the HI-613x IMT writes as logic 0:
ReserRveedserB EO RR IGE (FTEM) ReserRveedserReserLvEed SE WE ReserRveedserRvedserved
veIDd ved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
The HI-613x IMT offers an Extended Status reporting option, enabled when bit 2 in register 0x0029 is logic 1. When
this option is enabled, all but one of the Reserved status bits are used to convey additional status information. Although
the extended status bits do not comply with the IRIG-106 Chapter 10 standard, the host can reset the 7 normally
reserved bits after reading the BSW. If using the IMT-generated 16-bit Data Checksum (enabled when register 0x0029
bits 1:0 equal 1-0), be advised that the tallied checksum value is based on the BSW value that was written into the
data packet by the device, at individual MIL-STD-1553 message completion. The Block Status Word with Extended
Status is defined:
ReserRveedserB EO RR IGE (FTEM) GDB ReserSFS LE SE WE RRGSRARCWC2WCE
veIDd ved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IMT Block Status Word
with Extended Status Bits Enabled
(Not IRIG-106 Chapter 10 Compliant)
Bit No. Mnemonic
R/W Reset Function
15
14
Reserved
Reserved
R/W
R/W
0
0
Bit 15 is not used in IMT mode, always reads logic 0.
Bit 14 is not used in IMT mode, always reads logic 0.
Bus ID (Bus B / Bus A).
Bit 13 indicates the bus ID for the message. This bit is logic 0 for a
message occurring on Bus A. This bit is logic 1 for a message occurring
on Bus B.
13
BID
R/W
0
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Bit No. Mnemonic
R/W Reset Function
Error Occurred Flag.
This bit indicates a message error was encountered. This bit is set when
one or more of the following conditions are true (logical-OR):
•
•
•
•
•
•
•
•
•
an unfinished message is superseded by another valid command
Bit 10 Illegal Gap Error is set
Bit 9 Response Timeout is set
Bit 5 Length (Word Count) Error is set
Bit 4 Sync Type Error is set
Bit 3 Invalid Word Error is set
Bit 2 RT-RT Gap / Sync / Address Error is set
Bit 1 RT-RT Command Word 2 Error is set (except as noted)
Bit 0 Command Word Content Error is set (except as noted)
12
EO
R/W
0
Three exceptions where register bit 0 or 1 is set without affecting bit 12
state:
Bit 1 RT-RT Command Word 2 Errors that do not assert bit 12
•
RT-RT Transmit Command Word 2 subaddress field equals 00000
or 11111 (mode code command indicated)
•
RT-RT Transmit Command Word 2 has the same RT Address as
Receive Command Word 1
Bit 0 Command Word Content Error that does not assert bit 12
•
Undefined receive mode code 0~15 decimal.
RT-to-RT Transfer
11
10
RR
R/W
R/W
0
0
When logic 1, bit 11 indicates an RT-to-RT message, beginning with two
contiguous Command Words.
Illegal Gap Error
When logic 1, bit 10 indicates an illegal gap occurred on the bus, other
than Response Timeout. The IRIG-106 Standard refers to this bit as
Format Error, having the same definition.
IGE
Response Timeout.
When logic 1, bit 9 indicates a response timeout occurred. This bit is
set if an RT Status Word associated with this message failed to arrive
within the response time interval specified by bits 15-14 in the MT
Configuration Register 0x0029.
9
TM
R/W
0
For IRIG-106 compatibility, bits 15-14 in register 0x0029 should be
initialized to 00, corresponding to a 14µs response time, as defined by
MIL-STD-1553B (12µs bus dead time).
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Bit No. Mnemonic
R/W Reset Function
Good Data Block Transfer.
only if Extended Status is enabled
Bit 8 is set to logic 1 following completion of a valid, error-free message.
This bit is reset to logic 0 following completion of a message in which
error occurred. If an RT responds to a transmit command with Busy
status without transmitting the commanded data word(s), this message
does not reset the GDB bit.
8
GDB
R/W
0
7
6
Reserved
SFS
R/W
R/W
0
0
Bit 7 is not used in IMT mode, always reads logic 0.
Status Flag Set
only if Extended Status is enabled
Bit 6 is logic 1 when a status bit was set in an RT Status Word response.
Length (Word Count) Error
Bit 5 indicates that the number of data words transmitted by the BC or
RT differs from the Word Count specified in the Command Word. An RT
Status Word with the Busy bit set will not cause Word Count Error. A
transmit command with Response Timeout will not cause Word Count
Error.
5
LE
R/W
0
Sync Type Error
Bit 4 is logic 1 to indicate that a BC transmitted data sync with a
Command Word, or a command / status sync occurred with Data Word,
or an RT responded with data sync in its Status Word and/or command/
status sync in a Data Word.
4
3
SE
R/W
R/W
0
0
Invalid Word Error (WE)
Bit 3 is logic 1 when invalid word error occurred. This includes
Manchester decoding errors in the sync pattern or word bits, or the
wrong number of bits in the word, or parity error.
WE
RT-to-RT Gap/Sync/Address Error (RRGSA)
only if Extended Status is enabled
Bit 2 is logic 1 if one or more of these RT-RT message conditions occur:
•
MT Gap Check is enabled (bit 12 equals 1 in register 0x0029) and
an RT Status Word is received having a response time less than
4µs, per MIL-STD-1553B (mid-parity to mid-sync). In other words,
the bus “dead time” was less than 2µs.
2
RRGSA
R/W
0
•
•
One of the RTs responds with an invalid Status Word, having a sync
error, a Manchester encoding error, bit count error and/or parity error
One of the RT Status Words contains an RT Address that differs
from the RT Address in the corresponding Command Word.
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Bit No. Mnemonic
R/W Reset Function
RT-to-RT Command Word 2 Error (RRCW2)
only if Extended Status is enabled
Bit 1 is logic 1 if an RT-to-RT message occurs (two contiguous
Command Words) with one or more of the following illogical conditions:
1
RRCW2
R/W
0
•
•
Transmit Command Word 2 T/R bit equals 0 (receive)
Transmit Command Word 2 subaddress field equals 00000 or 11111
(mode command indicated)
•
Transmit Command Word 2 has the same RT Address as Receive
Command Word 1
Command Word Content Error (CWCE)
only if Extended Status is enabled
Bit 0 is logic 1 if a received Command Word violates one or more
MIL-STD-1553B requirements:
•
•
•
A non-mode broadcast transmit Command Word occurred. (non-
mode has 5-bit subaddress field equal to decimal 1~30)
0
CWCE
R/W
0
A receive mode code Command Word was received with mode code
in the range of 0~15 decimal (undefined)
A broadcast transmit mode code command occurred having a mode
code value for which broadcast is not allowed (mode code = decimal
0, 2, 16, 18 or 19)
14.7. IMT Message Filter Table
The IRIG-106 Message Monitor can select messages for monitoring through the use of a 128-word MT Filter Table,
located at fixed RAM address 0x0100. When the table bit corresponding to a new message Command Word is logic
1, that message is ignored by the monitor. If the table bit is logic 0, that message is recorded.
After MR master reset, all MIL-STD-1553 messages are monitored because the entire table ranging from 0x0100
to 0x017F inclusive is 0x0000. Thus every valid Command Word received on an idle bus marks the start of a new
MIL-STD-1553 message recorded by the monitor. When the table bit corresponding to a new message Command
Word is logic 1, that message is ignored by the monitor. The Message Filter Table is addressed using three fields
in the received Command Word: the 5-bit RT Address field, the T/R Transmit/Receive bit and the MSB of the 5-bit
Subaddress field. This is illustrated in Figure 10.
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Bit Fields Comprising Each Received Command Word
Terminal
Address
TA4:0
Word Count
(Mode Code)
WC4:0
Subaddress
SA4:0
Command
Sync
T/R
Bit
P
Filter Table
Address
0 0 0 0 0 0 0 1 0
Figure 10. Deriving the Monitor Filter Table Address from the Received Command Word
Each RT Address from 0 to 31 decimal has four 16-bit table words: two words enable/disable individual Receive
Subaddresses, two more words enable/disable individual Transmit Subaddresses. The first four table words apply to
Subaddress 0 and are illustrated in Table 13. This 4-word pattern repeats for all 32 Subaddresses, 0-31 decimal.
Table 13. IMT Message Filter Table
Filter Table addresses
RT Address 31 Subaddresses (4 words)
0x017C - 0x017F
Filter Table addresses
RT Address 30 Subaddresses (4 words)
0x0178 - 0x017B
.
.
.
.
.
.
Filter Table addresses
RT Address 2 Subaddresses (4 words)
0x0108 - 0x010B
Filter Table addresses
RT Address 1 Subaddresses (4 words)
0x0104 - 0x0107
Filter Table address 0x0103
RT Address 0, Transmit Subaddresses 31 to 16
Word Bit #
Transmit SA
Filter Table address 0x0102
Word Bit #
15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT Address 0, Transmit Subaddresses 15 to 0
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Transmit SA
Filter Table address 0x0101
RT Address 0, Receive Subaddresses 31 to 16
Word Bit #
Receive SA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT Address 0, Receive Subaddresses 15 to 0
Filter Table address 0x0100
Word Bit #
Receive SA
15 14 13 12 11 10
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
A subaddress message is monitored when the corresponding word
bit equals logic 0. The message is not monitored when the bit equals 1.
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Corresponding
Broadcast
Non-Broadcast
Message Types
Messages
1-32 Data Words:
Data N
.........
Data 1
Transmitting RT
Status Word
Transmit
Command Word
Message Data Block
stores message words
in the order received.
Number of words stored
depends on message type.
RT-to-BC
(Transmit) Command
No Broadcast
Version
Message
Data Block
Receiving RT
Status Word
1 to 36 Message
Words
1-32 Data Words:
1-32 Data Words:
Data N
Data N
.........
.........
Data 1
Data 1
Receive
Receive
Command Word
Command Word
Message Length
Word
Note 1
Note 2
Broadcast BC-to-RT
(Receive) Command
BC-to-RT
(Receive) Command
IRIG-106
Intra-Packet
Data Header,
3 Words
Response Time
Word
Receiving RT
Status Word
Block Status Word
See Next Page
1-32 Data Words:
1-32 Data Words:
Data N
Data N
Message Time
Stamp, Bits 63-48
.........
.........
Note 3
Data 1
Data 1
IRIG-106
Intra-Packet
Time Stamp,
4 Words
Message Time
Stamp, Bits 47-32
Transmitting RT
Status Word
Transmitting RT
Status Word
Increasing
Memory
Address
Message Time
Stamp, Bits 31-16
Transmit
Command Word
Transmit
Command Word
Message Time
Stamp, Bits 15-0
Receive
Command Word
Receive
Command Word
These three elements
are repeated for each
monitored message
RT-to-RT
Command
Broadcast RT-to-RT
Command
Mode Data Word
Notes:
Transmitting RT
Status Word
1. The Message Length Word indicates the number of bytes
stored in the Message Data Block. The range is 2 to 72 bytes,
corresponding to 1 to 36 16-bit words stored.
Transmit Mode
Command Word
No Broadcast
Version
Transmit Mode Code
With Data
2. The Response Time Word contains two 8-bit fields:
Bits 15 - 8 contain GAP2
Bits 7 - 0 contain GAP1
Receiving RT
Status Word
For all messages except RT-to-RT, the GAP1 byte indicates the
only RT response time. For RT-to-RT, the GAP1 byte indicates
the Transmit RT response time, and the GAP2 byte indicates the
Receive RT response time. For both, the gap is measured from
mid-parity zero-crossing of the preceding word, to the mid-sync
zero-crossing of the Status Word. The gap time resolution is
100ns per LSB, so the maximum indicated gap time is 25.5µs.
Mode Data Word
Mode Data Word
Receive Mode
Command Word
Receive Mode
Command Word
Broadcase Receive
Mode Code With Data
Receive Mode Code
With Data
3. The high order Message Time Stamp Word (bits 63~48)
is always 0x0000.
RT Status Word
Tx or Rx Mode
Tx or Rx Mode
Command Word
Command Word
Transmit or Receive
Broadcast Tx or Rx
Mode Code Without Data
Mode Code Without Data
Figure 11. IRIG-106 Data Fields and Message Storage
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15. IRIG-106 BUS MONITOR (IMT) CONFIGURATION AND OPERATION
The HI-613x is initialized for IRIG-106 Chapter 10 operation (IMT) by resetting bit 0 in the Bus Monitor Configuration
Register 0x0029 to logic 0. The MIL-STD-1553 bus monitors that comply with IRIG-106 produce “data packets” in a
format defined by the IRIG-106 standard. Figure 9 shows the overall data packet structure, comprised of three parts:
a Packet Header, a Packet Body (containing the monitored MIL-STD-1553 message information) and a Packet Trailer.
The HI-613x IMT may be configured to generate complete data IRIG-106 packets, including Packet Header and
Packet Trailer, or may be configured to generate only the Packet Body, without header or trailer. A range of options is
offered for configuring the Packet Header and Packet Trailer.
15.1. Generating complete IRIG-106 Data Packets
IMTHTD bit 3 in the MT Configuration Register 0x0029 is logic 0
The IMT generates the Packet Header and Packet Trailer after the first MIL-STD-1553 message is recorded when
starting a new packet. When each new message data packet is added to the Packet Body, the device updates the
Packet Header and generates a new Packet Trailer. Refer to Figure 9. When one data packet is finalized and the next
data packet begins, the device adjusts the Address List pointers so the new Packet Header starts at the last unwritten
Buffer address.
15.2. Generating only IRIG-106 Packet Body (no header or trailer)
IMTHTD bit 3 in the MT Configuration Register 0x0029 is logic 1
The IMT devotes the entire RAM Buffer for message data packets. For each monitored message, only the Intra-Packet
Timestamp, Intra-Packet Data Header, and Message Data Block are stored, per Figure 11 and the note in Figure 9.
When operated in this mode, the RAM Buffer is fully utilized for message data; the first Intra-Packet Timestamp occurs
at the Buffer Start Address initialized in the IMT Address List. The host assumes responsibility for generating the IRIG-
106 Packet Header, Channel Specific Data and Packet Trailer. Otherwise, there may be situations when IMT packet
body structure is simply preferred over SMT storage format, in a non-IRIG application that does not need the header
or trailer overhead.
When operating in IMT mode, MIL-STD-1553 message data is added to the unfinished data packet until the packet
is “finalized.” The host can initiate packet finalization by setting the PKTSTOP bit in the MT Configuration Register.
Criteria for automatic packet finalization can be specified using customized limits. These host-initialized limits for
packet completion are optional, enabled or disabled by configuring limit registers 0x002A through 0x002D. When the
applicable limit register contains zero, that criteria for packet finalization is disabled. The practical maximum value for
each of these limits is actually much smaller than limits shown below, as explained in the descriptions for registers
0x002A through 0x002D.
•
•
•
•
host-specified maximum MIL-STD-1553 message count (1 to 65,535) in register 0x002A
host-specified maximum word count (1 to 65,535 words) in register 0x002B
host-specified maximum recording time (655.35 ms max, 10 µs resolution) in register 0x002C
host-specified maximum intermessage gap (655.35 ms max, 10 µs resolution) in register 0x002D
The data packet ends and packet generation encapsulates the recorded data when the first of the set data packet
limits is reached.
An open IRIG-106 data packet is also finalized when written packet data first crosses within 64 words of overrunning
buffer space. This criteria, imminent buffer overrun, is mandatory and cannot be disabled. The current data packet is
terminated when written packet length is within 64 words of overwriting the Current Packet Start Address (maintained
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in Address List Word 1 by the device).
The host initializes a Monitor Address List in RAM to reserve address space for the IMT storage Buffer and define
buffer utilization interrupt behavior. For IMT mode, the 8-word Monitor Address List is defined as shown in Table 14.
Table 14. Monitor Address List for IMT Mode
Addr. List
Name
Function
Host initialized with a word count value, N, if this interrupt is enabled.
Packet Fill
Warning
Interrupt
Word 7
If enabled, an interrupt occurs when packet length reaches N words before Current
Packet Start Address (in Word 1) will be overwritten.
Words 6 − 5 Not used
The value in Words 5 and 6 is “don’t care”.
Maintained by the device.
Last Written
Block
Status Word
Address
This word is updated by the device each time a Block Status Word is added to the
end of the packet for a newly received MIL-STD-1553 message. The addressed
location contains the first word written for the last message.
Word 4
Host initialized with a RAM address value if this interrupt is enabled.
Buffer
Word 3
Word 2
Address
Interrupt
If enabled, an interrupt occurs when the matching RAM address is written. Address
must be within the range bounded by Words 0 and 2.
Buffer End
Address
Host initialized, defines monitor buffer upper address boundary.
Must be host initialized, usually to match Buffer Start Address.
Updated by device each time a new data packet is opened.
Current
Packet Start
Address
Word 1
Word 0
This value advances through the address range in circular buffer fashion for
successive packets.
SMT End of Message Interrupt.
Buffer Start
Address
Successful completion of a MIL-STD-1553 message, regardless of validity.
For purposes of this discussion, it is important to make a distinction between Buffer Addresses and Packet Addresses.
The Buffer address range is fixed and initialized when the host writes Address List Words 0 and 2. The Packet address
range is dynamic. The Current Packet Start Address must be initialized by the host for the first data packet; however
this value is maintained by the device each time a new packet it started.
•
Buffer Start Address and Buffer End Address define the IMT data storage boundaries. These limits usually do
not coincide with stored data packet boundaries, except the first data packet following device MR reset typically
begins at the Buffer Start Address.
•
Packet Start Address and Packet End Address express a smaller address range for storing an IMT data packet.
Because successive data packets are written in circular buffer fashion, there are times when Packet Start Ad-
dress approaches the Buffer End Address. The packet fills the remaining Buffer address range and wraps around
to continue storing the packet at the Buffer Start Address and beyond. In this case, Packet Start Address is
greater than Packet End Address, but both packet addresses occur between the Buffer Start and End Addresses.
•
•
Current Packet Start Address is initialized by the host (typically equal to Buffer Start Address) but is updated by
the device each time a data packet is finalized, and the next data packet has started at the following memory
address.
Initialized values for registers 0x002A – 0x002D may result in multiple small packets occurring within the Buffer
address range. If registers 0x002A through 0x002D all contain zero, data packet finalization defaults to “imminent
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buffer overrun” mode. Each data packet created will be slightly less than the allocated Buffer address range. Suc-
cessive IRIG-106 data packets are written in circular buffer fashion. Each new data packet starts one word after
the final word in the previously finalized data packet.
•
•
•
If the first data packet after reset begins at the Buffer Start Address, it will be finalized and the second data packet
will begin before reaching the Buffer End Address boundary.
Last-Written Block Status Word Address is updated by the device each time a Block Status Word is added to the
end of the packet for a newly received MIL-STD-1553 message.
Two optional buffer interrupts are offered. When enabled, the Buffer Address Interrupt occurs whenever the
matching RAM address in the Buffer is written. This address is fixed with respect to the Buffer Start and End Ad-
dresses.
•
When enabled, the Packet Fill Warning Interrupt is generated when the packet length reaches a specified num-
ber of words before Packet Start Address overwrite occurs. Because Packet Start Address “walks” through the
buffer address range for successive packets, the interrupt logic adjusts the Packet Fill Warning Interrupt address
automatically. The fill warning number can be any value, i.e. half-way, 8,192 for a 16,384-word buffer. Used in
conjunction with the Packet Ready interrupt, this packet “half full” setting produces alternating interrupts at the
“half full” and “full” packet conditions. To prevent packet start address overwrite, these two interrupts tell the host
when to offload data, a half packet at a time. In the event that the host is unable to immediately service a Packet
Ready interrupt, no data is lost when the IMT is configured to immediately start a new packet upon completion of
the prior packet (i.e., when PKTMR bit 7 equals logic 1 in the IMT Configuration Register 0x0029).
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16. REGISTERS USED BY THE IMT BUS MONITOR
In addition to the registers described here, a HI-6131 IMT Bus Monitor also utilizes one or more Memory Address
Pointer registers (described in Section 9.10) for managing SPI read/write operations. This comment does not apply for
parallel bus interface HI-6130 designs.
16.1. IMT Bus Monitor MT Configuration Register (0x0029)
IMT
MTTOM1TTOP0KTSGTOCPHKMTDTMTDTMVT0TTMB1TTTPBK0TMMRTSRMRT1SRMRT0CRMIWTHTMDTXMCFSUMS/M8STT/K
V1
0
0
0
0
0
0
0
0
0
0
RW
6
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
W
15 14 13 12 11 10
9
8
7
5
4
3
2
1
0
Bit No. Mnemonic
R/W Reset Function
MT Time Out Select.
This 2-bit field selects the Monitor “no response” time-out delay from
four available selections. Excluding RT-RT commands, the delay is
measured from command word mid-parity bit to status word mid-sync.
Bus
Dead
Time
Time Out (excludes
Bit 15:14
RT-RT Time Out
RT-RT)
15 − 14 MTTO1:0
R/W
0
00
01
10
11
16μs
21μs
80μs
138μs
18μs
23μs
82μs
140μs
61μs
66μs
122μs
180μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This adds
40µs for the embedded transmit command word and transmit-RT status
word within this interval.
MT Packet Stop.
If packet recording is underway when the PKTSTOP bit is set, the IMT
stops recording then post-processes the packet. If a MIL-STD-1553
message is underway when PKTSTOP is set, recording continues to
message completion. The IMT immediately begins recording a new
packet.
13
PKTSTOP
W
0
If packet recording is not underway, setting PKTSTOP has no effect.
This bit self-resets when written to logic 1. Writing logic 0 to this bit has
no effect.
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Bit No. Mnemonic
R/W Reset Function
Gap Check.
When this bit equals 1, the IMT monitor evaluates inter-message gaps
and RT response times for a minimum preceding bus dead time of 2 µs.
This dead time corresponds to an inter-message gap of 4µs, measured
per MIL-STD-1553, from mid-parity zero crossing of the preceding
word, to mid-sync zero crossing of the following word. A minimum gap
time violation results in a Format Error in the Block Status Word for the
message.
12
GCHK
R/W
0
When this bit equals 0 (recommended), the monitor does not check for
short inter-message gap times.
IMT Packet Header “Data Type Version”.
This IMT setting is only meaningful when MTHTD (register bit 3) equals
0, enabling automatic generation of IRIG-106 data packet header and
packet trailer.
The IRIG-106 Chapter 10 packet header contains an 8-bit field “Data
Type” field corresponding to the IRIG-106 version applied to the data.
Register bits 15-14 specify one of four Data Type values (0x01 – 0x04)
for insertion into the generated packet header:
11 − 10 MTDTV1:0
R/W
0
Bit 11:10
Header Data Type
IRIG Release
00
01
10
11
0x04
0x01
0x02
0x03
IRIG-106-09
IRIG-106-04
IRIG-106-05 (default)
IRIG-106-07
This selection does not affect data encoding, only the 8-bit Data Type
code inserted into the IRIG-106 packet header.
Monitor Time Tag Message Bit Select.
This 2-bit field selects the bit within the MIL-STD-1553 message where
time stamp occurs. Time stamp occurs at mid-bit transition:
Bit 9:8
Time Tag Event
00
01
10
11
Last Bit of Last Word in Message
First Bit of First (Command) Word in Message
Last Bit of First (Command) Word in Message
time tag disabled, stores time tag = 0
9 − 8
MTTTB1:0
R/W
0
For options 00 and 10, the “Last Bit” precedes the word’s parity bit. For
option 01, the “First Bit” occurs 0.5µs after command sync. While “First
Word” generally denotes a command word, message recording can
begin with a data word when register bit 5 equals 1.
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Bit No. Mnemonic
R/W Reset Function
IMT Packet Timer Mode.
When the PKTMR bit is logic 0, the packet timer resets when the IMT
is enabled. The packet timer then starts counting when the next MIL-
STD-1553 message begins, at detection of the first valid command word
(or alternate Start-Record Requirement selected by bits 6-5 below.)
7
PKTMR
R/W
0
If the PKTMR bit is logic 1 when the IMT is enabled, the packet timer
resets then immediately starts when the IMT is enabled. In this mode,
whenever a data packet is finalized, the packet timer resets then
restarts, and new packet recording is immediately started. If enabled,
a PKTRDY (packet-ready) interrupt is generated for the host, at packet
completion.
IMT Start-Record Requirement 1:0.
When register bits 6-5 equal 00, the IMT starts recording a new
MIL-STD-1553 message when a properly encoded, complete MIL-
STD-1553 word with command sync is decoded: The command
sync is followed by 16 properly encoded data bits plus a 17th parity bit
expressing odd parity. No data is recorded until this condition is met.
This is the usual setting. (default setting)
When register bits 6-5 equal 01, the IMT starts recording a new
MIL-STD-1553 message when a properly encoded, complete MIL-
STD-1553 word with command sync or data sync is decoded. The
properly encoded command sync (or data sync) is followed by 16
properly encoded data bits plus a 17th parity bit expressing odd parity.
If recording begins with data sync, the Sync Error flag will be set in the
Block Status Word.
When register bits 6-5 equal 10, the IMT starts recording a new MIL-
STD-1553 message upon detection of a properly encoded command
sync with two contiguous data bits. If the properly encoded command
sync with two contiguous data bits does not result in a valid command
word, the Invalid Word Error is set in the Block Status Word. This
selection begins recording for complete MIL-STD-1553 command words
as well as for command word fragments, or command words with bad
parity. Under some circumstances, this record option might be helpful for
debugging MIL-STD-1553 communication failure.
6 − 5
MTSRR1:0
R/W
0
When register bits 6-5 equal 11, the IMT starts recording new bus
activity upon detection of any properly encoded sync (command or
data) with two contiguous data bits. This selection begins recording
for complete MIL-STD-1553 command or data words as well as for
word fragments, or words with bad parity. If the properly encoded sync
with two contiguous data bits does not result in a valid Manchester II
word, the Invalid Word Error is set in the Block Status Word. If recording
begins with data sync, the Sync Error flag will be set in the Block Status
Word. Under some circumstances, this record option might be helpful for
debugging MIL-STD-1553 communication failure.
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Bit No. Mnemonic
R/W Reset Function
IMT Continue Recording After Invalid Word.
When bit 4 equals 0, the IMT stops recording an incomplete message
when an invalid MIL-STD-1553 word is decoded. The invalid word is not
stored, and the IMT awaits word detection per register bits 6-5 before
the next MIL-STD-1553 message is recorded. (default)
4
MTCRIW
R/W
0
When bit 4 equals 1, the MT continues recording an incomplete
message when an invalid MIL-STD-1553 word is decoded. The invalid
word is stored and the IMT continues monitoring the message until
completion or time-out occurs.
IMT (Data Packet) Header and Trailer Disabled.
When bit 3 equals 0, the IMT reserves space for an IRIG-106 packet
header and packet trailer in the RAM buffer assigned in the MT Address
List. The Packet Header and Packet Trailer are automatically generated
by the device at packet finalization and stored in the assigned buffer.
(default)
3
IMTHTD
R/W
0
When bit 3 equals 1, the IMT generates only the IRIG-106 Packet Body,
stored in the assigned buffer. The full buffer address range is used for
message storage.
IMT Extended Message Flag Enable.
When register bit 2 equals 0, the recorded status/error flags are limited
2
MTXMF
R/W
0
to the defined bits in the IRIG-106 Block Status Word. See Section 14.6.
When register bit 2 equals 1, expanded status/error flags are enabled,
occupying “reserved” bit positions in the IRIG-106 Block Status Word.
IMT Checksum Enable
This IMT setting is only meaningful when IMTHTD (register bit 3) equals
0, enabling automatic generation of IRIG-106 data packet header and
packet trailer.
1
0
IMTCKSM
R/W
R/W
0
0
When register bit 1 equals 1, a 16-bit checksum is tallied for the data
packet body, and stored in the packet trailer at packet finalization.
When register bit 1 equals 0, no checksum is tallied for the data packet
body.
Select Simple Monitor Terminal (SMT) or IRIG-106 Monitor Terminal
(IMT).
SMT / IMT
This register bit must equal logic 0 for IMT operation. When this bit is
zero, the bus monitor operates in IMT IRIG-106 mode with 48-bit time
tag counter resolution.
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16.2. IMT Bus Monitor Address List Start Address Register (0x002F)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
1
7
0
6
1
5
1
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is Read-Write and is fully maintained by the host. After MR pin master reset, this register is initialized
with 0x00B0, the default base address of the Monitor Address Table in device RAM. The host can overwrite the default
base address. This register is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status
and Reset Register, 0x0001. The Address List for IMT monitor is shown in Table 14 on page 126.
16.3. IMT Bus Monitor Next Message Storage Pointer (0x0030)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is read-only and is updated by the IMT after completion of a monitored MIL-STD-1553 message.
This register is cleared after nMR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the
Master Status and Reset Register, 0x0001. This register contains the RAM address for the next-written Block Status
Word, for the next MIL-STD-1553 message. After the first post-reset message is logged, this register mirrors the value
contained in the Current Packet Start Address, word 1 in the Monitor Address List (see Table 14 on page 126).
The IMT logic only updates this “next message address” register after message completion. Therefore, after reset, this
register does not contain a valid pointer address until the next valid message is completed. If the read value equals
zero, the “next message address” equals the buffer start address.
16.4. IMT Bus Monitor Last Message Buffer Address (0x0031)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This 16-bit register is read-only and is updated by the IMT upon completion of a monitored MIL-STD-1553 message.
This register is cleared after nMR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the
Master Status and Reset Register, 0x0001. This register contains the Block Status Word address in RAM for the last
completed MIL-STD-1553 message.
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16.5. IMT Packet Maximum Message Count Register (0x002A)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor buffer. The HI-613x IMT finalizes the unfinished packet when the number of
MIL-STD-1553 messages in the packet reaches the value in this register. If register value is zero, this criteria is not
used for determination of end-of-packet.
16.5.1. Practical IRIG-106 packet message count considerations
IRIG-106 Chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. The maximum
number of packet messages occurs when the BC continuously transmits back-to-back broadcast mode code
commands without data, each with the minimal allowable intermessage gap of 4 µs, yielding 2 µs dead time between
commands. This results in repeating message transmission every 22 µs. Therefore the maximum packet message
count is (100 ms / 22 µs) or 4,545 messages occurring in the maximum allowed 100 ms packet interval. Therefore, for
strict compliance with IRIG-106, the maximum attainable packet message count is 4,545 decimal.
The HI-613x device can be configured to record packet times exceeding the IRIG-106 limit. Without regard for maximum
packet time allowed by IRIG-106, the maximum message count governed by HI-613x RAM capacity is a lower value. If
the HI-613x is configured as IMT only, the maximum contiguous RAM space is 0x7FFF – 0x01BF = 0x7E40 = 32,320
words. Maximum message storage space occurs when the HI-613x IMT is configured to provide the data Packet Body,
without packet header or trailer. 14 words are used for packet header, leaving 32,306 words for messages. If the BC
continuously transmits back-to-back broadcast mode code commands without data, each message consumes 8 words
of buffer space. This unlikely repeating message sequence yields the highest packet possible message count for a
RAM-limited HI-613x monitor, which is 32,306 / 8 = 4,038 messages. Transmit and receive subaddress commands
typically require far more than 8 stored words per MIL-STD-1553 message, so normal bus traffic will probably fill the
IMT Buffer far in advance of 4,000 messages.
16.6. IMT Packet Maximum 1553 Word Count Register (0x002B)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor buffer. The HI-613x IMT finalizes the unfinished packet when the number of
16-bit MIL-STD-1553 message words in the packet reaches the value in this register. This word count is comprised
of BC command, RT status and message data words. It excludes IRIG-106 header and trailer (if used) and message
block data words and time stamp words. If the register value is zero, this register is not used for determination of end-
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of-packet.
16.6.1. Practical IRIG-106 packet word count considerations
IRIG-106 Chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. The maximum
number of MIL-STD-1553 packet words occurs when the BC continuously transmits back-to-back 32 data word
broadcast receive with 32 data words, each with the minimal allowable intermessage gap of 4 µs, yielding 2 µs dead
time between commands. This results in repeating message transmission every 662 µs. Therefore (100 ms / 662 µs)
or 151.1 such messages occur in the maximum allowed 100 ms packet interval. Therefore, for strict compliance with
IRIG-106, the maximum number of MIL-STD-1553 words in a maximum duration 100 ms IRIG-106 packet is 151.1
messages x 33 words/message = 4,985 words.
The HI-613x permits longer packet recording times than 100 ms. The maximum contiguous RAM space in the device
RAM for an IMT Buffer is about 32,200 words, achievable when the device is configured as IMT only (no concurrent
BC or RTs). To achieve even larger packets, the host can accumulate Packet Body increments read from HI-613x
RAM in a separate, larger RAM. The HI-613x would probably be configured without automatic packet header and
trailer generation, to record message data in the format shown in Figure 7 “IRIG-106 Message Data Storage” on page
67. Upon completion of each large packet (accumulated from multiple HI-613x “sub-packets”), the host generates the
packet header, channel specific data and packet trailer for the accumulated packet data body.
16.7. IMT Maximum Packet Time Register (0x002C)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor buffer. The HI-613x IMT finalizes the unfinished packet if the packet data
recording time (measured in 10 µs increments) reaches the value in this register. If register value is zero, the register
is not used for determination of end-of-packet.
16.7.1. Practical IRIG-106 packet time considerations
IRIG-106 Chapter 10 stipulates a maximum packet time of 100 ms. Therefore, for strict compliance with the standard,
the maximum count contained in this register would be (100 ms / 10 µs) = 10,000 decimal. The HI-613x device logic
allows a maximum packet time greater than 100 ms. If the register contains 0xFFFF, the maximum packet time is
655.35 ms.
16.8. IMT Packet Maximum Gap Time Register (0x002D)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
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This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which
is when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message
data is stored in “data packets” in the monitor buffer. If the elapsed time between successive MIL-STD-1553 words
(measured in 10 µs increments) reaches the value in this register, the HI-613x IMT finalizes an unfinished packet. The
maximum time interval is 655.35ms. The measured interval restarts after each Manchester word, and ends with gap
time-out, or detection of the next-occurring valid Manchester word on either bus. Under normal circumstances, this
register is used for determination of gaps between MIL-STD-1553 messages, however message fragments containing
valid Manchester words also preempt time-out and restart the timer.
16.8.1. Practical IRIG-106 maximum gap time considerations
Word validation occurs about 3us after Manchester word completion. When the programmed value in this register is
N, the in-process packet will finalize at (10N + 3) µs, unless a valid Manchester word started before the maximum
bus “dead time” of (N-2) x 10 µs. When the stored register value is zero, this register is not used for end-of-packet
determination.
Example: This register contains 20 decimal. The resultant maximum allowed bus “dead time” between Manchester
words is 180 µs. When gap time exceeds this limit, packet finalization occurs at 203 µs, and (if enabled) MT interrupts
occur for Packet Ready and Maximum Gap Time. A valid Manchester word starting after 180 µs is not included the
finalized packet, but may be the first word in the following packet when bits 6-5 in the MT Configuration Register equal
0-0 or 0-1.
16.9. IMT Packet Header Channel ID Register (0x002E)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register is only used when the MT is configured for IRIG-106 Chapter 10 operational mode, with automatic
packet header and packet trailer generation. That is, when IMT bit 0 is initialized to logic 0, and IMTHTD bit 3 is
initialized to logic 1 in the MT Configuration Register 0x0029.
The IRIG-106 Chapter 10 packet header includes a 16-bit Channel ID. The value contained in this register is used for
the Channel ID field, when generating the packet header. The host must load a nonzero value into this register during
initialization because Channel ID of 0x0000 is reserved for computer-generated data packets.
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HI-6130, HI-6131
16.10. IMT Monitor Time Tag Count Low Register (0x003A)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
16.11. IMT Monitor Time Tag Count Mid Register (0x003B)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
16.12. IMT Monitor Time Tag Count High Register (0x003C)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
The IMT Bus Monitor always uses a 48-bit time base. The current time base value is reflected in these three 16-bit
registers. These registers are read-only and are cleared after MR pin Master Reset. Count bits 47-32 reside in register
0x003C, count bits 31-16 reside in register 0x003B while register 0x003A contains bits 15-0.
The host cannot directly write into these registers, but can otherwise control the MT Time Tag count. By writing bits
15-14 in the Time Tag Counter Configuration Register 0x0039, the host can:
•
•
•
clear the 48-bit time tag count to zero (by loading three 0x0000 values)
simultaneously copy the 3-register time value into the three IMT Time Tag Utility Registers
simultaneously load the value contained in the three IMT Time Tag Utility Registers into the IMT Time Tag count
registers.
Finally, three IMT Time Tag Match Registers provide capability for generating a host interrupt when the time tag count
reaches any predetermined 48-bit value. For further information, refer to the description of the Time Tag Counter
Configuration Register 0x0039.
16.13. IMT Time Tag Utility Low Register (0x003D)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
HOLT INTEGRATED CIRCUITS
136
HI-6130, HI-6131
16.14. IMT Time Tag Utility Mid Register (0x003E)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
16.15. IMT Time Tag Utility High Register (0x003F)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These multifunction registers are read-write and are cleared after MR pin Master Reset. This utility register triplet is
used for simultaneously copying a 48-bit value into the three corresponding IMT Time Tag Count Registers. These
registers are also used for simultaneously capturing the 48-bit value from the IMT Time Tag Count Registers. Please
refer to the description for bits 15-14 in the Time Tag Counter Configuration Register 0x0039 in Section 9.9.
16.15.1.Loading a 48-bit value into the three 16-bit SMT Time Tag Count Registers
When loading or clearing Time Tag count, the 16-bit value in utility register 0x003D is copied into SMT Time Tag Coun-
ter register 0x003A. Simultaneously, count bits 47-17 and count bits 31-16 are copied from Time Tag Utility registers
0x003F and 0x003E into SMT Time Tag Counter registers 0x003C and 0x003B.
16.15.2.Capturing a 48-bit value from the three 16-bit SMT Time Tag Count Registers
When capturing Time Tag count, the 16-bit value in SMT Time Tag Count register 0x003A is copied into Time Tag Utility
Register 0x003D. Simultaneously, count bits 47-17 and count bits 31-16 in SMT Time Tag Count registers 0x003C and
0x003B are copied into Time Tag Utility registers 0x003F and 0x003E respectively.
16.16. IMT Time Tag Match Low Register (0x0040)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
16.17. IMT Time Tag Match Mid Register (0x0041)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
HOLT INTEGRATED CIRCUITS
137
HI-6130, HI-6131
16.18. IMT Time Tag Match High Register (0x0042)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These registers are read-write and are cleared after MR pin Master Reset. When the MTTTM bit 6 is logic 1 in the
Hardware Interrupt Enable Register 0x000F, an interrupt occurs when the value stored in this register triplet matches
the 48-bit value in the IMT Time Tag Count Registers.
Please refer to the description for MTTTM bit 6 in the Hardware Interrupt Registers described in Section 9.7.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
16.19. IMT Bus Monitor Interrupt Registers and Their Use
Section 9.4 on page 36 through Section 9.6 describe how the host uses three Hardware Interrupt registers, the Interrupt
Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When the IMT is enabled, three
additional registers are dedicated to IMT interrupts. Comparable to the Hardware Interrupt register triplet, the IMT has
•
•
•
An IMT Interrupt Enable Register to enable and disable interrupts
An IMT Pending Interrupt Register to capture the occurrence of enabled interrupts
An IMT Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding
interrupt condition is enabled. Numerous interrupt options are available for the IMT. At initialization, bits are set in the
IMT Interrupt Enable register to identify the interrupt-causing events for the IMT which are heeded by the HI-613x.
Most IMT applications only use a subset of available IMT interrupt options. Interrupt-causing events are ignored when
their corresponding bits are reset in the IMT Interrupt Enable Register. Setting an Interrupt Enable register bit from 0
to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever an IMT interrupt event occurs (and the corresponding bit is already set in the IMT Interrupt Enable Register),
these actions occur:
•
•
The Interrupt Log Buffer is updated.
A bit corresponding to the interrupt type is set in the IMT Pending Interrupt Register. The type bit is logically-ORed
with the preexisting register value, retaining bits for prior, unserviced IMT interrupts.
•
MT Interrupt Pending (MTIP) bit 1 used by SMT or IMT is set in the Hardware Pending Interrupt Register. The
MTIP bit is logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts
and the preexisting status of the BCIP and RTIP (Bus Controller and RT) interrupt pending bits.
•
If the matching bit is already set in the IMT Interrupt Output Enable Register, an IRQ output occurs.
If the matching bit in the IMT Interrupt Output Enable Register was not already set (i.e., low priority polled interrupt),
the host can poll the IMT Pending Interrupt Register to detect the occurrence of IMT interrupts, indicated by non-zero
value. Reading the IMT Pending Interrupt Register automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four
Interrupt Output Enable registers (hardware, BC, RT and SMT or IMT). Multiple interrupt-causing events can occur
simultaneously, so single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.4 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
Hardware Pending Interrupt Register to indicate when BC, RT, SMT and/or IMT interrupts occur. When MT Interrupt
Pending (MTIP) bit 1 used by SMT or IMT is set in the Hardware Pending Interrupt Register, the IMT Pending Interrupt
Register contains a nonzero value and may be read next to identify the specific IMT interrupt event(s). Or, the host
can directly interrogate the Interrupt Count & Log Address Register, followed by the Interrupt Log Buffer. Data sheet
section 9.4 has a detailed description.
HOLT INTEGRATED CIRCUITS
139
HI-6130, HI-6131
16.19.1.IMT Bus Monitor Interrupt Enable Register (0x0011)
MAXWMRADXSMMSAGXSGMAAPXTHIMPESTPOKPTRRDeYserRveedserBveUdFMPAKTTFRWeserRvedserRveedserRveedserRvedserved
IRIGOVF
0
0
0
0
0
0
0
RW
9
0
0
0
0
0
0
0
0
R
1
0
MR Reset
Host Access
Bit
15
14 13 12 11 10
8
7
6
5
4
3
2
0
16.19.2.IMT Bus Monitor Pending Interrupt Register (0x0008)
MAXWMRADXSMMSAGXSGMAAPXTHIMPESTPOKPTRRDeYserRveedserBveUdFMPAKTTFRWeserRvedserRveedserRveedserRvedserved
IRIGOVF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
R
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
16.19.3.IMT Bus Monitor Interrupt Output Enable Register (0x0015)
MAXWMRADXSMMSAGXSGMAAPXTHIMPESTPOKPTRRDeYserRveedserBveUdFMPAKTTFRWeserRvedserRveedserRveedserRvedserved
IRIGOVF
0
0
0
0
0
0
0
RW
9
0
0
0
0
0
0
0
0
R
1
0
MR Reset
Host Access
Bit
15
14 13 12 11 10
8
7
6
5
4
3
2
0
These three registers govern IMT interrupt behavior: the IMT Interrupt Enable Register, the IMT Pending Interrupt
Register and the IMT Interrupt Output Enable Register. When a bit is set in the IMT Interrupt Enable Register, the
corresponding IMT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is
unconditionally disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that
occurred while the bit was zero.
When an enabled IMT interrupt event occurs, the corresponding bit is set in the IMT Pending Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, MTIP bit 1 in the Hardware Pending Interrupt Register
is also set whenever one or more bits are set in the IMT Pending Interrupt Register.
If the corresponding bit is already set in the IMT Interrupt Output Enable Register, the IRQ output pin is asserted at
Pending Interrupt Register assertion. The IMT Interrupt Output Enable Register establishes two priority levels: high
priority interrupts generate an IRQ output while low priority interrupts do not. Both priority levels update the IMT
Pending Interrupt Register and the Interrupt Log Buffer. The host detects low priority (masked) interrupts by polling
IMT Pending Interrupt Register.
The table below first describes the common bits 15-3 in all three IMT interrupt registers and then describes register-
to-register differences for bits 2-0.
HOLT INTEGRATED CIRCUITS
140
HI-6130, HI-6131
Bit No. Mnemonic
Function
IRIG-106 Buffer Overflow.
Since start-of-packet, data recording got within 64 words of overwriting the Packet Start
Address. The in-process packet terminated at end-of-message. Next message begins
next packet.
15
14
IRIGOVF
IRIG-106 Maximum MIL-STD-1553 Word Count Interrupt.
The in-process packet terminated at end-of-message when the number of MIL-
STD-1553 message words recorded in the packet attained the maximum word count
stored in the MT Packet Maximum MIL-STD-1553 Word Count Register at address
0x002B.
MAXWRDS
IRIG-106 Maximum Message Count Interrupt.
The in-process packet terminated at end-of-message when the number of recorded
MIL-STD-1553 messages equals the maximum message count stored in the IMT
Packet Maximum Message Count Register at address 0x002A.
13
12
11
MAXMSGS
MAXGAP
MAXTIME
IRIG-106 Maximum Gap Time Exceeded Interrupt.
The in-process packet terminated when the bus monitor encountered a MIL-STD-1553
message gap interval exceeding the maximum gap time stored in the MT Packet
Maximum Gap Time Register at address 0x002D.
IRIG-106 Maximum Recording Time Exceeded Interrupt.
The in-process packet terminated when the bus monitor reached the maximum packet
time stored in the MT Maximum Packet Time Register at address 0x002C. When
timeout occurs, packet finalization occurs after completion of an unfinished message.
Host Packet Stop Interrupt.
10
9
HPSTOP
PKTRDY
The host asserted the PKSTOP bit in the MT Configuration Register to stop the bus
monitor. Recording stopped after in-process message completion.
Packet Ready Interrupt.
Above register bits 15-10 are logically ORed to derive the state of this bit.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
8
7
Reserved
Reserved
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
Buffer Address Match Interrupt.
6
5
BUFMAT
PKTFW
The buffer pointer value has reached the interrupt address in Word 3 of the IMT Address
List.
Packet Fill Warning Interrupt.
Host previously initialized Word 7 in the IMT Address List with a word count value, N.
The current buffer pointer address has reached N words before overwriting the Current
Packet Start Address stored in Word 1 of the IMT Address List.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
4
3
Reserved
Reserved
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
HOLT INTEGRATED CIRCUITS
141
HI-6130, HI-6131
Bit No. Mnemonic
2 − 0 Reserved
Function
Bits 2-0 cannot be written, and read back 000.
HOLT INTEGRATED CIRCUITS
142
HI-6130, HI-6131
17. SINGLE OR DUAL REMOTE TERMINAL(S) − OVERVIEW
The HI-613x can operate as one or two autonomous MIL-STD-1553 Remote Terminals, requiring minimal host support.
When a single Remote Terminal (RT) is enabled, its configuration and operation is nearly identical to the Holt HI-612x
integrated circuit. When two RTs are enabled, they operate simultaneously and independently, with the full flexibility
of the Holt HI-612x remote terminal architecture. Designated as RT1 and RT2, the configuration registers for the two
terminals are completely duplicated, although certain (i.e., interrupt management) registers are shared between the
two RTs. Each terminal has its own Descriptor Table, command Illegalization Table and host interrupt configuration.
The discrete input / output pins for the two Remote Terminals are completely duplicated. The following signal pins are
provided for Remote Terminals RT1 and RT2:
•
•
•
•
•
•
RT1 and RT2 Terminal Address 4 - 0 input pins
RT1 and RT2 Terminal Address Parity input pins
RT1 and RT2 (Address) Lock input pins
RT1 and RT2 Enable input pins
RT1 and RT2 Subsystem Fail input pins
RT1 and RT2 Mode Code 8 (Reset Remote Terminal) output pins
By writing the Master Status and Reset Register, Remote Terminals RT1 and RT2 can be independently reset using
“soft reset”. Either or both RTs can be configured to automatically assert soft reset when a valid “Reset Remote
Terminal” mode code command is received. In this configuration, the serial auto-initialization EEPROM should already
be programmed with the desired attributes for the two terminals. When a broadcast “Reset Remote Terminal” mode
command is received, RT1 and RT2 perform soft reset independently, although the read-from-EEPROM time interval
is doubled.
In this section of the data sheet, the Remote Terminal registers are described first, followed by the details for configuring
and operating one or both RTs.
HOLT INTEGRATED CIRCUITS
143
HI-6130, HI-6131
18. REGISTERS USED BY REMOTE TERMINALS RT1 AND RT2
In addition to the registers described here, HI-6131 Remote Terminals RT1 and RT2 also utilize one or more Memory
Address Pointer registers (described in Section 9.10) for managing SPI read/write operations. This comment does not
apply for parallel bus interface HI-6130 designs.
18.1. Remote Terminal 1 (RT1) Configuration Register (0x0017)
Remote Terminal 2 (RT2) Configuration Register (0x0020)
RTTOR1TTOR0TINHRATINHBBCSTDBCEUNMACINOVTICSEM2CPTRXDABLTBIATUWTOMBCS1D7MOCP17MOCP016MOCP8TOPT
INV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit No. Mnemonic
R/W Reset Function
RT-RT Time Out Select.
This 2-bit field selects the “no response” time-out delay for RT-to-RT
receive commands from four available selections:
Bit 15:14
Bus Dead Time
RT-RT Time Out
00
01
10
11
15μs
20μs
58μs
138μs
57μs
62μs
100μs
180μs
15 − 14 RTTO1:0
R/W
0
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This
interval includes 20µs each for the embedded transmit command word
and transmit-RT status word within this span.
RT Bus A Inhibit.
If this bit is logic 1, Bus A for this RT is inhibited, as defined by the
BSDTXO bit in register 0. The BSDTXO bit offers two options: inhibit
transmit and receive, or inhibit only transmit. Setting the RTINHA bit
inhibits Bus A for just this RT, while allowing normal Bus A operation by
the BC or the other RT.
13
RTINHA
R/W
0
Note: If this bit is logic 0, Bus A is not inhibited here but its operation
may otherwise be globally inhibited by logic 1 at the TXINHA pin, or logic
1 at the TXINHA bit in the Master Status & Reset Register.
HOLT INTEGRATED CIRCUITS
144
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
RT1 Bus B Inhibit.
If this bit is logic 1, Bus B for this RT is inhibited, as defined by the
BSDTXO bit in register 0. The BSDTXO bit offers two options: inhibit
transmit and receive, or inhibit only transmit. Setting the RTINHB bit
inhibits Bus B for just this RT, while allowing normal Bus B operation by
the BC or the other RT.
12
RTINHB
R/W
0
Note: If this bit is logic 0, Bus B is not inhibited here for this RT but its
operation may otherwise be globally inhibited by logic 1 at the TXINHB
pin, or logic 1 at the TXINHB bit in the Master Status & Reset Register.
Broadcast Commands Invalid.
If this bit is high, commands addressed to RT address 31 are treated
as invalid: There is no terminal recognition of commands to RT address
31; there is no RT command response, and no status updating for the
benefit of following “transmit status” or “transmit last command” mode
commands. If this bit is low, commands addressed to RT address 31 are
treated as valid broadcast commands.
11
BCSTINV
R/W
0
Dynamic Bus Control Enable.
When this bit is logic 1, this RT accepts bus control after receiving a
valid legal “dynamic bus control” mode command. The RT STEX bit
in the Master Configuration Register resets to 0 and the BCSTRT bit
in the Master Configuration Register is set to logic 1. If dynamic bus
control is allowed, the BCENA input pin and register bit in the Master
Configuration Register must both be logic 1, and the bus controller
should be fully initialized in advance to permit immediate operation.
10
DBCENA
R/W
0
When this bit is logic 0, the host must perform all actions necessary to
change from RT to Bus Controller mode. Typically the RT Descriptor
Table is configured to generate an IWA interrupt to alert the host upon
receiving a valid legal Dynamic Bus Control mode code command, MC0.
Undefined Mode Codes Invalid.
This bit determines whether the RT treats undefined mode code
commands as valid (default) or invalid commands. This bit applies only
to the following undefined mode code commands:
•
•
•
Mode Codes 0 through 15 with T/R bit = 0
Mode Codes16, 18 and19 with T/R bit = 0
Mode Codes 17, 20 and 21 with T/R bit = 1
If this bit is low (default state after nMR pin reset) undefined mode
code commands are considered valid, and RT response is based on
individual mode command settings in the Illegalization Table: If mode
command is legal, the RT “responds in form” and updates status. If a
mode command is illegal, the RT asserts Message Error status and (if
non-broadcast) transmits only its Status Word without associated data
word.
9
UMCINV
R/W
0
If this bit is high, undefined mode code commands are treated as invalid:
There is no RT recognition of an invalid command, no RT command
response, and no status updating for the benefit of following “transmit
status” or “transmit last command” mode commands.
HOLT INTEGRATED CIRCUITS
145
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Notice 2 Broadcast Data Storage.
If this bit is high, the terminal stores data associated with broadcast
commands separately from data associated with non-broadcast
commands to meet the requirements of MIL-STD-1553B Notice 2. If this
bit is low, broadcast command data is stored in the same buffer with
data from non-broadcast commands.
8
7
NOTICE2
SMCP
R/W
R/W
0
0
Simplified Mode Command Processing.
When this bit is asserted, the respective remote terminal RT1 or RT2
applies “Simplified Mode Command Processing” for all valid mode code
commands, as described in Section 21.5 on page 212.
Temporary Receive Data Buffer.
When this bit is asserted, the respective remote terminal RT1 or RT2
enables a temporary receive data buffer used during receive commands.
See Section 19.3 on page 168. When this bit is asserted, RT1 or RT2
stores received data words in a 32-word data buffer during message
processing. Only after error-free message completion, are the buffered
words are written into the data buffer memory assigned to the specific
subaddress in the RT1 or RT2 Descriptor Table. This bit should only
be modified when RT1STEX and RT2STEX bits are low in Master
Configuration Register 0x0000 (see Section 9.1 on page 29). Changing
the TRXDB bit when the RT1STEX or RT2STEX configuration bit is
logic-1 causes unpredictable results.
6
TRXDB
R/W
0
Alternate BIT Word Enable.
When this bit is logic 0, the respective remote terminal RT1 or RT2
responds to a “transmit BIT word” mode command (MC19) by sending
the word stored in its Built-In Test Word register. The Built-In Test Word
register for RT1 resides at address 0x001E. The Built-In Test Word
register for RT2 is at address 0x0027.
When this bit is logic 1, the respective remote terminal RT1 or RT2
responds to a “transmit BIT word” mode command (MC19) by sending
the word stored in its Alternate Built-In Test Word register. The Alternate
Built-In Test Word register for RT1 resides at address 0x001F. The
Alternate Built-In Test Word register for RT2 is at address 0x0028. Using
an Alternate Built-In Test Word register allow the user to fully define the
BIT word, while the default Built-In Test Word register locations contain
several predefined, device-controlled status bits.
5
ALTBITW
R/W
0
HOLT INTEGRATED CIRCUITS
146
HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Automatic Bus Shutdown Enable.
The Bus Controller exercises “shutdown“ control over Remote Terminal
connections to the inactive MIL-STD-1553 bus using the “transmitter
shutdown” (MC4) or “selected transmitter shutdown” (MC20 decimal)
mode code commands. These apply only to the inactive bus. The RT
cannot shutdown the bus where the command is received. When the
inactive bus transmitter is shutdown, the HI-613x device inhibits further
transmission affected on that bus for the affected RT(s). Once shutdown,
the transmitter can be reactivated by (a) an “override transmitter
shutdown” (MC5) mode command, (b) an “override selected transmitter
shutdown” (MC21 decimal) mode command, (c) a “reset remote
terminal” (MC8) mode command, (d) asserting hardware MR Master
Reset input pin or (e) software reset initiated by setting the RT1RESET
or RT2RESET bit in the Master Status and Reset Register 0x0001.
With the AUTOBSD bit reset, the device only transmits RT status upon
receiving MC4, MC5, MC20 or MC21. The host must perform bus
shutdown and override duties by asserting control of the TXINHA and
TXINHB bits in the Master Configuration Register, or by controlling the
input pins with the same function.
4
AUTOBSD
R/W
0
With AUTOBSD bit set, upon receiving MC4 (or MC20 with data word
matching “bus select” criteria), the device automatically fulfills transmit
shutdown for the inactive bus. When the BSDTXO bit in the Master
Configuration Register equals 0, the inactive bus receiver is also
shutdown (full bus shutdown vs. only transmit shutdown). The device
affirms shutdown status by setting the corresponding “shutdown status”
bits 15-12 in the applicable RT BIT Register(s), address 0x001E for RT1,
or 0x0027 for RT2.
With AUTOBSD bit set, upon receiving MC5 (or MC21 with data word
matching “bus select” criteria), the device automatically re-enables both
transmit and receive for the inactive bus (without regard to BSDTXO
bit in the Master Configuration Register). The device affirms shutdown
override status by resetting corresponding “shutdown status” bits 15-12
in the applicable RT BIT Register(s), address 0x001E for RT1, 0x0027
for RT2.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
MC17 Sync Option Bits 1:0
If register bits 3-2 equal 11, the data word received with a valid
“synchronize” mode command (MC17) is unconditionally loaded into
the Time-Tag counter, at address 0x0047 for RT1 or 0x0049 for RT2.
For non-broadcast MC17 commands, the counter load occurs before
status word transmission. If register bits 3-2 equal 00, the external host
assumes responsibility for actions needed to perform “synchronize”
duties upon reception of the valid MC17 “synchronize” mode code
command, but status transmission automatically occurs.
3 − 2
MC17OP1:0 R/W
0
The binary 01 and 10 combinations of register bits 3-2 support certain
extended subaddress schemes. If bits 3-2 equal 01, the received data
word is automatically loaded into the Time-Tag counter if bit 0 of the
received data word equals 0. The counter resides at address 0x0047
for RT1 or 0x0049 for RT2. If bits 3-2 equal 10, the received data word
is automatically loaded into the Time-Tag counter if bit 0 of the received
data word equals 1. For non-broadcast MC17 commands, the counter
load occurs before status word transmission.
Host reset of “service request” status bit for mode code 16.
If this bit is logic 0, reception of a “transmit vector word” mode command
(MC16) causes automatic reset of the Service Request status bit. The
Service Request bit is reset in the Status Word Bits register before
status word transmission begins. If the MCOPT1 bit is logic 1, the
external host assumes responsibility for resetting the Service Request
bit in the Status Word Bits register.
1
0
MC16OPT
MC8OPT
R/W
R/W
0
0
Automatic soft reset for mode code 8.
If this bit is logic 0, reception of a “reset remote terminal” mode
command (MC8) causes automatic assertion of SRESET software
reset. If non-broadcast mode command, reset occurs after status word
transmission is complete. If this bit is logic 1, the external host assumes
responsibility for actions needed to perform terminal reset.
18.2. Remote Terminal 1 (RT1) Operational Status Register (0x0018)
Remote Terminal 2 (RT2) Operational Status Register (0x0021)
F
4
3
2
1
0
P
P
A
A
A
A
A
A
A
T
T
T
T
T
T
T
R
R
R
R
R
R
LOCKReserRveedserRvedserMveCdNDMCRDMCTDR
ReserRvedserved
These bits latch pins
RW (see LOCK bit 9)
0
0
0
0
0
R
4
0
0
0
0
MR Reset
Host Access
Bit
15 14 13 12 11 10
9
8
7
6
5
3
2
1
0
At rising edge on the MR Master Reset input pin, register bits 15-9 capture the logic states (0 or 1) of the correspond-
ing input pins having like names. After reset, register bits 15-9 can be overwritten only if LOCK bit 9 is logic 0. If the
register LOCK bit is logic 1, these bits are read-only.
Bits 8-0 are read-only; these bits are cleared after MR pin master reset, but are unaffected by assertion of RTxRESET
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HI-6130, HI-6131
remote terminal software reset in the Master Status and Reset Register (0x0001).
Bit No. Mnemonic
R/W Reset Function
Remote Terminal Address bits 4-0.
Remote Terminal Address Parity.
These bits reflect the active remote terminal address. They reflect the
state of the input pins RTA4 through RTA0 that applied at the rising edge
of the MR master reset input signal. The RTAP bit, when appended
to the remote terminal address bits, provides odd parity. If the register
LOCK bit is high, bits 15-10 are read-only. If the register LOCK bit is low,
the host can overwrite these bits change the terminal address and parity.
15 − 11 RTA4:0
R/W
0
10
RTAP
Remote Terminal Address Lock.
This bit reflects the state of the LOCK input pin that applied at the rising
edge of the MR master reset input signal. After reset, the host can
overwrite bits 15-9 only if register LOCK bit 9 is logic 0. When the LOCK
bit is high, the host cannot overwrite register bits 15-9. To restore host
write capability for these bits, the MR master reset input signal must first
be asserted with the LOCK input pin held low to restore register LOCK
bit 9 to logic 0.
9
LOCK
R/W
0
0
8 − 6
Reserved
R
These bits are not used.
No Data Mode Command Flag.
Receive Data Mode Command Flag.
Transmit Data Mode Command Flag.
These three bits reflect the type of command stored in the RT Current
Command Register:
5
4
3
MCND
MCRD
MCTD
Bits
5-4-3
R
0
Current Command Type
Current Command Word
Subaddress, not mode code
Mode code, no data word
Mode code, received word
Mode code, transmit word
Mode code, undefined
000
100
010
001
111
Subaddress, transmit or receive
MC0 to MC15, T/R bit = 1
MC16 to MC31, T/R bit = 0
MC16 to MC31, T/R bit = 1
MC0 to MC15, T/R bit = 0
Remote Terminal Address Parity Fail.
This bit is set when RT address parity error occurs for the value
contained in register bits 15-10. It is low when correct odd parity applies
for bits 15-10.
2
RTAPF
R
R
0
0
1 − 0
Reserved
These bits are not used.
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18.3. Remote Terminal 1 (RT1) Current Command Register (0x0002)
Remote Terminal 2 (RT2) Current Command Register (0x0004)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
These 16-bit registers are read-only and are fully maintained by the device. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001).
This register contains the last valid command word received by the Remote Terminal over either MIL-STD-1553 bus.
This register is updated 5µs after the ACTIVE output is asserted.
18.4. Remote Terminal 1 (RT1) Current Control Word Address Register (0x0003)
Remote Terminal 2 (RT2) Current Control Word Address Register (0x0005)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
These 16-bit registers are read-only and are fully maintained by the device. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001).
These registers contain the address for the descriptor table Control Word corresponding to the current command
stored in the Current Command Register, above. These registers are updated 5 µs after the ACTIVE output is as-
serted for recognition of a valid command for the RT. Also see description for the “Current Message Information Word
Address” register.
18.5. Remote Terminal 1 (RT1) Descriptor Table Base Address Register (0x0019)
Remote Terminal 2 (RT2) Descriptor Table Base Address Register (0x0022)
MSB
Register Value
LSB
0
MR Reset
Host Access
Bit
0
0
0
0
0
0
1
0
0
0
0
5
0
0
3
0
2
0
1
R
RW
R
4
15 14 13 12 11 10
9
8
7
6
0
Register Address 0x0019 (RT1)
MSB
Register Value
LSB
0
MR Reset
Host Access
Bit
0
0
0
0
0
1
0
0
0
0
0
5
0
0
3
0
2
0
1
R
RW
R
4
15 14 13 12 11 10
9
8
7
6
0
Register Address 0x0019 (RT1)
These 16-bit registers are Read-Write and contain the starting address for the Remote Terminal’s Descriptor Table.
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These registers are initialized with default values after MR pin master reset, or by assertion of RTxRESET remote
terminal software reset in the Master Status and Reset Register (0x0001). For RT1, the post-reset register value is
0x0200. For RT2, the post-reset register value is 0x0400. After initialization, these registers are fully maintained by
the host. Bit 15 and bits 8:0 cannot be set and will always read logic 0.
18.6. Remote Terminal 1 (RT1) MIL-STD-1553 Status Word Bits Register (0x001A)
Remote Terminal 2 (RT2) MIL-STD-1553 Status Word Bits Register (0x0023)
ReserRvesderRveedserRvesdervMeEd INST SVCRREeQserRveedserRvesderved
TXANDCLR BCR BUSYSSYSRFeserTvFed
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
15 14 13 12 11 10
RW
R
RW
R RW
9
8
7
6
5
4
3
2
1
0
These 16-bit registers are Read-Write. With the exception of bits 4 and 10, these registers are maintained by the host.
These registers are cleared after MR pin master reset, or by assertion of RTxRESET remote terminal software reset
in the Master Status and Reset Register (0x0001).
Register bits 14-10 and 7-4 are read-only. Most of these bits read back zero, except for bits 4 and 10, which are main-
tained by the device. The remaining bits in the register are Read-Write and are maintained by the host. All bits are
active high. Register bits 10-0 are reflected in the outgoing MIL-STD-1553 RT status word. The RT status word reflects
the state of host-written register bits until overwritten by the host, unless the Transmit and Clear function (bit 15) is
enabled. When set, the Transmit and Clear bit resets itself and bits 9-5 and 3-0 after the next transmitted status word.
Bit No. Mnemonic
R/W Reset Function
Transmit and Clear.
When this bit is set, it resets itself and bits 9-5 and 3-0 after the next
transmitted status word. This bit does not affect operation of the
Transmit Status Word and Transmit Last Command mode codes.
Example: Transaction of a valid legal command with the INST and
TXANDCLR bits asserted results in status word transmission with the
Instrumentation bit set. If the following command is Transmit Status or
Transmit Last Command mode code, the Instrumentation bit remains
set.
15
TXANDCLR R/W
0
14 − 11 Reserved
R
R
0
0
These bits are not used, cannot be written, always read back 000.
Message Error status bit.
10
9
ME
The device maintains this read-only bit, based on prior message results.
Instrumentation status bit.
INST
R/W
0
The host maintains this read-write bit.
Service Request status bit.
8
SVCREQ
Reserved
R/W
R
0
0
The host maintains this read-write bit.
7 − 5
These bits are not used, cannot be written, always read back 000.
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
Broadcast Command Received status bit.
4
BCR
R
0
The device maintains this read-only bit, based on prior message results.
Busy status bit.
The host maintains this read-write bit. When set, the RT asserts its
Busy bit in status response for all valid commands. Instead of enabling
Busy for all commands, the host can assert Busy status for selected
commands by asserting the Busy bit in descriptor table Control Words
for the individual commands. When response to a command conveys
Busy status, the RT suppresses transmission of data words that would
normally accompany
3
BUSY
R/W
0
status for transmit commands. For messages transacted with
Busy status, the WASBUSY flag is asserted in the stored Message
Information Word.
Subsystem Fail status bit.
The host maintains this read-write bit. This register bit is logically ORed
with the RT’s SSYSF input pin. If either SSYSF register bit or SSYSF
pin is asserted, the SSYSF Subsystem Flag status bit is set. If the RT’s
Configuration Register MCOPT1 bit equals 0, reception of a “transmit
vector word” mode command (MC16) causes automatic reset of the
SSYSF status bit in this register; when this occurs, the register bit is
reset before status word transmission begins.
2
SSYSF
R/W
0
Dynamic Bus Control status bit.
1
0
DBC
TF
R
0
0
The host maintains this read-write bit.
Terminal Flag status bit.
The host maintains this read-write bit. When this bit is asserted, the
Terminal Flag status bit is set. If the Terminal Flag bit is set while
responding to subaddress transmit commands or mode code commands
16-31 that normally transmit a data word, all data word transmission is
suppressed.
R/W
18.7. Remote Terminal 1 (RT1) Current Message Information Word Register (0x001B)
Remote Terminal 2 (RT2) Current Message Information Word Register (0x0024)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
These 16-bit registers are Read-Only and are fully maintained by the device. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001). This register contains the data buffer address (assigned in the terminal’s Descriptor Table)
corresponding to the last decoded valid command’ for the Remote Terminal. This register is updated 5µs after the
ACTIVE output is asserted.
The value in this register points to the command’s Message Information Word (or MIW) in the Descriptor Table, The
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value of the current command word itself is stored in the Current Command Register for the Remote Terminal, RT1 or
RT2.
18.8. Remote Terminal 1 (RT1) Bus A Select Register (0x001C)
Remote Terminal 2 (RT2) Bus A Select Register (0x0025)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These 16-bit registers are Read-Write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001).
The BusASelect register is only used when theAUTOBSD bit in the RTConfiguration Register equals 1. ThisAUTOBSD
setting means the device automatically fulfills mode commands MC20 (decimal) “selected transmitter shutdown” or
MC21 “override selected transmitter shutdown”. “Transmitter shutdown” or “shutdown override” can only occur for
the inactive bus. If either mode command is received on Bus B, the inactive bus is Bus A. The device compares the
received mode data word to the contents of the Bus A Select register to determine whether inactive Bus A is selected
for “transmitter shutdown” or “transmitter shutdown override”. (Bus shutdown or shutdown override can only occur for
the inactive bus.) If the data word matches the value stored in the Bus A Select register and AUTOBSD equals 1, the
device automatically fulfills MC20 “transmitter shutdown” or MC21 “shutdown override” without host assistance: If the
mode command received was MC20 (bus shutdown), the Transmit Shutdown A bit in the RT’s BIT (built-in test) Word
Register is asserted. If mode command MC21 (override bus shutdown) was received, the Transmit Shutdown A bit in
the BIT Word Register is negated.
18.9. Remote Terminal 1 (RT1) Bus B Select Register (0x001D)
Remote Terminal 2 (RT2) Bus B Select Register (0x0026)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These 16-bit registers are Read-Write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001).
The Bus B Select register is only used when the AUTOBSD bit in the RT Configuration Register equals 1. This AUTO-
BSD setting means the device automatically fulfills mode commands MC20 (decimal) “selected transmitter shutdown”
or MC21 “override selected transmitter shutdown”. “Transmitter shutdown” or “shutdown override” can only occur for
the inactive bus. If either mode command is received on Bus A, the inactive bus is Bus B. The device compares the
received mode data word to the contents of the Bus B Select register to determine whether inactive Bus B is selected
for “transmitter shutdown” or “transmitter shutdown override”. (Bus shutdown or shutdown override can only occur for
the inactive bus.) If the data word matches the value stored in the Bus B Select register and AUTOBSD equals 1, the
device automatically fulfills MC20 “transmitter shutdown” or MC21 “shutdown override” without host assistance: If the
mode command received was MC20 (bus shutdown), the Transmit Shutdown B bit in the RT’s BIT (built-in test) Word
Register is asserted. If mode command MC21 (override bus shutdown) was received, the Transmit Shutdown B bit in
the BIT Word Register is negated.
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18.10. Remote Terminal 1 (RT1) Built-In Test (BIT) Word Register (0x001E)
Remote Terminal 2 (RT2) Built-In Test (BIT) Word Register (0x0027)
T
User Assigned Bits
TXAS
T
D
XBSRDXAS
R
D
XBSD
LBFALBFBBMTFR
EELFTFBINH
MR Reset
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Host Access
Bit
R
RW
R
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bits 11-6 in these 16-bit registers are read-write; the remaining bits are read-only. The ten assigned bits are written
by the device when predetermined events occur. The host may overwrite the device-written bits 5 and 4. After MR
pin master reset, bits 13-12, 5-4 and 0 are reset. Bits 15-14 will be set if the corresponding TXINHA or TXINHB input
pins are high. Bits 3-1 will be set if RT address parity error, or post-MR memory test failure or auto-initialization failure
occurred. These registers are not affected by assertion of RTxRESET remote terminal software reset in the Master
Status and Reset Register (0x0001). Remote terminals RT1 and RT2 use independent BIT Word registers.
If the ALTBITW option bit in the RT1 or RT2 Configuration Register is zero when a valid “transmit BIT word” mode
command (MC19) is received, the current value in this register is transmitted as the mode data word in the terminal
response. The value is also copied to the Remote Terminal’s assigned data buffer for MC19, after mode command
fulfillment.
Bit No. Mnemonic
R/W Reset Function
Transmit Bus A Shutdown.
Transmit Bus B Shutdown.
These read-only bits are set when the corresponding bus transmitter
was disabled by assertion of the bus TXINHA or TXINHB input pin, or
by fulfillment of a “transmitter shutdown” mode command, either MC4
or MC20. Refer to the description for the BSDTXO bit in the Master
Configuration Register (page 29) and the description for theAUTOBSD bit
in the RT Configuration Register for further information.
15
14
TXASD
TXBSD
R
0
Receive Bus A Shutdown.
Receive Bus B Shutdown.
These read-only bits are set when the corresponding bus receiver was
disabled concurrently with a bus transmitter by a “transmitter shutdown”
mode command MC4 or MC20. Refer to the description for the BSDTXO
bit in the Master Configuration Register (Section 9.1) and the description
for the AUTOBSD bit in the RT Configuration Register for further
information.
13
12
RXASD
RXBSD
R
0
11 − 6 ----------
R/W
R
0
0
User assigned bits.
Bus A Loopback Fail.
Bus B Loopback Fail.
5
4
LBFA
LBFB
These read-only bits are set if Bus A or Bus B loopback failure occurs
during self-test (see Section “24.2.1. Self-Test Control Register
(0x0028)” on page 226).
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HI-6130, HI-6131
Bit No. Mnemonic
R/W Reset Function
BIST Memory Test Fail.
This bit is set if error occurs during built-in self-test for device Random
Access Memory (RAM) (see Section “24.2.1. Self-Test Control Register
(0x0028)” on page 226).
3
BMTF
R
0
RT Address Parity Fail.
This bit is asserted when an RT1 or RT2 Operational Status Register
bits 15:10 reflect parity error. After MR master reset, bits 15:10 in the
RT’s Operational Status Register reflect input pin states, but will be
overwritten if subsequent auto-initialization is performed (if AUTOEN
pin is high) and the initialization EEPROM contains different data for RT
Operational Status Register bits 15:10.
2
RTAPF
R
0
Auto-Initialization EEPROM Load Fail.
This bit only applies when auto-initialization is enabled (AUTOEN input
pin state equals 1). This bit is set if, after MR master reset, failure occurs
when copying serial EEPROM to registers and RAM. When this occurs,
bit 0 or bit 1 will be set in the RT’s Operational Status Register (0x0002)
to indicate type of failure.
1
0
EELF
R
R
0
0
This bit is set when the Terminal Flag status bit is disabled while fulfilling
an “inhibit terminal flag bit” mode code command (MC6). This bit is reset
if terminal flag status bit disablement is cancelled later by an “override
inhibit terminal flag bit” mode code command (MC7).
TFBINH
18.11. Remote Terminal 1 (RT1) Alternate Built-In Test (BIT) Word Register (0x001F)
Remote Terminal 2 (RT2) Alternate Built-In Test (BIT) Word Register (0x0028)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
It is not affected by assertion of RTxRESET remote terminal software reset in the Master Status and Reset Register
(0x0001). If the ALTBITW option bit in the RT1 or RT2 Configuration Register equals one when a valid “transmit BIT
word” mode command (MC19) is received, the current value in this register is transmitted as the mode data word in
the terminal response. The value is also copied to the assigned data buffer for MC19, after mode command fulfillment.
18.12. Remote Terminal 1 (RT1) Time Tag Counter Register (0x0049)
Remote Terminal 2 (RT2) Time Tag Counter Register (0x004B)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
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This register is read-only and is cleared after MR pin Master Reset or assertion of RTxRESET remote terminal software
reset in the Master Status and Reset Register (0x0001). Reads to this register address return the current value of
the free running 16-bit Time Tag counter. Counter resolution is programmed by the TTCK2:0 bits in the Time Tag
Configuration Register. Options are: 2, 4, 8, 16, 32 and 64µs, or externally provided clock. The same clock source is
shared by RT1, RT2 and the BC.
The device automatically resets the Time-Tag Counter when a “synchronize” mode command without data (MC1) is
received. In addition, the host can reset, load or capture the Time Tag count at any time by asserting action bits in
the Time Tag Configuration Register. Load and capture operations utilize the RT Time Tag Utility Registers, described
below.
The MC17OP1:0 bits in the Remote Terminal Configuration Registers allow automatic loading of Time-Tag count using
the data word received with a “synchronize with data” mode command, MC17. If both of these bits equal one, the data
word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter.
For non-broadcast MC17 commands, the counter load occurs before status word transmission. If both MC17OP1 and
MC17OP0 bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties
upon reception of the valid MC17 “synchronize” command, but status transmission occurs automatically.
The binary 01 and 10 combinations of these bits support certain extended subaddressing schemes. If the MC17OP1:0
bits equal 01, the received data word is automatically loaded into the Time-Tag counter if the low order bit of the re-
ceived data word (bit 0) equals 0. If the MC17OP1:0 bits equal 10, the received data word is automatically loaded into
the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. For non-broadcast MC17 com-
mands, the counter is loaded before status word transmission.
18.13. Remote Terminal 1 (RT1) Time Tag Utility Register (0x004A)
Remote Terminal 2 (RT2) Time Tag Utility Register (0x004C)
MSB
0
Register Value
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
These 16-bit registers are Read-Write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are not affected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001). These registers have two functions associated with the two free-running Remote Terminal
Time Tag Counters:
18.13.1.RT Time Tag Counter Loading
When the RT1TTA1-0 bits 9-8 in Time Tag Counter Configuration Register 0x0039 are written to 1-0, the value con-
tained in the RT1 Time Tag Utility Register (0x0048) is loaded into the RT1 Time Tag Counter (0x0047).
When the RT2TTA1-0 bits 11-10 in Time Tag Counter Configuration Register 0x0039 are written to 1-0, the value
contained in the RT2 Time Tag Utility Register (0x0049) is loaded into the RT2 Time Tag Counter (0x004A).
18.13.2.RT Time Tag Count Match Interrupts
If the RT1TTM or RT2TTM interrupts are enabled in the Hardware Interrupt Enable Register (0x000F), then time tag
“count match” interrupts are enabled. When enabled for RT1, the hardware RT1TTM interrupt occurs when the free
running RT1 Time Tag Counter (0x0047) matches the value contained in the RT1 Time Tag Utility Register (0x0048).
When enabled for RT2, the hardware RT2TTM interrupt occurs when the free running RT2 Time Tag Counter (0x0049)
matches the value contained in the RT2 Time Tag Utility Register (0x004A).
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18.14. RT1 and RT2 Remote Terminal Interrupt Registers and Their Use
Section 9.4 on page 36 through Section 9.6 describe how the host uses three Hardware Interrupt registers, the Interrupt
Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When RT1/RT2 is enabled, three
additional registers are dedicated to the RT1/RT2 interrupts. Comparable to the Hardware Interrupt register triplet,
RT1/RT2 has
•
•
•
A RT1/RT2 Interrupt Enable Register to enable and disable interrupts
A RT1/RT2 Pending Interrupt Register to capture the occurrence of enabled interrupts
A RT1/RT2 Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available for RT1/RT2. At initialization, bits are set in the RT1/RT2
Interrupt Enable register to identify the interrupt-causing events for RT1/RT2 which are heeded by the HI-613x. Most
RT1/RT2 applications only use a subset of available RT1/RT2 interrupt options. Interrupt-causing events are ignored
when their corresponding bits are reset in the RT1/RT2 Interrupt Enable Register. Setting an Interrupt Enable register
bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever a RT1/RT2 interrupt event occurs (and the corresponding bit is already set in the RT1/RT2 Interrupt Enable
Register), these actions occur:
•
•
The Interrupt Log Buffer is updated.
A bit corresponding to the interrupt type is set in the RT1/RT2 Pending Interrupt Register. The type bit is logically-
ORed with the preexisting register value, retaining bits for prior, unserviced RT1/RT2 interrupts.
•
RT Interrupt Pending (RTIP) bit 1 shared by RT1 and RT2 is set in the Hardware Pending Interrupt Register. The
RTIP bit is logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts
and the preexisting status of the BCIP and MTIP (Bus Controller and MT) interrupt pending bits.
•
If the matching bit is already set in the RT1/RT2 Interrupt Output Enable Register, an IRQ output occurs.
If the matching bit in the RT1/RT2 Interrupt Output Enable Register was not already set (i.e., low priority polled
interrupt), the host can poll the RT1/RT2 Pending Interrupt Register to detect the occurrence of RT1/RT2 interrupts,
indicated by non-zero value. Reading the RT1/RT2 Pending Interrupt Register automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four
Interrupt Output Enable registers (hardware, BC, RT and SMT or IMT). Multiple interrupt-causing events can occur
simultaneously, so single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.4 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
Hardware Pending Interrupt Register to indicate when BC, RT, SMT and/or IMT interrupts occur. When RT Interrupt
Pending (RTIP) bit 1 shared by RT1 and RT2 is set in the Hardware Pending Interrupt Register, the RT1/RT2 Pending
Interrupt Register contains a nonzero value and may be read next to identify the specific RT1/RT2 interrupt event(s).
Or, the host can directly interrogate the Interrupt Count & Log Address Register, followed by the Interrupt Log Buffer.
Data sheet section 9.4 has a detailed description.
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18.14.1.Remote Terminal (RT) Interrupt Enable Register (0x0012)
RT2MICX8EQZIL2CMDIB
2R2 MERRIW2 A2ReserRveTd1MICX8EQZIL1CMDIB1R1 MERRIW1 A1ReserRveedserRvedserved
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
9
R
1
15 14 13 12 11 10
8
7
6
5
4
3
2
0
18.14.2.Remote Terminal (RT) Pending Interrupt Register (0x0009)
RT2MICX8EQZIL2CMDIB
2R2 MERRIW2 A2ReserRveTd1MICX8EQZIL1CMDIB1R1 MERRIW1 A1ReserRveedserRvedserved
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
18.14.3.Remote Terminal (RT) Interrupt Output Enable Register (0x0016)
RT2MICX8EQZIL2CMDIB
2R2 MERRIW2 A2ReserRveTd1MICX8EQZIL1CMDIB1R1 MERRIW1 A1ReserRveedserRvedserved
MR Reset
Host Access
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
9
R
1
15 14 13 12 11 10
8
7
6
5
4
3
2
0
Three registers govern RT interrupt behavior: the RT Interrupt Enable Register, the RT Pending Interrupt Register
and the RT Interrupt Output Enable Register. When a bit is set in the RT Pending Interrupt Enable Register, the
corresponding RT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is
unconditionally disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that
occurred while the bit was zero.
When an enabled RT interrupt event occurs, the corresponding bit is set in the Pending RT Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, RTIP bit 2 in the Hardware Pending Interrupt Register
is also set whenever a message sets at least one bit in the RT Pending Interrupt Register.
If the corresponding bit is set in the RT Interrupt Output Enable Register, the IRQ output is asserted at message
completion. The RT Interrupt Output Enable Register establishes two priority levels: high priority interrupts generate an
IRQ output while low priority interrupts do not. Both priority levels update the Pending Interrupt Register and Interrupt
Log Buffer. The host can detect low priority (masked) interrupts by polling Pending Interrupt registers.
The following table describes the shared bit descriptions used by all three RT interrupt registers.
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Bit No. Mnemonic
Function
RT2 Mode Code 8 Command Interrupt.
Remote terminal RT2 processed a valid MIL-STD-1553 “reset remote terminal” mode
code command. An RTxMC8 interrupt notifies the host when the Bus Controller
commands remote terminal reset.
The state of bit 0 in the RT2 Remote Terminal Configuration Register 0x0020
determines whether the mode code response is automatic or handled by the host. If
the RT2MC8 bit is reset in the RT Interrupt Enable register when RT2 decodes a valid
“reset remote terminal” mode command, bit 0 in the RT2 Remote Terminal Configuration
Register dictates whether the reset response is automatic, or host controlled. The event
does not affect the RT Pending Interrupt Register, the Interrupt Log or the IRQ output,
but the RT2MC8 output pin is asserted to indicate that RT2 needs reset. In the case of a
broadcast command to RT31, both MC8 pins will be asserted.
15
RT2MC8
RT2 Index Equals Zero Interrupt.
The “index equals zero” (IXEQZ) interrupt for RT2. Index counts are used in multi-
message bulk data transfers. “Index equals zero” occurs when the last expected
message was transacted.
14
IXEQZ2
Defined IXEQZ interrupt events comprise: (a) subaddresses using indexed buffer mode
when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes
when the pre-determined number of messages has been transacted.
RT2 Illegal Command Interrupt.
The Remote Terminal 2 encountered a valid illegal message, as defined in the RT2
Illegal Command Table.
Illegal commands are detected when a new valid command word is decoded and the
RT2 Illegalization Table bit corresponding to the received command is logic 1. (Table
bits are logic 0 for legal commands.) The RT2 Illegalization Table contains nonzero
values only when “illegal command detection” is being applied. When illegal commands
are received, RT2 responds by transmitting a status word with ME “message error” flag
set; no data words are transmitted.
13
ILCMD2
If the ILCMD2 bit is reset in the RT Interrupt Enable Register when a valid illegal
command is decoded, the event does not affect the RT Pending Interrupt Register, the
Interrupt Log or the IRQ output.
RT2 Broadcast Command Received Interrupt.
12
11
IBR2
Broadcast commands are enabled for Remote Terminal 2 and the terminal encountered
a valid command addressed to RT31, the broadcast command address.
RT2 Message Error Status Interrupt.
The Remote Terminal 2 set its Message Error status flag while processing a valid MIL-
STD-1553 message. Message errors are caused by Manchester encoding problems or
protocol errors.
MERR2
RT2 Interrupt When Accessed.
The Remote Terminal 2 processed a valid MIL-STD-1553 command having the IWA
interrupt enabled in its RT2 Descriptor Table entry. IWA interrupts are used to notify the
host each time certain command words are encountered.
10
9
IWA2
Reserved
Bit 9 cannot be written and reads back logic 0.
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Bit No. Mnemonic
Function
RT1 Mode Code 8 Command Interrupt.
Remote terminal RT1 processed a valid MIL-STD-1553 “reset remote terminal” mode
code command. An RTxMC8 interrupt notifies the host when the Bus Controller
commands remote terminal reset.
The state of bit 0 in the RT1 Remote Terminal Configuration Register 0x0017
determines whether the mode code response is automatic or handled by the host. If
the RT1MC8 bit is reset in the RT Interrupt Enable register when RT1 decodes a valid
“reset remote terminal” mode command, bit 0 in the RT1 Remote Terminal Configuration
Register dictates whether the reset response is automatic, or host controlled. The event
does not affect the RT Pending Interrupt Register, the Interrupt Log or the IRQ output,
but the RT1MC8 output pin is asserted to indicate that RT1 needs reset. In the case of a
broadcast command to RT31, both MC8 pins will be asserted.
8
RT1MC8
RT1 Index Equals Zero Interrupt.
The “index equals zero” (IXEQZ) interrupt for RT1. Index counts are used in multi-
message bulk data transfers. “Index equals zero” occurs when the last expected
message was transacted.
7
IXEQZ1
Defined IXEQZ interrupt events comprise: (a) subaddresses using indexed buffer mode
when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes
when the pre-determined number of messages has been transacted.
RT1 Illegal Command Interrupt.
The Remote Terminal 1 encountered a valid illegal message, as defined in the RT1
Illegal Command Table.
Illegal commands are detected when a new valid command word is decoded and the
RT1 Illegalization Table bit corresponding to the received command is logic 1. (Table
bits are logic 0 for legal commands.) The RT1 Illegalization Table contains nonzero
values only when “illegal command detection” is being applied. When illegal commands
are received, RT1 responds by transmitting a status word with ME “message error” flag
set; no data words are transmitted.
6
ILCMD1
If the ILCMD1 bit is reset in the RT Interrupt Enable Register when a valid illegal
command is decoded, the event does not affect the RT Pending Interrupt Register, the
Interrupt Log or the IRQ output.
RT1 Broadcast Command Received Interrupt.
5
4
IBR1
Broadcast commands are enabled for Remote Terminal 1 and the terminal encountered
a valid command addressed to RT31, the broadcast command address.
RT1 Message Error Status Interrupt.
The Remote Terminal 1 set its Message Error status flag while processing a valid MIL-
STD-1553 message. Message errors are caused by Manchester encoding problems or
protocol errors.
MERR1
RT1 Interrupt When Accessed.
The Remote Terminal 1 processed a valid MIL-STD-1553 command having the IWA
interrupt enabled in its RT1 Descriptor Table entry. IWA interrupts are used to notify
the host each time certain command words are encountered.
3
IWA1
2 − 0
Reserved
Bits 2-0 cannot be written, and read back 000.
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19. REMOTE TERMINAL RT1 AND RT2 CONFIGURATION AND OPERATION
19.1. Command Responses
A brief review of MIL-STD-1553 commands and responses is appropriate here to establish terminology used in the
rest of this data sheet. Shown in Figure 12, each command word is comprised of a sync field, three 5-bit data fields, a
single bit denoting Transmit / Receive direction and ends with a parity bit. The hardware decoder uses the sync field
to determine word type (command vs. data). Word validity is based on proper sync encoding, Manchester II encoding,
correct bit count and correct odd parity for the 16 data bits. Once a valid word with command sync is found, the sync
and parity are stripped before the command’s 16 data bits are stored for further processing.
Command
Sync
T/R
Bit
Word Count
Field *
Terminal
Address
Field
Subaddress
(SA) Field
Parity
Bit
* Word Count field is replaced by Mode Code
field when the SA field equals 0x00 or 0x1F
Figure 12. MIL-STD-1553 Command Word Structure
A “valid command” can be specifically addressed to the individual HI-6130 terminal (the command word’s embedded
Terminal Address field matches the terminal address latched in the Operational Status register) or can be a “broad-
cast command” addressed to all terminals. Broadcast commands are always addressed to RT address 31 (0x1F). In
systems where broadcast commands are disallowed, RT31 is not used as a conventional terminal address. When set,
the BCSTINV bit in the RT Configuration Register renders RT31 commands as “invalid”: broadcast commands are
indistinguishable from commands addressed to other terminals. Invalid commands are simply disregarded.
When the command word’s 5-bit SA (subaddress) field is in the range of 1 to 30 (0x01 to 0x1E) the command is con-
sidered a “subaddress command”. The terminal will either receive or transmit data words, and “direction” is specified
by the command’s T/R bit. The number of data words transacted is specified in the 5-bit word count field, ranging from
1 to 32 words. Thirty-two data words is represented when the word count field equals 0x00.
When the command’s 5-bit subaddress field equals 0 or 31 (0x1F) a “mode code” command is indicated; the low order
five bits no longer specify a word count, instead they convey a mode code value. This data sheet refers to mode code
commands by the mode code number. For example, a mode command with 5-bit mode code field of 0x10 is called
MC16, and the full range of mode code values is MC0 through MC31 (decimal).
Mode codes MC16 through MC31 (0x10 through 0x1F) have a single associated data word. When the command T/R
bit equals 0, the data word is contiguous with the command word and received by the RT. When the command’s T/R
bit equals 1, the data word is transmitted by the RT, following the terminal’s transmitted status word.
Mode codes MC0 through MC15 (0x0F) do not have associated data words. For these 16 commands, the command
T/R bit does not specify “direction”. These commands must be transmitted with T/R bit equal to 1. If the T/R bit is 0,
the mode command is “undefined”.
Twenty-two mode commands are “undefined mode commands ” in MIL-STD-1553B:
Mode Codes 0 through 15 with T/R bit = 0
Mode Codes16, 18 and19 with T/R bit = 0
Mode Codes 17, 20 and 21 with T/R bit = 1
The UMCINV bit in the RT Configuration Register determines how these undefined mode commands are handled by
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the HI-6130/31. If the UMCINV configuration bit equals 1, the undefined mode commands are treated as invalid. They
are not recognized by the device. There is no terminal response and status is not updated. If the UMCINV configuration
bit equals 0, the 22 undefined mode commands are considered valid; this is the default condition following reset. For
this case, terminal response depends on whether or not the application uses “illegal command detection.”
If illegal command detection is not used, all Illegalization Table entries should be logic 0, including the 22 entries
for these undefined commands. (The Illegalization Table is fully described in Section 19.2 on page 163. After MR reset,
all entries equal logic 0.) The terminal responds “in form”, transmitting clear status (and a single mode data word if the
command is MC17, MC20 or MC21 with T/R bit = 1). Terminal status is updated.
If illegal command detection applies, the Illegalization Table entries for these 22 undefined commands should be
initialized to logic 1. In this case, the terminal will respond with status word only, with Message Error bit set. No mode
data word is transmitted. Terminal status is updated.
Twenty-seven mode codes are considered “reserved” in MIL-STD-1553B:
Mode Codes 9 through 15 with T/R bit = 1
Mode Codes 22 through 31 with T/R bit = 1
Mode Codes 22 through 31 with T/R bit = 0
Treatment of these reserved mode commands depends on their respective Illegalization Table entries. As described
above for undefined mode commands, response depends on whether or not illegal command detection applies.
Any mode commands not implemented in the HI-6130/31 terminal should be treated the same as reserved mode com-
mands. For example, command MC0 (with T/R = 1) is probably unimplemented because the HI-6130 does not have
provisions for accepting “dynamic bus control”.
The important point is that “illegal command detection” should be universally applied (or not applied) when setting up
a HI-6130/31 Remote Terminal application. Here are the two options:
Not using Illegal command detection. The HI-6130/31 Illegalization Table is left in its default state (all locations
equal to MR post-reset 0x0000). The terminal responds “in form” to all valid commands, whether legal or illegal.
Using illegal command detection. The HI-6130/31 Illegalization Table is initialized by the host to implement “illegal
command detection”. The host sets bits for all illegal commands. This generally includes the reserved and unimple-
mented mode commands, unimplemented subaddresses (or specific word counts, T/R bit states, and/or broadcast vs.
non-broadcast status within subaddresses). Treatment for the undefined mode commands depends on UMCINV bit.
The host defines terminal response for all individual commands by initializing the Descriptor Table, fully described later.
At this point, a few comments about the Descriptor Table are appropriate.
The command SA (subaddress) field has a range of 0 to 31 (0x1F). When SA is in the range 1 to 30 (0x1E), the com-
mand is a transmit or receive “subaddress command”. The number of data words transmitted or received is expressed
in the low order 5 bits. When SA equals 0 or 31 (0x1F) the command is a mode command and the mode code value
is expressed in the low order 5 bits.
For each subaddress, separate table “descriptor blocks” for transmit and receive commands permit different data buff-
ering to be applied. The host initializes the table so each transmit-subaddress and each receive-subaddress uses one
of four methods for storing message data. During table initialization, memory is allocated in shared RAM for storing
message data according to the application requirements. Each transmit-subaddress and receive-subaddress has one
or more data pointers (depending on buffer method) addressing its reserved data buffer(s).
Each mode command also has its own table “descriptor block”. Mode commands have either one data word or no as-
sociated data words. Descriptor words used as data pointers by “subaddress commands” are instead used for direct
storage of transacted mode data words. Mode commands that transmit or receive mode data words have a dedicated
storage address range in shared RAM, eliminating the need for descriptor table data pointers.
Each mode command with mode data word has its own fixed address for data storage. This includes reserved mode
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codes with data word. Thus the HI-6130/31 can respond consistently for all mode commands; transmitted data values
for “in form” responses (when “illegal command detection” is not used) can be predetermined, even for the reserved
mode commands.
19.1.1. RT to RT Commands.
The MIL-STD-1553 standard allows for data word transmission from a specified transmitting terminal to a different
receiving terminal. When broadcast commands are allowed, data transmission can be addressed to the broadcast
terminal address, RT31. If broadcast is allowed, the host should initialize the BCSTINV (broadcast invalid) bit in the
RT Configuration Register to logic 0.
All RT to RT commands are characterized by a pair of contiguous command words: Command Word 1 is a receive
command addressed to the intended receiving terminal, then Command Word 2 is a transmit command addressed to
a single transmitting terminal. Command Word 2 cannot be broadcast address RT31. The HI-6130 automatically de-
tects and handles RT to RT commands, except when either command word contains a subaddress field equal to 0x0
or 0x1F. Either subaddress value indicates a mode code command; the device treats RT to RT commands with mode
code as invalid. If either RT-RT command word is addressed to the HI-6130/31 terminal but contains subaddress 0x0
or 0x1F, the command is not recognized; there is no RT command response, and no status updating for the benefit of
following “transmit status” or “transmit last command” mode commands.
When either RT-RT command word (with subaddress field not equal to 0x0 or 0x1F) is addressed to the HI-6130/21
terminal, but the other command word contains subaddress 0x0 or 0x1F, the RT-RT command is not recognized as
valid. There is no RT command response, and no status updating for the benefit of following “transmit status” or “trans-
mit last command” mode commands.
An RT-RT command pair where Command Word 1 is addressed to the HI-6130/21 terminal and Command Word 2 is
addressed to a different terminal is considered an “RT-RT receive” command. When the message is transacted, the
device sets the RTRT bit in the Receive Subaddress Message Information Word in the subaddress data buffer.
An RT-RT command pair where Command Word 2 is solely addressed to the HI-6130/21 terminal (not RT31) is con-
sidered an “RT-RT transmit” command. The Message Information Word does not distinguish the RT to RT transmit
message from an ordinary RT to BC transmit command.
19.2. Command Illegalization Table
The following pages describe various structures residing in the RAM shared between the host and HI-6130 or HI-6131
command processing logic. The host initializes these structures to control the terminal’s response to received com-
mands. The first structure described is the command Illegalization Table used for “illegal command detection”.
Illegal command detection is an optional process. When illegal command detection is not used, the terminal “responds
in form” to all valid commands: it sends Clear Status and transacts the number of data words defined in the received
command. When illegal command detection is not used, the bus controller cannot tell whether the command is legal
or illegal, from the terminal’s transmitted response.
If illegal command detection is used, the terminal responds differently when an illegal command is detected. The termi-
nal responds to illegal commands with “message error” status, transmitting only status word. Data word transmission
is suppressed if the command type inherently includes transmitted data words. The terminal responds to each legal
command with clear status and transacts the number of data words defined in the type of command received.
For consistency, apply illegal command detection to all illegal and unimplemented commands, and to all reserved or
undefined mode code commands, or “respond in form” to all of these commands (illegal command detection disabled)
by leaving the Illegalization Table in the all-cleared default state after MR master reset
The device uses a 256-word “Illegalization Table” in shared RAM to distinguish between legal and illegal commands.
After the (MR) master reset input is negated, HI-6130/31 performs internal self test including a shared RAM test which
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leaves all memory locations fully reset. Once self test is complete, the HI-6130/31 READY output goes high to indicate
HI-6130/31 readiness for host initialization. At this point, all entries in the Illegalization Table read logic 0, so by default,
illegal command detection is not applied.
To apply illegal command detection, the host (or auto-initialization) writes the Illegalization Table to set bits for all illegal
command combinations. This typically includes any unimplemented subaddresses and/or word counts, undefined
mode commands, reserved mode commands and any mode commands not implemented in the terminal design. Host
initialization of the table can be replaced by auto-initialization.
Once STEX is set in the RT Configuration Register, terminal execution begins. Each time a valid command is received,
a 1-bit entry (indexed using command word data bits) is fetched from the Illegalization Table:
If fetched Illegalization Table bit equals logic 0, the command is “legal”; the terminal responds “in form”, transmit-
ting clear status and transacting the number of data words defined for the message type. Terminal status is updated.
If fetched Illegalization Table bit equals logic 1, the command is “illegal”; the terminal responds with status word
only, with Message Error bit set. No data words are transmitted. Terminal status is updated.
When illegal command detection is not applied, all table entries should read logic 0; the terminal responds “in form” to
all valid commands.
The illegalization scheme allows any subset of command T/R bit, broadcast vs. non-broadcast status, subaddress
and word count (or mode code number), for a total of 4,096 legal/illegal command combinations. Commands may be
illegalized down to the word count level. For example, 10-word receive commands to a given subaddress may be legal,
while 9-word receive commands to the same subaddress are illegal.
Broadcast receive commands are illegalized separately from non-broadcast receive commands. Transmit and receive
commands for the same subaddress are illegalized separately. For mode commands, any combination of mode code
number, T/R bit and broadcast/non-broadcast status can be legal or illegal.
The Illegalization Table is located in shared RAM within the fixed address range of 0x0200 to 0x02FF for RT1 and
0x0300 to 0x03FF for RT2. See Figure 13. The table is comprised of 256 16-bit words. To cover the full range of 1
to 32 data words, each subaddress uses a pair of illegalization registers. The lower register (even memory address)
covers word counts 0 to 15, using one bit per word count. As in command encoding, “0” denotes 32 data words. Bit 0
corresponds to 32 data words, bit 1 corresponds to 1 data word and bit 15 corresponds to 15 data words. The upper
register (odd memory address) similarly covers word counts 16 to 31, using one bit per word count. Bit 0 corresponds
to 16 data words, while bit 15 corresponds to 31 data words.
When a command’s subaddress field equals 0 or 31 (0x1F), the command is a mode command. Table entries for mode
commands use bits to represent mode code numbers, not word counts. The lower register (even memory address)
covers mode codes 0 to 15, using one bit per mode code. Bit 0 corresponds to mode code 0, bit 15 corresponds to
mode code 15. The upper register (odd memory address) similarly covers mode codes 16 to 31, using one bit per
mode code. Bit 0 corresponds to mode code 16, bit 15 corresponds to mode code 31. There is no functional difference
between SA0 mode commands and SA31 mode commands. Since either subaddress indicates a mode command, the
subaddress 0 table words should match the subaddress 31 table words in each quadrant.
RT1 table entries from 0x0242 to 0x027D and RT2 table entries from 0x0342 to 0x037D do not have to be pro-
grammed. These correspond to broadcast transmit subaddress commands (undefined by MIL-STD-1553B) and are
always invalid. There is no terminal response.
Addressing for the Illegalization Table is derived from the command word T/R bit, subaddress field, MSB of the Word
Count (Mode Code) field and the command’s broadcast vs. non-broadcast status as shown below in Figure 13.
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Bit Fields Comprise Each Received Command Word
Terminal
Address
TA4:0
Word Count
Subaddress (Mode Code)
Command
Sync
T/R
Bit
SA4:0
WC4:0
P
“0” if
TA4:0 = 11111
else “1”
Table
Address
0 0 0 0 0 0 0 1
Figure 13. Deriving the Illegalization Table Address From the Received Command Word
Figure 15 on page 167 shows individual bit locations in the Illegalization Table for broadcast and non-broadcast variants
of all mode commands defined by MIL-STD-1553B. Locations are also identified for reserved mode codes and unde-
fined mode code commands.
The following examples illustrate how the Illegalization Table is initialized to distinguish between legal and illegal com-
mands when “illegal command detection” is being used. Remember: If the terminal does not use illegal command
detection, the table is left in its post-MR reset state, with all table locations reset to 0x0000. In this case, all command
responses are “in form”.
For “subaddress commands” (ordinary receive commands or transmit commands) individual table bits correspond
to word counts specified in the received command word. If a bit is 0, the corresponding word count is legal. If a bit is
1, the corresponding word count is illegal.
For example, transmit commands to RT1 subaddress 1 are controlled by the words at 0x02C2 and 0x02C3. In Figure
14, these words are located in the “RT Address Transmit” block. The word stored at 0x02C3 controls subaddress 1
transmit commands having word counts 16 to 31. The word stored at 0x02C2 controls subaddress 1 transmit com-
mands having word counts 1 to 15 or 32. (Reminder: In MIL-STD-1553B, zero corresponds to 32 words.)
Word at 0x02C3 (Tx Subaddr 1) 31 to 16 words
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Words
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Word at 0x02C2 (Tx Subaddr 1) 15 to 1 & 32 words
Bit
Words
15 14 13 12 11 10
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1 32
0
If the word stored at 0x02C3 = 0xFFFF and the word stored at 0x02C2 = 0xFF0F, then commands with 4, 5, 6, or 7
data words are the only legal transmit commands for subaddress 1 and all other word counts are illegal. Receive com-
mands and broadcast receive commands for Subaddresses1 through 30 are encoded similarly.
For “mode code commands” (characterized by command word subaddress field equal to 00000 or 11111 binary)
individual table bits correspond to individual mode code values. Here “transmit” and “receive” simply indicate the state
of the command word T/R bit. (For mode codes 0-15, the T/R bit does not indicate data direction since data is not
transacted when fulfilling these commands).
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HI-6130, HI-6131
0x02FF (0x03FF)
RT Address Tx Mode Codes 31 - 16
Tx Subaddress 31 Block (mode codes)
Tx Subaddress 30 Block
0x02FF (0x03FF)
0x02FE (0x03FE)
RT Address Tx Mode Codes 15 - 0
RT Addr Tx SA30 Word Counts 31 - 16
RT Addr Tx SA30 Word Counts 15 - 0 *
0x02FD (0x03FD)
0x02FC (0x03FC)
RT Address Transmit Quadrant
32 subaddress blocks
of 2 words each
* Word Count = 0
denotes 32 words
Tx Subaddress 1 Block
RT Address Tx Mode Codes 31 - 16
RT Address Tx Mode Codes 15 - 0
0x02C1 (0x03C1)
Tx Subaddress 0 Block (mode codes)
0x02C0 (0x03C0)
0x02C0 (0x03C0)
0x02BF (0x03BF)
RT Address Rx Mode Codes 31 - 16
RT Address Rx Mode Codes 15 - 0
Rx Subaddress 31 Block (mode codes)
Rx Subaddress 30 Block
0x02BF (0x03BF)
0x02BE (0x03BE)
RT Addr Rx SA30 Word Counts 31 - 16
RT Addr Rx SA30 Word Counts 15 - 0 *
0x02BD (0x03BD)
0x02BC (0x03BC)
RT Address Receive Quadrant
32 subaddress blocks
of 2 words each
* Word Count = 0
denotes 32 words
Rx Subaddress 1 Block
RT Address Rx Mode Codes 31 - 16
RT Address Rx Mode Codes 15 - 0
0x0281 (0x0381)
Rx Subaddress 0 Block (mode codes)
0x0280 (0x0380)
0x0280 (0x0380)
0x027F (0x037F)
Command
Sync
Tx Subaddress 31 Block (mode codes)
Tx Subaddress 30 Block
Broadcast Tx Mode Codes 31 - 16
Broadcast Tx Mode Codes 15 - 0
0x027F (0x037F)
0x027E (0x037E)
Broadcast Tx SA30 Word Counts 31 - 16
Broadcast Tx SA30 Word Counts 15 - 0 *
0x027D (0x037D)
0x027C (0x037C)
Broadcast Transmit Quadrant
32 subaddress blocks
of 2 words each
SA1 to SA30 are illegal
broadcast transmit!
* Word Count = 0
denotes 32 words
Tx Subaddress 1 Block
Broadcast Tx Mode Codes 31 - 16
Broadcast Tx Mode Codes 15 - 0
0x0241 (0x0341)
Tx Subaddress 0 Block (mode codes)
0x0240 (0x0340)
0x0240 (0x0340)
0x023F (0x033F)
Broadcast Rx Mode Codes 31 - 16
Broadcast Rx Mode Codes 15 - 0
Rx Subaddress 31 Block (mode codes)
Rx Subaddress 30 Block
0x023F (0x033F)
0x023E (0x033E)
Broadcast Rx SA30 Word Counts 31 - 16
Broadcast Rx SA30 Word Counts 15 - 0 *
0x023D (0x033D)
0x023C (0x033C)
Broadcast Receive Quadrant
32 subaddress blocks
of 2 words each
* Word Count = 0
denotes 32 words
Rx Subaddress 1 Block
Broadcast Rx Mode Codes 31 - 16
Broadcast Rx Mode Codes 15 - 0
0x0201 (0x0301)
Rx Subaddress 0 Block (mode codes)
0x0200 (0x0300)
RT1 (RT2)
0x0200 (0x0300)
RT1
(RT2)
Example Subaddress Blocks
from Each Table Quadrant
Illegalization Table Comprised of
32 2-word Blocks per Quadrant
Figure 14. Address Mapping for Illegalization Table
Note: RT1 table default start address is 0x0200. RT2 table default start address is 0x0300
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Figure 15 summarizes the 16 Illegalization Table locations for mode commands. These locations are scattered
throughout the overall Illegalization Table shown in Figure 13. Remember: the host must initialize all table locations
corresponding to both subaddress 0 and subaddress 31 (11111 binary).
Consider an example for RT1 in which all reserved and all undefined mode commands are illegal. If all RT1 defined
transmit mode commands are legal except MC0 (”dynamic bus control”) the eight table entries for transmit mode
commands would be:
0x02FF and 0x02C1 = 1111 1111 1111 0010 = 0xFFF2
0x02FE and 0x02C0 = 1111 1110 0000 0001 = 0xFE01
0x027F and 0x0241 = 1111 1111 1111 1111 = 0xFFFF
0x027E and 0x0240 = 1111 1110 0000 0101 = 0xFE05
The receive mode command words are encoded similarly. Continuing the same example where all reserved and all
undefined mode commands are illegal: If all RT1 defined receive mode commands are legal, the eight table entries for
receive mode commands would be:
0x02BF and 0x0281 = 1111 1111 1100 1101 = 0xFFCD
0x02BE and 0x0280 = 1111 1111 1111 1111 = 0xFFFF
0x023F and 0x0201 = 1111 1111 1100 1101 = 0xFFCD
0x023E and 0x0200 = 1111 1111 1111 1111 = 0xFFFF
Bit No. 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Transmit
Mode Commands
With Data
0x02FF
and
MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Tx MC31 - MC16
Tx MC15 - MC0
Status
R
R
R
R
R
R
R
R
R
R
U
U
D
D
U
D
0x02C1
Transmit
Mode Commands
Without Data
0x02FE
and
0x02C0
MC # 15 14 13 12 11 10
9
R
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
Status
R
R
R
R
R
R
Receive
Mode Commands
With Data
0x02BF
and
MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rx MC31 - MC16
Rx MC15 - MC0
Status
R
R
R
R
R
R
R
R
R
R
D
D
U
U
D
U
0x0281
Receive
Mode Commands
Without Data
0x02BE
and
0x0280
MC # 15 14 13 12 11 10
9
U
8
U
7
U
6
U
5
U
4
U
3
U
2
U
1
U
0
U
Status
U
U
U
U
U
U
Broadcast Transmit
Mode Commands
With Data
0x027F
and
MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Br.Tx MC31 - MC16
Br.Tx MC15 - MC0
Br.Rx MC31 - MC16
Br.Rx MC15 - MC0
0x0241
Status
R
R
R
R
R
R
R
R
R
R
U
U NB NB U NB
Broadcast Transmit
Mode Commands
Without Data
0x027E
and
0x0240
MC # 15 14 13 12 11 10
Status
9
R
8
D
7
D
6
D
5
D
4
D
3
2
1
0
R
R
R
R
R
R
D NB D NB
Broadcast Receive
Mode Commands
With Data
0x023F
and
0x0201
MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Status
R
R
R
R
R
R
R
R
R
R
D
D
U
U
D
U
Broadcast Receive
Mode Commands
Without Data
0x023E
and
0x0200
MC # 15 14 13 12 11 10
9
U
8
U
7
U
6
U
5
U
4
U
3
U
2
U
1
U
0
U
Status
U
U
U
U
U
U
RAM
Address
LEGEND
D = Defined Mode Command
R = Reserved Mode Code
U = Undefined Mode Command NB = Defined Code, But
Broadcast Not Allowed
Figure 15. Summary of RT1 Illegalization Table Addresses for Mode Code Commands
Note: RT2 is the same except the table starts at 0x0300 instead of 0x0200.
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19.3. Temporary Receive Data Buffer
The 32-word temporary receive data buffer resides in shared RAM in address space 0x01C0 to 0x01DF for RT1 and
0x01E0 to 0x01FF for RT2. The device optionally uses this buffer for temporary storage of receive data words until
successful message completion. To enable the buffer, the host asserts the TRXDC bit in the RT1 or RT2 Configuration
Register described in Section 18.1.
When enabled, the terminal stores received data words in the 32-word buffer during message processing. Upon error-
free message completion, all buffered words are written in a burst to the data buffer memory assigned to the specific
subaddress in the RT1 or RT2 Descriptor Table.
When the TRXDB bit in the RT1 or RT2 Configuration Register is negated, the temporary receive data buffer is dis-
abled. At 20us intervals, the terminal writes received data words to assigned subaddress data buffer memory as each
word is received. If message error occurs during data reception, data integrity is lost; valid data from the prior receive
message may be partially overwritten by data from a message ending in error. MIL-STD-1553 states that all received
data from messages ending in error should be disregarded.
In a typical application, the temporary buffer is not directly accessed by the host, although there is no restriction pre-
venting host data access. The host should never write data into the temporary buffer space.
19.4. Descriptor Table
The Descriptor Table, resides in shared RAM, at default address ranges 0x0400 to 0x05FF for RT1 and 0x0600 to
0x07FF for RT2. This table is initialized by the host (or auto-initialization) to define how the terminal processes valid
commands. Descriptor Table settings for each command specify where message data is stored, how data is stored,
whether host interrupts are generated, and other aspects essential to command processing. Before initializing the
RAM Descriptor Table, the RT enable input pin RT1ENA or RT2ENA must be asserted AND the corresponding
RTxENA bit must be set in the Master Configuration Register 0x0000. Terminal execution does not begin until the
RT1STEX or RT2STEX bits are set in “9.1. Master Configuration Register (0x0000)”.
Shown in Figure 16, the table consists of 128 consecutive “descriptor blocks”, each comprised of four 16-bit words.
The table is organized into four quadrants.
The Receive Subaddress and Transmit Subaddress quadrants define response for commands having a subaddress
field ranging from 1 to 30 (0x1E). These are simple N-data word receive or transmit commands, where N can range
from 1 to 32 words. When the command T/R bit equals 0, the receive command quadrant applies. When the T/R bit
equals 1, the transmit command quadrant applies.
Both subaddress quadrants are padded at top and bottom with unused Descriptor Blocks for subaddresses 0 and 31
(0x1F). The word space reserved for SA0 and SA31 aligns the table addressing, but values stored in these eight loca-
tions is not used. Command subaddresses 0 and 31 indicate mode commands. The response for commands contain-
ing either SA value is defined in the two mode command table quadrants. The Receive Mode Command quadrant
applies when the command word T/R bit equals 0, while the Transmit Mode Command quadrants applies when T/R
equals 1.
The term “Transmit Mode Command” is misleading. All defined mode commands with mode code less than 0x0F
haveT/R bit equal to 1, yet none of these mode commands transmits a data word. They transmit only the terminal sta-
tus word, just like receive commands. However, the RT responds to transmit mode commands with mode code 0x10
to 0x1F by transmitting a mode data word. Just three such transmit mode commands are defined.
Within the Receive and Transmit Mode Command quadrants, block addressing is based on the low order 5 bits in the
command word, containing the mode code value. This is fundamentally different from the Subaddress quadrants in
which block addressing is based on the 5-bit subaddress field. Figure 17 shows how to derive Control Word address
from the received Command Word. The Control Word address for the last valid command can also be found in the
Current Control Word Address register.
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All 128 4-word Descriptor Blocks start with a Control Word. There are four Control Word variants based on command
type: receive vs. transmit and mode vs. non-mode commands. All descriptor Control Words are initialized by the host
(or auto-initialization) to define basic command response. Each Control Word specifies the data buffer method and
host interrupt for a specific subaddress or mode command.
Each subaddress has both a Receive Subaddress block and a Transmit Subaddress block. Receive and transmit com-
mands to the same subaddress can be programmed to respond differently.
The function of the three remaining descriptor words (in each 4-word block) depends on which of the 4 data buffer
methods are specified in the Control Word.
Indexed (or Single Buffer) Method where a predetermined number of messages is transacted using a single data
buffer in shared RAM. Several host interrupt options are offered, including an interrupt generated when all N messages
are successfully completed.
Double (or Ping-Pong) Buffer Method where successive messages alternate between two data buffers in shared
RAM. Several host interrupt options are offered.
Circular Buffer Mode 1 where buffer boundaries determine when the bulk transfer is complete and message informa-
tion and time-tag words are stored with message data in a common buffer. Several host interrupt options are offered,
including an interrupt generated when the allocated data buffer is full.
Circular Buffer Mode 2 where the number of messages transacted defines bulk transfer progress, and message data
words are stored contiguously in one buffer while message information and time-tag words are stored in a separate
buffer. Several host interrupt options are offered, including an interrupt generated when all N messages are success-
fully completed.
The 4-word Descriptor Table entry for each command (its descriptor block) begins with a Control Word. There are four
types of descriptor Control Word:
•
•
•
•
Receive Subaddress Control Word
Transmit Subaddress Control Word
Receive Mode Command Control Word
Transmit Mode Command Control Word
The descriptor Control Word is initialized by the host to select data buffer method and interrupt options. After a com-
mand is processed by the HI-6130/31 terminal, the device updates the command’s descriptor Control Word. Update
will differ based on the chosen data buffer method. Reading the descriptor table can differ from other RAM accesses.
For HI-6130, see Section 25.1.1. For HI-6131, see Sections 25.2.6 and 25.2.8.
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32 4-Word Blocks per Quadrant
Descriptor Word 4 for Tx MC30
Descriptor Word 3 for Tx MC30
Descriptor Word 2 for Tx MC30
Control Word for Tx MC30
0x05FB
0x05FA
0x05F9
0x05F8
0x05FF
Mode Code 31 Block
Mode Code 30 Block
Transmit Mode Code Quadrant
(Mode Codes with T/R bit = 1)
32 Descriptor Blocks
of 4 words each
Mode Code 1 Block
Mode Code 0 Block
0x0580
0x057F
Descriptor Word 4 for Rx MC30
Descriptor Word 3 for Rx MC30
Descriptor Word 2 for Rx MC30
Control Word for Rx MC30
0x057B
0x057A
0x0579
0x0578
Mode Code 31 Block
Mode Code 30 Block
Receive Mode Code Quadrant
(Mode Codes with T/R bit = 0)
32 Descriptor Blocks
of 4 words each
Example 4-Word Descriptor Blocks
from Each Table Quadrant
Mode Code 1 Block
Mode Code 0 Block
0x0500
0x04FF
Descriptor Word 4 for Tx SA30
Descriptor Word 3 for Tx SA30
Descriptor Word 2 for Tx SA30
Control Word for Tx SA30
0x04FB
0x04FA
0x04F9
0x04F8
Subaddress 31 Block
Subaddress 30 Block
See Note.
Transmit Subaddress Quadrant
32 Descriptor Blocks
of 4 words each
Subaddress 1 Block
Subaddress 0 Block
See Note.
See Note.
0x0480
0x047F
Descriptor Word 4 for Rx SA30
Descriptor Word 3 for Rx SA30
Descriptor Word 2 for Rx SA30
Control Word for Rx SA30
0x047B
0x047A
0x0479
0x0478
Subaddress 31 Block
Subaddress 30 Block
Receive Subaddress Quadrant
32 Descriptor Blocks
of 4 words each
NOTE:
Subaddress 1 Block
Subaddress 0 Block
SA0 and SA31 indicate mode codes, so
are not valid Receive or Transmit Subaddresses.
See Note.
0x0400
Figure 16. Address Mapping for RT1 Descriptor Table
Note: Assumes default table base address = 0x0400. RT2 is the same with default base address 0x0600.
Before initializing the RT1 or RT2 Descriptor Table, input pin RT1ENA or RT2ENA must be asserted
AND the RT1ENA or RT2ENA bit must be set in Master Configuration Register 0x0000.
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Command RT Addr
Sync TA4:0
Subaddress Word Count
Command RT Addr
Sync TA4:0
Subaddress Mode Code
T/R
Bit
T/R
Bit
SA4:0
WC4:0
SA4:0
MC4:0
P
P
Descriptor Address Format
Depends On
Command Word’s Subaddress
0x0
0x3
0x0
0x2
0 0 0 0 0 0 1 0
0 0
0 0 0 0 0 0 1 1
0 0
Descriptor Table Address
for Subaddress Commands
SA4:0 equals 00001 to 11110
Descriptor Table Address
for Mode Code Commands
SA4:0 equals 00000 or 11111
Figure 17. Deriving a Descriptor Table Control Word Address From Command Word
(assumes table base address = 0x0200)
19.4.1. Receive Subaddress Control Word
Receive Subaddress Control Words apply when a valid command word T/R bit equals zero (receive) and the
subaddress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command
response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal
execution begins. If using ping-pong data buffers, Control Words should only be written when the applicable RT1ENA
or RT2ENA input pin is asserted AND the corresponding RT1ENA or RT2ENA bit is also set in the Master Configuration
Register 0x0000. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is set,
and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits are
updated by the device during terminal execution, that is, when the RT Configuration Register STEX bit equals 1. The
host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is
cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following
any read cycle to the Control Word address, the DBAC bit is reset.
Bit maintained by host
H
D
IXEQZIWA IBR MKBUDBACDPB BCASPTPONCIR2ZCNIR32CZNIR22ZCNI1R2SZNTO0PPPPENCIR2ECNIR1EN
SY
Bit maintained by device
H
H
H
H
D1
D
D
9
D
8
H
7
H
6
H
5
H
4
H
3
H
2
H
1
H
0
D1
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W Reset Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for (a) subaddresses using indexed buffer mode
when the INDX value decrements from 1 to 0, or (b) subaddresses using a
circular buffer mode when the pre-determined number of messages has been
transacted. If enabled, upon completion of command processing that results
in index = 0, an IXEQZ interrupt is entered in the Pending Interrupt Register,
output pin INT is asserted, and the interrupt is registered in the Interrupt Log.
15
IXEQZ
0
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Bit No. Mnemonic R/W Reset Function
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation when the subaddress receives any valid receive com-
mand. If enabled, upon completion of command processing, an IWA interrupt
is entered in the Pending Interrupt Register, output pin INT is asserted, and
the interrupt is registered in the Interrupt Log.
14
IWA
0
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables in-
terrupt generation when the subaddress receives a valid broadcast command.
If enabled, upon completion of message processing an IBR interrupt is entered
in the Pending Interrupt Register, output pin INT is asserted, and the interrupt
is registered in the Interrupt Log. This bit has no function if the BCSTINV bit is
high in the RT Configuration Register. In this case, commands to RT address
31 are not recognized as valid by the device.
13
IBR
0
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this receive subaddress. This bit is an alternative to globally applying Busy
status for all valid commands, enabled from the 1553 Status Bits Register.
See that register description for additional information. When Busy is asserted,
received data words are not stored and the DPB bit does not toggle after mes-
sage completion.
12
11
MKBUSY
0
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message
processing. The host may poll this bit to detect subaddress activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
0
DBAC
SR = 0
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong buffer
mode. This bit indicates the buffer to be used for the next occurring receive
command to this subaddress. When the DPB bit is logic 0, the next message
will use Data Pointer A; when DPB is logic 1, the next message uses Data
Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free
message completion. The DPB bit is not altered after messages ending in er-
ror, after illegal commands or after messages when the terminal responds with
Busy status. This bit is reset to logic 0 by MR master reset or SRST software
reset; therefore the first message received after either reset will use Buffer A.
This bit is “don’t care” for indexed single-buffer mode or either circular buffer
mode.
0
10
DPB
SR = 0
Broadcast Command.
Device logic sets this bit when a valid broadcast receive command is received
at this subaddress. If IBR bit 13 and Interrupt Enable Register IBR bit are both
set, the output pin INT is asserted. This bit has no function if the BCSTINV bit
is asserted in the the RT Configuration Register; in this case commands to RT
address 31 are not recognized as valid by the device. This bit is reset to logic
0 by MR master reset or SRST software reset.
0
9
BCAST
SR = 0
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Bit No. Mnemonic R/W Reset Function
Ping-Pong Enable Acknowledge.
This bit is controlled by the device and cannot be written by the host. It only
applies if PPEN bit 2 was initialized to logic one by the host after reset, en-
abling ping-pong buffer mode for this subaddress. Device logic asserts this bit
when it recognizes ping-pong is active for this subaddress. Before off-loading
the receive data buffer for this subaddress, the host can ask the device to
temporarily disable ping-pong by asserting STOPP bit 3. The device acknowl-
edges ping-pong is disabled by negating PPON. The host can safely off-load
the buffer without data collision while PPON is negated. After buffer servicing,
the host asks the device to re-enable ping-pong by negating STOPP bit 3. The
device acknowledges ping-pong is re-enabled by asserting PPON.
8
PPON
0
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for
this subaddress, ping-pong is disabled. Each new message overwrites exist-
ing data in the buffer specified by DPB bit 10, and the DPB bit does not toggle
after command completion.
Circular Mode 2 Zero Number.
Used only in circular buffer mode 2, this 4-bit field is initialized with the number
of trailing zeros in the initialized MIBA address. This is explained in Section
20.6, which fully describes circular buffer mode 2.
7-4
CIR2ZN
STOPP
0
0
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this subaddress.
The host resets this bit to ask the device to re-enable ping-pong. The device
confirms recognition of ping-pong enable or disable status by writing PPON bit
8. Refer to Section 20.3, which fully describes ping-pong mode.
3
Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable.
The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select buffer
mode. The table below summarizes how buffer mode selection is encoded.
In the case of ping-pong, the host initializes the PPEN bit to logic one after
reset to enable ping-pong buffering for this subaddress. The host asserts
STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the
STOPP bit asks the device to re-enable ping-pong. The device confirms ping-
pong enable or disable state changes by writing the PPON bit. PPEN bit 2
should only be initialized or otherwise written when the applicable RT1ENA or
RT2ENA input pin is asserted, AND the corresponding RT1ENA or RT2ENA bit
is also set in the Master Configuration Register 0x0000.
2
1
0
PPEN
0
0
0
CIR2EN
CIR1EN
PPEN
CIR2EN
CIR1EN
Don’t Care
Don’t Care
1
Buffer Mode
Ping-Pong
1
0
0
Don’t Care
1
0
Circular Mode 2
Circular Mode 1
Indexed Single
Buffer
0
0
0
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19.4.2. Transmit Subaddress Control Word
Transmit Subaddress Control Words apply when a valid command word T/R bit equals one (transmit) and the
subaddress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command
response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal
execution begins. If using ping-pong data buffers, Control Words should only be written when the applicable RT1ENA
or RT2ENA input pin is asserted AND the corresponding RT1ENA or RT2ENA bit is also set in the Master Configuration
Register 0x0000. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is
set, and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits
are updated by the device during terminal execution, that is, when the RT Configuration Register STEX bit equals 1.
The host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3,12 and 14-15 can be written anytime. This
register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits.
Following any host read cycle to the Control Word address, the DBAC bit is reset.
Bit maintained by host
H
D
IXEQZIWA
MKBUDSBYACDPB BCASPTPONCIR2ZCNIR32CZNIR22ZCNI1R2SZNTO0PPPPENCIR2ECNIR1EN
Bit maintained by device
H
H
X
H
D1
D
D
9
D
8
H
7
H
6
H
5
H
4
H
3
H
2
H
1
H
0
D1
X
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W Reset Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for (a) subaddresses using indexed buffer mode
when the INDX value decrements from 1 to 0, or (b) subaddresses using a
circular buffer mode when the pre-determined number of messages has been
transacted. If enabled, upon completion of command processing that results
in index = 0, an IXEQZ interrupt is entered in the RT Pending Interrupt Reg-
ister, output pin INT is asserted, and the interrupt is registered in the Interrupt
Log.
15
IXEQZ
0
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation when the subaddress receives any valid transmit com-
mand. If enabled, upon completion of command processing, an IWA interrupt
is entered in the RT Pending Interrupt Register, output pin INT is asserted,
and the interrupt is registered in the Interrupt Log.
14
13
IWA
-----
0
0
Not Used
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this transmit subaddress. This bit is an alternative to globally applying Busy
status for all valid commands, enabled from the 1553 Status Bits Register.
See that register description for additional information. When Busy is as-
serted, data words are not transmitted and the DPB bit does not toggle after
message completion.
12
MKBUSY
0
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Bit No. Mnemonic R/W Reset Function
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message
processing. The host may poll this bit to detect subaddress activity, instead of
using host interrupts. This bit is reset to logic zero by MR master reset, SRST
software reset or a read cycle to this memory address.
0
11
DBAC
SR = 0
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong
buffer mode. This bit indicates the buffer to be used for the next occurring
transmit command to this subaddress. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode or
either circular buffer mode.
0
10
DPB
SR = 0
Broadcast Received.
The device sets this bit when a broadcast-transmit command is received
for this subaddress. Because non-mode broadcast-transmit commands are
always illegal, the assertion of this bit in the Control Word by the device indi-
cates an illegal command was received. Terminal response varies, depending
on whether or not illegal command detection applies (any bits set in Illegal-
ization Table). This bit has no function if the BCSTINV bit is asserted in the
RT Configuration Register; in this case commands to RT address 31 are not
recognized as valid by the device. This bit is reset to logic 0 by MR master
reset or SRST software reset.
0
9
BCAST
SR = 0
Ping-Pong Enable Acknowledge.
This bit is controlled by the device and should not be written by the host. It
only applies if PPEN bit 2 was initialized to logic one by the host after reset,
enabling ping-pong buffer mode for this subaddress. The RT asserts this
bit when it recognizes ping-pong is active for this subaddress. Before load-
ing the transmit data buffer for this subaddress, the host can ask the RT to
temporarily disable ping-pong by asserting STOPP bit 3. The RT acknowl-
edges ping-pong is disabled by negating PPON. The host can safely load the
buffer without data collision while PPON is negated. After buffer servicing, the
host asks the RT to re-enable ping-pong by negating STOPP bit 3. The RT
acknowledges ping-pong is re-enabled by asserting PPON.
8
PPON
0
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for
this subaddress, ping-pong is disabled. Each new message transmits data
from the same buffer, specified by DPB bit 10, and the DPB bit does not
toggle after command completion.
Circular Mode 2 Zero Number.
Used only in circular buffer mode 2, this 4-bit field is initialized with the
number of trailing zeros in the initialized MIBA address. This is explained in
Section 20.6, which fully describes circular buffer mode 2.
7-4
CIR2ZN
0
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Bit No. Mnemonic R/W Reset Function
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this subaddress.
The host resets this bit to ask the RT to re-enable ping-pong. The RT con-
firms recognition of ping-pong enable or disable status by writing PPON bit 8.
Refer to Section 20.3, which describes ping-pong mode in detail.
3
STOPP
0
Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable.
The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select
buffer mode. The table below summarizes how buffer mode selection is
encoded.
In the case of ping-pong, the host initializes the PPEN bit to logic one after
reset to enable ping-pong buffering for this subaddress. The host asserts
STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the
STOPP bit asks the device to re-enable ping-pong. The device confirms ping-
pong enable or disable state changes by writing the PPON bit. PPEN bit 2
should only be initialized or otherwise written when the applicable RT1ENA or
RT2ENA input pin is asserted, AND the corresponding RT1ENA or RT2ENA
bit is also set in the Master Configuration Register 0x0000.
2
1
0
PPEN
0
0
0
CIR2EN
CIR1EN
PPEN
CIR2EN
CIR1EN
Don’t Care
Don’t Care
1
Buffer Mode
Ping-Pong
1
0
0
Don’t Care
1
0
Circular Mode 2
Circular Mode 1
Indexed Single
Buffer
0
0
0
19.4.3. Data Buffer Options for Mode Code Commands
Data buffer options for mode code commands differ from options offered for subaddress commands. Mode commands
cannot use either circular data buffer method, but may use double (ping-pong) buffering or single (indexed) buffering.
Single message Index mode (INDX = 0) is suitable in many applications (see Section 20.4.1). An alternative called
Simplified Mode Command Processing (SMCP) may be globally applied for all mode code commands (see Section
21.5).
To use single (indexed) buffer or double (ping-pong) buffer for mode commands, the SMCP bit in the RT Configuration
Register is logic 0. The Control Word PPEN bit for each mode command determines whether ping-pong or indexed
buffering is used.
To use Simplified Mode Command Processing, the SMCP bit in the RT Configuration Register is set to logic 1. The
Control Word PPEN bit for mode commands is “don’t care” (no longer specifies index or ping-pong buffer mode)
because Simplified Mode Command Processing stores mode command data and message information words directly
within each mode command’s redefined Descriptor Table block. When SMCP is enabled, mode code command
descriptor blocks (in the Descriptor Table) do not contain data pointers to reserved buffers elsewhere in the shared
RAM. Instead, each 4-word descriptor block itself contains the message information word, the time-tag word and the
data word transacted for each mode command (for mode codes 16-31 decimal).
When Simplified Mode Command Processing is used, the range of active bits is reduced in each receive or transmit
mode command Control Word. Interrupt control and response is not affected by the SMCP option. Simplified Mode
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Command Processing is fully presented in the later data sheet section 21.5.
19.4.4. Receive Mode Control Word
Receive Mode Control Words apply when the command word T/R bit equals zero (receive) and the subaddress field
has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior,
and conveys activity status to the host. It is initialized by the host before terminal execution begins. If using ping-pong
data buffers, Control Words should only be written when the applicable RT1ENA or RT2ENA input pin is asserted AND
the corresponding RT1ENA or RT2ENA bit is also set in the Master Configuration Register 0x0000. Failure to meet
this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is set, and successive messages will
repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits are updated by the device during
terminal execution, that is, when the RT Configuration Register STEX bit equals 1. The host can write bit 2 only when
STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset.
Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word
address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Pro-
cessing), the receive mode Control Word looks like this:
Bit maintained by host
H
D
IBR
IXEQZIWA
MKBU
D
S
B
Y
ACDPB BCASPTPON
STOPPPPEN
Bit maintained by device
H
H
H
H
D1
D
D
9
D
8
X
7
X
6
X
5
X
4
H
3
H
2
X
1
X
0
D1
X
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
When SMCP applies, the number of active mode Control Word bits is reduced:
Bit maintained by host
H
D
IBR
IXEQZIWA
MKBU
D
S
B
Y
AC
BCASPTPON
Bit maintained by device
H
H
H
H
D1
X
D
9
D
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
D1
X
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W Reset Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for mode code commands using indexed buffer
mode when the INDX value decrements from 1 to 0. Upon completion of
command processing that results in INDX = 0, when IXEQZ interrupts are en-
abled, an IXEQZ interrupt is entered in the RT Pending Interrupt Register, the
INT output pin is asserted, and the interrupt is registered in the Interrupt Log.
15
IXEQZ
0
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Bit No. Mnemonic R/W Reset Function
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation at each instance of a valid mode code command. Upon
completion of command processing, when IWA interrupts are enabled, an
IWA interrupt is entered in the RT Pending Interrupt Register, the INT output
pin is asserted, and the interrupt is registered in the Interrupt Log.
14
IWA
0
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables
interrupt generation at each instance of a valid broadcast receive mode code
command. Upon completion of command processing, when IBR interrupts
are enabled, an IBR interrupt is entered in the Pending Interrupt Register, the
INT output pin is asserted, and the interrupt is registered in the Interrupt Log.
This bit has no function if the BCSTINV bit is high in the RT Configuration
Register. In this case, commands to RT address 31 are not recognized as
valid by the device.
13
IBR
0
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the RT 1553 Status Bits Register. See
that register description for additional information. When Busy is asserted,
mode data words received with MC16-MC31 are not stored and the DPB bit
does not toggle after message completion.
12
11
MKBUSY
0
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message pro-
cessing. The host may poll this bit to detect mode command activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
0
DBAC
SR = 0
Data Pointer B.
This status bit is maintained by the device and only applies for mode com-
mands using ping-pong buffer mode. This bit indicates the buffer to be used
for the next occurring mode command. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands, or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode.
0
10
DPB
SR = 0
Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
having T/R bit = 0. This bit has no function if the BCSTINV bit is asserted in
the RT Configuration Register. In this case, RT address 31 commands are
not recognized as valid by the HI-6130/31. This bit is reset to logic 0 by MR
master reset or SRST software reset.
0
9
BCAST
SR = 0
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Bit No. Mnemonic R/W Reset Function
Ping-Pong Enable Acknowledge.
This bit is read only and only applies for mode commands using ping-pong
mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The
device asserts this bit when it recognizes ping-pong is active for this mode
code. Before off-loading the receive data buffer for this mode code, the host
can ask the device to temporarily disable ping-pong by asserting STOPP
bit 3. The device acknowledges ping-pong is disabled by negating PPON.
The host can safely load or off-load the buffer without data collision while
PPON is negated. After buffer servicing, the host asks the device to re-enable
ping-pong by negating STOPP bit 3. The device acknowledges ping-pong is
re-enabled by asserting PPON.
8
PPON
0
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive
for this subaddress, ping-pong is disabled. Each new message overwrites
existing data in the buffer specified by DPB bit 10, and the DPB bit does not
toggle after command completion.
7-4
3
-----
0
0
Not Used
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this mode code.
The host resets this bit to ask the device to re-enable ping-pong. The device
confirms recognition of ping-pong enable or disable status by writing PPON
bit 8.
STOPP
Ping-Pong Buffer Enable.
The PPEN bit is initialized by the host to select buffer mode. If this bit is high,
ping-pong buffering is selected. If this bit is low, indexed single buffering is
selected.
After reset, the host initializes this bit to logic 1 to enable ping-pong buffering
for this mode code. The host asserts STOPP bit 3 to ask the device to
temporarily disable ping-pong. Negating the STOPP bit asks the device to
re-enable ping-pong. The device confirms ping-pong enable or disable state
changes by writing the PPON bit 8. PPEN bit 2 should only be initialized
or otherwise written when the applicable RT1ENA or RT2ENA input pin is
asserted, AND the corresponding RT1ENA or RT2ENA bit is also set in the
Master Configuration Register 0x0000.
2
PPEN
0
0
1,0
-----
Not Used.
19.4.5. Transmit Mode Control Word
Transmit Mode Control Words apply when the command word T/R bit equals one (transmit) and the subaddress field
has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior,
and conveys activity status to the host. It is initialized by the host before terminal execution begins. If using ping-pong
data buffers, Control Words should only be written when the applicable RT1ENA or RT2ENA input pin is asserted AND
the corresponding RT1ENA or RT2ENA bit is also set in the Master Configuration Register 0x0000. Failure to meet
this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is set, and successive messages will
repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits are updated by the device during
terminal execution, that is, when the RT Configuration Register STEX bit equals 1. The host can write bit 2 only when
STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset.
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Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word
address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code
Processing), the transmit mode Control Word looks like this:
Bit maintained by host
H
D
IBR
IXEQZIWA
MKBU
D
S
B
Y
ACDPB BCASPTPON
STOPPPPEN
Bit maintained by device
H
H
H
H
D1
D
D
9
D
8
X
7
X
6
X
5
X
4
H
3
H
2
X
1
X
0
D1
X
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
When SMCP applies, the number of active mode Control Word bits is reduced:
Bit maintained by host
H
D
IBR
IXEQZIWA
MKBU
D
S
B
Y
AC
BCASPTPON
Bit maintained by device
H
H
H
H
D1
X
D
9
D
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
D1
X
MSB 15 14 13 12 11 10
LSB
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic RW Reset Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for mode code commands using indexed buffer
mode when the INDX value decrements from 1 to 0. Upon completion of
command processing that results in INDX = 0, when IXEQZ interrupts are en-
abled, an IXEQZ interrupt is entered in the RT Pending Interrupt Register, the
INT output pin is asserted, and the interrupt is registered in the Interrupt Log.
15
14
IXEQZ
0
0
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation at each instance of a valid mode code command. Upon
completion of command processing, when IWA interrupts are enabled, an
IWA interrupt is entered in the RT Pending Interrupt Register, the INT output
pin is asserted, and the interrupt is registered in the Interrupt Log.
IWA
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables
interrupt generation at each instance of a valid broadcast transmit mode code
command. Upon completion of command processing, when IBR interrupts
are enabled, an IBR interrupt is entered in the RT Pending Interrupt Register,
the INT output pin is asserted, and the interrupt is registered in the Interrupt
Log. This bit has no function if the BCSTINV bit is high in the RT Configura-
tion Register. In this case, commands to RT address 31 are not recognized
as valid by the device.
13
IBR
0
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Bit No. Mnemonic RW Reset Function
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the RT 1553 Status Bits Register. See
that register description for additional information. When Busy is asserted,
mode data words are not transmitted with MC16-MC31, and the DPB bit does
not toggle after message completion. The MKBUSY bit is not heeded if set
in the Control Word for mode code command MC8 “reset remote terminal”.
For this command only, Busy is inhibited for the status response transmitted
before the reset process begins.
12
MKBUSY
0
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message pro-
cessing. The host may poll this bit to detect mode command activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
0
11
DBAC
SR = 0
Data Pointer B.
This status bit is maintained by the device and only applies for mode com-
mands using ping-pong buffer mode. This bit indicates the buffer to be used
for the next occurring mode command. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands, or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode.
0
10
DPB
SR = 0
Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
having T/R bit = 1. This bit has no function if the BCSTINV bit is asserted in
the RT Configuration Register. In this case, RT address 31 commands are
not recognized as valid by the HI-6130/31. This bit is reset to logic 0 by MR
master reset or SRST software reset.
0
9
BCAST
SR = 0
Ping-Pong Enable Acknowledge.
This bit is read only and only applies for mode commands using ping-pong
mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The
device asserts this bit when it recognizes ping-pong is active for this mode
code. Before loading the transmit data buffer for this mode code, the host can
ask the device to temporarily disable ping-pong by asserting STOPP bit 3.
The device acknowledges ping-pong is disabled by negating PPON. The host
can safely load or off-load the buffer without data collision while PPON is ne-
gated. After buffer servicing, the host asks the device to re-enable ping-pong
by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled
by asserting PPON.
8
PPON
0
If PPEN bit 2 is asserted and PPON bit 8 is negated when a new command
arrives for this mode code, ping-pong disable handshake is in effect: The
device applies single-buffer index mode using Data Pointer A or Data Pointer
B, per DPB bit 10. The DPB bit does not toggle after command completion.
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Bit No. Mnemonic RW Reset Function
7-4
-----
0
Not Used
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this mode code.
The host resets this bit to ask the device to re-enable ping-pong. The device
confirms recognition of ping-pong enable or disable status by writing PPON
bit 8.
3
STOPP
0
Ping-Pong Buffer Enable.
The PPEN bit is initialized by the host to select buffer mode. If this bit is high,
ping-pong buffering is selected. If this bit is low, indexed single buffering is
selected.
After reset, the host initializes this bit to logic 1 to enable ping-pong buffering
for this mode code. The host asserts STOPP bit 3 to ask the device to tempo-
rarily disable ping-pong. Negating the STOPP bit asks the device to re-enable
ping-pong. The device confirms ping-pong enable or disable state changes
by writing the PPON bit 8. PPEN bit 2 should only be initialized or otherwise
written when the applicable RT1ENA or RT2ENA input pin is asserted, AND
the corresponding RT1ENA or RT2ENA bit is also set in the Master Configu-
ration Register 0x0000.
2
PPEN
0
0
1,0
-----
Not Used.
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20. REMOTE TERMINAL RT1 AND RT2 MESSAGE DATA BUFFERS
The memory structures described up to this point comprise not more than 2K words of the lower memory address
space. The remaining memory is allocated by the host for message data storage, to fulfill application requirements.
This section describes the remaining data structures in shared RAM that control (and result from) command process-
ing.
By initializing the RT Descriptor Table, the host allocates memory space for storing data for each subaddress used in
the Remote Terminal application. Each legal Receive Subaddress and each legal Transmit Subaddress are usually
assigned unique buffer memory spaces. (Exception: To comply with the requirements for MIL-STD-1553 data wrap-
around, it is convenient to assign the data wrap-around subaddress to use the same buffer space for both receive and
transmit commands.)
As an option, data from broadcast receive commands can be stored separately from data resulting from non-broadcast
receive commands. Each subaddress buffer can use any of four data storage methods offered.
Subaddress (non-mode) commands are transacted with one to 32 data words. These are stored in a data buffer in
shared RAM. For receive commands, the device stores data received during message processing in the shared RAM
buffer. Later, the host retrieves these data words from the buffer. In the case of transmit commands, the host has
previously stored transmit data words in the transmit subaddress buffer. The device retrieves these data words for
transmission while processing the transmit command.
For each complete message processed, the message data stored in the buffer is comprised of these elements:
1. Message Information Word.
2. Time-Tag Word.
3. One to 32 Data Words transmitted or received during message transaction ( except no data word for mode code
commands 0 - 15 decimal).
The Message Information word and Time-Tag word are generated by the device and stored in assigned buffer space
to aid the host in further message processing. The Message Information word contains message type, word count and
message error information. The 16-bit Time-Tag word contains the value in the device internal Time-Tag counter when
the command is validated.
The host initializes the Descriptor Table entry for each subaddress or mode command to select one of four data buffer-
ing methods.
1. Indexed (Single Buffer) Method (see 20.4).
A predetermined number of messages (N) is transacted using a single data buffer in shared RAM. Several host in-
terrupt options are offered, including host interrupt when all N messages are successfully completed. This method
also supports single-message mode when N is purposely initialized to zero.
2. Double (or Ping-Pong) Buffer Method (see 20.3).
Successive messages alternate between two 34-word data buffers in shared RAM. Several host interrupt options
are offered.
3. Circular Buffer Mode 1 (see 20.5).
Buffer boundaries determine when the bulk transfer is complete. Message information and time-tag words are
stored in the same buffer with data words. Several host interrupt options are offered, including host interrupt when
the allocated data buffer is full.
4. Circular Buffer Mode 2 (see 20.6).
The number of messages transacted defines bulk transfer progress. Message data words are stored contiguously
in one buffer while message information and time-tag words are stored in a separate buffer. Several host interrupt
options are offered, including host interrupt when all N messages are completed.
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The data buffer options are summarized in Table 15.
Simplified Mode Command Processing.
This is a global option that applies for all mode code commands, when enabled. Mode commands have either one data
word, or no data word. Instead of using data buffers for storing this limited mode command data, the message data is
stored directly within the Descriptor Table. This option for mode commands is described in section 21.5.
Broadcast Data Separation
When the NOTICE2 option is enabled, data words resulting from broadcast receive commands will be stored separate-
ly from data resulting from non-broadcast receive commands when using indexed or ping-pong buffer modes. When
NOTICE2 applies, all subaddresses using indexed or ping-pong modes must have an assigned 34-word broadcast
data buffer in addition to the primary buffers listed above. Broadcast data segregation cannot be done using either
circular buffer mode.
Table 15. Summary of Data Buffer Modes.
Buffer
Mode
Data Buffer(s)
Number and Size
Message Info
Word
Suitable for
Mode Codes?
Primary Application
One. Host defines
size for N messages buffer as data
Stored in same Yes, only single For transacting N (multiple) messages
Indexed
Ping-Pong
Circular 1
message mode with optional host interrupt when done
Two 34-word buffers, Stored in same
one message each
For transacting single messages,
Yes
buffer as data
alternating between A and B buffers
One. Host defines
size for N words
Stored in same
buffer as data
For transacting messages until buffer is
full / empty, optional interrupt when done
No
One. Host defines
Stored in
For transacting N (multiple) messages
Circular 2 size for N messages, separate buffer
plus Msg Info Block (Msg info block)
No
with optional host interrupt when done.
Data buffer holds contiguous pure data.
20.1. Subaddress Message Information Words
20.1.1. Receive Subaddress Command
For receive subaddress commands, the device stores the received data words plus two additional words. The device
adds a receive subaddress Message Information Word and a Time-Tag Word to the received data words. The device
stores the Message Information and Time-Tag words ahead of the data words associated with the receive command,
as shown below. If message error occurs, the RT stores only the receive subaddress Message Information Word and
Time-Tag Word. Once a message error is detected, the device sets the MERR bit in the receive subaddress Message
Information word. When this occurs, all data words are considered invalid. Whenever the receive subaddress Mes-
sage Information Word MERR bit is set, the host should disregard the record’s data word(s).
Here is an example data structure for a 3-word receive command. Notice that the receive subaddress Data Pointer
points to the data structure starting address, not the first data word. The data pointer is located in the receive subad-
dress command’s Descriptor Block, fully described later:
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Data Buffer
Hex Address
Word Description
Device Writes Word ...
Data pointer equals 0x1500 → 0x1500
Message Information Word After message completion
0x1501
0x1502
0x1503
0x1504
Time-Tag Word
Data Word 1
Data Word 2
Data Word 3
“
“
“
After message completion (See Note)
“
“
“
“
“
“
“
“
“
“
Note: The data words are written
after message completion when the
RT Configuration Register bit TRXDB
is 1, otherwise written when received.
T
R
T
TMOEIWRRDEGRARPEWRRCTE
S
R
Y
R
NE
M
R
E
R
RRWASBIL
S
C
Y
MDTXRTRERR BUSIDWC4 WC3 WC2 WC1 WC0
MSB 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LSB
The following bits comprise the receive subaddress Message Information Word:
Bit No. Mnemonic Function
Time-Out Error.
This bit is asserted for RT-RT receive messages when the transmitting terminal fails to
start its status word and data transmission before time-out occurs, per TOSEL0-1 bits in
the RT Configuration Register.
15
TMOERR
Invalid Word Error.
14
13
IWDERR
GAPERR
Assertion of this bit indicates Manchester error or parity error was observed in a received
data word.
Gap Error.
Assertion of this bit indicates bus activity was detected immediately after the last expected
receive data word or that a gap occurred before all expected data words were received.
Word Count Error.
This bit is asserted if command is received with less data words than the command word
specifies. For example, a receive command for three data words is received with two
contiguous data words.
12
WCTERR
Sync Error.
11
10
SYNERR
MERR
This bit is asserted when an incorrect (command/status) sync type occurs in received data
words.
Message Error.
This bit is asserted when message error status change occurs during command process-
ing. See bits 7 and 11-15 for details.
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Bit No. Mnemonic Function
Was Busy.
This bit is asserted when the terminal responds to the receive command with BUSY
status, due to global BUSY bit set in RT 1553 Status Bits Register, or command-specific
MKBUSY bit set in the descriptor table Control Word. Received data words were buffered
normally.
9
8
WASBSY
ILCMD
Illegal Command Received.
This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal
command detection” is being applied. See Section 19.2 for further information.
RT-RT Transmit Remote Terminal Error.
This bit is set when the terminal decodes a valid RT-RT receive command, but one of four
potential errors is detected in the second command word, CW2: (1) CW2 is addressed
to broadcast address RT31. (2) the CW2 T/R bit equals 0, (3) the CW2 subaddress is a
7
TXRTERR mode command indicator, 00000 or 11111, or (4) CW2 has same non-broadcast terminal
address as receive command word CW1.
The TXRTERR bit is also set when status word received from the transmitting terminal
is invalid (e.g., parity error) or bits 15:11 in the status word reflect the wrong RT address
(does not match CW2).
Remote Terminal to Remote Terminal Transfer.
6
5
RTRT
Assertion of this bit indicates the receive command was an error-free RT-to-RT transfer.
Bus Identification.
BUSID
WC4:0
If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans-
acted on Bus B.
Word Count.
4-0
This 5-bit field contains the word count extracted from the command word. Zero indicates
32 words.
20.1.2. Transmit Subaddress Command
The external host is responsible for organizing the data packet (i.e., storing N data words) in shared RAM and initializ-
ing the applicable data pointer. The host must allocate two memory locations at the starting address of the data record
for device storage of the transmit subaddress Message Information Word and Time-Tag Word.
Here is an example data structure for a 3-word transmit command. Notice that the Data Pointer points to the data
structure starting address, not the first data word. The data pointer is located in the transmit subaddress command’s
Descriptor Block.
Data Buffer
Hex Address
Word Description
Word is Written By ...
Data pointer equals 0x1500 → 0x1500
Message Information Word Device, after message completion
0x1501
0x1502
0x1503
0x1504
Time-Tag Word
Data Word 1
Data Word 2
Data Word 3
“
“
“
“
Host, prior to terminal’s data transmit
“
“
“
“
“
“
“
“
“
“
“
“
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T
R
T
GAPEWRRCTERR MERRWASBIL
S
C
Y
MD
R
BUSIDW4 W3 W2 W1 W0
X
X
X
X
7
MSB 15 14 13 12 11 10
9
8
6
5
4
3
2
1
0
LSB
The following bits comprise the transmit subaddress Message Information Word.
Bit No. Mnemonic Function
15,14
-----
Not Used.
Gap Error.
13
GAPERR
Assertion of this bit indicates bus activity was detected immediately after the transmit com-
mand word, when a gap was expected.
Word Count Error.
12
11
WCTERR
-----
This bit is asserted if command is received with unexpected data word(s).
Not Used.
Message Error.
10
9
MERR
This bit is asserted when message error status change occurs during command process-
ing. See bits 12 and 13 for details.
Was Busy Status.
This bit is asserted when the terminal responds to the transmit command with BUSY
status, due to global BUSY bit set in RT 1553 Status Bits Register, or command-specific
MKBUSY bit set in the descriptor table Control Word. No data words were transmitted.
WASBSY
Illegal Command Received.
This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand equals one. The Illegalization Table should only contain nonzero values when “il-
legal command detection” is being applied. See Section 19.2 for further information.
8
ILCMD
7
6
-----
Not Used.
Remote Terminal to Remote Terminal Transfer.
RTRT
Assertion of this bit indicates the transmit command was an error-free RT-to-RT transfer.
Bus Identification.
5
BUSID
WC4:0
If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans-
acted on Bus B.
Word Count.
4-0
This 5-bit field contains the word count extracted from the command word. Zero indicates
32 words.
20.2. Mode Command Message Information Words
Mode command data structures in shared RAM are similar to those for subaddresses. Mode codes 0 through 15
(0x0F) do not have an associated data word, so data structures for these mode code values have just a Message
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Information Word and Time-Tag Word. The Message Information Word is stored at the memory address specified by
the descriptor table Data Pointer. Mode codes 16 through 31 (0x10 through 0x1F) have one associated data word.
The Message Information Word is stored at the memory address specified by the descriptor table Data Pointer, and
the Time-Tag Word is stored in the following location. The data word is stored at the memory address specified by the
Data Pointer plus two locations.
20.2.1. Receive Mode Command
The receive mode command data structure contains a Message Information Word, a Time-Tag Word and may con-
tain one Data Word. If a receive mode command has a data word, the device may apply the data as defined by MIL-
STD-1553, plus store the received single mode data word at the address specified by the Data Pointer, plus two
locations. Refer to the Mode Code Command Summary in Table 17.
Here is an example data structure for a receive mode command with data (mode code values 0x10 through 0x1F).
Notice that the Data Pointer points to the data structure starting address, not the mode data word. The data pointer is
located in the receive mode command’s Descriptor Block, fully described later:
Data Buffer
Hex Address
Word Description
Word is Written By ...
Data pointer equals 0x1500 → 0x1500
Message Information Word Device, after message completion
0x1501
0x1502
Time-Tag Word
Mode Data Word
“
“
“
“
“
“
“
“
Three receive mode commands with data are not defined under MIL-STD-1553B. These are MC16, MC18 and MC19
(mode codes 0x10, 0x12 and 0x13 respectively). However the device responds “in form” if illegal command detection
is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the RT Configuration Register
is logic 0.
For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag
Word.
Here is an example data structure for a receive mode command without data (mode code values 0x00 through 0x0F).
Note: None of these receive mode commands are defined under MIL-STD-1553B but the device responds “in form” if
illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the
RT Configuration Register is logic 0. Notice that the data pointer points to the data structure starting address, the mes-
sage information word. The data pointer is located in the receive mode command’s Descriptor Block, fully described
later:
Data Buffer
Hex Address
Word Description
Word is Written By ...
Data pointer equals 0x1500 → 0x1500
Message Information Word Device, after message completion
Time-Tag Word
0x1501
“
“
“
“
WCTERR
IWDEGRARPERR SYNE
M
R
E
R
RRWASBIL
S
C
Y
MD
BUSIDMC4 MC3 MC2 MC1 MC0
X
X
7
X
6
MSB 15 14 13 12 11 10
9
8
5
4
3
2
1
0
LSB
The following bits comprise the receive mode Message Information Word:
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Bit No. Mnemonic Function
15
-----
Not Used.
Invalid Word Error.
14
IWDERR
Assertion of this bit indicates Manchester error or parity error was observed in a received
data word.
Gap Error.
13
12
11
10
GAPERR
WCTERR
SYNERR
MERR
Assertion of this bit indicates bus activity was detected immediately after a received mode
data word or that a gap occurred before the data word was received.
Word Count Error
This bit is asserted if the command is received without expected mode data word, or with
extra word.
Sync Error.
This bit is asserted when incorrect (command/status) sync type occurs in received mode
data word.
Message Error.
This bit is asserted when message error status change occurs during command process-
ing. See bits 11- 14 for details.
Was Busy Status.
This bit is asserted when the terminal responds to the mode command with BUSY status,
due to global BUSY bit set in the RT 1553 Status Bits Register, or command-specific MK-
BUSY bit set in the descriptor table Control Word.
9
8
WASBSY
ILCMD
Illegal Command Received.
This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand equals one. The Illegalization Table should only contain nonzero values when “il-
legal command detection” is being applied. See Section 19.2 for further information.
7,6
5
-----
Not Used.
Bus Identification.
BUSID
If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans-
acted on Bus B.
Mode Code.
4-0
MC4:0
This 5-bit field contains the mode code extracted from the command word.
20.2.2. Transmit Mode Command
The transmit mode command data structure contains a Message Information Word, a Time-Tag word and may contain
one Data Word. For mode commands with associated data word (mode codes 16-31 decimal) the host is responsible
for loading the Mode Command Data Table before transmit mode commands are received (e.g., Transmit Vector Word
mode code). Two mode codes have internally generated data words: MC18 “Transmit Last Command” and MC19
“Transmit BIT Word”. For these, the device automatically transmits the data word then copies the transmitted data
value to the stored data structure.
Here is an example data structure for a transmit mode command with data (mode code values 0x10 through 0x1F).
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This applies to MC16 “Transmit Vector Word”. Notice that the data pointer points to the data structure starting address,
not the mode data word. The data pointer is located in the transmit mode command’s Descriptor Block, fully described
later:
Data Buffer
Hex Address
Word Description
Word is Written By ...
Data pointer equals 0x1500 → 0x1500
Message Information Word Device, after message completion
0x1501
0x1502
Time-Tag Word
Mode Data Word
“
“
“
“
Host, prior to terminal’s data transmit
(except MC18, MC19 are written by
the device after completion)
Three transmit mode commands with data are not defined under MIL-STD-1553B. These are MC17, MC20 and MC21
(mode codes 0x11, 0x14 and 0x15 respectively). However the device responds “in form” if illegal command detection
is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the RT Configuration Register
is logic 0.
For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag
Word. Here is an example data structure for a transmit mode command without data (mode code values 0x00 through
0x0F). Again, the data pointer points to the data structure starting address. The data pointer is located in the transmit
mode command’s Descriptor Block, fully described later:
Data Buffer
Hex Address
Word Description
Word is Written By ...
Data pointer equals 0x1500 → 0x1500
Message Information Word Device, after message completion
Time-Tag Word
0x1501
“
“
“
“
WCTERR
GAPERR
MERRWASBIL
S
C
Y
MD
BUSIDMC4 MC3 MC2 MC1 MC0
X
X
X
X
7
X
6
MSB 15 14 13 12 11 10
9
8
5
4
3
2
1
0
LSB
The following bits comprise the mode transmit Message Information Word:
Bit No. Mnemonic Function
15,14
-----
Not Used.
Gap Error.
13
GAPERR
This bit is high when bus activity was detected immediately after the mode command
word, when a gap was expected.
Word Count Error
12
11
WCTERR
-----
This bit is asserted if command is received with unexpected data word(s).
Not Used.
Message Error.
10
MERR
This bit is asserted when message error status change occurs during command process-
ing. See bits 12-13 for details.
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Bit No. Mnemonic Function
Was Busy Status.
This bit is asserted when the terminal responds to the mode command with BUSY status,
due to global BUSY bit set in RT 1553 Status Bits Register, or command-specific MK-
BUSY bit set in the descriptor table Control Word. No mode data word was transmitted.
9
WASBSY
Illegal Command Received.
This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal
command detection” is being applied. See Section 19.2 for further information.
8
ILCMD
7,6
5
-----
Not Used.
Bus Identification.
BUSID
If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans-
acted on Bus B.
Mode Code.
4-0
MC4:0
This 5-bit field contains the mode code extracted from the command word.
20.3. Ping-Pong Data Buffering
20.3.1. Double Buffered (Ping-Pong) Mode
Ping-pong buffer mode is a method for storing message and time-tag information and data associated with messages.
Each unique MIL-STD-1553 subaddress and mode code is assigned a pair of data buffers for transmit commands and
a pair of data buffers for receive commands. The device retrieves buffer data for transmit commands, or stores buffer
data for receive commands. During ping-pong operation, the device alternates message storage between Data Buffer
A and Data Buffer B, on a message-by-message basis.
When a subaddress or mode command uses ping-pong data buffer mode, its 4-word descriptor block in the Descriptor
Table is defined as follows:
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
Data Pointer A
Data Pointer B
Broadcast Data Pointer
If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two
words are stored at addresses N+2 and N+3.
Prior to starting terminal operation, enable ping-pong buffering for any subaddress (or mode code) by asserting the
PPEN bit and negating the STOPP bit in the descriptor Control Word. When the device detects ping-pong is selected
(PPEN = 1) and enabled (STOPP = 0), it asserts the Control Word PPON bit to confirm ping-pong is active.
During ping-pong operation, the RT determines the active data buffer at the beginning of message processing. The
Control Word DPB bit indicates the data pointer to be used by the next command. DPB equals logic 0 means Data
Pointer A is used next; DPB equals logic 1 means Data Pointer B is used next. For ping-pong, Data Pointers A and B
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are static values pointing to the first address in each buffer. At the conclusion of error-free message processing, the
Control Word DPB bit is inverted so the next command “ping-pongs” to the other data buffer. Each new message to the
subaddress or mode code overwrites message data and information words written two messages back. The DPB bit
does not toggle when a message ends in error, or if the command was illegal, or if Busy status applied for the received
command. In these cases, the next command will overwrite the same buffer. Figure 18 is a general illustration of ping-
pong buffer mode. Figure 19 shows a specific example.
20.3.2. Ping-Pong Enable / Disable Handshake
Because ping-pong messages and host buffer servicing are asynchronous, there is potential for “data collision”. Here
is a data collision example: The host reads data from an earlier message while the device simultaneously writes new
message data to the same buffer. The host reads a mix of new and old message data. Collisions can occur for both
transmit and receive messages.
A handshake scheme lets the external host asynchronously service ping-pong data buffers without data collision. To
off-load or load a subaddress (or mode code) buffer, the application software performs the following sequence:
a. Host asserts the Control Word STOPP bit to suspend ping-pong operation for the subaddress. When the device
recognizes STOPP bit assertion, it negates the PPON bit to acknowledge ping-pong is disabled. While PPON
remains low, the last written (or read) data buffer is protected against device updates. During this time, new
messages use the active buffer indicated by the Control Word DPA bit. Recurring messages repeatedly use the
same buffer until ping-pong resumes.
b. Host services the last-used data buffer. If the Control Word DPB bit equals logic 1, the last command used
Buffer A. The host application software off-loads or loads inactive Buffer A while the remote terminal uses
active Buffer B for new message(s). If the DPB bit equals logic 0, the last command used Buffer B. The host
application software off-loads or loads inactive Buffer B while the remote terminal uses active Buffer A for any
new messages. Each new receive message overwrites buffer contents from the last receive message. To avoid
possible data loss, host buffer servicing should be timed for completion before a second message can occur.
c. Host negates the Control Word STOPP bit to resume ping-pong operation for the subaddress. When the RT
recognizes the STOPP bit is reset, it sets the PPON bit to acknowledge ping-pong is again active. As long as
PPON remains set, the device alternates between data buffers A and B for new messages.
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Data Word 32
Data Words 2-31
Data Word 1
Time-Tag Word
Data Word 32
Broadcast Message
(if NOTICE2 is asserted)
Data Words 2-31
Message Info Word
Data Word 1
Time-Tag Word
Subaddress
Buffer Space
for Broadcast
(optional)
Message #2
Message #4
Message #6
etc.
Message Info Word
Assigned
Subaddress
Data Buffer B
B’cast Data Pointer
Data Pointer A
Increasing
Memory
Address
Data Pointer B
Control Word
Data Word 32
Data Words 2-31
Data Word 1
Time-Tag Word
Descriptor Block
for Subaddress
Message #1
Message #3
Message #5
etc.
Message Info Word
Assigned
Subaddress
Data Buffer B
Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
Message processing alternates between Data Buffers A and B. Upon sucessful message completion, the DPB
bit in Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every
other message.
Separate buffer for broadcast messages is optional. There is no alternate buffer for successive
broadcast messages.
Figure 18. Illustration of Ping-Pong Buffer Mode
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20.3.3. Broadcast Message Handling in Ping-Pong Mode
For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast mes-
sages separately from non-broadcast message data. Some applications may not include this requirement. The stan-
dard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the
device provides alternative strategies.
When the NOTICE2 bit in the RT Configuration Register is 1 and the BCSTINV bit is 0, ping-pong mode subaddresses
(or mode codes) will buffer data words from broadcast and non-broadcast messages separately. Broadcast message
information and data are stored in the broadcast data buffer; non-broadcast message information and data are stored
in ping-pong buffers A and B. Since there is just one broadcast data buffer, the NOTICE2 option treats broadcast
messages as exceptions to normal ping-pong mode. When using the NOTICE2 option, broadcast data buffer servicing
should have high priority, because a closely following broadcast message will overwrite the broadcast buffer.
Every mode command and subaddress (including transmit subaddresses) must have an assigned valid broad-
cast data pointer when NOTICE2 is asserted. When the NOTICE2 bit in the RT Configuration Register is 1 and the
BCSTINV bit is 0, reception of a broadcast-transmit message updates the Message Information and Time-Tag Words
for the assigned broadcast buffer, but no data is transmitted on the bus. Since broadcast-transmit is not allowed,
multiple transmit subaddresses may share a common “bit bucket” broadcast buffer. A two word buffer is sufficient for
storing the MIW and Time-Tag Word.
When using ping-pong mode, there are two ways to handle broadcast messages, when broadcast is enabled:
Option 1 for Ping-Pong Mode Broadcast Messages:
This option isolates broadcast message information in the broadcast data buffer. If the descriptor Control Word IBR bit
and Interrupt Enable Register IBR bit are both set, reception of broadcast messages generates an INT host interrupt.
To prevent data loss, the broadcast data buffer must be serviced before the next broadcast message occurs. Broadcast
messages do not affect non-broadcast message ping-pong; the Control Word DPB bit does not toggle after broadcast
message completion.
Option 1 Setup: At initialization, host asserts the NOTICE2 bit in the RT Configuration Register and sets the IBR
(Interrupt Broadcast Received) bit in descriptor Control Word(s). The IBR bit is asserted in the Interrupt Enable Register.
When a broadcast command is received, message information and data is stored in the broadcast data buffer and
an INT interrupt is generated. The host must read the Interrupt Log to determine the originating subaddress (or mode
code), then service the broadcast data buffer for that subaddress (or mode code) before another broadcast message
to the same subaddress (or mode code) arrives.
Option 2 for Ping-Pong Mode Broadcast Messages:
The second alternative stores both broadcast and non-broadcast message information in the ping-pong data buffers
A and B. IWA interrupts can signal arrival of any new message. The RT handles broadcast messages just like non-
broadcast messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages
during host buffer servicing. All messages toggle the Control Word DPB bit in message post-processing. For Notice II
compliance, separation of broadcast and non-broadcast data occurs within the host.
Option 2 Setup: At initialization, host negates the NOTICE2 bit in the RT Configuration Register. If IWA interrupts are
used, the host asserts the descriptor Control Word IWA (Interrupt When Accessed) bit 14 and the corresponding bit is
asserted in the Interrupt Enable Register. Using this option, the IBR interrupt is probably not used.
The host typically services the ping-pong data buffers A and B whenever a message is transacted. Using the setup
above, this occurs whenever the subaddress IWA interrupt generates an INT interrupt output for the host. The host
must read the Interrupt Log to determine the originating subaddress or mode code. The applicable data buffer is
indicated by the DPB bit in the Receive Control Word. The Message Information Word BCAST bit is asserted if the
message was broadcast.
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Device sets Control Word BCAST
bit (DPB bit remains static)
IBR interrupt is generated
0x1565
Data Word 32
Data Words 2-31
0x1547 - 0x1564
0x1546
Assigned
Subaddress
Broadcast
Data Buffer
Data Word 1
Time-Tag Word BC
Msg Info Word BC
0x1545
Receive Message #2
Broadcast, 32 Data Words
0x1544
Device resets Control Word
DPB and BCAST bits
0x1543
Data Word 32
0x1525 - 0x1542
0x1524
Data Words 2-31
Data Word 1
Time-Tag Word B
Msg Info Word B
Data Word 32
Assigned
Subaddress
Data Buffer B
0x1523
Receive Message #3
Non-Broadcast, 32 Data Words
0x1522
Device resets Control Word
DPB bit
0x1521
Data Words 2-31
0x1503 - 0x1520
0x1502
Data Word 1
Time-Tag Word A
Msg Info Word A
Assigned
Subaddress
Data Buffer A
0x1501
Receive Message #1
Non-Broadcast, 32 Data Words
0x1500
RAM
Address
Message #4 also uses
this buffer, if not broadcast
Increasing
Memory
Address
Broadcast Data Pointer = 0x1544 start address in RAM
Data Pointer B = 0x1522 Buffer B start address in RAM
B’cast Data Pointer
Data Pointer B
Data Pointer A = 0x1500 Buffer A start address in RAM
Control Word = 0x2010 Ping-Pong Mode, IBR Interrupt
Initialized Descriptor Values
Data Pointer A
Control Word
Descriptor Block
for a
Receive Subaddress
Following reset (which resets Control Word DPB bit), the subaddress transacts 4 commands of 32 data words each.
The NOTICE 2 option is enabled so the device segregates data from broadcast and non-broadcast messages.
Message #2 is a broadcast command, while the other three messages are non-broadcast. Notice that the broadcast
message does not affect DPB bit, but the following message resets BCAST bit. The interspersed broadcast command
does not affect alternation between Buffer A and Buffer B.
Figure 19. Ping-Pong Buffer Mode Example for a Receive Subaddress
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20.4. Indexed Data Buffer Mode
Also called “single buffer mode”, indexed buffering is one method for storing message and time-tag information and
data associated with messages. Buffer mode is selected for each subaddress or mode code in the Descriptor Table
Control Words. Indexed mode is enabled when Control Word PPEN, CIR1EN and CIR2EN bits are all zero.
When a subaddress or mode command uses the indexed data buffer mode, its 4-word descriptor block in the Descrip-
tor Table is defined as follows:
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
Data Pointer A
INDX Index Word
Broadcast Data Pointer
If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two
words are stored at addresses N+2 and N+3.
As the name implies, all message information and data is stored in a single buffer, indexed by descriptor word Data
Pointer A. The descriptor Control Word DPB bit is “don’t care”. The host initializes the desired message count in de-
scriptor INDX word. During message processing, the device retrieves or stores data words from the address specified
by descriptor Data Pointer A, automatically incrementing the pointer address as words are read or stored. Data Pointer
A is updated during command post-processing with the current buffer address unless the message index count in de-
scriptor INDX (word 3 of descriptor block) decrements to zero upon completion of the message. Figure 20 is a general
illustration of indexed single buffer mode. Figure 21 shows a specific example.
To set up a terminal subaddress to buffer multiple messages, the host writes the desired index count (INDX) to subad-
dress descriptor word 3. The initial INDX value ranges from zero to 3FF hex (1023) messages. The device decrements
the INDX count each time an error-free message is transacted, and the data pointer is updated to the first memory
address to be used for the next message. If INDX decrements from one to zero and Control Word IXEQZ bit 15 is as-
serted, the IXEQZ bit is set in the Interrupt Pending Register. If the corresponding bit in the Interrupt Enable Register
is asserted, an INT interrupt is generated when INDX decrements from one to zero.
INDX counter decrement does not occur if the command was illegalized or if INDX already equals zero. Once INDX
equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not up-
dated after successful message completion.
When using Index Mode with a non-zero INDX value, the host must remember the initial Data Pointer A address. The
Data Pointer A word is not automatically reinitialized to the buffer start address when INDX decrements from 1 to 0.
20.4.1. Single Message Mode
When Index Mode is initialized with an INDX value of zero, the subaddress or mode code is operating in “Single
Message Mode”. Here, the same data block is repeatedly over-read (for transmit data) or overwritten (for receive or
broadcast data). The DPA pointer is not updated at the end of each message. The chief advantage of single message
mode is simplicity. In comparison to other data buffering options, the single message buffer uses an absolute minimum
amount of memory space. The IXEQZ interrupt cannot be used for this scheme (INDX is always zero) but IWA inter-
rupts may be used. Single message mode is best suited to synchronous data transfer where the host processor can
reliably read or write new message data prior to the start of the next message to the same subaddress or mode code.
20.4.2. Broadcast Message Handling in Index Mode
For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast mes-
sages separately from non-broadcast message data. Some applications may not include this requirement. The stan-
dard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the
device supports alternative strategies.
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When the NOTICE2 bit is logic 1 in the RT Configuration Register, broadcast message data is stored in a broadcast
data buffer assigned for the subaddress or mode command. Each subaddress or mode command must have an as-
signed, valid non-zero broadcast buffer address. Non-broadcast message data is stored in Data Buffer A.
There are two ways to deal with broadcast messages in indexed buffer mode:
Option 1 for Index Mode Broadcast Messages:
The first alternative isolates broadcast message information in the broadcast data buffer. If the descriptor Control Word
IBR bit and Interrupt Enable Register IBR bit are both set, reception of broadcast messages generates an INT interrupt
to the host. The broadcast data buffer must be processed before another broadcast message arrives to prevent loss
of data. Broadcast messages do not decrement the INDX register, and Data Pointer A is not updated in message post-
processing. This scheme may be well suited for Single Message Mode (INDX = 0) when the host can reliably service
either the broadcast data buffer or data buffer A before the next receive message arrives for the same subaddress (or
mode code).
Option 1 Setup: At initialization, host asserts NOTICE2 bit in the RT Configuration Register and sets the Control Word
IBR (Interrupt Broadcast Received) bit for each index mode descriptor block. The IBR bit is also asserted in the Inter-
rupt Enable Register.
When a broadcast command is received, message information and data are stored in the broadcast data buffer. If
descriptor Control Word IBR bit is set, an INT interrupt is generated. The host must read the Interrupt Log to determine
the originating subaddress (or mode code) then service the broadcast data buffer for that subaddress (or mode code)
before the next broadcast message to the same subaddress (or mode code) arrives.
Option 2 for Index Mode Broadcast Messages:
The second alternative stores both broadcast and non-broadcast message information in data buffer A. Optional IBR
interrupts can signal arrival of broadcast messages. The RT handles broadcast messages just like non-broadcast
messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages during host
buffer servicing. All messages decrement the INDX register and Data Pointer A is updated in message post-process-
ing. This scheme is compatible with Single Message Mode or conventional N-message indexing. For Notice II compli-
ance, separation of broadcast and non-broadcast data occurs within the host.
Option 2 Setup:At initialization, host negates the NOTICE2 bit in the RT Configuration Register. If broadcast interrupts
are used, the Control Word IBR (Interrupt Broadcast Received) bit is asserted at each desired index mode descriptor
block. The IBR bit is also asserted in the Interrupt Enable Register.
Using option 2, the host has several options for servicing data buffer A: (a) when INDX decrements from one to zero
(using the IXEQZ interrupt), (b) when a broadcast message occurs (using the IBR interrupt) or (c) when any message
arrives (using the IWA interrupt).
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Data Word N
Data Word(s)
Data Word 1
Time-Tag Word
Increasing
Memory
Address
Data Word N
Data Word(s)
Next
Message
Message Info Word
Data Word 1
Time-Tag Word
Data Word N
Data Word(s)
Broadcast
Message
(if NOTICE2
is asserted)
Message Info Word
B’cast Data Pointer
INDX Index Count
Data Pointer A
Data Word 1
Time-Tag Word
Subaddress
Buffer Space
for Broadcast
(optional)
Current
Message
Message Info Word
Control Word
Data Word N
Data Word(s)
Descriptor Block
for Subaddress
Data Word 1
Time-Tag Word
Preceding
Message
Message Info Word
Assigned
Subaddress
Buffer Space
Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
Upon successful message completion, if non-zero the INDX count in Descriptor Word 3 is decremented.
If decremented result is non-zero, Data Pointer A is adjusted so next message is stored above
just-completed message. If decremented INDX is zero, Data Pointer A remains static
and IXEQZ interrupt occurs if enabled in Control Word.
Figure 20. Illustration of Indexed Buffer Mode
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For Message #2,
Index decrements to zero.
Data Pointer A = 0x1505 (static)
IXEQZ Interrupt is generated
Data Word 4
0x150A
0x1509
0x1508
0x1507
0x1506
0x1505
0x1504
0x1503
0x1502
0x1501
0x1500
For Message #3 and beyond,
the data buffer is overwritten.
Index remains zero (static)
Data Pointer A = 0x1505 (static)
and no IXEQZ interrupt occurs.
Data Word 3
Data Word 2
Data Word 1
Time-Tag Word 1
Msg Info Word 1
Messages #2, #3, etc
Receive 4 Words
Index decrements to one
Data Pointer A = 0x1505
Data Word 3
Data Word 2
Data Word 1
Time-Tag Word 1
Msg Info Word 1
Messages #1
Receive 3 Words
Index equals two
RAM
Address
Assigned
Receive
Subaddress
Buffer
Increasing
Memory
Address
B’cast Data Pointer
INDX Index Count
Data Pointer A
Broadcast Data Pointer = 0xXXXX Don’t Care
Index = 0x0002 Initialize index for 2 messages
Data Pointer A = 0x1500 Buffer Start Address in RAM
Control Word = 0x8000 Index Mode, IXEQZ Interrupt
Initialized Descriptor Values
Control Word
Descriptor Block
for a
Receive Subaddress
Figure 21. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled)
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20.5. Circular Buffer Mode 1
The device offers two circular data buffer modes as alternatives to ping-pong and indexed buffering. These circular
buffer options only apply for subaddress commands, not mode code commands. Circular buffering simplifies software
servicing of the remote terminal when implementing bulk data transfers. A circular buffer mode can be selected for
any subaddress by properly initializing its descriptor Control Word. Circular Buffer Mode 1 is selected when descriptor
Control Word PPEN and CIR2EN bits are both 0, and the CIR1EN bit is logic 1.
When a subaddress uses circular buffer mode 1, its four word block in the Descriptor Table is defined as follows:
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
SA (Buffer Start Address)
CA (Buffer Current Address)
EA (Buffer End Address)
If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two
words are stored at addresses N+2 and N+3.
Figure 22 provides a generalized illustration of Circular Buffer Mode 1, while Figure 23 shows a specific example.
Circular Buffer Mode 1 uses a single user-defined buffer that merges all transmit or receive data, along with message
information. Two words (Message Information and Time-Tag) are stored at the beginning of the block for each mes-
sage, followed by the message data word(s). The Mode 1 buffer pointers roll over (are reset to their base addresses)
when the allocated data buffer memory is full.
For each valid receive message, the device enters a Message Information word, Time-Tag word and data word(s)
into the circular receive buffer. For each valid transmit message, the device enters a Message Information word and
a Time-Tag word into reserved memory locations within the circular transmit buffer. The device automatically controls
the wrap around of circular buffers.
Two pointers define circular buffer length: start of buffer (lowest address) and end of buffer (highest address). User
specifies the start of buffer (SA) by writing the lowest address value into the second word of a unique subaddress
descriptor block. The user defines the bottom of the buffer (EA) by writing the highest address value to the fourth
word of that unique descriptor block. Both SA and EA remain static during message processing. The third word in the
descriptor block identifies the current address CA (i.e., last accessed address plus one). The circular buffer wraps to
the start address after completing a message that results in CA being greater than or equal to EA. If CA increments
past EA during message processing, the device will access memory addresses greater than the EA value. Reserve 33
address locations past the EA address to accommodate a worst-case 32 data word message with a record starting at
address = EA minus 1.
Each receive subaddress and transmit subaddress may have a unique circular buffer assignment. The RT decodes the
command word T/R bit, subaddress field and word count / mode code field to select the unique command descriptor
block containing the Control Word, SA pointer, CA pointer and EA pointer.
For receive messages, the device stores the Message Information word to the address specified by CA, the Time-Tag
word into CA+1 and the data into the next “N” locations starting with CA+2. For transmit messages, the device stores
the Message Information word to the address specified by CA and the Time-Tag word into CA+1. Retrieval of data for
transmission starts at address CA+2. When entering multiple transmit command data packets into the circular buffer,
delimit each data packet with two reserved memory locations. The device stores the Message Information word and
Time-Tag word into the reserved locations when processing the command.
Message processing for all commands begins with the device reading the unique descriptor block for the subaddress
or mode code specified by the T/R bit, subaddress and word count fields in the received command word.
For receive messages, the device stores “N” received data words in the circular data buffer. The first data word re-
ceived is stored at the location specified by the CA pointer +2. After message completion, the device stores the Mes-
sage Information word and Time-Tag words to addresses CA and CA+1 respectively. If no errors were detected, the
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device updates descriptor CA register. If the next address location (last stored data word +1) is less than or equal to
EA, CA is updated to (last stored address +1). If the next address location (last stored data word +1) is greater than
EA, the data buffer is full (or empty); CA is updated to the SA value. If descriptor Control Word IXEQZ bit is asserted
(and if Interrupt Enable Register IXEQZ bit is asserted) the device generates an interrupt to indicate full receive buffer
by asserting the INT interrupt output.
Although all messages store Message Information and Time-Tag words, no data is stored if the message ended with
error, or if the Busy status bit was set or if the commend was illegal (example: illegalized word count). Such messages
do not update CA, so the next message overwrites the same buffer space.
For transmit commands, the device begins transmission of data retrieving the first data word stored at address CA+2.
(Reminder: addresses CA and CA+1 are reserved for the Message Information and Time-Tag words.) When message
processing is complete, the device writes the Message Information and Time-Tag words into the buffer. If no errors
were detected, the device updates descriptor CA register. If the next address location (last retrieved data word +1) is
less than or equal to EA, CA is updated to (last retrieved address +1). If the next address location (last retrieved data
word +1) is greater than EA, the transmit data buffer is empty; CA is updated to the SA value. If the descriptor Control
Word IXEQZ bit is asserted (and if the Interrupt Enable Register IXEQZ bit is asserted) the device indicates “transmit
buffer empty” by asserting the INT interrupt output.
Circular Buffer Mode 1 does not support NOTICE2 segregation of broadcast data, even when the NOTICE2 bit equals
1 in the RT Configuration Register. Data from broadcast and non-broadcast receive commands is stored in the same
buffer. The BCAST bit in the Message Information Word reflects broadcast or non-broadcast status for each stored
message. If broadcast messages are not expected during data block transmission, the host can illegalize broadcast
commands for the subaddress. Broadcast illegalization can be done either permanently, or only when data block
transmission is scheduled.
For transmit subaddresses using Circular Buffer Mode 1, occurrences of broadcast-transmit commands to RT31 do
not result in bus transmission. However these messages update the Message Information Word addressed by the
Current Address (CA) pointer (and following Time-Tag Word) but afterwards, the CA pointer remains unchanged. The
next transmit command to the same subaddress, whether broadcast or not, overwrites the Message Information and
Time-Tag Word locations written by the previous broadcast transmit command.
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End
Address
Data Word N
Data Word(s)
Data Word 1
Time-Tag Word
Last Message
in Data Block
Message Info Word
More Messages
in Data Block
Data Word N
Data Word(s)
Data Word 1
Time-Tag Word
End Address
Current Address
Start Address
Control Word
Current
Message
Current
Address
Message Info Word
More Messages
in Data Block
Data Word N
Data Word(s)
Descriptor Block
for Subaddress
Data Word 1
Time-Tag Word
Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
FirstMessage
in Data Block
Start
Address
Message Info Word
Assigned
Subaddress
Circular Buffer
Increasing
Memory
Address
Descriptor block is initialized so Current Address equals buffer Start Address. After each successful
message transaction, Current Address is adjusted to point past last data word accessed. If adjusted
Current Address points past End Address, the Current Address is reinitialized to match Start Address
and an optional interrupt is generated to notify host that the pre-determined data block
was fully transacted.
Figure 22. Illustration of Circular Buffer Mode 1
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(1 + Data Word 32 address) ≥ End Address.
0x1565
Data Word 32
Device updates Current Address to
equal the Start Address, 0x1500.
IXEQZ interrupt is generated.
0x1547 - 0x1564
0x1546
Data Words 2-31
Buffer End
Address
Data Word 1
Time-Tag Word 3
Msg Info Word 3
0x1545
Receive Message #3
32 Data Words
0x1544
(1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x1544.
0x1543
Data Word 32
0x1525 - 0x1542
0x1524
Data Words 2-31
Data Word 1
Time-Tag Word 2
Msg Info Word 2
Data Word 32
0x1523
Receive Message #3
32 Data Words
0x1522
(1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x1522.
0x1521
0x1503 - 0x1520
0x1502
Data Words 2-31
Data Word 1
Time-Tag Word 1
Msg Info Word 1
0x1501
Receive Message #3
32 Data Words
Buffer Start
Address
0x1500
RAM
Address
Unless serviced by host
after Message #3 Interrupt,
Message #4 will overwrite
buffer, starting at 0x1500
End Address
Current Address
Start Address
Control Word
End Address = 0x1545 Buffer end address in RAM
Current Address = 0x1500 Buffer current address in RAM
Start Address = 0x1500 Buffer start address in RAM
Control Word = 0x8001 Circular Mode 1, IXEQZ Interrupt
Initialized Descriptor Values
Increasing
Memory
Address
Descriptor Block
for a
Receive Subaddress
Unlike Indexed mode, Data Block completion is based on Buffer Full / Buffer Empty, not number of messages.
Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior.
The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss.
Figure 23. Circular Buffer Mode 1 Example for a Receive Subaddress
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20.6. Circular Buffer Mode 2
Circular Buffer Mode 2 segregates message data and message information in separate host-defined buffers. Separat-
ing data from message information simplifies the host software that loads or unloads the data to or from the buffer. After
a predetermined number of messages has been transacted, buffer address pointers for data and message information
are automatically reset to their base addresses. Figure 24 is a generalized illustration of Circular Buffer Mode 2, while
Figure 25 shows a specific example.
Circular Buffer Mode 2 is selected when the Control Word PPEN bit is zero and the CIR2EN bit is logic 1. When the
CIR2EN bit is high, the CIR1EN bit is don’t care. The descriptor Control Word DPB bit is not used.
Any receive subaddress using circular buffer mode 2 has two circular buffers: a data storage buffer and a message
information buffer. A separate buffer pair may be used for transmit commands to the same subaddress, if it also uses
circular buffer mode 2. Each transmit and receive subaddress using circular buffer mode 2 may have unique data buf-
fer and message info buffer assignments. Careful management (involving the bus controller) may allow buffer sharing,
as long as multiple message sequences to a given subaddress are not interrupted by messages to other subaddresses
that use the same buffer space.
When a subaddress uses circular buffer mode 2, its Descriptor Table 4-word block is defined as follows:
Descriptor Word 1 Control Word
Descriptor Word 2 SA (Buffer Start Address)
Descriptor Word 3 CA (Buffer Current Address)
Descriptor Word 4 MIBA (Message Info Buffer Addr)
If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two
words are stored at addresses N+2 and N+3. The first word in the descriptor block is the Control Word. The second
and third words in the descriptor are the Start Address (SA) and Current Address (CA) pointers. The Message Informa-
tion Buffer Address (MIBA) points to the storage location for the Message Information Word from the next occurring
message.
Each time a message is completed, the device writes a new Message Information Word and Time-Tag Word in the
MIB (Message Information Buffer) at the MIBA address and following location, respectively. The MIBA pointer is not
updated if message error occurred, if the Busy status bit was set, or if the command was illegalized (for example an
illegal word count expressed in the command word.) For these situations, the Message Information and Time-Tag
words are still written, but MIB updates for the following message will overwrite the just-written Message Information
and Time-Tag word addresses.
For error-free receive messages, received data words are stored in the data buffer after message completion, starting
at the CA address value. The CA value is then updated for next-message readiness.
After writing the two MIB words, the device updates the MIBA value to show the buffer address to be used by the next
message. Until the predetermined number of error-free messages is transacted, the MIBA value is double-incremented
at each update. Before updating the MIBA in Descriptor Word 4, the pre-existing MIBA value is incremented once then
checked for ‘full count,” occurring when all N low-order address bits initialized to zero (explained below) become N
“one” bits. Full count means the predetermined number of successful messages was completed. When this occurs, the
CA and MIB pointers are automatically written to their initialized values by the device.
To preserve data integrity, the TRXDB bit should be set in the RT Configuration Register to avoid storing incomplete
data from messages resulting in error. With TRXDB asserted, the host is not bothered by message retries caused
by errors. The Buffer Empty/Full interrupt (if enabled) is generated only upon successful transaction of the entire N-
message data block.
To initialize Circular Buffer Mode 2, the host must know the number of messages to be transacted, always a power of
two: 1, 2, 4, 8, 16, 32, 64, 128, 256 or 512 messages. The host writes descriptor Control Word bits 7:4 with an encoded
4-bit value to set the fixed number of messages to be transacted. This is illustrated in Table 16. The host initializes the
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descriptor block MIBA pointer with a Message Information Buffer starting address. Because the MIB stores two words
for each message, the allocated MIB space should equal 2x the number of messages.
The initially-loaded MIB base address value is restricted. Some lower bits of the starting address must be zero so the
device can restore the MIBA pointer to the initial MIB base address after the predetermined message count is transact-
ed. As illustrated in Table 16, the required number of logic-0 bits depends on the message count. Initializing the MIBA
base address with more trailing zeros than indicated is acceptable; initializing less trailing zeros will cause malfunction.
Allocated space in the data buffer (see column 3, Table 16) assumes each message has the maximum 32 data words.
If messages contain less than 32 words, the data buffer size can be reduced. Since Circular Buffer Mode 2 counts
messages, values in all remaining Table 16 columns remain valid when message word count is reduced.
The host may read the MIBA value to determine the number of messages that have occurred since initialization. By
reading the initially-zeroed lower bits of the MIB Address, the host may determine the number of the next occurring
message.
From Table 16, a block of 128 messages requires 8 trailing zeros in the initial MIBA address, for example, 0x0F00.
After each message is completed, the MIBA value is updated (0x0F02, 0x0F04, etc.) The device detects message
block completion when all required initially-zero trailing address bits equal 1 after MIBA is incremented once. In our
example, MIBA would increment from 0x0FFE to 0x0FFF. When “full count” occurs, the device updates MIBA to the
original value (e.g., 0x0F00) and copies the SA starting address value to CA current address register, ready for buffer
service by the host. The device optionally generates a “buffer empty-full” interrupt for the host when block transfer is
completed.
During block transfer, the host can read the MIBA value to determine the number of additional messages needed be-
fore the N-message data block is complete.
Message processing for all commands begins with the RT reading the unique descriptor block for the subaddress
specified by the T/R bit, subaddress and word count fields in the received command word.
Table 16. Circular Buffer Mode 2 (Initialization factors based on message block size)
Control Word
Bits 7:4
CIR2ZN Field
Required Data
Space if 32
Words / Msg
Required
MIB Space, 2
Words / Msg
Number of
Messages
Initial MIBA Value, Showing the
Required Leading and Trailing Zeros
2
4
0010 (2)
0011 (3)
0100 (4)
0101 (5)
0110 (6)
0111 (7)
1000 (8)
1001 (9)
1010 (A)
64
128
4
8
0xxxxxxxxxxxx00
0xxxxxxxxxxx000
0xxxxxxxxxx0000
0xxxxxxxxx00000
0xxxxxxxx000000
0xxxxxxx0000000
0xxxxxx00000000
0xxxxx000000000
0xxxx0000000000
8
256
16
16
32
64
128
256
512
512
32
1,024
2,048
4,096
8,192
16,384
64
128
256
512
1,024
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For receive subaddresses using Circular Buffer Mode 2, the device stores received data words in the circular data
buffer. The first data word received for each message is stored at the location indicated by the CA pointer. After
the correct number of words is received (as specified in the command word) the device writes Message Information
and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address and MIBA
Message Information pointers for next-message readiness. If the predetermined total number of messages has not
yet been transacted, MIBA points to the next location in the message information buffer and CA points to the next
location in the data buffer. If the completed message is the last message in the block, the CA current (data) address
and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4 tell the
device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the Interrupt
Enable Register IXEQZ bit is asserted) the device generates a Buffer Full / Empty interrupt, asserting the INT interrupt
output.
For transmit subaddresses using Circular Buffer Mode 2, the device transmits data from the assigned RAM buffer,
starting at the location specified by the CA pointer. The first data word transmitted is stored at the location specified
by the CA pointer. After all data words are transmitted (as specified in the command word) the device writes Message
Information and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address
and MIBA Message Information pointers for next-message readiness. If the predetermined total number of messages
has not yet been transacted, MIBA points to the next location in the message information buffer and CA points to the
next location in the data buffer. If the completed message is the last message in the block, the CA current (data) ad-
dress and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4
tell the device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the
Interrupt Enable Register IXEQZ bit is asserted) the device generates a Buffer Full / Empty interrupt, asserting the INT
interrupt output.
Circular Buffer Mode 2 does not support NOTICE2 segregation of broadcast data, even when the NOTICE2 bit equals
1 in the RT Configuration Register. Data words from broadcast receive commands are stored in the same buffer with
data from non-broadcast receive commands. The BCAST bit in the Message Information Word reflects broadcast or
non-broadcast status for each stored message. If broadcast messages to the subaddresss are not expected during
data block transmission or will result in data block error, the host can illegalize broadcast commands for the subad-
dress, either permanently or only when block transmission is scheduled.
For transmit subaddresses using Circular Buffer Mode 2, occurrences of broadcast-transmit commands to RT31 do
not result in bus transmission. However these messages update the Message Information Word addressed by the
Message information Block (MIB) pointer (and the following Time-Tag Word) but afterwards, the MIB and CA pointers
remain unchanged. The next transmit command to the same subaddress, whether broadcast or not, overwrites the
Message Information and Time-Tag Word locations written by the previous broadcast transmit command.
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Data Word N
Data Word(s)
Time-Tag Word
Last Message
in Data Block
Last Message
in Data Block
Message Info Word
Data Word 1
Increasing
Memory
Address
Data Word N
Data Word(s)
Time-Tag Word
Current
Message
MIB Address
Current Address
Start Address
Control Word
Message Info Word
Current
Message
Current
Address
Data Word 1
Time-Tag Word
Message Info Word
Data Word N
Data Word(s)
FirstMessage
in Data Block
Descriptor Block
for Subaddress
Assigned
Subaddress
Message Info Buffer
(MIB)
Start
Address
Data Word 1
FirstMessage
in Data Block
Assigned
Subaddress
Circular Data
Buffer
Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
Segregated storage for data and message information simplifies host loading / offloading of buffered data.
Descriptor MIB Address tracks number of messages. Full count occurs when N initialized 0-bits become N 1-bits.
When full number of messages in block is transacted, an optional interrupt is generated to notify host.
Figure 24. Illustration of Circular Buffer Mode 2
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Msg Count increments to 4,
full count, data block complete.
Device updates CA to equal
buffer Start Address 0x1500.
Device updates MIBA to equal
MIB Start Address 0x1600.
IXEQZ interrupt is generated.
0x157F
Data Word 32
Data Words 2-31
0x1561 - 0x157E
0x1560
Receive Message #4
32 Data Words
Data Word 1
Data Word 32
Data Words 2-31
Msg Count increments to 3.
Device updates CA to 0x1560
and updates MIBA to 0x1606.
0x155F
0x1607
0x1606
0x1605
0x1604
0x1603
0x1602
0x1601
0x1600
0x1541 - 0x155E
0x1540
Time-Tag Word 4
Msg Info Word 4
Time-Tag Word 3
Msg Info Word 3
Time-Tag Word 2
Msg Info Word 2
Time-Tag Word 1
Msg Info Word 1
Receive Message #3
32 Data Words
Data Word 1
Data Word 32
Data Words 2-31
0x153F
Msg Count increments to 2.
Device updates CA to 0x1540
and updates MIBA to 0x1604.
Receive Message #2
0x1521 - 0x153E
0x1520
Data Word 1
32 Data Words
0x151F
Msg Count increments to 1.
Device updates CA to 0x1520
and updates MIBA to 0x1602.
Data Word 32
0x1501 - 0x151E
0x1500
Data Words 2-31
Receive Message #1
32 Data Words
Data Word 1
RAM
RAM
Address
Address
Message
Information
Buffer (MIB)
Data Word
Buffer
MIB Address
Current Address
Start Address
Control Word
MIB Address = 0x1600 MIB start address in RAM
Current Address = 0x1500 Buffer current address in RAM
Start Address = 0x1500 Buffer start address in RAM
Control Word = 0x8042 Circular Mode 2, 4 messages, IXEQZ Interrupt
Initialized Descriptor Values
Increasing
Memory
Address
Descriptor Block
for a
Receive Subaddress
Data Block completion is based on number of messages, not Buffer Full or Buffer Empty.
Example is set to successfully transact four 32 data word receive messages, then generate IXEQZ interrupt for host.
The data buffer requires minimal processing by host because message information words are stored separately in MIB.
Figure 25. Circular Buffer Mode 2 Example for a Receive Subaddress
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21. REMOTE TERMINAL RT1 AND RT2 MODE COMMAND PROCESSING
21.1. General Considerations
The device provides decoding for all mode code combinations, consistent with MIL-STD-1553B requirements. Several
mode command options are provided to suit any application requirement:
In the RT Configuration Register, the option bit UMCINV (Undefined Mode Codes Invalid) globally defines whether un-
defined mode code commands are treated as valid (default) or invalid commands. This bit applies only to the following
22 mode code commands that are undefined in MIL-STD-1553B:
Mode Codes 0 through 15 with T/R bit = 0
Mode Codes16, 18 and19 withT/R bit = 0
Mode Codes 17, 20 and 21 with T/R bit = 1
If the UMCINV bit is low (default after MR reset) undefined mode code commands are considered valid and RT re-
sponse is based on individual mode command settings in the Illegalization Table: If the command’s table bit equals
0, the mode command is legal; the RT responds “in form” and updates status. If the command’s table bit equals 1 the
mode command is illegal, the RT asserts Message Error status and (if non-broadcast) transmits only its Status Word
without associated data word. Table 17 describes explicit terminal response for each mode code value and command
T/R bit state, based on various option settings.
If UMCINV is asserted, the 22 undefined mode code commands are treated as invalid: There is no terminal recognition
of the command. No command response occurs and status remains unchanged for the benefit of following “transmit
status” or “transmit last command” mode commands.
If UMCINV is low, the device determines legal vs. illegal status of commands from the Illegalization Table. If the termi-
nal does not use illegal command detection, the Illegalization Table should be left in its post-reset default state, all val-
ues equal logic 0. In this case, the terminal provides “in form” response to all valid commands. The terminal responds
with clear status and a transmitted mode data word for mode commands 16-31 with T/R bit equals 1. Assigned data
buffer locations can be initialized to provide predictable “in form” responses for all transmit mode codes 16-31. (If UM-
CINV is asserted, the terminal will not respond or update status for received mode codes 17, 20 and 21 with T/R = 1.)
To use illegal command detection, the host modifies the Illegalization Table to make illegal any combination subad-
dress and mode code commands. This may include undefined mode codes, reserved mode codes, and/or mode codes
not implemented in the application.
Note: Mode command MC0 “dynamic bus control” cannot be implemented in the device since the HI-6130/31 cannot
act as a Bus Controller. Therefore, the “dynamic bus control acceptance” status bit cannot be set in the outgoing status
word from this device.
21.2. Mode Command Interrupts
For mode commands, interrupt generation is programmed by the top three bits in the descriptor table Control Word.
Notice that broadcast-transmit interrupts can be enabled for mode code values in the range of 0 - 15, but broadcast-
transmit mode codes 16 - 31 are not allowed. When a mode command is received and the IWA interrupt bit is asserted
in its descriptor Control Word, that command will generate a host interrupt if the IWA bit is high in the Interrupt Enable
Register. The IWA bit is asserted in the Pending Interrupt Register and the INT interrupt output is asserted.
Before INT interrupt assertion, the device updates the Interrupt Log buffer, writing a new IIW Interrupt Information Word
and a new IAW Interrupt Address Word. The IWA (interrupt when accessed) bit is asserted in the new IIW to indicate
interrupt type. The IAW contains the Descriptor Table address for the mode command’s Control Word, based on mode
code value and command word T/R bit state. The host reads the IAW to determine the command that caused the
interrupt.
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21.3. Mode Command Data Words
Mode commands having mode code values from 0 through 15 (decimal) do not have an associated data word. These
are received as Command Word only, never having a contiguous data word. The terminal response to valid mode com-
mands 0-15 always consists of Status Word only, assuming command was not broadcast.
Mode commands having mode code values from 16 through 31 (decimal) always have an associated data word. When
the command word T/R bit equals 0, the terminal receives a data word, contiguously following the Command Word.
When valid legal mode commands 16-31 arrive with T/R bit equal to 1, the terminal responds by transmitting its status
word with a single data word.
When the SMCP option bit in the RT Configuration Register is zero, individual data words for mode codes 16-31 deci-
mal are stored in an indexed or ping-pong buffer assigned by the mode command’s Descriptor Table entry. Circular
buffer methods are not available for mode code commands.
When the SMCP option bit in the RT Configuration Register is asserted, individual data words for mode codes 16-31
decimal are stored within the Descriptor Table itself. This is explained next.
Table 17. Mode Code Command Summary
Mode Code
Command
T/R bit
Associated Broadcast See
MIL-STD-1553 Defined Function
Data Word
Allowed
Note
Binary
Dec.
00000
to
01111
0
to
15
Undefined mode commands 0 - 15 when
0
No
No
(1)
(3)
T/R bit = 0
1
1
1
1
1
1
1
1
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
0
1
2
3
4
5
6
7
8
Dynamic Bus Control
Synchronize (without data)
Transmit Status Word
No
No
No
No
No
No
No
No
No
No
Yes
No
Initiate Self-Test
Yes
Yes
Yes
Yes
Yes
Yes
Transmitter Shutdown
Override Transmitter Shutdown
Inhibit Terminal Flag
Override Inhibit Terminal Flag
Reset Remote Terminal
01001
to
01111
9
to
15
Reserved Mode Commands 9 - 15 with
T/R bit = 1
1
No
Yes
(2)
(1)
0
1
0
1
0
10000
10000
10001
10001
10010
16
16
17
17
18
Undefined Mode Command
Transmit Vector Word
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
No
Synchronize With Data
Undefined Mode Command
Undefined Mode Command
(1)
(1)
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Mode Code
Binary Dec.
Command
T/R bit
Associated Broadcast See
MIL-STD-1553 Defined Function
Data Word
Allowed
Note
1
0
1
0
1
0
1
10010
10011
10011
10100
10100
10101
10101
18
19
19
20
20
21
21
Transmit Last Command
Undefined Mode Command
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
Yes
No
(1)
Transmit Built-In Test Word
Selected Transmitter Shutdown
Undefined Mode Command
(1)
Override Selected Transmitter Shutdown
Undefined Mode Command
(1)
(2)
01001
to
01111
22
to
31
Reserved Mode Commands 22 - 31 with
T/R bit = 0
0
Yes
Yes
Yes
No
01001
to
01111
22
to
31
Reserved Mode Commands 22 - 31 with
T/R bit = 1
1
(2)
NOTES:
1. The 22 undefined mode commands can be rendered invalid by setting the UMCINV (undefined mode codes
invalid) option bit in Configuration Register1. If UMCINV is asserted, there is no recognition of the undefined com-
mand by the terminal. If UMCINV is zero, the commands are considered valid. Terminal response when UMCINV
equals 0 is wholly determined by the Illegalization Table:
a. If a command’s bit in the Illegalization Table equals zero, the terminal responds “in form” with Clear Status.
Mode commands 17, 20 and 21 are undefined when T/R bit equals one, but will transmit a contiguous data
word. Mode commands 16, 18 or 19 are undefined when T/R bit equals 0, but will receive a contiguous data
word.
b. If a command’s bit in the Illegalization Table equals one, the command is considered illegal. The Message
Error (ME) status bit is asserted and the terminal transmits status without data word. Illegal mode commands
16-31 will not transmit or receive a mode data word.
2. Response to the reserved mode commands is fully defined by Illegalization Table settings. As described in (a) and
(b) above, the terminal illegalizes any reserved mode command having Illegalization Table bit equal to 1, and re-
sponds “in form” when the Table bit equals zero. The “in form” response for reserved mode commands 16 through
31 transacts a received or transmitted data word.
3. HI-6130/31 cannot fulfill Bus Control duties.
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21.4. Standard Mode Command Processing
Data buffer options for mode commands differ from buffer options for subaddress commands. Mode commands can
use ping-pong buffering or indexed buffering. When mode commands use indexed buffers, “single message mode”
(INDX = 0) is recommended. When using indexed or ping-pong buffers for mode commands:
•
For mode commands without associated data word (mode codes 0-15 decimal), only the Message Information
and Time-Tag words are updated in the mode command’s assigned data buffer in RAM.
•
For mode commands 16-31 (decimal) that receive a data word, indexed and ping-pong buffer methods copy the
received mode data word to the mode command’s assigned data buffer in shared RAM, after the message is
transacted. The Message Information and Time-Tag words are also updated.
•
For most mode commands 16-31 (decimal) that transmit a data word, the device reads the data word for transmit
from the buffer location assigned in the Descriptor Table. Exceptions occur for MC18 “transmit last command”
and for MC19 “transmit BIT word.” The MC18 data word is automatically provided by the device, based on recent
command transactions. The MC19 data word for RT1 comes from register 0x1E or 0x1F, selected by the ALT-
BITW option in the RT1 Configuration Register (section 18.1). For RT2, the MC19 data word comes from register
0x27 or 0x28, selected by the ALTBITW option in the RT2 Configuration Register. For both MC18 and MC19,
the transmitted data word is automatically recorded in the mode command’s assigned data buffer in RAM, after
message completion. The Message Information and Time-Tag words are also updated.
21.5. Simplified Mode Command Processing
Mode commands have a buffer alternative that is unavailable for subaddress commands. The SMCP bit in the RT Con-
figuration Register selects Simplified Mode Command Processing, a global option applying to all mode commands.
When the SMCP bit is high, mode command descriptor blocks (in the Descriptor Table) do not contain data pointers
to reserved buffers elsewhere in the shared RAM. Instead, each 4-word descriptor block itself contains the message
information word, the time-tag word and the data from the most recent occurrence of each mode command:
Descriptor Word 1 Mode Command Control Word
Descriptor Word 2 Message Information Word
Descriptor Word 3 Time-Tag Word
Descriptor Word 4 Mode Data Word
Descriptor Word 1 contains the receive or transmit mode command Control Word. When SMCP is used, just two Con-
trol Word bits are used: DBAC (descriptor block accessed) and BCAST (broadcast).
When SMCP is enabled, the host need not initialize the mode code command segments in the Descriptor Table. When
Simplified Mode Command Processing is selected, the host does not write Descriptor Words 2-3 in the Descriptor
Table entries for mode commands. For mode code values 0 to 15 decimal, the Descriptor Word 4 serves no function
because these mode codes do not have an associated data word. For transmit mode code values 16 to 31, the host
may initialize Descriptor Word 4. The default transmit value is 0x0000. Mode command MC16 “transmit vector word”
is one of the three defined mode commands that transmit a data word: MC16, MC18 and MC19. Its Descriptor Word 4
should be initialized if a value other than 0x0000 is needed. MC18 and MC19 are discussed below.
•
For mode commands without associated data word (mode codes 0-15 decimal), Simplified Mode Command
Processing updates the Message Information and Time-Tag words in Descriptor Words 2 and 3, and Descriptor
Word 1 (bits 9,11). For these commands, SMCP does not update Descriptor Word 4, which may be non-zero if
written earlier by the host.
•
•
For receive mode commands 16-31 (decimal) that receive a data word, Simplified Mode Command Processing
copies the received mode data word to Descriptor Word 4. The Message Information and Time-Tag words in
Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated.
For most transmit mode codes 16-31 (decimal), the device reads the data word for transmission from each
command’s Descriptor Word 4. Exceptions occur for MC18 “transmit last command” and for MC19 “transmit built-
in test word”. The MC18 data word is automatically provided, based on the last command transacted. The MC19
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data word for RT1 comes from register 0x1E or 0x1F, selected by the ALTBITW option in the RT1 Configuration
Register (section 18.1). For RT2, the MC19 data word comes from register 0x27 or 0x28, selected by theALTBITW
option in the RT2 Configuration Register. For MC18 and MC19, the transmitted data value is automatically copied
to the mode command’s Descriptor Word 4 after message completion. The Message Information and Time-Tag
words in Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated.
The Appendix shows terminal response to all possible subaddress and mode code command combinations. The
table summarizes terminal response for the full range of message conditions, including errors, incomplete messages,
etc. The table explicitly describes terminal response and impact on terminal Status Word, Descriptor Control Words
and data buffer Message Information Words. The table includes effects for all pertinent setup options and identifies all
interrupt options available. Bold text blocks indicate error-free messages or “in form” Clear Status responses when the
terminal is not using “illegal command detection”.
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22. SERIAL EEPROM PROGRAMMING UTILITY
The HI-6130 or HI-6131 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-
initialization events. The device copies host-configured registers and RAM (configuration tables and possibly data
buffers) to serial EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in SPI modes 1 or 3 and have 128-byte pages. The serial SPI data
is clocked at 8.3 MHz SCK frequency. A 2K x 8 EEPROM can restore the lower 1K x 16 device address space. A 64K
x 8 EEPROM retains the entire 32K x 16 register/RAM address space.
22.1. Writing the Auto-Initialization EEPROM
A deliberate series of events initiates copy of data from HI-6130 or HI-6131 registers and RAM to serial EEPROM.
This reduces the likelihood of accidental EEPROM overwrites. The following series of events must occur to initiate
programming:
1. Using a fresh host initialization immediately following MR master reset as the basis for EEPROM copy
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN, TXINHA and TXINHB pins in logic
0 state, apply MR master reset and wait for READY output assertion. Verify that the IRQ interrupt output does
not pulse low at READY assertion, indicating likely RT address parity error at the RTA4:0 and RTAP pins. Using
known good parameters, the host initializes device registers, the RAM descriptor table and transmit data buffers
(if necessary).
•
If auto-initialization will be used to configure the Bus Controller, the BCENA input pin should be logic 1. The
corresponding BCENA bit 12 in Master Configuration Register 0x0000 should be logic 1, but BCSTRT register
bit 13 must remain in the post-reset logic 0 state.
•
If auto-initialization will be used to configure the Bus Monitor, the MTRUN input pin should be logic 1. The cor-
responding MTENA bit 8 in Master Configuration Register 0x0000 should be logic 0. Until EEPROM program-
ming is complete, the terminal should be disconnected from MIL-STD-1553 buses (or other measures taken)
to prevent bus activity detection by the monitor.
•
If auto-initialization will be used to configure Remote Terminals RT1 and/or RT2, the RT1ENA and/or RT2ENA
input pins should be logic 1. The corresponding RT1ENA and/or RT2ENA bits 6 and 7 in Master Configura-
tion Register 0x0000 should be logic 1, but RT1STEX and RT2STEX register bits 4 and 5 must remain in the
post-reset logic 0 state.
Skip to step 3.
2. Using the existing EEPROM configuration as the baseline for a new EEPROM configuration
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. If the application includes the Bus Controller, the BCENA
input pin should be at logic 0. With the AUTOEN pin in logic 1 state and the TXINHA and TXINHB pins in logic 0
state, apply and release MR master reset and wait for READY output assertion. Verify that the IRQ output does not
pulse low (or go and remain low) at READY assertion. Confirm that the EECKE and RAMIF bits are logic 0 in the
Operational Status Register 0x0002. If register bits 4 or 5 (RT1STEX, RT2STEX) in Master Configuration Register
0x0000 were set by auto-initialization, reset them now. Modify register and RAM values to reflect the new changes.
3. If the application includes the Bus Controller, the BCENA input pin should be set to logic 1 now. Do not assert
BCSTRT bit 13 in Master Configuration Register 0x0000.
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EEPROM programming is locked out at step 4 for the following conditions:
•
•
ACTIVE output pin assertion occurs after MR master reset.
RT1STEX bit 4, RT2STEX bit 5 or MTENA bit 8 is set in Master Configuration Reg 0x0000.
4. The host writes a 2-part “unlock code” to RAM address 0x004E. The unlock code value selectively enables any
combination of terminal devices (BC, MT, RT1, RT2) to automatically start execution, after subsequent auto-initial-
ization sequences are performed. Programmed here, the same combination of terminal devices is simultaneously
enabled after every initialization. Unlock words are encoded as shown in Table 18.
Table 18. Terminal Unlock Word Encoding
Word 1
0xA00A
0xA03A
0xA0CA
0xA0FA
0xA30A
0xA33A
0xA3CA
0xA3FA
0xAC0A
0xAC3A
0xACCA
0xACFA
0xAF0A
0xAF3A
0xAFCA
0xAFFA
Word 2
0x5FF5
0x5FC5
0x5F35
0x5F05
0x5CF5
0x5CC5
0x5C35
0x5C05
0x53F5
0x53C5
0x5335
0x5305
0x50F5
0x50C5
0x5035
0x5005
Initialize RT1 2
No auto init. 1
X
Initialize RT2 3
No auto init.
Initialize MT 4
No auto init.
Initialize BC 5
No auto init.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Note 1: Default. No terminal devices (BC, MT, RT1, RT2) are started. The host must write Master Configuration
Register 0x0000 to start terminals.
Note 2: The RT1ENA register bit 6 in register 0x0000 must be set before step 4. During auto-initialization events,
the RT1ENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
RT1STEX bit 4 is automatically set in Master Configuration. Register 0x0000, starting Remote Terminal RT1 execution.
Note 3: The RT2ENA register bit 7 in register 0x0000 must be set before step 4. During auto-initialization events,
the RT2ENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
RT2STEX bit 5 is automatically set in Master Configuration Register 0x0000, starting Remote Terminal RT2 execution.
Note 4: The MTENA register bit 8 in register 0x0000 must be set before step 4. During auto-initialization events, the
MTRUN and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization, the
SMT or IMT MTENA bit is automatically set in Master Configuration Register 0x0000, starting Bus Monitor execution.
Note 5: The BCENA register bit 12 in register 0x0000 must be set before step 4. During auto-initialization events,
the BCENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
BCSTRT bit 13 is automatically pulsed in Master Configuration Register 0x0000, starting Bus Controller execution.
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The four terminals can be automatically started (or not started) in any combination. For example, exclusive-ORing
both default unlock Words 1 and 2 with 0x0FF0 results in unlock Word 1 = 0xAFFA and Word 2 = 0x5005. This
combination automatically and simultaneously enables execution for all four terminal devices: BC, MT, RT1 and
RT2, at every subsequent auto-initialization from EEPROM. Individual soft resets for a single terminal device will
automatically enable that device, if enabled here.
5. The EECOPY input pin is driven high for at least 1 ms, then driven low. In response, the READY output goes low
while EEPROM memory is written. The unlock code at address 0x004E is cleared. Device register and RAM con-
tents are written to the serial EEPROM, one byte at a time.
During programming, terminal checksums are tallied for the RT1, RT2 and SMT/IMT terminal devices, if used. An
overall 32K checksum is also tallied. These checksums, stored in the EEPROM, are used for error detection later,
during auto-initialization and soft reset events. There is no Bus Controller soft reset.
EEPROM location corresponds to
Checksum Type
RAM Address
Overall Checksum
RT1 Checksum
0x004E
0x01C0
0x01E0
0x005C
RT2 Checksum
SMT or IMT Checksum
On the following pages, see the list of registers included in the stored overall and terminal checksums. When the
READY output goes high, EEPROM copy is complete.
6. For terminal devices selected for auto-enable by step 4 unlock word selection, the RT1STEX, RT2STEX, MTENA
and/or BCSTRT bits are set in the 2-byte EEPROM image corresponding to Master Configuration Register 0x0000.
During subsequent auto-initialization events, these are the last bits written, just before READY assertion. Terminal
devices having enable bits set to logic 1 in the EEPROM image are automatically and simultaneously enabled
just before READY assertion. Terminal devices not automatically enabled (by step 4 unlock word selection) have
logic 0 enable bits RT1STEX, RT2STEX, MTENA and/or BCSTRT in the 2-byte EEPROM image corresponding
to Master Configuration Register 0x0000. After auto-initialization, these terminal devices remain in standby until
enabled by host write to the Master Configuration Register 0x0000.
22.2. Overall 32K Word Checksum Used by Auto-Initialization
When auto-initialization is performed, the overall checksum (stored in EEPROM by the EECOPY process) is used
for error checking. EECOPY stored this checksum value in the two 8-bit locations corresponding to RAM address
0x004E. This checksum covers the entire 32K word register and RAM address range from 0 to 0x7FFF, excluding the
following register addresses. At auto-initialization, the following registers are not written using EEPROM data:
Table 19. Registers are not written using EEPROM data
Address
0x0002
0x0007
0x0008
0x0009
0x000A
Excluded Register Name
Master Status & Reset Register
BC Pending Interrupt Register
MT Pending Interrupt Register
RT1 & RT2 Pending Interrupt Register
Interrupt Log Address Pointer
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Address
0x000B
0x000C
0x000D
0x000E
0x0018
0x001E
0x0021
0x0027
0x0030
0x0031
0x0035
0x0036
0x0037
0x003A
0x003B
0x003C
0x0043
0x0044
0x0049
0x004B
Excluded Register Name
RT1 Memory Address Pointer
RT2 Memory Address Pointer
MT Memory Address Pointer
BC Memory Address Pointer
RT1 Operational Status Register
RT1 Built-In Test Word Register
RT2 Operational Status Register
RT2 Built-In Test Word Register
MT Current Address Pointer
MT Last Address Pointer
BC Frame Time Remaining Register
BC Message Time Remaining Register
BC Condition Code Register
MT Time Tag Counter Low
MT Time Tag Counter Mid
MT Time Tag Counter High
BC Time Tag Counter Low
BC Time Tag Counter High
RT1 Time Tag Counter
RT2 Time Tag Counter
The overall checksum includes individual terminal checksums for RT1, RT2 and Bus Monitor, which the EECOPY
process stored at EEPROM locations corresponding to RAM addresses 0x01C0, 0x01E0 and 0x005C respectively. All
checksums stored by the EECOPY process use two’s complement format. Each checksum is calculated by summing
the individual 16-bit data values (ignoring carry) over the full set of included register and RAM addresses. The summa-
tion is then complemented, then incremented (ignoring carry) to yield the stored two’s complement checksum value.
When the device performs checksum-based error checking, a new summation is tallied (ignoring carry) for the indi-
vidual 16-bit data values over the range of included register and RAM addresses. When this summation is added to
the previously stored two’s complement checksum, the result is zero when the new data summation is the same as
that tallied by EECOPY when the checksum was stored.
The registers tallied in each of the RT1, RT2 and SMT or IMT terminal checksums are summarized on the next pages.
These individual checksums are used for error checking during soft reset events. Soft reset occurs for RT1, RT2 or
SMT / IMT when RT1RESET bit 10, RT2RESET bit 11 and/or MTRESET bit 12 is set in the Master Status and Reset
Register 0x0001. One, two or three terminal reset bits can be individually or simultaneously set, without affecting other
on-chip terminals or the Bus Controller. The HI-613x Bus Controller does not have soft reset.
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23. RESET AND INITIALIZATION
This section describes the software reset mechanisms. Hardware Master Reset returns the device to the uninitialized
state, requiring register and RAM initialization before terminal execution can begin. Hardware reset is initiated by
assertion of the MR Master Reset pin (200ns minimum assertion time). Software reset is individually or simultaneously
asserted for the Bus Monitor, RT1 or RT2 by setting the corresponding bit(s) in the Master Status and Reset Register.
The Bus Controller does not have software reset. If AUTOEN is enabled, both hardware and software reset copy
initialization values from EEPROM into registers and RAM.
23.1. Hardware Master Reset and Optional Auto-Initialization
Hardware master reset is initiated by a low to high transition on the MR pin; it should be applied after power-up, but
may be used any time afterward. When asserted, the MR input pin causes immediate unconditional hardware reset for
all device terminals. Command processing is terminated and reset, the bus decoders and encoders are cleared, and
all Time Tag counters are reset. All internal logic is cleared. Registers are restored to the power up reset states shown
in Table 5. The READY, ACTIVE and IRQ output pins are negated if previously asserted. The READY pin remains low
until the entire reset process is complete. During this interval, a host read cycle to any address returns the value of the
Master Status and Reset Register 0x0002.
After a low to high transition on the MR pin, these events occur:
1. After 200ns, input states for the RT1A4-RT1A0, RT1AP and RT1LOCK pins are latched into the RT1 Operational
Status Register 0x0018. Input states for the RT2A4-RT2A0, RT2AP and RT2LOCK pins are latched into the RT2
Operational Status Register 0x0021. The input state for the AUTOEN pin is latched into the Master Status and
Reset Register 0x0002.
2. At master reset, there are four pin-selected combinations for RAM self-test on/off and auto-initialize on/off. For the
4 combinations, hardware MR rising edge to READY assertion times are summarized in the following table.
Table 20. READY delay times: from MR input pin rising edge to READY output pin rising edge
MTSTOFF Pin
State
AUTOEN Pin
State
READY Delay
Combinations
(μs)
No RAM test, No auto-initialize
Perform RAM test, No auto-initialize
No RAM test, auto-initialize
1
0
1
0
0
0
1
1
164
1480
63,100
64,400
Perform RAM test, auto-initialize
If memory error occurs, the BMTF bits are set in the RT1 BIT Word and RT2 BIT Word registers. If the MTSTOFF
pin is logic 1, the RAM test is bypassed. This option might be chosen if a faster reset process is needed. Regard-
less of the MTSTOFF pin state, all RAM locations above address 0x004F are reset to 0x0000.
3. After internal processes are initialized, the device checks the state of the AUTOEN bit latched into the Master
Status and Reset Register 0x0002 at step 1:
If the AUTOEN bit in the Master Status and Reset Register 0x0002 is logic 0, auto initialization from EEPROM is
bypassed. After the RAM memory test is complete, the device asserts the READY output pin to indicate that the device
is ready for host initialization of registers and RAM:
•
•
The Master Configuration Register 0x0000 is initialized to indicate which terminal devices are enabled (BCENA,
RT1ENA and RT2ENA). The corresponding input pins must already be logic 1, or these register bits cannot be
set. If using Bus Monitor, the MTRUN input pin should be logic 1 but the corresponding MTENA register bit should
remain logic 0 until initialization is completed. Likewise, the BCSTART, RT1STEX and RT2STEX bits remain low
at this time.
Other configuration registers are initialized by the host to define interrupt behavior and time tag counter behavior
for enabled terminal devices.
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•
If using RT1 and/or RT2, the following registers are initialized: the RT Configuration Register(s), the RT Descrip-
tor Table Base Address Register(s), the RT Bus A/B Select Register(s) and the RT Interrupt Enable Register. In
RAM, the RT Illegalization Table(s) and RT Descriptor Table(s) are initialized. Initial data for assigned Transmit
Subaddress Data Buffers may be initialized at this time.
•
•
•
If using the Bus Controller, the BC Configuration, BC Instruction List Start Address and BC Interrupt Enable Reg-
isters are initialized. In RAM, the BC Instruction List and BC Message Control Blocks are initialized.
If using a Simple Bus Monitor, the MT Configuration, SMT Address List Start Address and SMT Interrupt Enable
registers are initialized. In RAM, the SMT Address List and SMT Filter Table are initialized.
If using an IRIG-106 Bus Monitor (IMT), the following registers are initialized: the IMT Configuration register, the
IMT Address List Start Address Register, the IMT Packet Max Message Count Register, the IMT Packet Max
Word Count Register, the IMT Max Packet Time Register, the IMT Max Gap Time Register, the IMT Channel ID
Register and the IMT Interrupt Enable Register. In RAM, the IMT Address List and IMT Filter Table are initialized.
•
Upon completing all initialization for registers and RAM, the host writes the Master Configuration Register 0x0000
to start operation for the enabled terminal devices. A combination of BCSTART, RT1STEX, RT2STEX and/or
MTENA register bits are asserted to match the subset of initialized terminal devices (BC, RT1, RT2 and MT).
Device operation begins.
If the AUTOEN bit in the Master Status and Reset Register 0x0002 is logic 1, auto initialization from EEPROM is
performed after completion of the RAM memory test. The READY output pin remains at logic 0 during the self-initial-
ization process. Initialization data is read from the previously-written external EEPROM and copied to the entire range
of registers and RAM, from address 0x0000 to address 0x7FFF. This process typically requires 63 ms (see Table 20).
During auto initialization, the written value for each register or RAM location is read back for confirmation. If the value
read fails to match the corresponding value in EEPROM, an initialization error is saved. This error results in action
taken later when the initialization process is finished.
While performing initialization a running checksum is tallied. A properly-configured serial EEPROM contains a 16-bit
checksum value stored at the EEPROM byte pair locations corresponding to RAM address 0x004E. The stored check-
sum is tallied as if RAM address 0x004E equals zero, and twenty-five register locations listed in Table 19 are also
excluded from the stored checksum value. The stored value is actually the twos complement of the 16-bit memory
checksum, (CHECKSUM + 1). As each individual register and RAM location is initialized, its written value is added to a
copy of the stored checksum value from EEPROM. If all locations match at the end, the running checksum tally added
to the twos complemented EEPROM checksum should equal zero.
After initialization, when READY is asserted, the 16-bit twos complement checksum value is copied from EEPROM to
device RAM address 0x004E.
If an initialization error occurred, the following events take place immediately after READY assertion:
•
•
the IRQ interrupt output pin is asserted.
The Master Status and Reset Register 0x0001 is written to indicate type of error. If checksum failure, the EECKF
register bit is asserted. If data mismatch between EEPROM and read back RAM value, the RAMIF register bit
is asserted.
•
•
The EELF bit is asserted in the RT1 Built-In Test Word Register and in the RT2 Built-In Test Word Register.
If RAMIF read back error occurred, the address of the first occurring instance is written to register address
0x0024. See Section “23.2. Memory Test Fail Address Register (0x0024)” on page 221 for further information.
Additional locations beyond the saved address may have mismatch, but only the first instance is logged.
After copying the full range of register and RAM addresses, the RT1STEX, RT2STEX and MTENA bits in the Master
Configuration Register 0x0000 are still zero. In the same register, the BCSTART bit always reads zero, but the BCAC-
TIVE bit in the Master Status and Reset Register 0x0001 is still zero.
The EEPROM is written using methods described in Section 22.1. Each of the four terminal devices can indepen-
dently be configured to self-start when error-free auto-initialization is complete, or not self-start, requiring a host write
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to the Master Configuration Register after READY assertion. In the EEPROM byte pair corresponding to Master Con-
figuration Register 0x0000:
•
•
•
If the EEPROM RT1STEX and RT1ENA bits are both logic 1, and if the RT1ENA pin is also high, and if the
RT1APF bit is logic 0 in the RT1 Operational Status Register, Remote Terminal 1 will automatically start just be-
fore READY assertion. Once RT1 is started, the Master Configuration Register RT1STEX bit will read logic 1. If
the EEPROM RT1STEX bit is logic 0, the host must write the Master Configuration Register RT1STEX bit high
after READY assertion to start Remote Terminal 1. The RT1ENA register bit and input pin must both be logic 1
before RT1STEX assertion.
If the EEPROM RT2STEX and RT2ENA bits are both logic 1, and if the RT2ENA pin is also high, and if the
RT2APF bit is logic 0 in the RT2 Operational Status Register, Remote Terminal 2 will automatically start just be-
fore READY assertion. Once RT2 is started, the Master Configuration Register RT2STEX bit will read logic 1. If
the EEPROM RT2STEX bit is logic 0, the host must write the Master Configuration Register RT2STEX bit high
after READY assertion to start Remote Terminal 2. The RT2ENA register bit and input pin must both be logic 1
before RT2STEX assertion.
If the EEPROM BCTRIG bit is logic 1, and if the BCENA input pin is also high, the Bus Controller will automati-
cally start just before READY assertion. Once the BC is started, the Master Configuration Register BCTRIG and
BCSTART bits will continue to read logic zero, but the BCACTIVE bit in the Master Status and Reset Register
0x0001 will read logic 1. If the EEPROM BCTRIG bit is logic 0, the host must assert the Master Configuration
Register BCSTART bit after READY assertion to start the Bus Controller. The BCENA input pin must be logic one
before BCSTART assertion. The BCSTART register bit self-resets, but the BCACTIVE bit in the Master Status
and Reset Register 0x0001 will read logic 1.
•
If the EEPROM MTENA bit is logic 1, and if the MTRUN input pin is also high, the Bus Monitor will automatically
start just before READY assertion. Once the Bus Monitor is started, the Master Configuration Register MTENA
will read logic 1. If the EEPROM MTENA bit is logic 0, the host must write the Master Configuration Register
MTENA bit high after READY assertion to start the Bus Monitor. The MTRUN input pin must be logic 1 before
MTENA assertion.
Note that automatic-self-start for RT1 and RT2 requires the corresponding RTAPF status bit to be logic 0 in the RT
Operational Status Register. This indicates valid odd parity for the terminal address and parity bits latched
in the RT Operational Status Register, not necessarily the state of the RT address and parity pins. Because
auto-initialization follows master reset, the mirrored pin states latched at reset is overwritten by EEPROM values if
RTxLOCK input pin is logic 0.
•
When the RT1LOCK or RT2LOCK input pin is logic 1 at Master Reset rising edge, the corresponding RT
Operational Status Register terminal address and parity bits reflect address input pin states 200ns after reset
rising edge.
•
When the RT1LOCK or RT2LOCK input pin is logic 0 at Master Reset rising edge, the latched RT address,
parity and RTxLOCK bit values are overwritten by values from the initialization EEPROM.
If automatic-self-start for RT1 or RT2 was blocked due to invalid odd parity for the terminal address and parity bits
latched in the RT Operational Status Register, the RT1STEX or RT2STEX bit cannot be asserted in the Master Config-
uration Register until the parity error is corrected. The host may overwrite the RT1 or RT2 Operational Status Register
to correct the parity error, then assert RT1STEX or RT2STEX in the Master Configuration Register.
If automatic-self-start for terminal devices was blocked due to RAMIF or EECKF auto-initialization errors, the host can
override the error condition after READY assertion by setting the RT1STEX, RT2STEX, BCSTART and/or MTENA
bits in the Master Configuration Register, providing the other operational conditions (in the 4-bullet list above) are met.
A method for programming the initialization EEPROM from a fully configured terminal is explained in Section 22. If a
different method is used for writing the serial EEPROM, for successful self-initialization after Master Reset, the twos-
complemented checksum (described earlier) must be saved in EEPROM locations corresponding to device RAM ad-
dress 0x004E.
If a different method is used for writing the serial EEPROM, in order to perform soft resets, twos-complement checksum
must be written for Remote Terminal 1 at 0x01C0, Remote Terminal 2 at 0x01E0 and the Monitor Terminal at 0x005C.
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A compatible serial EEPROM uses a SPI interface for byte-access read and write operations. Sixteen-bit register and
RAM values in the HI-613X are stored as upper and lower bytes in the EEPROM, in “big endian” fashion. For example,
the upper byte for register address 0x0000 is stored at EEPROM address 0x0000 while the lower byte is stored at
EEPROM address 0x0001. A 64K x 8 EEPROM is required to store the entire 32K x 16 address range.
Serial EEPROM data mapping follows the device memory map shown in Figure 2. The four exceptions:
1. the two EEPROM bytes corresponding to device RAM address 0x004E must contain the expected overall check-
sum value and if software resets are expected
2. the two EEPROM bytes corresponding to device RAM address 0x01C0 must contain the expected terminal check-
sum value for Remote Terminal 1
3. the two EEPROM bytes corresponding to device RAM address 0x01E0 must contain the expected terminal check-
sum value for Remote Terminal 2
4. the two EEPROM bytes corresponding to device RAM address 0x005C must contain the expected terminal check-
sum value for the Bus Monitor.
The serial EEPROM used for auto-initialization should be fully written to cover the HI-6130/31 upper address limit of
0x7FFF. Ideally the EEPROM image reflects a post-MR reset followed by fresh initialization by the host, with nothing
written to reset-cleared registers or RAM as a result of command processing.
23.2. Memory Test Fail Address Register (0x0024)
MSB
0
Memory Test Fail Address Register
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
2
0
1
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
9
8
7
6
5
4
0
If the AUTOEN input pin is logic 1, auto-initialization from EEPROM is enabled. When one or more initialized RAM
locations do not match their two corresponding serial EEPROM byte locations, RAMIF bit 13 is set in the Hardware
Pending Interrupt Register 0x0006, as well as RAMIF bit 0 in the Master Status and Reset Register 0x0001. Such
failure may occur during auto initialization, or execution of a partial reset caused by assertion of the RT1RESET,
RT2RESET or MTRESET bits in the Master Status and Reset Register, 0x0001. The address of the first occurring
RAM/EEPROM mismatch is written to the Memory Test Fail Address Register, 0x0024. Additional locations beyond the
saved address may have mismatch, but just the first instance is logged and the test stops.
Once terminal operation starts, register 0x0024 reverts to its normal function, the RT2 Current Message Info Word
Register, if terminal RT2 is enabled.
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23.3. Software Reset
23.3.1. Remote Terminal 1 (RT1)
This is initiated when RT1RESET bit 10 is set in the Master Status and Reset Register 0x0001. The following actions
are performed.
Table 21. RT1 Soft Reset Summary
Action
Registers Affected
0x0000 Master Configuration Register, RT1STEX bit 4
0x0006 Hardware Pending Int Register, RTIP bit 2
0x0006 Hardware Pending Int Register, RT1APF bit 3
0x0009 RT1 and RT2 Pending Int Register, RT1 int bits 8 – 3
0x0018 RT1 Operational Status Register
Clears these individual register bits
0x001A RT1 MIL-STD-1553 Status Word Bits Register
0x001E RT1 Built-In Test Word Register
Clears these entire register addresses
0x0049 RT1 Time Tag Counter
0x000F Hardware Interrupt Enable Register
0x0012 RT1 & RT2 Interrupt Enable Register (see note)
0x0013 Hardware Interrupt Output Enable Register
0x0016 RT1 & RT2 Interrupt Output Enable Register (see note)
0x0017 RT1 Configuration Register
Loads these registers from EEPROM
0x0019 RT1 Descriptor Table Base Address Register
0x001C RT1 Bus A Select Register
These 522 locations comprise the RT1
Terminal Checksum stored at 0x01C0 by
EECOPY process
0x001D RT1 Bus B Select Register
0x001F RT1 Alternate BIT Word Register
0x004A RT1 Time Tag Utility Register
0x0200 through 0x02FF: RT1 Illegalization Table
0x0400 through 0x05FF: RT1 Descriptor Table
Note: This register reload potentially affects both RTs.
RT1 automatically starts (RT1STEX is set in register 0x0000) after soft reset completion, if these requirements are
met:
•
•
The RT1ENA pin is logic 1 during the soft reset event
The RT1ENA pin and RT1ENA bit 6 were both logic 1 in the Master Configuration Register when EECOPY
created the EEPROM image.
•
The RT1STEX bit 4 is logic 1 in the EEPROM Master Configuration Register image because the EECOPY unlock
codes during programming were Unlock Word 1 = 1010-XXXX-XX11-1010 and Unlock Word 2 = 0101-XXXX-
XX00-0101 where X denotes “don’t care”.
To manually start RT1 after soft reset completion (indicated by READY signal assertion), the host must set RT1STEX
bit 4 in register 0x0000, if RT1 auto-start was disabled or otherwise failed for one or more of these reasons:
•
•
The RT1ENA pin was logic 0 during the soft reset event.
The RT1ENA pin was logic 0 and/or RT1ENA bit 6 was logic 0 in the Master Configuration Register when
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EECOPY created the EEPROM image. A new EEPROM image is needed to allow auto-start after RT1 soft reset.
•
The RT1STEX bit 4 is logic 0 in the EEPROM Master Configuration Register image because the unlock codes
used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after RT1 soft reset.
23.3.2. Remote Terminal 2 (RT2)
This is initiated when RT2RESET bit 11 is set in the Master Status and Reset Register 0x0001. The following actions
are performed.
Table 22. RT2 Soft Reset Summary
Action
Registers Affected
0x0000 Master Configuration Register, RT2STEX bit 3
0x0006 Hardware Pending Int Register, RTIP bit 2
0x0006 Hardware Pending Int Register, RT2APF bit 4
0x0009 RT1 and RT2 Pending Int Register, RT2 int bits 15 – 10
0x0021 RT2 Operational Status Register
Clears these individual register bits
0x0023 RT2 MIL-STD-1553 Status Word Bits Register
0x0027 RT2 Built-In Test Word Register
Clears these entire register addresses
0x004B RT2 Time Tag Counter
0x000F Hardware Interrupt Enable Register
0x0012 RT1 & RT2 Interrupt Enable Register (see note)
0x0013 Hardware Interrupt Output Enable Register
0x0016 RT1 & RT2 Interrupt Output Enable Register (see note)
0x0020 RT2 Configuration Register
Loads these registers from EEPROM
0x0022 RT2 Descriptor Table Base Address Register
0x0025 RT2 Bus A Select Register
These 522 locations comprise the RT2
Terminal Checksum stored at 0x01E0 by
EECOPY process
0x0026 RT2 Bus B Select Register
0x0028 RT2 Alternate BIT Word Register
0x004C RT2 Time Tag Utility Register
0x0300 through 0x03FF: RT2 Illegalization Table
0x0600 through 0x07FF: RT2 Descriptor Table
Note: This register reload potentially affects both RTs.
RT2 automatically starts (RT2STEX is set in register 0x0000) after soft reset completion, if these requirements are
met:
•
•
The RT2ENA pin is logic 1 during the soft reset event
The RT2ENA pin and RT2ENA bit 7 were both logic 1 in the Master Configuration Register when EECOPY
created the EEPROM image.
•
The RT2STEX bit 5 is logic 1 in the EEPROM Master Configuration Register image because the EECOPY unlock
codes during programming were Unlock Word 1 = 1010-XXXX-11XX-1010 and Unlock Word 2 = 0101-XXXX-
00XX-0101 where X denotes “don’t care”.
To manually start RT2 after soft reset completion (indicated by READY signal assertion), the host must set RT2STEX
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HI-6130, HI-6131
bit 5 in register 0x0000, if RT1 auto-start was disabled or otherwise failed for one or more of these reasons:
•
•
The RT2ENA pin was logic 0 during the soft reset event
The RT2ENA pin was logic 0 and/or RT2ENA bit 7 was logic 0 in the Master Configuration Register when
EECOPY created the EEPROM image. A new EEPROM image is needed to allow auto-start after RT2 soft reset.
•
The RT2STEX bit 5 is logic 0 in the EEPROM Master Configuration Register image because the unlock codes
used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after RT2 soft reset.
23.3.3. Bus Monitor SMT / IMT
This is initiated when MTRESET bit 12 is set in the Master Status and Reset Register 0x0001. The following actions
are performed.
Table 23. SMT / IMT Soft Reset Summary
Action
Registers Affected
0x0000 Master Configuration Register, MTENA bit 8
0x0006 Hardware Pending Int Register, MTIP bit 1
0x0008 MT Pending Interrupt Register
Clears these individual register bits
0x0030 MT Next Message Buffer Address Pointer
0x0031 MT Last Message Buffer Address Pointer
0x003A MT Time Tag Counter, Low
Clears these entire register addresses
0x003B MT Time Tag Counter, Mid
0x003C MT Time Tag Counter, High
0x000F Hardware Interrupt Enable Register
0x0011 MT Interrupt Enable Register
0x0013 Hardware Interrupt Output Enable Register
0x0015 MT Interrupt Output Enable Register
0x0029 MT Configuration Register
0x002A IMT Packet Maximum Message Count Register
0x002B IMT Packet Maximum MIL-STD-1553 Word Count Register
0x002C IMT Packet Maximum Time Register
0x002D IMT Packet Maximum Gap Time Register
0x002E IMT Packet Channel ID Register
Loads these registers from EEPROM
These 561 locations comprise the MT
Terminal Checksum stored at 0x005C by
EECOPY process
0x002F MT Buffer Address Table Start Address Register
0x003D MT Time Tag Utility Register, Low
0x003E MT Time Tag Utility Register, Mid
0x003F MT Time Tag Utility Register, High
0x0040 MT Time Tag Match Register, Low
0x0041 MT Time Tag Match Register, Mid
0x0042 MT Time Tag Match Register, High
0x00B0 through 0x00BF: MT Buffer Address Table(s)
0x0100 through 0x017F: MT Message Filter Table
Note: Soft reset for the Bus Monitor re-initializes the buffer address pointers, but does not clear the allocated buffer
space in the buffer(s).
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The Bus Monitor automatically starts (MTENA is set in register 0x0000) after soft reset completion, if the following
requirements are met. Message recording commences when a new valid command is received:
•
•
•
The MTRUN pin is logic 1 during the soft reset event
The MTRUN pin was logic 1 in the Master Configuration Register when EECOPY created the EEPROM image.
The MTENA bit 12 is logic 1 in the EEPROM Master Configuration Register image because EECOPY used these
unlock codes during EEPROM programming: Unlock Word 1 = 1010-XX11-XXXX-1010 and Unlock Word 2 =
0101-XX00-XXXX-0101 where X denotes “don’t care”.
To manually start the Bus Monitor after soft reset completion (indicated by READY signal assertion), the host must
set MTENA bit 12 in register 0x0000, if auto-start was disabled or otherwise failed for one or more of these reasons:
•
•
The MTRUN pin was logic 0 during the soft reset event
The MTRUN pin was logic 0 in the Master Configuration Register when EECOPY created the EEPROM image.
A new EEPROM image is needed to allow auto-start after MT soft reset.
•
The MTENA bit 12 is logic 0 in the EEPROM Master Configuration Register image because the unlock codes
used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after Bus Monitor soft reset.
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24. SELF-TEST
The HI-613x provides several host-directed RAM self-tests, as well as an automatic (but optional) RAM self-test
performed after Master Reset. In addition, on-line analog and off-line digital transmit/receive loopback tests are
provided, with different options for BC and RT terminal modes.
24.1. Optional RAM Self-Test after Hardware Master Reset
When the MTSTOFF input pin is logic 0, the HI-613x device automatically performs RAM self-test after each hardware
master reset, following the rising edge of MR input signal. See Section “23.1. Hardware Master Reset and Optional
Auto-Initialization”. The READY output pin goes low at MR assertion. READY remains low after MR rising edge and
during RAM self-test. The RAM self-test performed is the increment/decrement (Inc/Dec) method described on page
231. When successful RAM self-test is complete, the READY output pin goes high, indicating that device registers
and RAM can be configured for operation. The entire RAM address space from 0x0050 to 0x7FFF is cleared to
0x0000. RAM self-test after hardware master reset is optional. If the MTSTOFF input pin is logic 1, RAM testing is
skipped, speeding up READY assertion. Table 20 on page 218 shows the reset timing options.
24.2. Host-Directed Self-Test
The HI-613x device supports host-directed RAM self-test (sometimes called RAM built-in self-test, or RAM BIST)
and single-word transmit/receive loopback, which may be off-line digital or on-line analog. Host-directed self-test is
configured and operated using register read/write operations.
The host initiates self-test mode by asserting the TEST input pin to logic 1. When the TEST pin is high, four registers
are active for performing RAM self-test or RT mode loopback self-tests:
24.2.1. Self-Test Control Register (0x0028)
FRAMRABFFRABILSERLB2SERLB1SERL0BSTRRBTPARSBSFANILot UNseodt ULsBeAdLOLBGSYLNBCBUSLBESLTALRBPTASLBSFAIL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR Reset
RW
15 14 13 12 11 10
R
RW
R
Host Access
Bit
9
8
7
6
5
4
3
2
1
0
The function of this register is multiplexed by the device TEST input pin. When the TEST pin is logic 0 (normal
operating mode) and the RT2ENA input pin is logic 1, register address 0x0028 functions as the RT2 Alternate BIT
Word Register described in Section 18.11 on page 155.
When the TEST input pin is logic 1, register address 0x0028 functions as the Self-Test Control Register, a Read-Write
register used for RAM memory testing, or analog or digital loopback tests. Bits 0, 1, 8, 9 are Read-Only. The remaining
bits in this register are Read-Write.
After test completion, the TEST input pin should be reset to logic 0, restoring all register bits to Read-Write. If using
remote terminal RT2, the host should restore the desired alternate BIT Word value for RT2 at register address 0x0028.
Descriptions below apply when the TEST input pin is logic 1; the register is operating as the Self-Test Control Register.
This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self test (RAM BIST). Register
bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback).
Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal RAM
memory after every MR pin master reset, unless the MTSTOFF input pin is logic 1. This option may be used to speed
up reset completion. Self-Test Control Register bits 15 - 8 provide a means for the host to perform RAM self-test at
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other times. Register bits 13:11 select RAM test type. Then bit 10 assertion starts the selected RAM test, and bits 9-8
report a pass/fail result after test completion. All tests are destructive, overwriting data present before test commence-
ment.
NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset.
Bit No. Mnemonic R/W Reset Function
Full RAM Access Enable.
During normal operation, some bits in certain RAM locations (e.g., Descrip-
15
14
FRAMA
R/W
R/W
0
0
tor Table Control Words) cannot be written by the host. When the FRAMA
bit is asserted, host writes to RAM are unrestricted to permit full testing.
During normal completion, this bit must be reset to logic 0.
RAM BIST Force Failure.
RBFFAIL
When this bit is asserted, RAM test failure is forced to verify that RAM BIST
logic is functional.
RAM BIST Select Bits 2-0.
This 3-bit field selects the RAM BIST test mode applied when the RB-
START bit is set:
Test
RBSEL2:0 Selected RAM Test
Time
000
001
Idle
-
Pattern Test, described below
14.42ms
Write 0x0000 to RAM address range 0x0000 -
0x7FFF
010
011
100
101
170μs
500μs
170μs
500μs
13,12,11 RBSEL2:0 R/W
0
Read and verify 0x0000 over RAM address range
0x0000 - 0x7FFF
Write 0xFFFF to RAM address range 0x0000 -
0x7FFF
Read and verify 0xFFFF over RAM address range
0x0000 - 0x7FFF
Inc / Dec Test performs only steps 5 - 8 of the Pat-
tern Test below
110
111
1.32ms
-
Idle
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Bit No. Mnemonic R/W Reset Function
Description of the RAM BIST “PATTERN” test selected when register
bits
RBSEL2:0 = 001:
Note: Test read /write accesses to addresses 0x0000 - 0x0050 involve 81
RAM locations not accessible to the host. These accesses do not affect the
host-accessible registers, overlaying the same address range.
1. Write 0x0000 to all RAM locations, 0x0000 through 0x7FFF.
2. Repeat the following sequence for each RAM location from 0x00000
through 0x7FFF:
a.
b.
c.
d.
e.
f.
g.
h.
i.
Read and verify 0x0000
Write then read and verify 0x5555
Write then read and verify 0xAAAA
Write then read and verify 0x3333
Write then read and verify 0xCCCC
Write then read and verify 0x0F0F
Write then read and verify 0xF0F0
Write then read and verify 0x00FF
Write then read and verify 0xFF00
Write 0x0000 then increment RAM address and go to step (a)
j.
13,12,11 RBSEL2:0 R/W
(continued)
0
3. Write 0xFFFF to all RAM locations, 0x0000 through 0x7FFF
4. Repeat the following sequence for each RAM location from 0x00000
through 0x7FFF:
a.
b.
c.
d.
e.
f.
g.
h.
i.
Read and verify 0xFFFF
Write then read and verify 0x5555
Write then read and verify 0xAAAA
Write then read and verify 0x3333
Write then read and verify 0xCCCC
Write then read and verify 0x0F0F
Write then read and verify 0xF0F0
Write then read and verify 0x00FF
Write then read and verify 0xFF00
Write 0xFFFFthen increment RAM address and go to step (a)
j.
5. Write each cell’s memory address into each RAM location from 0x00020
to 0x7FFF.
6. Read each memory location from 0x00000 to 0x7FFF and verify it con-
tains its address.
7. Write 1s complement of each cell’s memory address, into each RAM
location (same addr range).
8. Read each memory location and verify it contains the 1s complement of
its address.
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register
bits RBSEL2:0. The RBSTRT bit can only be set if the TEST input pin
is high and if register bit 15 is already asserted. This bit is automatically
cleared upon test completion. Register bits 9-8 indicate pass / fail test
result.
10
RBSTRT
R/W
0
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Bit No. Mnemonic R/W Reset Function
RAM BIST Pass.
9
RBPASS
R
0
Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when RBSTRT bit 10 is set.
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the
selected RAM test. This bit is automatically cleared when RBSTRT bit 10
is set. When BIST failure occurs, a clue to the failing RAM address can be
read at register address 0x001B. For speed, the RAM BIST concurrently
tests 4 quadrants of the RAM address range, in parallel. If test failure
occurs, register address 0x001B contains the RAM address being tested
in the lowest RAM quadrant. Actual failure has occurred in any of these
four locations: at RAM address “ADDR” stored in register 0x001B, or
ADDR+0x2000, or ADDR+0x4000 or ADDR+0x6000. When the TEST input
pin is logic 0, register address 0x001B function reverts to the read-only RT1
Current Message Information Word Register described in Section 18.7 on
page 152.
8
RBFAIL
R
0
7,6
5
-----
R
0
0
Not Used. These bits cannot be set. A READ will return 0-0.
Loopback Test Analog.
The device supports either digital or analog loopback testing for either bus
transceiver. When the LBALOG bit is low, digital loopback is selected and
no data is transmitted onto the selected external MIL-STD-1553 bus. When
the LBALOG bit is high, analog loopback is selected and a test word is
transmitted onto and received from the selected external MIL-STD-1553
bus.
LBALOG
R/W
Loopback Test Word Sync Select.
When the LBSYNC bit is high, the loopback test word is transmitted with
command sync. When the LBSYNC bit is low, the loopback test word is
transmitted with data sync.
4
3
LBSYNC
R/W
R/W
0
0
Loopback Test Bus Select.
LBBUSEL
When this bit is low, loopback testing occurs on Bus A. When this bit is
high, loopback testing occurs on Bus B.
Loopback Test Start.
Writing logic 1 to this bit initiates the loopback test selected by register bits
3, 4 and 5. The LBSTRT bit can only be set if the external TEST pin is al-
ready asserted, and is automatically cleared upon test completion. Register
bits 1,0 indicate pass / fail test result.
2
1
0
LBSTART
LBPASS
LBFAIL
R/W
R
0
0
0
Loopback Test Pass.
Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when LBSTART bit 2 is set.
Loopback Test Fail.
Device logic asserts this bit when failure occurs while performing the
selected loopback test. Failure is comprised of Manchester encoding error,
parity error, wrong sync type or data mismatch. This bit is automatically
cleared when LBSTART bit 2 is set.
R
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24.2.2. Loopback Test Transmit Data Register (0x001F)
MSB
Loopback Test Transmit Data Register
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
This register is cleared after MR pin master reset, but is not affected by SRST software reset. The function
of this register is multiplexed by the device TEST input pin. When TEST is logic 0 (normal operating mode) and the
RT1ENA input pin is logic 1, register address 0x001F is the RT1 Alternate BIT Word Register described in Section
18.11 on page 155.
When the TEST input pin is logic 1, register address 0x001F becomes the Loopback Test Transmit Data Register,
a Read-Write register used for analog or digital loopback tests. When a loopback test is performed, the value in this
register is transmitted, and should appear in the Loopback Test Receive Data Register 0x0002. See Section “24.2.1.
Self-Test Control Register (0x0028)” on page 226 (bits 0-5) for additional information.
After test completion, the TEST input pin should be reset to logic 0. If using remote terminal RT1, the host should
restore the desired alternate BIT Word value for RT1 at register address 0x001F.
24.2.3. Loopback Test Receive Data Register (0x0002)
MSB
Loopback Test Receive Data Register
LSB
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
MR Reset
Host Access
Bit
R
15 14 13 12 11 10
0
This register is cleared after MR pin master reset, but is not affected by SRST software reset. The function of
this register is multiplexed by the device TEST input pin. When the TEST input pin is logic 0 (normal operating mode)
and the RT1ENA input pin is logic 1, register address 0x0002 is the RT1 Current Command Register described in
Section 18.3 on page 150.
When the TEST input pin is logic 1, register address 0x0002 becomes the Loopback Test Receive Data Register, a
read-only register used for analog or digital loopback tests. When loop back is performed, the value in the Loopback
Test Transmit Data Register 0x001F is transmitted and should appear in this register. See Section “24.2.1. Self-Test
Control Register (0x0028)” on page 226 (bits 0-5) for additional information.
After test completion, the TEST input pin should be reset to logic 0, reverting this register address 0x0002 to the read-
only RT1 Current Command Register. The contained register value will not have meaning until RT1 receives its next
valid command.
24.2.4. RAM Self-Test Fail Address Register (0x001B)
MSB
RAM BIST Fail Address Register
LSB
0
0
0
0
0
0
0
9
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
MR Reset
Host Access
Bit
RW
15 14 13 12 11 10
8
0
Upon test completion, Self-Test Control Register bit 9 (see Section “24.2.1. Self-Test Control Register (0x0028)” on
page 226) is set if the test passed, otherwise bit 8 is set if the test failed. If failure occurs, the first failed RAM address
is written to the RAM BIST Fail Address Register. (This is actually an offset value within a memory quadrant; see the
Self-Test Control Register bit 8 description.) Memory test fail also asserts the BTMF (BIST Memory Test Fail) bit 3 in
both RT1 and RT2 BIT Word Registers, at addresses 0x001E and 0x0027 respectively.
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HI-6130, HI-6131
At test completion, the host should clear the Self-Test Control Register 0x0028, and then reset the TEST input pin to
logic 0.
24.2.5. Host-Directed RAM Self-Test
Host-directed RAM self-test overwrites preexisting RAM contents and should only be performed when complete re-
configuration of the RAM address space will occur after RAM test completion. If the device is operational, terminal
execution should be stopped. If asserted, reset bits 4-8 and bit 12 in “9.1. Master Configuration Register (0x0000)”,
stopping BC, MT, and RT1-2. Or, reset the BCENA, RT1ENA, RT2ENA and MTRUN input pins, if asserted. Assert the
TEST pin to activate register 0x0028 as the Self-Test Control Register.
After asserting the TEST input pin, RAM self-test is configured and started by writing bits 15:10 in the Self-Test Control
Register, described on page 226. Register bits 13:11 select one of the five test protocols. Register bit 15 is usually set
to provide unrestricted RAM read/write access. Register bit 10 is then asserted to start the RAM test selected by bits
13:11. All of these bits may be written simultaneously, and bits 7:0 should be written as zeros. Test time varies based
on complexity; test times are shown in the Self-Test Control Register description.
Upon RAM test completion, Self-Test Control Register bit 9 is set if the RAM test was successful, otherwise bit 8 is
set if the test failed. If failure occurs, the first failed RAM address is written to the RAM Self-Test Fail Address Register
0x001B. The written value is actually an offset value within a memory quadrant; see the data sheet description for
Self-Test Control Register, bit 8. Memory test fail also asserts the BTMF (BIST Memory Test Fail) bit 3 in the BIT Word
Register 0x0014.
At RAM test completion, the host should clear the Self-Test Control Register 0x0028, reset the TEST input pin to logic
0, then re-initialize registers and RAM, and finally restart terminal execution.
24.2.6. Host-Directed RT-Mode Loopback Testing (On-Line Analog or Off-Line Digital)
RT mode loopback testing involves transmission and reception of a single Manchester-encoded word with correct parity.
On-line Analog Loopback transmits the specified test word onto the external MIL-STD-1553 bus. The internal receiver
for the same bus is totally independent from the encoder logic used for bus transmission. The bus receiver detects
and decodes the received replica of the transceiver’s own transmission. Off-line Digital Loopback does not disturb the
selected MIL-STD-1553 bus; the digital signal paths used for encoding and transmission (as well as reception and
decoding) are fully tested without involving the external MIL-STD-1553 bus; only the analog bus driver and analog
receiver are bypassed for digital loopback tests. The HI-613x cannot be configured for loopback transmitting on one
bus and receiving on the other bus.
RT mode loopback testing requires one or both RTs to be enabled. If RT1 is not already running, assert the RT1ENA
pin and set the RT1ENA bit in “9.1. Master Configuration Register (0x0000)”. Then set the RT1STEX bit in register
0x0000. RT2 can similarly be enabled, if desired. Then initiate test mode by asserting the TEST input pin to logic 1.
Write a 16-bit transmit value to the Loopback Test Transmit Data Register 0x001F. With the TEST input set to logic
1, the host can write bits 5:3 in the Self-Test Control Register 0x0028 to select analog or digital loopback, command
sync or data sync, and select test Bus A or Bus B. Then, without modifying bits 5:3, write the Self-Test Control Register
again to set bit 2, starting loopback test. Note: Self-Test Control Register bits 5:2 can be written simultaneously; the
remaining register bits 15:6 and 1:0 should all be written as zeros.
After 20μs or so, RT loopback transmission is complete. Self-Test Control Register bit 1 is set for successful loopback
test, otherwise bit 0 is set if loopback failed. The received word has been written into the Loopback Test Receive Data
Register 0x0002. It should match the value in the Loopback Test Transmit Data Register 0x001F. Test failure also
asserts either the LBFA (Loopback Fail A) bit 5 or LBFB (Loopback Fail B) bit 4 in the Built-In Test Word Register,
0x0014.
At RT loopback test completion, the host should clear Self-Test Control Register 0x0028, and then reset the TEST
input pin to logic 0.
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HI-6130, HI-6131
24.2.7. Programmed BC-Mode Digital Loopback Testing (Off-Line)
For any BC message block, off-line digital loopback self-test can be programmed. The TEST input pin should be logic
0, normal operational state. BC transmission onto the 1553 bus is inhibited for the message, but the digital transmit
encoding and receive decoding signal paths can be checked.
The BC Instruction List in RAM comprises a series of 2-word entries, an instruction Op Code Word followed by a
Parameter Word. While sequencing through the Instruction List, the BC control logic fetches and executes conditional
and unconditional instruction op codes referenced by the BC Instruction List Pointer 0x0034. For executable messages,
the Parameter Word following the Op Code Word contains the starting address of a Message Control/Status Block.
As described in Section “10.4. Bus Controller Message Control / Status Blocks” on page 63, each Message Control/
Status Block begins with a BC Control Word. When Control Word SELFTST bit 6 is set, off-line self-test is enabled,
inhibiting transmission onto the 1553 bus. Instead the output of the bus Manchester II serial encoder is routed directly
to the decoder input for the bus selected by Control Word bit 7 (USEBUSA). A validity check is performed on the
received replica of each transmitted word (sync, encoding, bit count and parity). As received, each word replica is
stored in the Loopback Word location in the Message Control/Status Block. The data value for the final word received
is also checked with the transmitted final word. If any word fails validity check (or if the final word has data mismatch)
test logic sets the LBE (loopback error) bit 8 in the Block Status Word.
After message processing, off-line self-test success or failure can be determined by reading the received Loopback
Word (stored in the Message Control/Status Block if BC is using 16-bit time base) or by reading the LBE (loopback
error) bit 8 in the Block Status Word. (Note: If the BC is using 32-bit time base, the final received loopback word in the
Loopback Word location is overwritten at the end of message post-processing when time tag bits 31:16 are written
there.)
The “BADMSG” BC condition code 0xC is updated based on the outcome of the off-line SELFTST loopback message.
BADMSG is set to logic 1 for Loopback Test error. This permits conditional execution, including jumps or subroutine
calls, based on the outcome of the message having SELFTST asserted in its Control Word.
The BADMSG condition code is also set for Format Error or No Response error, but is not affected by a Status
Set condition. For non-broadcast commands using off-line SELFTST loopback, No Response error always occurs
since the BC message processor expects an RT response. Since BC bus transmission is inhibited, off-line SELFTST
loopback should use broadcast commands. This avoids BADMSG condition codes caused by No Response error.
24.2.8. Continuous BC-Mode Analog Loopback Testing (On-Line)
The BC performs continuous analog loopback on all Bus Controller transmissions when executing normal Message
Control/Status Blocks having off-line SELFTST bit = 0 in each Control Word. The TEST input pin is logic 0, normal
operational state. For each Manchester II word transmitted by the BC, a validity check is performed on the received
replica, checking sync, encoding, bit count and parity. In the Message Control/Status Block, each received word replica
is stored in the Loopback Word location when decoded, overwriting the previous word stored there. The data value for
the final BC word received is also checked for data value. If any word fails validity check (or if the final word has data
mismatch) test logic sets the LBE (loopback error) bit 8 in the Block Status Word. (Note: If the BC is using 32-bit time
base, the final word replica in the Loopback Word location is overwritten at the end of message post-processing when
time tag bits 31:16 are written there.)
The “BADMSG” BC condition code 0xC is updated based on the outcome of continuous BC-mode analog loopback
checking. The BADMSG condition code is set for Loopback Error, Format Error or No Response error, but is not
affected by a Status Set condition. BC analog loopback failure also sets LBE loopback error bit 8 in the Block Status
Word.
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HI-6130, HI-6131
25. HOST INTERFACE
25.1. HI-6130 Host Bus Interface
The HI-6130 uses a parallel bus interface for communications with the host. Host interface to registers and RAM
is enabled through the Chip Enable (CE) pin, and accessed via 16-bit data bus and several host-originated control
signals described below. Timing is identical for register operations and RAM operations via the host bus interface,
but read and write operations have different signal timing. The HI-6130 parallel host bus interface is capable of faster
communication than the HI-6131 Serial Peripheral Interface.
Depending on the chosen microprocessor family, the processor’s hardware bus interface may be described as an
“external bus interface,” “memory interface” or may have a different name. The user can also implement a software
controlled “bit-banged” interface to the HI-6130, at the cost of substantially slower RAM and register read/write times.
The bus interface is compatible with the two prevalent bus control signal methods: “Intel style” interface, characterized
by separate strobes for read and write operations (OE and WE), and “Motorola style” interface, characterized by a
single read/write strobe (STR) and a data direction signal (R/W). Bus control style is selected using the BTYPE con-
figuration pin, which sets the function of two other input pins to serve as either OE and WE, or STR and R/W.
The BWID configuration pin selects either 8- or 16-bit bus widths. When the BWID pin is connected to ground, 8-bit
mode is selected; two bytes are sequentially transferred for each 16-bit word operation. In 8-bit mode only, the BENDI
configuration pin selects bus “endianness.” This is the system attribute that indicates whether integers are represented
with the most significant byte stored at the lowest address (big endian) or at the highest address (little endian). Internal
device storage is “big endian”. For processor compatibility, the BENDI pin sets the order for byte accesses when the
host bus is configured for 8-bit width, that is, when BWID equals 0. When BENDI is low, “little endian” is chosen; the
low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). When BENDI is high, “big endian” is cho-
sen and the high order byte is transacted on the host bus before the low order byte. In 8-bit mode, all transacted data
uses bus data bits 7:0 and bus data bits 15:8 are not used. Further, bus address bit A0 (LB) always equals 0 during
the first byte read/write access, and equals 1 during the second byte access
When the BWID pin is connected high or left unconnected, 16-bit bus width is used. For 16-bit bus operation, the A0
(LB) address pin is not used and the BENDI input pin is “don’t care.”
25.1.1. Bus Wait States and Data Prefetch
The HI-6130 has a WAIT output pin that tells the host to add wait states when additional access time is needed during
bus read cycles. For compatibility with different host processors, the state of the WPOL input pin sets the WAIT output
as active high or active low. The WAIT output can be ignored when the host processor read cycle time is always slow
enough to work with the HI-6130 bus. When using fast host processors, cycle time is sometimes slowed down by
configuring the processor to add one or more wait states during every read or write cycle, but slow-down affects all
cycles, even when unnecessary.
Data prefetch is a technique used by the HI-6130 to speed up host multi-word read access to registers or RAM by
eliminating wait states. Prefetching occurs when HI-6130 logic requests data before it is actually needed. Because
register or RAM locations are often read sequentially, performance improves when data is prefetched in address se-
quence order. For every host read cycle, the device first reads the addressed location, then prefetches the following
address, to speed up access in the likely event that the following word will be read next.
For the HI-6130, WAIT is always asserted for the first word fetched in any read sequence. The first read cycle has a
long access time because there is no prefetch. This may be the first byte read in 8-bit mode, or the first word read in
16-bit mode. After each word (or byte) is fetched for a read operation, the next word (or byte) is prefetched to speed-up
the read cycle time when sequential address read sequences occur. After the first word read, the following words read
in sequence are accessed without WAIT, resulting in faster overall multi-word read timing. As long as bytes or words
are read in address order, additional wait states are unnecessary.
Data prefetch during read cycles is blocked when the next RAM address is a Control Word in the Descriptor Table. The
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HI-6130, HI-6131
table base address (set by the value in register 0x0005) and every fourth word thereafter is a Control Word. This con-
sists of table addresses having these address offsets from the table start address of 0, 4, 8, 0xC… 0x1F8 and 0x1FC.
If allowed, prefetch (like any other read) would reset the Control Word DBAC status bit, so prefetch is disallowed in
this range. Thus for HI-6130, multi-word sequential read sequences will assert WAIT every fourth word when
reading RAM within the 512-word Descriptor Table address range.
For fastest read access under all conditions, the user can set host processor bus timing (by adjusting processor wait
states for the chip select assigned to the HI-6130) to match the faster read cycle time for prefetched data, while the
HI-6130 WAIT output adds one or more additional wait states for the slower initial read cycle.
Timing diagrams for bus read and write operations are shown in Section 27. Separate diagrams show “Intel style” and
“Motorola style” control interfaces.
25.2. HI-6131 Serial Peripheral Interface
In the HI-6131, internal RAM and registers occupy a 32K x 16 address space. The lowest 80 addresses access
registers and the remaining addresses access RAM locations. Timing is identical for register operations and RAM
operations via the serial interface, and read and write operations have likewise identical timing.
25.2.1. Serial Peripheral Interface (SPI) Basics
The HI-6131 uses an SPI synchronous serial interface for host access to registers and RAM. Host serial communication
is enabled through the Chip Enable (CE) pin, and is accessed via a three-wire interface consisting of Serial Data Input
(SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All programming cycles are completely
self-timed, and no erase cycle is required before write.
The SPI (Serial Peripheral Interface) protocol specifies master and slave operation; the HI-6131 operates as an SPI
slave.
The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes.” Without describing details of the SPI modes, the HI- 6131 operates in
the two modes where input data for each device (master and slave) is clocked on the rising edge of SCK, and output
data for each device changes on the falling edge. These are known as SPI Mode 0 (CPHA = 0, CPOL = 0) and SPI
Mode 3 (CPHA = 1, CPOL = 1). Be sure to set the host SPI logic for one of these modes.
The difference between SPI Modes 0 and 3 is the idle state for the SCK signal, which is logic 0 for Mode 0 state and
logic 1 for Mode 3 state (see Figure 26). There is no configuration setting in the HI-6131 to select SPI Mode 0 or Mode
3 because compatibility is automatic. Beyond this point, the HI-6131 data sheet only shows the SPI Mode 0 SCK signal
in timing diagrams.
The SPI protocol transfers serial data as 8-bit bytes. Once CE chip enable is asserted, the next 8 rising edges on SCK
latch input data into the master and slave devices, starting with each byte’s most-significant bit. The HI-6131 SPI can
be clocked at 20 MHz.
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SCK (SPI Mode 0)
SCK (SPI Mode 3)
SI
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
MSB
LSB
LSB
High Z
High Z
SO
MSB
CE
Figure 26. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0
and 3
Multiple bytes may be transferred when the host holds CE low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks. A rising edge on CE chip enable terminates the serial transfer and reinitializes the HI-
6131 SPI for the next transfer. If CE goes high before a full byte is clocked by SCK, the incomplete byte clocked into
the device SI pin is discarded.
Two byte transfers are needed for SPI exchange of 16- bit register values or RAM data. “Big endian” byte order is used
for SPI data transfers. The high order byte (bits 15:8) is transferred before the low order byte (bits 7:0).
In the general case, both master and slave simultaneously send and receive serial data (full duplex) per Figure 26.
However the HI-6131 operates half duplex, maintaining high impedance on the SO output, except when actually trans-
mitting serial data. When the HI-6131 is sending data on SO during read operations, activity on its SI input is ignored.
Figure 27 and Figure 28 show actual behavior for the HI-6131 SO output.
25.2.2. HI-6131 SPI Commands
For the HI-6131, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the
device after assertion of CE. Since HI-6131 command byte reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte.
The HI-6131 SPI command set uses the most significant command bit to specify whether the command is Read or
Write. The command byte MSB is zero for read commands, and one for write commands.
25.2.3. Fast-Access Commands for Registers 0-15
The SPI command set includes directly-addressed read commands for registers 0 through 15. The 8-bit pattern for
these read commands has the general form
0-0-R-R-R-R-0-0
where RRRR is the 4-bit register address. These fast-access read commands appear in Table 24.
25.2.4. Fast-Access Write Commands for Registers 0-63
The SPI command set includes directly-addressed write commands for registers 0 through 63. The 8-bit pattern for
these read commands has the general form
1-0-R-R-R-R-R-R
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HI-6130, HI-6131
where RRRRRR is the 6-bit register address. The fast-access write commands appear in Table 24.
Figure 27 and Figure 28 show read and write timing as it appears for fast-access register operations. The command
byte is immediately followed by two data bytes comprising the 16-bit data word read or written. For a register read or
write, CE is negated after the 2-byte data word is transferred.
25.2.5. Indirect Addressing of RAM and Registers
Refer to the HI-6131 SPI command set shown in Table 25. All SPI commands other than fast-access use a Memory
Address Pointer register to indicate the starting address for read or write transactions. Four “Memory Address Point-
ers” reside at register addresses 0x000B through 0x000E. Just one Memory Address Pointer (MAP) is active (enabled)
at any time.
The active Memory Address Pointer is selected by writing the MAPSEL bits 11-10 in the Master Configuration Register.
Or use the SPI instruction op codes 0xD8, 0xD9, 0xDA or 0xDB which enable MAP registers 0x000B, 0x000C, 0x000D
or 0x000E respectively, by automatically writing MAPSEL bits 11-10 in the Master Configuration Register.
The active Memory Address Pointer must be initialized before any read or write operation, other than fast-access.
To write the active MAP register, use a fast-access write op code, followed by the desired 16-bit memory address:
•
•
•
•
Writing MAP register 0x000B uses SPI op code 0x8B followed by 16-bit address.
Writing MAP register 0x000C uses SPI op code 0x8C followed by 16-bit address
Writing MAP register 0x000D uses SPI op code 0x8D followed by 16-bit address.
Writing MAP register 0x000E uses SPI op code 0x8E followed by 16-bit address.
To read the active MAP register, use a fast-access write op code. The current MAP 16-bit value is clocked out in the
next 16 sequential SCK clock cycles:
•
•
•
•
Reading MAP register 0x000B uses SPI op code 0x2C
Reading MAP register 0x000C uses SPI op code 0x30
Reading MAP register 0x000D uses SPI op code 0x34
Reading MAP register 0x000E uses SPI op code 0x38
While SPI command op codes are always 8 bits, transacted addresses and register or memory data are always 16-
bit words, transferred by the SPI as two sequential bytes. After a 2-byte read/write completion, the active Memory
Address Pointer automatically increments to the following register address. The host can extend the read or write
operation to the next register address by continuing to hold CE low while clocking SCK 16 additional times. This auto-
increment feature can be used to access one or more sequential register addresses above the command address.
Auto-increment applies (ranging to the top of the address space) as long as SCK continues to be clocked under
continuous CE assertion. Caution: When the primary address pointer is used for auto-incrementing multi-word read/
write and reaches the top of the address range (0x7FFF) the next increment rolls over the MAP value to 0x0000. The
host should avoid this situation.
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0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB
SI
Command Byte
MSB
LSB MSB
LSB
High Z
High Z
SO
Data Byte 0
Data Byte 1
CE
Host may continue to assert CE
here to read sequential word(s).
Each word needs 16 SCK clocks.
Figure 27. Single-Word (2-Byte) Read From RAM or a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
LSB MSB
LSB MSB
LSB
MSB
SI
Command Byte
Data Byte 0
Data Byte 1
High Z
SO
CE
Host may continue to assert CE
here to write sequential word(s).
Each word needs 16 SCK clocks.
Figure 28. Single-Word (2-Byte) Write To RAM or a Register
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Three single-byte SPI commands modify the value in the active Memory Address Pointer, selected by MAPSEL bits
11-10 in the Master Configuration Register:
Command Address Pointer Operation
0xD0
0xD2
0xD4
increment enabled Memory Address
Pointer value
add 2 to enabled Memory Address
Pointer value
add 4 to enabled Memory Address
Pointer value
The “Add 4” command may be useful when sequentially accessing the same word (for example, the Control Word) in
a series of 4-word Descriptor Table entries. The “Add 2” command might be useful for reading the Interrupt Log Buf-
fer, comprised of 2-word log entries. In both cases, the Add command would be probably followed by Read command
0x40 to read the location addressed by the current pointer value. Similarly, Write command 0xC0 writes the location
addressed by the current pointer value. Two command bytes cannot be “chained”; the host SPI Slave Select CE must
be negated after the Add command, then reasserted for the following Read or Write command.
The active Memory Address Pointer is not affected by fast-access read/writes to the low register addresses because
fast-access SPI commands use a separate, internal pointer not directly accessible to the host.
Two single-byte SPI commands use the current value of the enabled Memory Address Pointer without first loading or
otherwise modifying it:
Command Read Operation
0x40
read location addressed by enabled
Memory Address Pointer
Command Write Operation
0xC0 write location addressed by enabled
Memory Address Pointer
Either of these commands can be used to read or write a single location, or may be used to start a multi-word read or
write that uses the MAP pointer’s auto-increment feature.
One single-byte SPI command increment the current value of the enabled Memory Address Pointer, then performs a
write:
Command Write Operation
add 1 to enabled Memory Address
0xC8
Pointer then write addressed location
25.2.6. Data Prefetch for SPI Read Cycles
Data prefetch is a technique used by the HI-6131 to speed up host multi-word read access to registers or RAM.
Prefetching occurs when HI-6131 logic accesses data before it is actually needed. Because register or RAM loca-
tions are often read sequentially, performance improves when data is prefetched in address sequence order. For any
SPI read cycle, the HI-6131 first fetches the addressed location, then increments the memory address pointer and
prefetches the following address, to speed up access in the likely event that the following word will be read next. For
the HI-6131, read cycle prefetch allows the SPI host to read sequential locations back-to-back, continuing as long as
the host asserts chip select and provides SPI clock. This is described as the Memory Address Pointer “auto-increment”
feature.
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There is an exception: read cycle prefetch is blocked when the next RAM address is a Control Word in the RT1 or
RT2 Descriptor Table. If allowed, pre-fetch (like any other read) resets the Control Word DBAC status bit. To preserve
DBAC status bit function, prefetch is disabled when reading Control Words within Descriptor Table address range.
The table base address (set by the value in register 0x0019 for RT1 or register 0x0022 for RT2) and every fourth word
thereafter is a Control Word. This consists of table addresses having these offsets from the table start address: 0, 4,
8, 0xC through and including 0x1F8 and 0x1FC. See further information in Section 25.2.8.
These two commands can be used to read or write a single location, or may be used to start a multi-word read or write
that uses the pointer’s auto-increment feature.
25.2.7. Special Purpose Commands
Several other HI-6131 SPI commands load or otherwise modify the active Memory Address Pointer before initiating a
read or write process. These commands were tailored to the specific needs of HI-6131 Remote Terminal host software.
Using a single-byte SPI command, the active Memory Address Pointer can be directly loaded with the memory ad-
dress for the RT1 or RT2 descriptor table Control Word corresponding to the last completed MIL-STD-1553 command.
The Control Word is then read.
Command Read Operation
Copy RT1 Current Control Word
Address register 3 into the enabled
0x48
0x50
Memory Address Pointer. Read the
location addressed by the new pointer
value.
Copy RT2 Current Control Word
Address register 5 into the enabled
Memory Address Pointer. Read the
location addressed by the new pointer
value.
This command can be used to read just the current RT1 or RT2 Control Word, or may be used to start a multi-word
read because memory pointer auto-increment occurs after the Control Word is read.
Six single-byte SPI commands add an offset to the current address pointer value, then read the addressed memory
location; the read value is then written to the address pointer register 15. The new pointer value is used to start a read
or write operation:
Command Read Operation
Read the location addressed by the
enabled Memory Address Pointer. Write
the value just read into the Memory
0x68
Address Pointer. Then read.
Add 1 to the enabled Memory Address
Pointer. Read value at newly addressed
location and write it into the Memory
0x70
Address Pointer. Then read.
Add 2 to the enabled Memory Address
Pointer. Read value at newly addressed
location and write it into the Memory
0x78
Address Pointer. Then read.
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Command Write Operation
Read the location addressed by the
enabled Memory Address Pointer. Write
the value just read into the Memory
Address Pointer. Then write.
0xE8
0xF0
0xF8
Add 1 to the enabled Memory Address
Pointer. Read value at newly addressed
location and write it into the Memory
Address Pointer. Then write.
Add 2 to the enabled Memory Address
Pointer. Read value at newly addressed
location and write it into the Memory
Address Pointer. Then write.
Primary use occurs when an RT1 or RT2 Descriptor Table Control Word was just read. For example, the last op code
performed was 0x48, reading the RT1 Control Word for the last command. After reading the Control Word, the enabled
Memory Address Pointer automatically incremented. The host can examine flag bits contained in the just-read Control
Word to determine the applicable data buffer (e.g., Data Buffer A, Data Buffer B or the Broadcast Data Buffer) then
directly service that buffer using these op codes; the three data buffer pointers occur in the three words following the
initially read Control Word.
These six commands can be used to read or write a single location, or may be used to start a multi-word read or write
that uses the pointer’s auto-increment feature.
When some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single-
byte SPI command may be useful if polling the RT1 or RT2 Descriptor Table for message activity. In this situation,
the host may poll a series of Descriptor Table Control Words looking for instances where the DBAC activity bit is set.
The DBAC (Descriptor Block Accessed) flag is set in the Control Word each time the corresponding command is com-
pleted. The process of reading the Control Word automatically resets the register’s DBAC bit so the host can detect
activity the next time the DBAC flag is set by the device.
Since RT1 or RT2 Descriptor Table Control Words are spaced four words apart, this command is useful when polling
a series of descriptor table Control Words:
Command Read Operation
read addressed location then add 4 to
pointer
0x60
Primary use occurs when the address pointer initially points to the first Descriptor Table Control Word in a series of
Control Words to be polled (every fourth word).
After 8 SCK clocks for the SPI command, each instance of this command reads a single location using 16 SCK clocks.
If CS remains low after 24 clocks and SCK continues, a multi-word read begins, using the address pointer’s auto-
increment feature. The second word read is at (Control Word address + 4), the next Control Word in the table.
Another single-byte SPI command is useful when servicing interrupts. When enabled interrupts occur, two words are
written to the circular 64-word Interrupt Log Buffer, and the Interrupt Log Address register 0x000A is updated to show
the storage address where interrupt information words will be stored for the next occurring interrupt. Buffer starting
address is 0x0180 and ending address is 0x01BF. Because two words are written to the buffer for each interrupt, the
Interrupt Log Address register always contains an even value in the range of 0x0180 to 0x01BE.
When servicing an interrupt that just occurred, the host wants timely information on that interrupt. An SPI command is
provided to simplify interrupt handling:
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Command Read Operation
Write enabled Memory Address Pointer
with the current bit 8:0 address value
in Interrupt Log Address register minus
1. (See note.) If address bits 8:0 equal
0x0180, then 0x1BF is written into Mem-
ory Address Pointer. Then read the new-
ly-addressed RAM location, containing
the last-written Interrupt Address Word.
Then decrement the Memory Address
Pointer, which then addresses the cor-
responding Interrupt Information Word
0x58
Note: Bits 15:9 in the Interrupt Log Address register contain the interrupt count since the Log Address register was last
read. These bits are not written to the Memory Address Pointer.
This command can be used to read a single location (the last-written Interrupt Address Word), or may be used to
start a multi-word read in which the Memory Address Pointer automatically decrements after each word is read, read-
ing words stored in the Interrupt Log Buffer, in Last In First Out order. This is the only SPI op code that decrements
the Memory Address Pointer for multi-word operations. Repeated memory pointer decrements will wrap around the
0x0180 to 0x01BF Interrupt Log Buffer boundary.
25.2.8. RT Descriptor Table Prefetch Exceptions
For the SPI-interface HI-6131, the enabled Memory Address Pointer (register 0x000F) contains the address for each
new word read by the host. When starting a read access, the host usually writes the enabled Memory Address Pointer
with the address for the first word to read. The host then uses an SPI op code to initiate the read process. After the
addressed word is transferred by SPI to the host, the HI-6131 continues to read and transmit words from sequential
RAM memory addresses, as long as the host continuously asserts chip select while providing SCK serial clock pulses.
After fetching each new word, the device increments the Memory Address Pointer and prefetches the data contained
in the newly addressed location. The next word is prefetched even when the host does not ultimately read the follow-
ing address. For HI-6131, sequential reads from the RT1 or RT2 Descriptor Table that rely on MAP auto-increment will
stop advancing when the next address contains a RT Descriptor Table Control Word. Properly designed SPI transfers
overcome this behavior.
Using SPI command op codes, the HI-6131 host must consider prefetch and pointer behavior when reading data from
the Descriptor Table. Applied outside the RT Descriptor Table, the following SPI sequence would read data from six
successive memory addresses. But below, applied within the table, the sequence gets stuck at the fourth word read.
Below we assume the RT1 Descriptor Table starts at default base address, 0x0400. The host first uses SPI op codes
0xD8 and 0x8B to enable Memory Address Pointer 0x000B then write the table start address 0x0400 into it. The se-
quence then uses op code 0x40 (and MAP auto-increment) to read the first MAP-addressed location and successive
locations.
Notice: There is no MAP auto-increment or data prefetch when MAP equals 0x0403, so the final two read cycles re-
peat the previous read value and address.
FROM
HOST
FROM
HI-6131 COMMENT
===== ======= ==========================================
0xD8
0x8B
---- SPI op enables memory address pointer (MAP) 0x000B.
---- SPI op code writes memory address pointer (MAP).
0x0400 ---- RT1 Descriptor Table start address written to MAP.
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0x40
---- SPI op code to “read location addressed by MAP”
---- <data> data from 0x0400 (SCK continues afterward)
---- <data> data from 0x0401 (SCK continues afterward)
---- <data> data from 0x0402 (SCK continues afterward)
---- <data> data from 0x0403 (SCK continues afterward, Control Word next)
---- <data> data from 0x0403 (SCK continues afterward, Control Word next)
---- <data> data from 0x0403 (SCK stops and /CS is then negated)
Using a different SPI op code sequence, the host can read the entire RT1 Descriptor Table without getting stuck at the
first Control Word read by the multi-word transfer using op code 0x40:
FROM
HOST
FROM
HI-6131 COMMENT
===== ======= ==========================================
0xD8
0x8B
---- SPI op enables memory address pointer (MAP) 0x000B.
---- op code writes memory address pointer (MAP)
0x03FF ---- decremented table start addr 0x0400 - 1 written to MAP
0xD0
0x40
---- op code increments enabled MAP
---- op code reads MAP-addressed location
---- <data> data from 0x0400 (SCK continues afterward)
---- <data> data from 0x0401 (SCK continues afterward)
---- <data> data from 0x0402 (SCK continues afterward)
---- <data> data from 0x0403 (SCK stops and /CS is negated)
0xD0
0x40
---- op code increments enabled MAP
---- op code reads MAP-addressed location
---- <data> data from 0x0404 (SCK continues afterward)
---- <data> data from 0x0405 (SCK continues afterward)
---- <data> data from 0x0406 (SCK continues afterward)
---- <data> data from 0x0407 (SCK stops and /CS is negated)
0xD0
0x40
---- op code increments enabled MAP
---- op code reads MAP-addressed location
---- <data> data from 0x0408 (SCK continues afterward)
---- <data> data from 0x0409 (SCK continues afterward)
---- <data> data from 0x040A (SCK continues afterward)
---- <data> data from 0x040B (SCK stops and /CS is negated)
The host may repeat this sequence until the entire RT1 Descriptor Table is read. The repeating read process is not
shown, but the sequence could end like this, stopping at the upper table boundary…
0xD0
0x40
---- op code increments enabled MAP
---- op code reads MAP-addressed location
---- <data> data from 0x05FC (SCK continues afterward)
---- <data> data from 0x05FD (SCK continues afterward)
---- <data> data from 0x05FE (SCK continues afterward)
---- <data> data from 0x05FF (SCK stops and /CS is negated) TABLE ENDS
In most situations, the repeating op code block (0xD0 with 8 SCK clocks and op code 0x40 with 72 SCK clocks) would
be implemented as a loop, rather than straight-line code. A total of 128 loop repetitions would be required to read the
RT Descriptor Table from start to finish.
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Table 24. Fast-Access SPI Commands for Lower Registers
Op Code Bits 5:2 Convey the 4-Bit Register Read Address.
Command Bits 5:0 Convey the 6-Bit Register Write Address.
Command Bits
7 6 5 4 3 2 1 0 Byte
HEX
Command Bits
7 6 5 4 3 2 1 0 Byte
HEX
Fast-Access Read
Fast-Access Write
0 0 0 0 0 0 0 0 0x00 Read Register 0
0 0 0 0 0 1 0 0 0x04 Read Register 1
0 0 0 0 1 0 0 0 0x08 Read Register 2
0 0 0 0 1 1 0 0 0x0C Read Register 3
0 0 0 1 0 0 0 0 0x10 Read Register 4
0 0 0 1 0 1 0 0 0x14 Read Register 5
0 0 0 1 1 0 0 0 0x18 Read Register 6
0 0 0 1 1 1 0 0 0x1C Read Register 7
0 0 1 0 0 0 0 0 0x20 Read Register 8
0 0 1 0 0 1 0 0 0x24 Read Register 9
0 0 1 0 1 0 0 0 0x28 Read Register 10
0 0 1 0 1 1 0 0 0x2C Read Register 11
0 0 1 1 0 0 0 0 0x30 Read Register 12
0 0 1 1 0 1 0 0 0x34 Read Register 13
0 0 1 1 1 0 0 0 0x38 Read Register 14
0 0 1 1 1 1 0 0 0x3C Read Register 15
1 0 0 0 0 0 0 0 0x80 Write Register 0
1 0 0 0 0 0 0 1 0x81 Write Register 1
1 0 0 0 0 0 1 0 0x82 Write Register 2
1 0 0 0 0 0 1 1 0x83 Write Register 3
1 0 0 0 0 1 0 0 0x84 Write Register 4
1 0 0 0 0 1 0 1 0x85 Write Register 5
1 0 0 0 0 1 1 0 0x86 Write Register 6
1 0 0 0 0 1 1 1 0x87 Write Register 7
1 0 0 0 1 0 0 0 0x88 Write Register 8
1 0 0 0 1 0 0 1 0x89 Write Register 9
1 0 0 0 1 0 1 0 0x8A Write Register 10
1 0 0 0 1 0 1 1 0x8B Write Register 11
1 0 0 0 1 1 0 0 0x8C Write Register 12
1 0 0 0 1 1 0 1 0x8D Write Register 13
1 0 0 0 1 1 1 0 0x8E Write Register 14
1 0 0 0 1 1 1 1 0x8F Write Register 15
1 0 0 1 0 0 0 0 0x90 Write Register 16
1 0 0 1 0 0 0 1 0x91 Write Register 17
1 0 0 1 0 0 1 0 0x92 Write Register 18
1 0 0 1 0 0 1 1 0x93 Write Register 19
1 0 0 1 0 1 0 0 0x94 Write Register 20
1 0 0 1 0 1 0 1 0x95 Write Register 21
decimal 15
is end of read
address range
and so on,
to 63 decimal
.
.
1 0 1 1 1 1 0 1 0xBD Write Register 61
1 0 1 1 1 1 1 0 0xBE Write Register 62
1 0 1 1 1 1 1 1 0xBF Write Register 63
decimal 63
is end of write
address range
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Table 25. SPI Commands using Memory Address Pointer
Hex Read or
Read
Byte
Write
Select / Enable a Memory Address Pointer
Enable Memory Address Pointer at register 0x000B
0xD8
0xD9
0xDA
0xDB
-------
-------
-------
-------
Enable Memory Address Pointer at register 0x000C
Enable Memory Address Pointer at register 0x000D
Enable Memory Address Pointer at register 0x000E
Memory Address Pointer Operations (no data is written or read)
Add 1 to the current value of the enabled Memory Address Pointer
Add 2 to the current value of the enabled Memory Address Pointer
Add 4 to the current value of the enabled Memory Address Pointer
Read / Write RAM or Register Location Using Current Address Pointer Value
Read location addressed by the current value of the enabled Memory Address Pointer
Write location addressed by the current value of the enabled Memory Address Pointer
Increment Address Pointer Then Write Addressed RAM or Register Location
Write addressed location after incrementing the enabled Memory Address Pointer
Special Purpose Commands
0xD0
0xD2
0xD4
-------
-------
-------
0x40
0xC0
R
W
0xC8
W
Copy RT1 current Control Word address (register 3) to enabled Memory Address Pointer, then
read the location addressed by the new pointer value (read the current Control Word for RT1)
0x48
0x50
R
R
Copy RT2 current Control Word address (register 5) to enabled Memory Address Pointer, then
read the location addressed by the new pointer value (read the current Control Word for RT2)
0x68
0x70
R
R
Add 0 to the current value of the enabled Memory Address Pointer. Then . . .
Add 1 to the current value of the enabled Memory Address Pointer. Then . . .
Add 2 to the current value of the enabled Memory Address Pointer. Then copy value from
newly addressed location to the enabled Memory Address Pointer then read newly addressed
location.
0x78
R
0xE8
0xF0
W
W
Add 0 to the current value of the enabled Memory Address Pointer. Then . . .
Add 1 to the current value of the enabled Memory Address Pointer. Then . . .
Add 2 to the current value of the enabled Memory Address Pointer. Then copy value from
newly addressed location to the enabled Memory Address Pointer then write newly addressed
location.
0xF8
0x60
0x58
W
R
Read then add 4 to the current value of the enabled Memory Address Pointer.
Write storage address of last-written Interrupt Address Word to the enabled Memory Address
Pointer, then read the Interrupt Address Word from the Interrupt Log buffer.
Decrement Memory Address Pointer after read operation
R
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26. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS
Bits Updated
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
in Descriptor
Control Word
Invalid Command
Word (Manchester,
parity or bit count error) No Status Word change.
No terminal response,
the message is ignored.
No Message Info Word
None
No change
No change
is written
Any valid command
No terminal response,
to RT31 (broadcast).
the message is ignored.
when the BCSTINV
No Status Word change.
bit in the RT
No Message Info Word
None
is written
(Broadcast commands
Configuration
are rendered invalid.)
Register equals 1.
RT Address Parity Error For commands to the RT’s
based on RTA and
RTAP
bits in the Operational
Status Register
own address or to broadcast
address RT31: No terminal
response, message is ignored.
No Status Word change.
RTAPF
(not
optional)
No Message Info Word
is written
No change
Any valid non-mode
(subaddress 1-30)
transmit command
to RT31 (undefined
broadcast transmit).
No terminal response,
Set Message Error (ME)
and BCR status bits.
DBAC bit set.
DPB bit toggles.
BCAST bit set.
IWA
MERR bit set.
IBR
BUSID bit updated.
(IXEQZ)
Any valid non-mode
(subaddress 1-30)
transmit command
except for RT31. The
corresponding bit
in the Illegalization
Table equals 0.*
Normal Status Word response
(Clear Status). Data words for
transmit are read from the
RAM data buffer assigned
by the Descriptor Table entry
for the transmit subaddress.
Normal CS update:
BUSID bit updated.
DBAC bit set.
DPB bit toggles.
BCAST bit reset.
IWA
MERR bit reset.
IBR
ILCMD bit reset.
(IXEQZ)
RTRT bit updated.
(Other error bits reset).
Any valid non-mode
(subaddress 1-30)
transmit command
except for RT31. The
corresponding bit
in the Illegalization
Table equals 1. **
ILCMD bit set.
Assert Message Error (ME)
status, then transmit
ME Status Word
DBAC bit set.
BUSID bit updated.
ILCMD
DPB bit toggles. MERR bit set.
BCAST bit reset. RTRT bit updated.
(Other error bits reset).
IWA
without following data words.
Normal Status Word response
(Clear Status). After message
completion, the data words
Any valid non-mode
(subaddress 1-30)
receive command.
The corresponding
bit in the Illegalization
Table equals 0. *
Normal update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(Other error bits reset).
DBAC bit set.
IWA
IBR
(IXEQZ)
received are stored in the data DPB bit toggles.
buffer RAM location assigned
by the Descriptor Table entry
for the receive subaddress.
BCAST bit reset.
*
Terminal is using “illegal command detection” and command is legal
OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response).
** Terminal is using “illegal command detection” and command is illegal.
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Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Assert Message Error (ME)
status and set BCR if
broadcast.
Any received data words are
ignored and are not saved.
When data reception stops,
transmit Status Word.
Any valid non-mode
(subaddress 1-30)
receive command.
The corresponding bit
in the Illegalization
Table equals 1. **
ILCMD bit set.
ILCMD
DBAC bit set.
DPB bit toggles.
BCAST bit
BUSID bit updated.
IWA
MERR bit set.
IBR
RTRT bit updated.
(IXEQZ)
updated.
(Other error bits reset)
MERR bit set.
BUSID bit updated.
Valid receive
No terminal response.
Set Message Error (ME) status. BCAST bit
If broadcast (RT31), also set
the BCR status bit.
DBAC bit set.
command followed
by invalid data word
(Manchester, parity
or bit count error).
MERR
IWDERR bit set.
IWA
updated.
ILCMD bit reset.
IBR
DPB bit toggles. RTRT bit updated
(Other error bits reset).
Valid receive command
followed by one or
more
good data words, then If broadcast (RT31), also set
a data word having
Command Sync.
MERR bit set.
DBAC bit set.
No terminal response.
BUSID bit updated.
MERR
IWA
IBR
Set Message Error (ME) status. BCAST bit
SYNERR bit set.
ILCMD bit reset.
updated.
DPB bit toggles.
the BCR status bit.
(Other error bits reset).
MERR bit set.
BUSID bit updated.
Set WCTERR (too few)
or GAPERR (too
many).
Any valid command
followed by wrong
number of data
words (too few or
too many words)
No terminal response.
Set Message Error (ME) status. BCAST bit
If broadcast (RT31), also set
the BCR status bit.
DBAC bit set.
MERR
IWA
IBR
updated.
DPB bit toggles. ILCMD bit reset.
RTRT bit updated.
(Other error bits reset).
RT-RT where CW1
is a valid non-mode
receive command.
CW2 is a non-mode
transmit command
valid for different RT.
(Normal RT-RT
Normal CS update:
BUSID bit updated.
RTRT bit set.
Normal Status Word response
(Clear Status). If RT-RT
Command
Word 1 is broadcast (RT31)
set the BCR status bit.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
(IXEQZ)
RTCWERR bit reset.
DPB bit toggles. ILCMD bit reset.
(All error bits reset).
receive message)
RT-RT where CW1
is a valid non-mode
receive command.
Transmit command
CW2 has an error:
T/R bit = 0, or CW2
subaddress equals
0 or 31 (mode code),
or CW2 has same RT
address as CW1.
MERR bit set.
BUSID bit updated.
RTRT bit set.
No terminal response.
DBAC bit set.
BCAST bit
updated.
Set Message Error (ME) status.
If RT-RT Command Word 1 is
broadcast (RT31) also set
the BCR status bit,
MERR
IWA
IBR
RTRTCWERR bit set.
DPB bit toggles. ILCMD bit reset.
(Other error bits reset).
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Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
RT-RT where CW1
is a valid non-mode
receive command.
CW2 is valid for
different RT but
transmitting RT does
not respond in time.
MERR bit set.
BUSID bit updated.
No terminal response.
DBAC bit set.
BCAST bit
updated
Set Message Error (ME) status.
If RT-RT Command Word 1 is
broadcast (RT31), also set
the BCR status bit.
MERR
RTRT bit set.
IWA
TMOERR bit set.
IBR
DPB bit toggles. ILCMD bit reset.
(Other error bits reset).
RT-RT receive
command (CW1 is
valid). The transmitting
RT response has one
of these errors:
invalid word
(Manchester,
(sync, bit count,
parity or word count
error). Also includes
transmitting RT
response with Message
Error or Busy status
followed by no data
words.
MERR bit set.
BUISID bit reset.
RTRT bit set.
IWDERR bit set,
or WCTERR bit set
for Tx RT Busy case.
ILCMD bit reset.
(Other error bits reset).
No terminal response.
Set Message Error (ME) status. DBAC bit set.
If RT-RT Command Word 1 is
broadcast (RT31) also set
the BCR status bit.
MERR
IWA
IBR
BCAST bit reset.
DPB bit toggles.
RT-RT command
where CW2 is a
valid non-mode
(subaddress 1-30)
transmit command.
CW1 is a non-mode
receive command
for RT31. (Normal
broadcast RT-RT
transmit)
Normal Status Word
response. Clear status
is transmitted with the
commanded number of
data words. Data words for
transmit are read from the
RAM data buffer assigned
in the Descriptor Table entry
for the transmit subaddress.
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit set.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
IWA
(IXEQZ)
(All error bits reset).
Valid mode code
command to RT31
(broadcast). The
BCSTINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
No Message Info Word
is written
No change
None
None
Register equals 1.
No terminal response,
the message is ignored.
No Status Word change.
NOTE:
This only applies for the
undefined mode codes:
MC0 to MC15 with T/R = 0
MC16,18 & 19 with T/R = 0
MC17,20 & 21 with T/R = 1
Valid undefined
mode code
command. The
UMCINV bit in the RT
Configuration
No Message Info Word
is written
No change
Register equals 1.
HOLT INTEGRATED CIRCUITS
247
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
If MC2 (transmit status)
or MC18 (transmit last
command) status word
from last command is
transmitted. If MC18,
data word transmitted
is read from an internal
register.
OR
If not MC2 or MC18,
normal Status Word
response. If broadcast,
assert Status Word
BCR bit.
Valid defined mode
code command
(including reserved
mode code) not
“illegalized” by
Illegalization Table
(table bit equals 0 *)
Normal CS update:
BUSID bit updated.
DBAC bit set.
BCAST bit
updated.
IWA
MERR bit reset.
IBR
ILCMD bit reset.
(IXEQZ)
For mode codes 16-31
with T/R bit = 1 which
transmit a data word,
the word for transmit
is read from the Mode
Command Data Table.
AND
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
For all mode commands
with mode data word
(mode codes 16-31),
the transmitted or
received data word is
written to command’s
Descriptor Word 4.
Set Message Error (ME) status.
If not broadcast (RT31),
transmit.
Status Word without a following
mode data word. If broadcast
(RT31), also assert the BCR
status bit.
Valid defined mode
code command that
is “illegalized” by the
IllegalizationTable
ILCMD bit set.
DBAC bit set.
BUSID bit updated.
BCAST bit
ILCMD
IWA
IBR
AND
MERR bit reset.
updated.
For mode commands with
a mode data word
RTRT bit reset.
(Other error bits reset.)
DPB bit toggles.
(table bit equals 1 **)
(mode codes 16-31),
no updates are made to
the Mode Command Data
Table or to the command’s
Word 4 in Descriptor Table.
*
Terminal is using “illegal command detection” and command is legal
OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response).
** Terminal is using “illegal command detection” and command is illegal.
HOLT INTEGRATED CIRCUITS
248
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
If bit in Illegalization Table that
corresponds to the undefined
mode code command equals
1 **
Set Message Error (ME) status,
If not broadcast (RT31),
transmit
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
ILCMD bit set.
BUSID bit updated.
MERR bit reset.
ILCMD
IWA
IBR
Status Word without a
following mode data word.
If broadcast (RT31), also
assert the BCR status bit.
OR
If bit in Illegalization Table that
corresponds to the undefined
mode code command equals
0 *
Normal Status Word (Clear
Status) response. If command
was broadcast (RT31),
assert the BCR status bit.
AND
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. ILCMD bit reset.
RTRT bit reset.
Normal CS update:
BUSID bit updated.
MERR bit reset.
IWA
IBR
(IXEQZ)
Valid undefined mode
code command.
The UMCINV bit
in the RT Configuration
Register equals 0.
(All error bits reset.)
For mode codes 16-31
with T/R bit = 1 which
transmit a data word,
the word for transmit
is read from the Mode
Command Data Table.
AND
For all mode commands
with mode data word
(mode codes 16-31),
the transmitted or
received data word is
written to command’s
Descriptor Word 4.
*
Terminal is using “illegal command detection” and command is legal
OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response).
** Terminal is using “illegal command detection” and command is illegal.
HOLT INTEGRATED CIRCUITS
249
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
MERR bit set.
BUSID bit updated.
Valid receive
No terminal response.
Set Status Word ME bit,
If broadcast, also set
Status Word BCR bit.
DBAC bit set.
BCAST bit
updated.
command followed
by invalid data word
(Manchester, parity
or bit count error).
MERR
IWDERR bit set.
IWA
ILCMD bit reset.
IBR
DPB bit toggles. RTRT bit updated.
(Other error bits reset.)
Superseded Message:
Terminal receives an
incomplete message
interrupted by a gap
of at least 3.5 us,
followed by a new
valid command on
the same bus or
on the other bus
OR
Terminal is transacting unless second command
a transmit message on is MC2 (transmit status)
one bus and receives
the start of a valid
command on the other
bus.
No change
to superseded
command’s
No Msg Info
None for
super-
seded
Word written for
the superseded
command.
Terminal aborts processing
for first message and
responds in full to the
second (superseding)
message. The Status
Word BCR bit reflects
broadcast status for:
the second command,
Control Word.
command
For superseding For superseding
IWA
IBR
(IXEQZ)
command’s
Control Word:
DBAC bit set.
BCAST bit
updated
command’s
data buffer, a
normal CS update:
BUSID bit updated.
MERR bit reset.
DPB bit toggles. ILCMD bit reset.
RTRT bit updated.
or MC18 (transmit last
command).
(All error bits reset.)
Busy bit is set in the 1553
Status Bits register. Status
Terminal is Busy for a
valid receive command Word is transmitted,
either globally (BUSY
bit set in Status Word
Bits register) or in
response to a particular set. After message
valid receive command completion, data words
(MKBUSY bit set in the received are stored in
command’s Descriptor the data buffer assigned
unless broadcast. If
broadcast, the BCR bit
in Status Word is also
WASBSY bit set.
DBAC bit set.
BCAST bit
updated.
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
IWA
IBR
DPB bit toggles. RTRT bit updated.
(All error bits reset.)
Table control word.)
by the receive subaddress
Descriptor Table entry.
Terminal is Busy for a
valid transmit
command
Busy bit is set in the 1553
Status Bits register. If not
broadcast, Status Word is
transmitted without data.
DBAC bit set.
WASBSY bit set.
BCAST bit
either globally (BUSY
bit set in Status Word
Bits register) or in
response to a particular If broadcast, the BCR bit
valid receive command in Status Word is also
(MKBUSY bit set in the set.
BUSID bit updated.
updated,
MERR bit reset.
(mode
IWA
IBR
ILCMD bit reset.
commands
RTRT bit updated.
with T/R = 1)
(All error bits reset.)
DPB bit toggles
command’s Descriptor
Table control word.)
HOLT INTEGRATED CIRCUITS
250
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
DYNAMIC BUS
CONTROL (MC0):
Mode code command
with mode code
00000 and T/R bit
equals 1
HI-6110 is not equipped to
accept bus control duties. The
host must initialize device to
respond using either of the two
following methods:
RT is not using “illegal
command detection.”
Respond “in form”: Reset
Message Error (ME) status
and transmit Status Word.
DBAC bit set.
Normal CS update:
IWA
The mode code’s bit
in Illegalization Table
equals 0 *
BCAST bit reset. BUSID bit updated.
DPB bit toggles. MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
(All error bits reset.)
OR
OR
The mode code’s bit
in Illegalization Table
equals 1 **
RT is using “illegal
command detection”and
mode code is illegalized.
Set Message Error (ME)
status and transmit Status
Word.
DBAC bit set.
ILCMD bit set.
ILCMD
IWA
BCAST bit reset. BUSID bit updated.
DPB bit toggles. MERR bit reset.
RTRT bit reset.
(Other error bits reset.)
MC0 EXCEPTIONS:
MERR bit set.
DBAC bit set.
Broadcast address
RT31 (broadcast not
allowed)
No Status Word transmit.
Set the Message Error
(ME) and BCR status bits.
BUSID bit updated.
BCAST bit set.
MERR
IWA
IBR
ILCMD bit reset.
DPB toggles.
RTRT bit reset.
(Other error bits reset.)
MERR bit set.
WCTERR bit set.
DBAC bit set.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
BUSID bit updated.
BCAST bit reset.
ILCMD, RTRT bits
DPB bit toggles.
MERR
IWA
reset.
(Other error bits reset.)
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(MC0 is not ndefined
when T/R bit equals 0)
No Message Info
No Change
None
Word is written
Register equals 1 ***
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
251
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
Register equals 0.
Illegalization Table
bit equals 0 *
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
Respond “In form”:
Reset Message Error
(ME) status and transmit Status
Word.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
IWA
IBR
(All error bits reset.)
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
Register equals 0.
Illegalization Table
bit equals 1 **
ILCMD bit set.
MERR bit set.
Set Message Error
DBAC bit set.
ILCMD
IWA
IBR
(ME) status and transmit Status BCAST bit reset. BUSID bit updated.
Word. DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
HOLT INTEGRATED CIRCUITS
252
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
Message Error (ME) status
then transmit Status Word.
If broadcast, set the Status
Word BCR bit and suppress
Status Word transmit.
SYNCHRONIZE
WITHOUT DATA
(MC1):
Mode code command
with mode code
00001 and T/R bit
equals 1
Normal update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
Reset the Time Tag counter
to 0x0000.
MC1 EXCEPTIONS:
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Message Info
No Change
None
Word is written
Register equals 1 ***
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
The Time Tag counter is
not reset.
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Normal update:
DBAC bit set.
BCAST bit
updated.
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
The Time Tag counter is
not reset.
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
ILCMD bit set.
DBAC bit set.
MERR bit set.
ILCMD
IWA
IBR
BCAST bit
updated.
BUSID bit updated.
RTRT bit reset.
DPB bit toggles.
(Other error bits reset.)
MERR bit set.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
MERR
IWA
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
253
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
No Status Word updates,
Transmit Status from last
valid command (assuming
last command was not a
“Transmit Status” or a
“Transmit last Command”
mode command.
TRANSMIT STATUS
(MC2):
Mode code command
with mode code
00010
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
IWA
and T/R bit equals 1
(All error bits reset.)
MC2 EXCEPTIONS:
MERR bit set.
Broadcast address
RT31
No Status Word transmit.
Set the Message Error
DBAC bit set.
BCAST bit set.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
(broadcast not allowed) (ME) and BCR status bits.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
IBR
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
No Status Word change.
UMCINV bit in the RT
(mode code is undefined
Configuration
No Message Info
Word is written
No Change
None
when T/R bit equals 0)
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
The Illegalization Table suppress status response.
bit equals 0 *
Time Tag counter is not reset.
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0
The Illegalization Table.
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
DBAC bit set.
MERR bit set.
ILCMD
IWA
IBR
BCAST bit
updated.
BUSID bit updated.
RTRT bit reset.
DPB bit toggles.
(Other error bits reset.)
MERR bit set.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset. ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
WCTERR bit set.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
254
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
Message Error (ME) status
then transmit Status Word.
If broadcast, set the
Status Word BCR bit and
suppress status transmit.
Host should initiate self-
test then update Built-In
Test word at shared RAM
address 0x0093. Resume
terminal execution.
INITIATE
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
SELF TEST (MC3):
Mode code command
with mode code
00011
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
and T/R bit equals 1
MC3 EXCEPTIONS:
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Message Info
No Change
None
Word is written
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
DBAC bit set.
BCAST bit
updated.
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
255
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
TRANSMITTER
SHUTDOWN (MC4):
Mode code command
with mode code
00100
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
Message Error (ME) status
then transmit Status Word. If
broadcast, set Status Word
BCR bit and suppress status.
transmit. After Status trans-
mission, inhibit the inactive bus:
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
and T/R bit equals 1
The device automatically shuts down either transmit and receive or transmit only for the inactive bus,
depending on the state of the BSDTXO bit in the Master Configuration Register. Refer to the description of the
AUTOBSD bit in the RT Configuration Register for further information. When MC4 results in transmitter shutdown,
the condition is reflected by assertion of a TXASD or TXBSD bit in the corresponding RT Built-In Test Register
at register address 0x001E (RT1) or address 0x0027 (RT2). If BSDTXO equals logic 0, an RXASD or RXBSD
bit will also be asserted, indicating full bus shutdown (transmit and receive). Once shutdown, the inactive bus
transmitter (or transmitter and receiver) can be reactivated by an “Override Transmitter Shutdown” MC5 or MC21
or “Reset Remote Terminal” MC8 mode code command, or by software reset (initiated by setting the RT1RESET
or RT2RESET bit in the Master Status and Reset Register 0x0001) or by hardware reset initiated by asserting the
MR Master Reset input pin.
MC4 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration Register
equals 1 ***
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration Register
equals 0.
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
The Illegalization Table
bit equals 1 **
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
256
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
Message Error (ME) status
then transmit Status Word.
If broadcast, set the
Status Word BCR bit and
suppress status transmit.
This command is only used
with dual redundant buses.
After Status transmission,
reactivate inactive bus:
OVERRIDE
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
TRANSMITTER
SHUTDOWN (MC5):
Mode code command
with mode code
00101
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
and T/R bit equals 1
The device automatically re-enables transmit and receive for the inactive bus, without considering BSDTXO bit
status in the Master Configuration Register. The device affirms re-enabled bus status by resetting all four TXASD,
TXBSD, RXASD and RXBSD “shutdown status” bits in the Built-In Test Register at register address 0x001E for
RT1 or 0x0027 for RT2. Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the
resulting hardware transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits
remain high. See Built-In Test Register description for further information.
MC5 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
257
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
INHIBIT TERMINAL
FLAG BIT (MC6):
Mode code command then transmit Status Word.
with mode code
00110
and T/R bit equals 1
Default response: Reset
Message Error (ME) status
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
If broadcast, set the
Status Word BCR bit and
suppress status transmit.
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
The device automatically sets the TF Inhibit bit in the BIT Word register at address 0x0013. While the TF inhibit bit
is set, the device disregards assertion of the Terminal Flag (TF) bit in the 1553 Status Bits register (0x0006) and
only transmits status with the Terminal Flag status bit reset.
Once the Terminal Flag has been inhibited, it can be reactivated by an “Override Inhibit Terminal Flag” MC7 or
“Reset Remote Terminal” MC8 mode command, by software reset (asserting the SRST bit in the RT Configuration
Register) or by asserting the MR master reset input pin.
MC6 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
258
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
OVERRIDE INHIBIT
TERMINAL FLAG BIT Message Error (ME) status
(MC7): then transmit Status Word.
Default response: Reset
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
Mode code command If broadcast, set the
with mode code 00111 Status Word BCR bit and
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
and T/R bit equals 1
suppress status transmit.
The device automatically resets the TF Inhibit bit in the BIT Word register at address 0x0013. While the TF inhibit
bit is reset, the device transmits status with the Terminal Flag status bit set if the Terminal Flag (TF) bit is asserted
in the 1553 Status Bits register (0x0006).
MC7 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
259
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
RESET REMOTE
TERMINAL (MC8):
Mode code command Message Error (ME)
with mode code
01000
and T/R bit equals 1
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
Default response: Reset
DBAC bit reset.
BCAST bit
updated.
IWA
IBR
status. If not broadcast,
transmit Status Word.
DPB bit toggles. RTRT bit reset.
(All error bits reset.)
After Status transmission, the device automatically resets the status Message Error (ME) Busy and Broadcast
Command received (BCR) bits in its internal status register. The BIT Word at shared RAM address is reset to
0x0000. If either transmitter was shutdown, the shutdown condition is overridden. If the Terminal Flag (TF) status
bit was inhibited, the inhibit is reset.
This command does not reset any of the host-programmed registers that configure the terminal for operation.
To complete the terminal reset process, the host must assert either MR hardware master reset (with or without
auto-initialization) or assert the SRST bit in the RT Configuration Register to execute software reset. See following
section entitled Reset and Initialization for additional details. Because MC8 requires host interaction, most
applications will probably utilize the IWA interrupt to alert the host when received.
MC8 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
GAPERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
260
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
RESERVED MODE
CODES MC9 - MC15:
Mode code command
with mode codes
01001 through 01111
and T/R bit equals 1
The reserved mode code
commands do not have
defined terminal actions.
Host must initialize device
to respond using either of
the two following methods:
RT is not using “illegal
command detection.”
Respond “in form”: Reset
Message Error (ME) status
and transmit Status Word.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. ILCMD bit reset.
RTRT bit reset.
Normal CS update:
BUSID bit reset.
MERR bit reset.
IWA
The mode code’s bit
in Illegalization Table
equals 0 *
(All error bits reset.)
OR
OR
The mode code’s bit
in Illegalization Table
equals 1 **
RT is using “illegal
command detection”and
mode code is illegalized.
Set Message Error (ME)
status and transmit Status
Word.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
ILCMD bit set.
BUSID bit updated.
MERR bit set.
ILCMD
IWA
MC9 - MC15
EXCEPTIONS:
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
No Message Info
Word is written
No Change
None
Config. Reg. equals 1 *** when T/R bit equals 0)
T/R bit equals 0
AND
UMCINV bit in the RT
Config. Reg. equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Config. Reg. equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
261
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default CS response:
Reset Message Error (ME)
and BCR status bits. then
transmit Status Word
TRANSMIT VECTOR
WORD (MC16):
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
Mode code command followed by the data word
IWA
with mode code
10000
and T/R bit equals 1
stored in the assigned index or
ping-pong data buffer (or in
Descriptor Word 4 for SMCP
Simplified Mode Command
Processing).
(All error bits reset.)
MC16 EXCEPTIONS:
MERR bit set.
BUSID bit updated.
ILCMD bit reset.
DBAC bit set.
BCAST bit set.
DPB toggles.
Broadcast address
RT31 (broadcast not
allowed)
No Status Word transmit.
Set the Message Error
(ME) and BCR status bits.
MERR
IWA
IBR
RTRT bit reset.
(Other error bits reset.)
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Message Info
Word is written
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
No Status Word transmit.
Set the Message Error
(ME) status bit. If broadcast,
set the BCR status bit.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
IBR
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
262
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
SYNCHRONIZE WITH Default response: Reset
DATA WORD (MC17): Message Error (ME)
Mode code command status. and transmit
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
IWA
with mode code
10001
Status Word. If broadcast,
set BCR status bit and
and T/R bit equals 1
suppress Status response.
(All error bits reset.)
Device stores received data word in the assigned ping-pong or index data buffer (or in Descriptor Word 4 for
SMCP Simplified Mode Command Processing). RT Configuration Register MCOPT2 and MCOPT3 bits allow
automatic Time-Tag count loading using the data word received. If MCOPT2 equals 1, the received data word
is automatically loaded to the Time-Tag counter if the low order bit of the received data word (bit 0 equals 0. If
MCOPT3 equals 1, the received data word is automatically loaded to the Time-Tag counter if the low order bit of
the received data word (bit 0) equals 1. If both bits are set, the received data word is unconditionally loaded into
the Time-Tag counter. For non-broadcast commands, counter load occurs before status word transmission.
MC17 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Config. Reg.
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
Config. Reg. equals 0. Status Word. If broadcast,
ILCMD bit reset.
The Illegalization Table set the BCR status bit and
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
bit equals 0 *
suppress status response.
T/R bit equals 0
AND
UMCINV bit in the RT
Config. Reg. equals 0.
The Illegalization Table
bit equals 1 **
No Status Word transmit.
Set the Message Error
(ME) status bit.
If broadcast, set the
BCR status bit.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
Mode code command
word not followed by a Set the Message Error
contiguous data word
(missing data word)
No Status Word transmit.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
IBR
(ME) status bit. If broadcast,
set the BCR status bit.
(Other error bits reset.)
MERR bit set.
Mode code command
word followed by data
word with Manchester
encoding or parity error If broadcast, set the
(bad data word) BCR status bit.
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit
updated.
IWDERR bit set.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
263
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Status
is not updated. Transmit
Status Word from the previous
command, with data word
containing the last valid
command word (assuming it
was not a “Transmit Status” or
a “Transmit Last Command”
mode command.
TRANSMIT LAST
COMMAND (MC18):
Mode code command
with mode code
10010
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
IWA
and T/R bit equals 1
(All error bits reset.)
Transmitted data word is automatically provided from an internal register, and is copied to assigned index or ping-
pong buffer (or to Descriptor Word 4 for SMCP Simplified Mode Command Processing)
MC18 EXCEPTIONS:
MERR bit set.
DBAC bit set.
Broadcast address
RT31 (broadcast not
allowed)
No Status Word transmit.
Set the Message Error
(ME) and BCR status bits.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
BCAST bit set.
DPB toggles.
RTRT bit reset.
(Other error bits reset.)
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Message Info
Word is written
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
No Status Word transmit.
Set the Message Error
(ME) status bit. If broadcast,
set the BCR status bit.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
IBR
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
HOLT INTEGRATED CIRCUITS
264
HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
Message Error (ME) and
BCR status bits. then
TRANSMIT BIT WORD
(MC19):
Mode code command
with mode code
10011
Normal CS update:
BUSID bit reset.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
transmit Status Word
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
followed by data word from
either BIT Word Register or
Alternate BIT Word Register,
depending on Configuration
Reg. 2 option bit ALTBITW.
IWA
and T/R bit equals 1
(All error bits reset.)
Transmitted data word is automatically copied to the assigned index or ping-pong buffer (or to Descriptor Word 4
for SMCP Simplified Mode Command Processing)
MC19 EXCEPTIONS:
MERR bit set.
DBAC bit set.
Broadcast address
RT31 (broadcast not
allowed)
No Status Word transmit.
Set the Message Error
(ME) and BCR status bits.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
BCAST bit set.
DPB toggles.
RTRT bit reset.
(Other error bits reset.)
Invalid command word.
OR
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No terminal response,
the message is ignored.
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Message Info
Word is written
No Change
None
Register equals 1 ***
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
ILCMD bit reset.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
No Status Word transmit.
Set the Message Error
(ME) status bit. If broadcast,
set the BCR status bit.
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
Mode code command
word is followed by a
contiguous data word
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
IBR
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
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Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
Default response: Reset
Message Error (ME)
status. and transmit
Status Word. If broadcast,
set BCR status bit and
suppress Status response.
This command is intended
for use in 1553 systems
with more than one dual
redundant bus.
SELECTED
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
TRANSMITTER
SHUTDOWN (MC20):
Mode code command
with mode code
10100
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
IWA
(All error bits reset.)
and T/R bit equals 1
After Status Word transmission, the device stores received data word in the assigned index or ping-pong buffer
(or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies).
If the AUTOBSD bit in the RT Configuration Register equals 1, the received data word is compared to the value in
the Bus Select Register corresponding to the inactive bus. For example, if the command is received on Bus A, the
comparison uses the Bus B Select Register value. If the compared values match, the device automatically shuts
down either transmit and receive or transmit only for the inactive bus, depending on the state of the BSDTXO
bit in the Master Configuration Register 0x0000. See descriptions for the BSDTXO bit in Master Configuration
Register and the AUTOBSD bit in the RT Configuration Register(s) for further information. When a bus transmitter
(or transmitter and receiver) is shut down by this mode command, bus status is reflected by assertion of a TXASD
or TXBSD bit in the RT Built-In Test Register at register address 0x001E for RT1, 0x0027 for RT2. If BSDTXO
equals logic 0, an RXASD or RXBSD bit will also be asserted. See RT Built-In Test Register description for further
information.
If the AUTOBSD bit in the RT Configuration Register equals 0, the IWA interrupt is typically used to alert the host
when an MC20 command is received. The host must evaluate whether the received mode data word matches
the bus selection criteria. If bus selection match occurs, the host fulfills bus shutdown command using one of two
options:
1. set the bus shutdown bit INHBUSA or INHBUSB for the inactive bus in the RT Configuration Register(s) to
inhibit both transmit and receive,
OR
2. assert the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to inhibit only transmit. The
inactive bus receiver remains active; all valid commands are heeded without transmit. This option is rarely
applied.
Once shutdown, the inactive bus transmitter (or transmitter and receiver) can be reactivated five ways: an
“Override Transmitter Shutdown” MC5, a MC21 command with data word that matches “bus select” criteria, a
“Reset Remote Terminal” MC8 mode code command, a software reset initiated by setting the RT1RESET or
RT2RESET bit in the Master Status and Reset Register 0x0001, or by hardware reset initiated by asserting the
MR Master Reset input pin.
MC20 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration Register
equals 1 ***
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
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Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
Mode code command
word not followed by a Set the Message Error
contiguous data word
(missing data word)
No Status Word transmit.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
WCTERR bit updated.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
(ME) status bit. If broadcast,
set the BCR status bit.
MERR bit set.
Mode code command
word followed by data
word with Manchester
encoding or parity error
(bad data word)
No Status Word transmit.
Set the Message Error
(ME) status bit. If broadcast,
set the BCR status bit.
DBAC bit set.
BCAST bit
updated.
IWDERR bit set.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
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HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
OVERRIDE
SELECTED
TRANSMITTER
SHUTDOWN (MC21): status. and transmit
Mode code command Status Word. If broadcast,
with mode code
10101
Default response: Reset
Message Error (ME)
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
IWA
set the BCR status bit and
suppress Status response.
(All error bits reset.)
and T/R bit equals 1
After Status Word transmission, the device stores the received data word in the assigned index or ping-pong
buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies).
If the AUTOBSD bit in the RT Configuration Register equals 1, the received data word is compared to the value
in the Bus Select Register corresponding to the inactive bus. For example, if the command is received on Bus A,
the comparison uses the Bus B Select Register value. If the compared values match, the device automatically
re-enables transmit and receive for the inactive bus, regardless of the state of the BSDTXO bit in the Master
Configuration Register. The device affirms fully re-enabled bus status by resetting all four TXASD, TXBSD,
RXASD and/or RXBSD bits in the RT Built-In Test Register at register address 0x001E for RT1, address 0x0027
for RT2. Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the resulting
hardware transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain
high. See RT Built-In Test Register description for further information.
If the AUTOBSD bit in the Master Configuration Register equals 0, the IWA interrupt is typically used to alert
the host when an MC21 command is received. The host must evaluate whether the received mode data word
matches the bus selection criteria. If bus selection match occurs, the host fulfills the “override shutdown”
command using one of two options:
1. reset the RTINHA or RTINHB bus shutdown bit corresponding to the inactive bus in the applicable RT Configu-
ration Register to re-enable both transmit and receive, if the host used this bit to shut down transmit and receive
for an earlier MC4 or MC20 command. Note: Resetting the RTINHA or RTINHB shutdown bit cannot restore
bus transmit capability if the TXINHA or TXINHB input pin is asserted,
OR
2. reset the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to re-enable transmit if the host
used this pin to shut down transmit only for an earlier MC4 or MC20 command.
MC21 EXCEPTIONS:
Invalid command word.
No terminal response,
OR
the message is ignored.
T/R bit equals 0 and
UMCINV bit in the RT
Configuration
No Message Info
Word is written
No Status Word change.
(mode code is undefined
when T/R bit equals 0)
No Change
None
Register equals 1 ***
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Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 0 *
Respond “In form”: Reset
Message Error (ME) status.
If not broadcast, transmit
Status Word. If broadcast,
set the BCR status bit and
suppress status response.
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
DBAC bit set.
BCAST bit
updated.
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
T/R bit equals 0
AND
UMCINV bit in the RT
Configuration
Register equals 0.
The Illegalization Table
bit equals 1 **
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
DBAC bit set.
BCAST bit
updated.
ILCMD
IWA
IBR
DPB bit toggles.
MERR bit set.
Mode code command
word not followed by a Set the Message Error
contiguous data word
(missing data word)
No Status Word transmit.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
WCTERR bit set.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
(ME) status bit. If broadcast,
set the BCR status bit.
MERR bit set.
Mode code command
word followed by data
word with Manchester
encoding or parity error
(bad data word)
No Status Word transmit.
Set the Message Error
(ME) status bit. If broadcast,
set the BCR status bit.
DBAC bit set.
BCAST bit
updated.
IWDERR bit set.
BUSID bit updated.
ILCMD bit reset.
MERR
IWA
IBR
DPB bit toggles. RTRT bit reset.
(Other error bits reset.)
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.
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HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
RESERVED MODE
The reserved mode code
CODES MC22 - MC31: commands do not have
Mode code
defined actions.
commands
having mode codes
10110 through 11111
Host must initialize device
to respond using either of
the two following methods:
Mode code is illegalized.
Set Message Error (ME)
status and transmit Status
Word. If T/R bit equals 1,
suppress data word
DBAC bit set.
ILCMD bit set.
ILCMD
IWA
The mode code’s bit
in Illegalization Table
equals 1 **
(RT is using “illegal
command detection”)
BCAST bit reset. MERR bit set.
DPB bit toggles. BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
transmission.
OR
OR
The mode code’s bit
in Illegalization Table
equals 0 *
(RT not using “illegal
command detection,”
respond “in form”)
If T/R bit equals 1,
DBAC bit set.
Normal CS update:
IWA
Reset Message Error (ME)
status. Transmit Status Word
with contiguous data word read
from assigned index or ping-
pong buffer (or from Descriptor
Word 4 if the SMCP option
applies.)
BCAST bit reset. BUSID bit updated.
DPB bit toggles. MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
(All error bits reset.)
If T/R bit equals 0,
Reset Message Error (ME)
status and transmit Status. If
DBAC bit reset.
BCAST bit
updated.
Normal CS update:
BUSID bit updated.
MERR bit reset.
IWA
IBR
broadcast, also set BCR status DPB bit toggles. ILCMD bit reset.
and suppress Status transmit.
Device stores received data
word in assigned index or ping-
pong buffer (or in Descriptor
Word 4 if SMCP Simplified
Mode Command Processing
applies).
RTRT bit reset
(All error bits reset.)
MC22 - MC31
EXCEPTIONS:
No terminal response, the
Invalid command word. message is ignored.
No Status Word change.
No Message Info
Word is written
No Change
None
MERR bit set.
T/R bit equals 0 and
mode code command
word is not followed by (ME) status bit.
a contiguous data word If broadcast, set the
(missing data word)
No Status Word transmit.
Set the Message Error
DBAC bit set.
BCAST bit
updated.
WCTERR bit set.
BUSID bit updated.
ILCMD, RTRT bits
MERR
IWA
IBR
DPB bit toggles. reset.
(Other error bits reset.)
BCR status bit.
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HI-6130, HI-6131
Bits Updated
in Descriptor
Control Word
Circumstances for
Received Message
Terminal Response to
Received Command
Bits Updated in Data
Buffer Msg Info Word Options
Interrupt
T/R bit equals 0 and
command word is
followed by data word
with Manchester or
parity error (bad data
word)
MERR bit set.
IWDERR bit set.
No Status Word transmit.
Set the Message Error
(ME) status bit.
If broadcast, set the
BCR status bit.
DBAC bit set.
BCAST bit
updated.
MERR
BUSID bit updated.
IWA
ILCMD, RTRT bits
IBR
DPB bit toggles. reset.
(Other error bits reset.)
MERR, WCTERR bits
set.
BUSID bit updated.
ILCMD, RTRT bits
reset.
T/R bit equals 1 and
mode code command
word is followed by a
contiguous data word
No Status Word transmit.
Set the Message Error
(ME) status bit.
DBAC bit set.
BCAST bit reset.
DPB bit toggles.
MERR
IWA
(Other error bits reset.)
MERR bit set.
T/R bit equals 1 and
mode code command
is addressed to RT31
No Status Word transmit.
Set the Message Error
(ME) and BCR status bits.
DBAC bit set.
BCAST bit set.
DPB bit toggles. reset.
(Other error bits reset.)
BUSID bit updated.
ILCMD, RTRT bits
MERR
IWA
IBR
*
Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
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27. ELECTRICAL CHARACTERISTICS
27.1. Absolute Maximum Ratings
Supply voltage (VDD)
Logic input voltage range
-0.3 V to +5.0 V
-0.3 V to +3.6 V
Receiver differential voltage 10 Vp-p
Driver peak output current
Power dissipation at 25°C
Solder Temperature
+1.0 A
1.0 W
275oC for 10 sec.
175oC
Junction Temperature
Storage Temperature
-65oC to +150oC
27.2. Recommended Operating Conditions
Operating Supply voltage
(VDD)
3.3 VDC ± 5%
Operating Temperature Range
Industrial
Extended
-40oC to +85oC
-55oC to +125oC
NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device.
These are stress ratings only. Operation at the limits is not recommended.
27.3. DC Electrical Characteristics
VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Limits
Parameters
Symbol
Test Conditions
Unit
Min
3.15
-
Typ Max
Operating Voltage
VDD
ICC1
3.3
4
3.45
10
V
Not Transmitting
mA
Power Supply Current
Continuous supply current
while one bus transmits
@ 100% duty cycle, 70Ω
resistive load
See Note 1 on next page
ICC2
-
720
760
mA
PD1
PD2
Not Transmitting
-
-
-
60
mW
mW
Power Dissipation
Transmit one bus @ 100%
duty cycle, 70Ω resistive load
See Note 2 on next page
420
550
Min. Input Voltage (High)
Max. Input Voltage (Low)
VIH
VIL
Digital Inputs
Digital Inputs
70%
-
-
-
-
VDD
VDD
30%
Max. Input Current (High):
39 inputs with pull-down.
Digital Inputs (each digital
input pulled high)
IIH
-
-
100
μA
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HI-6130, HI-6131
Limits
Typ Max
Parameters
Symbol
Test Conditions
Unit
Min
Max. Input Current (High):
39 inputs with pull-up.
Digital Inputs (each digital
input pulled high)
IIH
IIL
IIL
+1
-
-
-
-
-100
-
μA
μA
μA
Max. Input Current (Low)
39 inputs with pull-up.
Digital Inputs (each digital
input pulled low)
-
Max. Input Current (Low)
39 inputs with pull-down.
Digital Inputs (each digital
input pulled low)
-1
Min. Output Voltage (High)
Max. Output Voltage (Low)
VOH
VIH
IOUT = -1.0mA, Digital outputs
IOUT = 1.0mA, Digital outputs
90%
-
-
-
-
VDD
VDD
10%
RECEIVER (Measured at Point “AD” in Figure 34 unless otherwise specified)
Input Resistance
RIN
CIN
Differential
Differential
20
-
-
-
-
-
-
-
-
-
-
5
kΩ
Input Capacitance
-
40
-
pF
Common Mode Rejection Ratio
Input Level
CMRR
VIN
-
dB
Differential
9
Vp-p
V-pk
Vp-p
Vp-p
Vp-p
Vp-p
Input Common Mode Voltage
VICM
-5
+5
20.0
0.28
14.0
0.2
Detect
VTHD
VTHND
VTHD
VTHND
1.15
-
Threshold Voltage
(Direct-Coupled)
1 Mhz Sine Wave (Measured
at Point “AD“ in Figure 34)
No Detect
Detect
0.86
-
Threshold Voltage
(Transformer-Coupled)
1 Mhz Sine Wave (Measured
at Point “AT“ in Figure 35)
No Detect
TRANSMITTER (Measured at Point “AD” in Figure 34 unless otherwise specified)
Direct Coupled
VOUT
VOUT
35Ω Load
6.0
-
-
9.0
Vp-p
Vp-p
Output Voltage
70Ω Load (Measured at Point
Transformer Coupled
18.0
27.0
“AT“ in Figure 35)
Output Noise
VON
Differential, inhibited
-
-
-
10.0
90
mVp-p
mV
Direct Coupled
VDYN
35Ω Load
-90
Output Dynamic Offset Voltage
70Ω Load (Measured at Point
Transformer Coupled
VDYN
-250
-
250
mV
“AT“ in Figure 35)
Output Resistance
Output Capacitance
ROUT
COUT
Differential, not transmitting
1 MHz sine wave
10
-
-
-
-
kΩ
15
pF
Note 1: In actual use, the highest practical transmit duty cycle is 96%, occurring when a Remote Terminal responds to a series
of 32 data word transmit commands (RT to BC) repeating with minimum intermessage gap of 4μs (2μs dead time) and typical HI-
6110 RT response delay of 5μs.
Note 2: While one bus continuously transmits, the power delivered by the 3.3V power supply is 3.3V × 720mA typical = 2.4W. Of
this, 420mW is dissipated in the device, the remainder in the load.
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27.4. AC Electrical Characteristics ― HI-6131 Host Bus Interface Timing
VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Limits
Parameters
Symbol
Units
Min
Typ
Max
HI-6131 INTERFACE TIMING (SPI Host Bus Interface)
SCK clock Period
tCYC
tCES
tCEH
tCPH
tDS
50
25
25
100
10
10
25
100
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE set-up time to first SCK rising edge
CE hold time after last SCK falling edge
CE inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK high time
-
-
-
tDH
-
tSCKH
tSCKL
tDV
-
SCK low time
-
SO valid after SCK falling edge
SO high-impedance after CE inactive
20
75
tCHZ
-
SERIAL INPUT TIMING DIAGRAM
t CPH
t CEH
CE
tCES
SCLK
SI
tDS
tDH
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
CE
tSCKH
tSCKL
SCLK
SO
t CHZ
t DV
MSB
LSB
Hi Impedance
Hi Impedance
Figure 29. HI-6131 Host Bus Interface Timing Diagram
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HI-6130, HI-6131
27.5. AC Electrical Characteristics ― HI-6130 Host Bus Interface Timing
Limits
Parameters
Symbol
Units
Min
Typ
Max
WRITE TIMING
READ TIMING
Write strobe
Write inactive time
tWR
tINACT
-
55
25
80
-
-
-
-
-
-
ns
ns
ns
Write cycle, tWR + tINACT
Wait assertion time
Wait time
tWAS
tW
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
130
Read strobe, sequential address, 8-bit bus mode
Read strobe, sequential address, 16-bit bus mode
Read strobe, non-sequential address
tSR8
tSR16
tNSR
tINACT
55
65
110
25
-
-
-
-
Read inactive time
Read cycles in 8-bit bus mode (see note below)
Read cycle, sequential address, 8-bit bus mode, tSR8 + tINACT
-
-
80
-
-
-
-
ns
ns
Read cycle, non-sequential address, 8-bit bus mode, tWAS + tW + tSR8 + tINACT
Read cycles in 16-bit bus mode (see note below)
230
Read cycle, sequential address, 16-bit bus mode, tSR16 + tINACT
Read cycle, non-sequential address, 16-bit bus mode, tWAS + tW + tSR16 + tINACT
-
-
90
-
-
-
-
ns
ns
240
NOTE: When reading a series of sequential addresses, the read cycle for the first word (or byte) location is always longer because
the HI-6130 asserts the WAIT output. As long as sequential addresses are then read, automatic prefetch speeds up read access
for following words (or bytes) since these occur without WAIT assertion.
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HI-6130, HI-6131
HOST WRITE IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
using BTYPE = 1 (“Intel Style” - OE Output Enable and WE Write Enable)
showing 2 bytes written for a single 16-bit word
ADDRESS
A15:1
A0 LB
CS
OE
tINACT
OE or WE
assertion
for the next
tWR
tWR
tINACT
WE
Read or Write
WAIT
D7:0
BYTE 0
BYTE 1
All timing intervals equal 0 ns MIN unless otherwise indicated.
HOST WRITE IN WORD MODE (16-BIT BUS WIDTH)
using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable)
showing a one-word write cycle. Successive writes to sequential addresses have same timing.
ADDRESS
A15:1
CS
OE
tINACT
OE or WE
assertion
for the next
Read or Write
tWR
WE
WAIT
D15:0
WORD
All timing intervals equal 0 ns MIN unless otherwise indicated.
Figure 30. Register and RAM Write Operations for BTYPE = 1
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HI-6130, HI-6131
HOST WRITE IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select)
showing 2 bytes written for a single 16-bit word
ADDRESS
A15:1
A0 LB
CS
R / W
tWR
tWR
STR assertion
for the next
Read or Write
tINACT
tINACT
STR
WAIT
D7:0
BYTE 0
BYTE 1
All timing intervals equal 0 ns MIN unless otherwise indicated.
HOST WRITE IN WORD MODE (16-BIT BUS WIDTH)
using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select)
showing a one-word write cycle. Successive writes to sequential addresses have same timing.
ADDRESS
A15:1
CS
R / W
tWR
STR assertion
for the next
Read or Write
tINACT
STR
WAIT
D15:0
WORD
All timing intervals equal 0 ns MIN unless otherwise indicated.
Figure 31. Register and RAM Write Operations for BTYPE = 0
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HI-6130, HI-6131
HOST READ IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable)
showing 2 bytes read for a single 16-bit word
ADDRESS
A15:1
A0 LB
CS
WE
tINACT
WE or OE
assertion
for the next
Write or Read
tNSR
tSR8
tINACT
OE
tWAS
WAIT
D7:0
tW
BYTE 0
BYTE 1
High-Z
High-Z
High-Z
All timing intervals equal 0 ns MIN unless otherwise indicated.
After first byte is read, prefetch allows faster access times for successive reads, as long as addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
HOST READ IN WORD MODE (16-BIT BUS WIDTH)
using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable)
showing two successive words read from sequential addresses
ADDRESS
ADDRESS + 1
A15:1
CS
WE
OE
tINACT
WE or OE
assertion
for the next
Write or Read
tNSR
tSR16
tINACT
tWAS
WAIT
D15:0
tW
WORD
WORD
High-Z
High-Z
High-Z
All timing intervals equal 0 ns MIN unless otherwise indicated.
After first word is read, prefetch allows faster access times for successive reads, as long as addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
Figure 32. Register and RAM Read Operations for BTYPE = 1
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HI-6130, HI-6131
HOST READ IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select)
showing 2 bytes read for a single 16-bit word
ADDRESS
A15:1
A0 LB
CS
R / W
tINACT
tNSR
tSR8
STR assertion
for the next
Read or Write
tINACT
STR
WAIT
D7:0
tWAS
tW
BYTE 0
BYTE 1
High-Z
High-Z
High-Z
All timing intervals equal 0 ns MIN unless otherwise indicated.
After first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
HOST READ IN WORD MODE (16-BIT BUS WIDTH)
using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select)
showing two successive words read from sequential addresses
ADDRESS
ADDRESS + 1
A15:1
CS
R / W
STR
tINACT
tNSR
tSR16
tINACT
STR assertion
for the next
Read or Write
tWAS
WAIT
D15:0
tW
WORD
WORD
High-Z
High-Z
High-Z
All timing intervals equal 0 ns MIN unless otherwise indicated.
After first word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
Figure 33. Register and RAM Read Operations for BTYPE = 0
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HI-6130, HI-6131
28. MIL-STD-1553 BUS INTERFACE
TRANSMITTER
BUSA/B
1:2.5
55Ω
55Ω
Tx Data from
Manchester
Encoder
35Ω
Point “AD”
BUSA/B
Isolation
Transformer
TXINHA/B
RECEIVER
2.5:1
55Ω
55Ω
Rx Data to
Manchester
Decoder
Point “AD”
35Ω
Isolation
Transformer
Figure 34. MIL-STD-1553 Direct Coupled Test Circuits
Point
“AT”
TRANSMITTER
BUSA/B
52.5Ω
(.75 Zo)
1:2.5
1:1.4
Tx Data from
Manchester
Encoder
35Ω (.5 Zo)
BUSA/B
52.5Ω
(.75 Zo)
Isolation
Transformer
Coupling
Transformer
TXINHA/B
Point
“AT”
RECEIVER
52.5Ω
(.75 Zo)
1.4:1
2.5:1
Rx Data to
Manchester
Decoder
35Ω (.5 Zo)
52.5Ω
(.75 Zo)
Coupling
Transformer
Isolation
Transformer
Figure 35. MIL-STD-1553 Transformer Coupled Test Circuits
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29. THERMAL CHARACTERISTICS
Junction Temp, Tj (oC)
Part Number
Package Style
Condition
θja (oC/W)
TA = 25oC TA = 85oC TA = 125oC
Mounted on
circuit board
HI-6130PQx
HI-6131PQx
100-pin PQFP
64-pin PQFP
52.7
47.75
31.1
56
53
41
37
116
113
101
97
156
153
141
137
Mounted on
circuit board
Heat sink pad
unsoldered
HI-6131PCx
64-pin QFN
Heat sink pad
soldered
22.8
30. ADDITIONAL PIN / PACKAGE CONFIGURATIONS
Notes:
1. All VCC, VCCP and GND pins must be connected.
2. See page 1 for HI-6130, 100-Pin PQFP Package Configuration.
30.1. HI-6131PCx (64-pin QFN)
BCTRIG - 1
48 - BENDI
47 - TEST
RAMEDC - 2
46 - RT1LOCK
45 - MTSTOFF
44 - BCENA
43 - BUSA
CE - 3
MODE - 4
SI - 5
SCK - 6
42 - VCCP
SO - 7
41 - BUSA
VCC - 8
HI-6131PCx
MCLK - 9
GND - 10
RT1A_0 - 11
RT1A_1 - 12
RT1A_2 - 13
MR - 14
40 - BUSB
39 - VCCP
38 - BUSB
37 - RT2ENA
36 - RT2A_0
35 - RT2A_1
34 - RT2A_2
33 - RT2A_3
RT1A_3 - 15
RT1A_4 - 16
TOP VIEW
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HI-6130, HI-6131
30.2. HI-6131PQx (64-pin PQFP)
48 - BENDI
47 - TEST
46 - RT1LOCK
45 - MTSTOFF
44 - BCENA
43 - BUSA
BCTRIG - 1
RAMEDC - 2
CE - 3
MODE - 4
SI - 5
SCK - 6
42 - VCCP
41 - BUSA
40 - BUSB
39 - VCCP
SO - 7
VCC - 8
HI-6131PQx
MCLK - 9
GND - 10
RT1A_0 - 11
RT1A_1 - 12
RT1A_2 - 13
MR - 14
38 - BUSB
37 - RT2ENA
36 - RT2A_0
35 - RT2A_1
34 - RT2A_2
33 - RT2A_3
RT1A_3 - 15
RT1A_4 - 16
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30.3. HI-6132Cxx (121BGA, 121LGA or 121PGA)
Top View
11
10
9
8
7
6
5
4
3
2
1
RAM DATA DATA DATA DATA
RT1 MTPKT RT1
B
TYPE
nIRQ
BENDI
L
K
J
L
K
J
EDC
14
11
9
4
SSF
RDY
MC8
DATA DATA AUTO DATA
AC-
TIVE
ACK DATA
IRQ
nCE
VDD
WPOL DNC
12
10
EN
6
2
BC
TRIG
DATA
13
TX
INHA
DATA DATA
7
DATA
0
DATA
DNC
1
MODE
MISO
READY TEST
5
DATA
15
TX
INHB
DATA DATA
8
RT2 MTST RT1
MOSI
GND
DNC
H
G
F
H
G
F
3
MC8
OFF LOCK
BC
VDD
BUS
A
BUS
A
nWAIT SCLK nRE
BUS
VDD
GND
VDD
GND
ENA
nBUS nBUS
B
nWE
MCLK GND
VDD
GND
nECS
GND
GND
VDD
VDD
GND
GND
VDD
VDD
nSPI
A
RT1
A2
RT1
A0
RT1
VDD
A1
RT2
ENA
BUS nBUS
B
E
D
C
B
A
E
D
C
B
A
B
RT1
A3
RT1 ADDR
A4
ADDR RT2
RT2
A0
RT2
A1
BUS
B
nMR
GND
8
10
LOCK
ADDR RT1 ADDR
ENA
E
MOSI
EE
MT
RT2
A2
RT2 ADDR
A3 14
DNC
DNC
BWID
1
0
2
COPY RUN
ADDR ADDR ADDR ADDR
TT
RT2 ADDR ADDR
SSF
VDD ESCK
1
3
4
6
CLK
13
15
ADDR RT1
E
ADDR MTT ADDR ADDR RT2
ADDR
12
RT2
A4
5
AP
MISO
7
CLK
9
11
AP
11
10
9
8
7
6
5
4
3
2
Notes:
a. DNC: Do Not Connect.
b. All connections denoted VDD must be connected to 3.3V DC power.
c. All 10 connections denoted GND must be connected to circuit ground.
d. BUS/nSPI (F10) selects 16-bit wide parallel bus or SPI operation (see Section “6.5. Selection of Host Interface
(HI-6132 only)” on page 24).
e. nCE: The chip enable signal is shared between 16-bit parallel and SPI host interfaces (SPI Slave Select).
f. One column #1 pad (nBUSA) and three column #2 pads (BUSA, BUSB, nBUSB) connect to the external
transformers. These conduct high current when the device is transmitting. The three column #2 bus pins may
connect through designated column #1 pads to achieve conductor width having sufficient current handling
capacity. Since nBUSA is an outside pad, just a single pad is needed.
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31. ORDERING INFORMATION
HI - 6130 PQ x F
PART NUMBER LEAD FINISH
100% Matte Tin (Pb-free, RoHS compliant)
F
PART NUMBER TEMPERATURE RANGE
FLOW BURN IN
I
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
I
No
No
T
M
T
M
Yes
PART NUMBER PACKAGE DESCRIPTION
PQ 100 PIN PLASTIC QUAD FLAT PACK, PQFP (100PQS)
HI - 6131 Px x x
PART NUMBER LEAD FINISH
Blank
F
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
PART NUMBER TEMPERATURE RANGE
FLOW BURN IN
I
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
I
No
No
T
M
T
M
Yes
PART NUMBER PACKAGE DESCRIPTION
PC
PQ
64 PIN PLASTIC CHIP-SCALE PACKAGE, 9 x 9mm QFN (64PCS)
64 PIN PLASTIC QUAD FLAT PACK, PQFP (64PQTS)
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HI-6130, HI-6131
HI - 6132 Cx x
PART NUMBER TEMPERATURE RANGE
FLOW BURN IN
I
-40oC to +85oC
-55oC to +125oC
I
No
No
T
T
PART NUMBER PACKAGE DESCRIPTION
CG
CP
121 LAND GRID ARRAY - LGA (121LGA) (Pb-free, RoHS compliant)
121 PIN GRID ARRAY - PGA (121PGA) (Pb-free, RoHS compliant)
121 BALL GRID ARRAY - BGA (121BGA), non-collapsing high melt
temperature Pb90 / Sn10 solder balls.
CB
CF
121 BALL GRID ARRAY - BGA (121BGA), non-collapsing polymer-core
Sn96.5 / Ag3.5 solder balls. (Pb-free, RoHS compliant).
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32. REVISION HISTORY
Revision
Date
Description of Change
DS6130, Rev. New.
8/10/11
Initial Release
Corrected numerous typographical errors. Updated cross references.
Corrected IMT Message Filter Tables 11 and 12. Corrected Monitor Address List for
IMT Mode, Table 13.
Rev. A.
9/19/11
Correct numerous RAM address errors.
Added section on Hardware Reset and Initialization
Clarified text descriptions in Sections “Monitor Terminal (MT) Address List” and
“Monitor Terminal (MT) Data Buffers” (previously called “Monitor Terminal (MT)
Stack Address Table” and “Monitor Terminal (MT) Command and Data Stacks”
respectively.
Replaced Section 9.3 with new Sections “9.3. Overview of Interrupts” and “9.4.
Hardware Interrupt Behavior”.
Updated Section “9.5. Interrupt Count & Log Address Register (0x000A)”.
Added Section 9.6 ”Interrupt Log Buffer” on page 38. Corrected and moved
Figure 15 to Section 9.6 (now Figure 3). Deleted previous Section 19.4 “Interrupt
Log Buffer”.
Updated Section “11.15. Bus Controller Interrupt Registers and Their Use”.
Updated Section “13.14. SMT Bus Monitor Interrupt Registers and Their Use”.
Updated Section “16.19. IMT Bus Monitor Interrupt Registers and Their Use”.
Rev. B.
3/14/12
Updated Section “18.14. RT1 and RT2 Remote Terminal Interrupt Registers and
Their Use”.
Corrected errors in description of bits 7, 6, and 5 in Section “18.1. Remote Terminal
1 (RT1) Configuration Register (0x0017)
Remote Terminal 2 (RT2) Configuration Register (0x0020)”. Added register
diagram.
Replaced the word “stack(s)” with “buffer(s)” throughout the document.
Clarified text descriptions in Sections “Standard Mode Command Processing” and
“Simplified Mode Command Processing”.
Corrected reference to MTENA input pin throughout the document. Should be
called MTRUN input pin.
Corrected typographical errors.
Added hermetically sealed ceramic package option, HI-6132.
Updated cross references and Table of Contents.
Updated table in Section “27.5. AC Electrical Characteristics ― HI-6130 Host Bus
Interface Timing”.
Rev. C.
Rev. D.
3/25/12
5/22/12
Remove BGA package option. Add LGA and PGA options.
Insert values for “tbd” in Thermal Characteristics table.
In Section “11.6. Bus Controller (BC) Condition Code Register (Read 0x0037)” on
page 83, BADMSG was incorrectly labelled bit 13 instead of 12.
In Section “18.1. Remote Terminal 1 (RT1) Configuration Register (0x0017)
Remote Terminal 2 (RT2) Configuration Register (0x0020)” on page 144,
ALTBITW and AUTOBSD.
corrected text descriptions for bits
Clarified certain descriptions in Appendix, Section 26.
Update PQFP-64 and QFN-64 package dimemsions.
HOLT INTEGRATED CIRCUITS
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HI-6130, HI-6131
Revision
Date
Description of Change
Corrected ordering information for HI-6132 variant.
Added new Section, “23.2. Memory Test Fail Address Register (0x0024)”.
Added new Section, “24. Self-Test”.
Added Self-Test Registers and Memory Test Fail Address Register to “Table 5.
Register Summary”.
Rev. E.
11/9/12
Made numerous clarifications and typo corrections throughout datasheet.
Corrected typos on HI-6132Cxx pin-out (pins D7, B3, A2).
Updated ordering information table for HI-6132Cxx.
Corrected pinout of HI-6132Cxx package varients (121BGA, 121LGA and 121PGA).
Corrected other minor typographical errors.
Rev. F.
12/5/12
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HI-6130, HI-6131
33. PACKAGE DIMENSIONS
HI-6130: 100-PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 100PQS
.0197
BSC
(0.50)
.630
(16.0)
.551
(14.0)
BSC SQ
BSC SQ
.009 ± .002
(.22 ± .05)
.024 ± .006
(.60 ± .15)
.039
(1.0)
typ
.008
(0.20)
min
See Detail A
.008
(0.20)
R max
.059 ± .004
(1.50 ± .10)
.055 ± .002
(1.40 ± .05)
0°
7°
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.003
(0.08)
R min
Detail A
HI-6131: 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
inches (millimeters)
Package Type: 64PCS
Heat sink pad on bottom of package.
Heat sink must be left floating or connected to VDD
DO NOT connect to GND.
.
.354
(9.00)
BSC
.27 ± .006
(6.80 ± .15)
.0197
BSC
(0.50)
.354
(9.00)
.27 ± .006
(6.80 ± .15)
BSC
Top View
Bottom
View
.010
typ
(0.25)
.016 ± .004
(0.40 ± .10)
.008
typ
(0.20)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.039
(1.00)
max
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HI-6130, HI-6131
HI-6131: 64 PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 64PQTS
.02
(0.50)
BSC
.394
(10.00)
.473
(12.00)
BSC SQ
BSC SQ
.009 ± .002
(0.22 ± .05)
.024 ± .006
(.6 ± .15)
0.039
(1.0)
.055 ± .002
(1.40 ± .05)
.006
(0.15)
R max
0°
See Detail A
.063
(1.60)
max
7°
.0063
(0.16)
R min
.004 ± .002
(0.10 ± .05)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
inches (millimeters)
Package Type: 121LGA
HI-6132: 121 Land Grid Array (LGA)
Top View
Bottom View
.075 ± .008
(1.905 ± .203)
.590 (14.986)
10 EQ. SP. @ .050 (1.27)
= 0.5 (12.7)
CERAMIC PACKAGE
L
L
K
K
J
METAL COVER
J
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
.008
121x Ø = 0.0338 (0.859)
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HI-6130, HI-6131
HI-6132: Pin Grid Array
(121PGA)
Top View
Bottom View
.500
.075±.008
.590
10X .050
CERAMIC PACKAGE
METAL COVER
L
L
K
J
K
J
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9 10 11
.008
+0.0020
–0.0019
121X Ø.0338
Ø.012 M
Ø.006 M
C A B
C
121X .120
Dimensions in inch
inches (millimeters)
Package Type: 121BGA
HI-6132: 121 Ball Grid Array (BGA)
Top View
Bottom View
.075 ± .008
(1.905 ± .203)
.590 (14.986)
10 EQ. SP. @ .050 (1.27)
= 0.5 (12.7)
CERAMIC PACKAGE
L
L
K
K
J
METAL COVER
J
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
.008
121x Ø = 0.0338 (0.859)
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