HI-8151PQIF [HOLTIC]
CMOS High Voltage Display Driver; CMOS高电压显示驱动器
| 型号： | HI-8151PQIF |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | CMOS High Voltage Display Driver |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8050/51, HI-8150/51
CMOS High Voltage
Display Driver
November 2007
GENERALDESCRIPTION
APPLICATIONS
!
Dichroic Liquid Crystal Displays
Standard Liquid Crystal Displays
5 Volt Serial Data to Parallel High Voltage
MEMS Drivers
The HI-8050, HI-8051, HI-8150 and HI-8151 are CMOS
integrated circuits designed for high voltage LCD display
drive applications. The HI-8050 & HI-8051 have TTL logic
inputs whereas the HI-8150 & HI-8151 have CMOS logic
inputs. They drive up to 38 segments at voltages between
+5 and -30 volts. The optional voltage converter on the
HI-8050 & HI-8150 can be used to generate the negative
display drive voltage. All products have test inputs to
facilitate opens and shorts testing as well as automatic
blanking of the display if the +5V power is lost.
!
!
!
PAD CONFIGURATION (Top View)
BPIN
BPOSC
VDD
N/C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
S27
S26
S25
S24
S23
S22
S21
S20
DOUT38
DOUT32
DOUT30
T2
T1
N/C
The HI-8050 and HI-8150 are designed to replace the
HI-8010 and HI-8020 devices in all 5 volt applications. They
offer significantly enhanced ESD protection along with a
considerably faster serial input data rate.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CONVOSC
CONVOUT
VEE
HI-8050PQI
HI-8150PQI
HI-8050PQT
&
S37
S38
S1
S2
S3
S4
S5
S6
The data is serially clocked into the device on the negative
edge of the clock and latched in parallel to the segment
outputs on the high to low transition of the load input. Serial
output data changes on the positive edge of the clock
allowing the cascading of multiple drivers for larger dis-
plays.
HI-8150PQT
BPOUT
N/C
S7
The device layout supports all previous pinouts of the
HI-8010/HI-8020 products. In addition, new technology
and features afford new packaging options. Consult your
Holt Sales Representative to explore the possibilities.
64 Pin plastic PQFP
(See page 6 for HI-8051 & HI-8151pin configurations)
FEATURES
FUNCTIONAL BLOCK DIAGRAM
! 4 MHz serial input data rate
! 38 segment outputs
DATA IN
DIN Þ
CL Þ
DOUT38
DOUT32
DOUT30
38 Stage
Shift Register
Þ
! Cascadable
CS Þ
CLK
LE
CONTROL
LOGIC
! 5 Volt inputs translated to 35 Volts
8020OPT Þ
38 Bit Latch
! Test pins allow hardware all "ON", all "OFF" or
alternating
LD Þ
Oscillator
Divider
BPIN Þ
BPOSC Þ
! Monitors 5 volt supply and forces all
segments to "OFF" condition if lost
Voltage
Translators
Voltage
Translator
! Negative voltage converter available on-chip
! CMOS low power
High Voltage
Drivers
High Voltage
Buffer
! Military processing available
38 SEGMENTS
Þ BPOUT
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8050, Rev. F)
11/07
HI-8050/51, HI-8150/51
PIN DESCRIPTION TABLE
SIGNAL
VSS
FUNCTION
DESCRIPTION
POWER
0 Volts
8020OPT
LOGIC INPUT Open or high logic level selects the HI-8010/HI-8110 CL / CS logic. A low
selects the HI-8020/HI-8120 Logic (HI-8050 & HI-8150 only)
CS
CL
LOGIC INPUT Chip select - Active low
LOGIC INPUT Serial data input clock - Active low
LD
LOGIC INPUT Latches data in shift register to the segment outputs - Active high
LOGIC INPUT Serial input data to the shift register
DIN
BPIN
INPUT
Backplane frequency input. Either driven from an external source or connected
to BPOSC and an external resistor and capacitor.
BPOSC
VDD
OUTPUT
POWER
INPUT
Internal oscillator pin. Connected to BPIN and an external resistor and capacitor
+5V 5ꢀ, Positive voltage of the backplane and segments
CONVOSC
Used in conjunction with CONVOUT to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
CONVOUT
OUTPUT
Used in conjunction with CONVOSC to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
VEE
S1 to S38
BPOUT
T1
POWER
OUTPUT
OUTPUT
Negative voltage of the backplane and segments - between VSS and VDD - 35V
Segment outputs to LCD display
Backplane output to LCD display (See Figure 3 for cascading drivers)
LOGIC INPUT Used in conjunction with T2 to control display mode. Normal mode is logic low.
LOGIC INPUT Used in conjunction with T1 to control display mode. Normal mode is logic low.
T2
DOUT30
OUTPUT
OUTPUT
OUTPUT
Logic output from the 30th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
DOUT32
DOUT38
Logic output from the 32nd bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
Logic output from the 38th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver.
HOLT INTEGRATED CIRCUITS
2
HI-8050/51, HI-8150/51
FUNCTIONAL DESCRIPTION
DOUT
INPUT LOGIC
The DOUT30, DOUT32, and DOUT38 pins are available for
cascading devices to drive more segments (See Figure 3) and
for verifying the integrity of the shift register data. The outputs
can drive 2 TTL loads. They change on the positive edge of
CL.
The data is clocked into a serial shift register from the DIN in-
put on the negative edge of CL while CS is held low. LD is
normally held low and pulsed high only when data from the
shift register is parallel latched to the segment outputs. CS
must be low when LD is pulsed. The latches are transparent
while LD is high. A logic "1" in the shift register causes the
corresponding segment output to be out of phase with the
BP output. All four logic inputs are TTL compatible on the
HI-8050/51and CMOS compatible on the HI-8150/51.
AUTOMATIC SEGMENTS OFF
A threshold device detects when the 5V supply is below ap-
proximately 1V and forces all the segments and the backplane
to the same level. This feature is used to discharge the VEE
capacitor when the 5V power is switched off, to prolong the life
of the LCD display.
BPOSC and BPIN
The user has the option of creating the backplane frequency
internally or providing a signal from an external source. For
an internal oscillator, BPIN and BPOSC are connected to-
gether and the appropriate R & C combination is applied as
shown in Figure 1. The resulting backplane frequency is ap-
proximately:
8020OPT
The CL and CS inputs function the same as the HI-8010 and
HI-8110 product (See Figure 5) if this pin is left open or held
high. If held low, the two pins function the same as the HI-8020
and HI-8120 product (See Figure 6). This input is available
only on the HI-8050 (TTL) and HI-8150 (CMOS) products.
fBP =
1
256 RC
The value of the resistor must be greater than 30KW.
.
(R = 220KW, C = 220pF, fBP » 100HZ)
TEST INPUTS
Alternatively, BPOSC is left open and an external backplane
signal of the desired frequency is applied to the BPIN input.
The test functions available are:
VEE & NEGATIVE VOLTAGE CONVERTER
T2
0
0
1
1
T1 Display Mode
VEE can be connected to a negative power supply. Alterna-
tively, the HI-8050 & HI-8150 have the option of generating
the VEE voltage with a built-in -25 volt negative voltage con-
verter (See Figure 2). When not used, the open CONVOSC
pin is detected and all power consuming circuitry is dis-
abled. The converter will survive a short between two seg-
ments and still maintain a VEE voltage of -20V.
0
1
0
1
Normal
All Off
All On
Alternating On/Off Segments
The test inputs must be tied to the appropriate logic level for
correct circuit operation. Both test inputs are TTL compatible
on the HI-8050/51 and CMOS compatible on the HI-8150/51.
VDD
68KW
R
C
OSC
CONVOSC
RSENSE
÷ 256
Control
VDD
VDD
Q
IN5818, IN5819
CONVOUT
330µH
R
BPIN
VSS
BPOSC
VEE
C
TO BACKPLANE
TRANSLATOR
AND DRIVER
10µF
VSS
VSS
Figure 2. OPTIONAL VOLTAGE CONVERTER
Figure 1. INTERNAL OSCILLATOR CIRCUIT
HOLT INTEGRATED CIRCUITS
3
HI-8050/51, HI-8150/51
LD
CL
1MW
1µF
1MW
BPOUT
CS
DIN
CS CL LD
DIN DO
CS CL LD
CS CL LD
1µF
1500pF
DIN
DO
DIN
DO
R
V
os
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
C
1MW
1µF
1MW
SEG
n
1µF
360pF
BACK
PLANE
SEGMENTS
SEGMENTS
SEGMENTS
Figure 4. OFFSET MEASUREMENT
Figure 3. RC OSCILLATOR AND CASCADED
DEVICES
DATA IN
DATA IN
DIN Þ
DIN Þ
DOUT
Þ
38 Stage
Shift Register
38 Stage
Shift Register
DOUT
Þ
CL Þ
CS Þ
CL Þ
CS Þ
CLK
CLK
Figure 5. HI-8010/HI-8110 CL & CS LOGIC
(8020OPT = OPEN or HIGH)
Figure 6. HI-8020/HI-8120 CL & CS LOGIC
(8020OPT = LOW)
CL
INPUT
tCL
DIN
INPUT
VALID
VALID
tDS
tDH
CS
INPUT
tCSS
tLCS
tLS
tCSH
tCSL
LD
INPUT
tLS
tLW
tCDO
DOUT
OUTPUT
VALID
VALID
VALID
Figure 7. TIMING DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-8050/51, HI-8150/51
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V
Supply Voltage VDD ..........................0V to 7V Operating Temperature Range(Industrial) ....... -40°C to +85°C
VEE................VDD-35V to 0V (Hi-Temp/Mil) ..... -55°C to +125°C
Voltage at any input, except BPIN..-0.3V to VDD+0.3V Storage Temperature ..................................... -65°C to +125°C
Voltage at BPIN input ..............VDD-35V to VDD+0.3V
DC current per input pin .....................................10 mA
Power Dissipation............................................500 mW
Solder Temperature (Leads) ..................... +280°C for 10 sec.
(Package) ........................................ +220°C
Junction Temperature, Tj .......................................... £+175°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V 5ꢀ, VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
7.0
UNITS
V
Operating Voltage
Supply Current:
(Static, No Load, Converter Off, fBP = 0Hz)
VDD
3.0
@ +85°C
@ +125°C
@ +125°C
Logic Inputs
Logic Inputs
Logic Inputs
Logic Inputs
200
µA
µA
µA
V
IDD
300
IEE
VILTTL
VIHTTL
VILCMOS
VIHCMOS
VILX
VIHX
IIN1
120
Input Low Voltage, HI-8050/51 only (except BPIN)
Input High Voltage, HI-8050/51 only (except BPIN)
Input Low Voltage, HI-8150/51 only (except BPIN)
Input High Voltage, HI-8150/51 only (except BPIN)
Input Low Voltage, BPIN
0
2
0.8
VDD
0.3 VDD
VDD
0.6 VDD
VDD
100
V
0
V
0.7 VDD
VEE
0.8 VDD
V
V
Input High Voltage, BPIN
V
Input Current
(except T1 & T2)
(T1 & T2)
VIN = 0V to 5V
VIN = 0V to 5V
nA
µA
pF
KW
W
Input Current
IIN2
10
Input Capacitance
(Guaranteed, not tested)
CI
10
15
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
RSEG
RBP
IL = 10µA
IL = 10µA @ 25°C
VOH = 4.5
10
450
600
-3.0
Source Current
Sink Current
@ No Load
IDOH
IDOL
VEEC
IDD
mA
mA
V
VOL = 0.4
3.2
-22
Voltage Converter:
See Fig. 2
-21.5
-21
1.8
(VDD - VSS = 5V, TA = 25°C)
@ 0.1mA Load
@ 10KW Load
See Fig. 2
mA
V
VEEC
VOS
See Fig. 2
-20
Offset Voltage
(Guaranteed, not tested)
See Fig. 4
25
mV
HOLT INTEGRATED CIRCUITS
5
HI-8050/51, HI-8150/51
AC ELECTRICAL CHARACTERISTICS (See Figure 7)
VDD = 5V 5ꢀ , VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
VDD
MIN
TYP
MAX
UNITS
Clock Period
non-cascaded
cascaded
tCL
tCL
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
250
500
125
250
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Pulse Width
non-cascaded
cascaded
tCW
tCW
tDS
Data In - Setup
Data In - Hold
tDH
80
Chip Select - Setup to Clock
Chip Select - Hold to Clock
Load - Setup to Clock
Chip Select - Setup to Load
Load Pulse Width
tCSS
tCSH
tLS
100
120
120
0
tCSL
tLW
130
120
Chip Select - Hold to Load
Data Out Valid, from Clock
tLCS
tCDO
170
HI-8051 & HI-8151 PIN CONFIGURATIONS
(See page 1 for HI-8050 & HI-8150 pin configurations)
LD
DIN
BPIN
BPOSC
VDD
S37
S38
S1
1
2
3
4
5
6
7
8
9
10
11
12
13
S26
S25
S24
S23
S22
S21
S20
DOUT 38
N/C
T2
T1
BPOUT
S19
39
38
37
36
35
34
33
32
31
30
29
28
27
HI-8051PQI
HI-8151PQI
HI-8051PQT
&
S2
S3
S4
S5
HI-8151PQT
S6
52 Pin Plastic PQFP
HOLT INTEGRATED CIRCUITS
6
HI-8050/51, HI-8150/51
ORDERING INFORMATION
HI - 8x5xPQ x x
PART
NUMBER
LEAD
FINISH
Blank
F
Tin / Lead (Sn / Pb) Solder
100ꢀ Matte Tin (Pb-free RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
FLOW
I
-40°C TO + 85°C
-55°C TO +125°C
I
No
No
T
T
PART
NUMBER
INPUT
LEVELS
PACKAGE
DESCRIPTION
HI-8050PQ
HI-8051PQ
HI-8150PQ
HI-8151PQ
TTL
TTL
64 PIN PLASTIC THIN FLAT QUAD PACK PTQFP (64PTQS)
52 PIN PLASTIC QUAD FLAT PACK PQFP (52PQS)
64 PIN PLASTIC THIN FLAT QUAD PACK PTQFP (64PTQS)
52 PIN PLASTIC QUAD FLAT PACK PQFP (52PQS)
CMOS
CMOS
HOLT INTEGRATED CIRCUITS
7
HI-8050/51, HI-8150/51 PACKAGE DIMENSIONS
52-PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 52PQS
.0256
(.65)
BSC
.520
(13.2)
.394
(10.0)
BSC SQ
BSC SQ
.012 .003
(.30 .08)
.035 .006
(.88 .15)
.063
(1.6)
typ
.008
(.20)
min
See Detail A
.008 .003
(.215 .085)
R min
.084 .013
(2.13 .32)
.079 .008
(2.00 .20)
0° £ Q £ 7°
.005
(.13)
R min
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
DETAIL A
64 PIN PLASTIC THIN QUAD FLAT PACK (TQFP)
inches (millimeters)
Package Type: 64PTQS
.0157
(0.40)
BSC
.276
(7.00)
.354
(9.00)
BSC SQ
BSC SQ
.007 .004
(0.18 .05)
.024 .006
(0.60 .15
.055 .002
(1.4 .05)
.008
(0.20)
R max
See Detail A
.063
(1.60)
max
0° £ Q £ 7°
.003
(0.08)
R min
.004 .002
(0.10 .05)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
HOLT INTEGRATED CIRCUITS
8
相关型号：
©2020 ICPDF网 联系我们和版权申明