HX6136FSNC [HONEYWELL]

FIFO, 1KX36, 30ns, Synchronous, CMOS, CQFP132, CERAMIC, QFP-132;


型号：	HX6136FSNC
厂家：	Honeywell
描述：	FIFO, 1KX36, 30ns, Synchronous, CMOS, CQFP132, CERAMIC, QFP-132 时钟先进先出芯片内存集成电路
文件：	总16页 (文件大小：879K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FIFO – HX6409/HX6218/HX6136

First-In First-Out Memory

HX6409/HX6218/HX6136

The HX6409, HX6218, and HX6136 are high speed,

low power, first-in first-out memories with clocked read

and write interfaces. The HX6409 is a 4096-word by 9-

bit memory array; the HX6218 is a 2048-word by 18-bit

memory array; and the HX6136 is a 1024-word by 36-

bit memory array. The FIFOs support width expansion

while depth expansion requires external logic control

using state machine techniques. Features include

programmable parity control, an empty/full flag, a

quarter/three quarter full flag, a half full flag and an

error flag.

together for single-clock operation or the two clocks

may be run independently for asynchronous read/write

applications. Clock frequencies up to 28 MHz are

achievable in the three configurations.

Honeywell’s FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data

acquisition,

multiprocessor

interfaces,

and

communications buffering.

Honeywell’s enhanced SOI RICMOS™ IV (Radiation

Insensitive CMOS) technology is radiation hardened

through the use of advanced and proprietary design,

layout and process hardening techniques. The FIFO is

Input ports are controlled by a free running clock (CKW)

and a write-enable pin ENW . When ENW is

asserted, data is written into the FIFO on the rising

edge of the CKW signal. While ENW is held active,

data is continually written into the FIFO on each CKW

cycle.

fabricated

with

Honeywell’s

radiation-hardened

technology, and is designed for use in systems

operating in radiation environments. The SOI

RICMOS™ IV process is a 5-volt, SOI CMOS

technology with a 150 Å gate oxide and a minimum

drawn feature size of 0.8µm, (0.65µm effective gate

length—L_eff). Additional features include tungsten via

plugs, Honeywell’s proprietary SHARP planarization

process, and a lightly doped drain (LDD) structure.

The output port is controlled in a similar manner by a

free running read clock (CKR) and a read enable pin

( ENR ). In addition, the three FIFOs have an output

enable pin ( OE ) and a master reset pin ( MR ). The

read (CKR) and write ( CKW ) clocks may be tied

FEATURES

. 1K x 36, 2K x 18, 4K x 9

configurations

. Dynamic and static transient

upset hardness through 1x10⁹

. Empty, full, half full, 1/4 full,

¾ full, error flags

. Fabricated with RICMOS™ IV

Silicon on Insulator (SOI) 0.8

µm process (Leff = 0.65µm)

. Total dose hardness through

1x10⁶rad(Si)

rad(Si)/s

. Parity generation/checking

. Fully asynchronous with

simultaneous read and write

operation

. Dose rate survivability through

1x10¹¹rad(Si)/s

. Soft error rate of <1x10^-10

upsets/bit-day

. Output enable (OE)

. Neutron hardness through

. No latchup

. CMOS or TTL compatible I/O

. Single 5V ±10% power supply

. Various flat pack options

1x10¹⁴cm^-2

. Read/write cycle times

36 ns (-55°to 125°C)

. Expandable in Width

www.honeywell.com/radhard

FIFO – HX6409/HX6218/HX6136

LOGIC BLOCK DIAGRAM

FLAG DECODE TABLE

Word Count

2K x 18

EF _Fault

E / F

QF / TQF

State

4K x 9

1K x 36

Empty fault (Enabled Read

when Empty)

Empty

Less than or equal to ¼ full

1 to 1024

1 to 512

1 to 256

Less than or equal to ½ full

Greater than ½ full

Greater than or equal to ¾ full

Full

1025 to 2048

2049 to 3071

3072 to 4095

4096

513 to 1024

1025 to 1535

1536 to 2047

2048

257 to 512

513 to 767

768 to 1023

1024

Full fault (Enabled Write when

Full)

4096

2048

1024

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FIFO – HX6409/HX6218/HX6136

SIGNAL DEFINITIONS

Signal Name

I/O

Description

Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when

ENW is active and the FIFO is not full.

D: 0 – 35

Data Outputs: Data Outputs are read out of the FIFO memory and updated on the

rising edge of CKR when ENR is active and the FIFO is not Empty. The Data

Outputs are in a high impedance state if OE is not active.

Q: 0 – 35

Enable Write: An active low signal that enables the write of the Data Inputs on the

CKW rising edge (if FIFO is not full).

ENW

ENR

Enable Read: An active low signal that enables the read and update of the Data

Outputs on the CKR rising edge (if FIFO is not empty).

Write Clock: The rising edge clocks data into the FIFO when ENW is low (active).

On the rising edge, this signal also updates the Half Full, ¾ Full, Full, and Full Fault

Flags.

CKW

Read Clock: The rising edge clocks data out of the FIFO when ENR is low (active).

On the rising edge, this signal also updates the ¼ Full, Empty, and Empty Fault Flags.

Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is

greater than half full.

CKR

Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated

on the rising edge of CKW.

E / F

¼ Full or ¾ Full Flag: ¼ Full is updated on the rising edge of CKR, and ¾ Full is

updated on the rising edge of CKW. ¼ Full signifies 256 or less words in the 1K x 36

FIFO and ¾ Full signifies 256 words or less until a full condition.

Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full

Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already

empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault

condition is detected, the Fault Flag remains latched until the empty or full condition is

removed.

QF / TQF

EF _Fault

Master Reset: Active low signal which, when active, resets device to empty condition

Output Enable: Active low signal which, when active, enables low impedance Data

Outputs, Q: 0 – 35

PROGRAMMABLE PARITY OPTIONS

Conditions

Parity Disabled

Generate Even Parity, Q8, Q17, Q26, Q35

Generate Odd Parity, Q8, Q17, Q26, Q35

Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal

Check for Odd Parity, Error on Q8, Q17, Q35, Error is a Low Signal

www.honeywell.com/radhard

FIFO – HX6409/HX6218/HX6136

RADIATION CHARACTERISTICS

Total Ionizing Radiation Dose

All FIFO configurations will meet all stated functional

and electrical specifications over the entire operating

temperature range after the specified total ionizing

radiation dose. All electrical and timing performance

parameters will remain within specifications after

rebound at VDD = 5.5 V and T = 125°C extrapolated to

ten years of operation. Total dose hardness is assured

by wafer level testing of process monitor transistors and

product using 10 KeV X-ray and Co60 radiation

sources. Transistor gate threshold shift correlations

have been made between 10 KeV X-rays applied at a

dose rate of 1x10⁵rad(Si)/min at T = 25°C and gamma

rays (Cobalt 60 source) to ensure that wafer level X-ray

testing is consistent with standard military radiation test

environments.

Each FIFO will meet any functional or electrical

specification after exposure to a radiation pulse o≤f50

ns duration up to 1x10¹¹rad(Si)/s, when applied under

recommended operating conditions. Note the current

conducted by the inputs, outputs and power supply

during the pulse may significantly exceed the normal

operating levels. The application design must

accommodate these effects.

Neutron Radiation

Each FIFO configuration will meet any functional or

timing specification after a total neutron fluence of up to

1x10¹⁴cm^-2applied under recommended operating or

storage conditions. This assumes equivalent neutron

energy of 1 MeV.

Transient Pulse Ionizing Radiation

Soft Error Rate

Each FIFO configuration is capable of writing, reading

and retaining stored data during and after exposure to a

transient ionizing radiation pulse of≤50 ns duration up

to 1x10⁹rad(Si)/s, when applied under recommended

operating conditions. To ensure validity of all specified

performance parameters before, during, and after

radiation (timing degradation during transient pulse

radiation is≤10%), it is suggested that stiffening

capacitance be placed near the package VDD and

VSS, with a maximum inductance between the package

(chip) and stiffening capacitor of 0.7nH per part. If there

are no operate-through or valid stored data

requirements, typical circuit board mounted de-coupling

capacitors are recommended.

This FIFO configuration has a soft error rate (SER)

performance of <1x10^-10upsets/bit-day, under

recommended operating conditions. This hardness

level is defined by the Adams 90% worst-case cosmic

ray environment.

Latchup

This FIFO configuration will not latch up due to any of

the above radiation exposure conditions when applied

under recommended operating conditions. Fabrication

with the SOI substrate with its oxide isolation ensures

latchup immunity.

RADIATION-HARDNESS RATINGS (1)

Parameter

Total Dose

Transient Dose Rate Upset

Transient Dose Rate Survivability

Soft Error Rate

Limits (2)

Units

rad(Si)

rad(Si)/s

Test Conditions

T_A=25°C

Pulse width ≤50ns

>1x10⁶

>1x10⁹

>1x10¹¹

<1x10^-10

>1x10¹⁴

Pulse width ≤50ns, X-ray, VDD=6.0 V, T_A=25°C

T_A=125°C, Adams 90% worst case environment

1 MeV equivalent energy, Unbiased, T_A=25°C

upsets/bit-day

Neutron Fluence

N/cm²

(1) Device will not latch up due to any of the specified radiation exposure conditions.

(2) Operating conditions (unless otherwise specified): VDD= 4.5V to 5.5V, TA = 55˚C to 125˚C.

www.honeywell.com/radhard

FIFO – HX6409/HX6218/HX6136

ABSOLUTE MAXIMUM RATINGS (1)

Rating

Units

˚C

˚C/W

˚C

Symbol

VDD

VPIN

TSTORE

TSOLDER

IOUT

VPROT

ΘJC

Parameter

Supply Voltage Range (2)

Voltage on Any Pin (2)

Storage Temperature (Zero Bias)

Soldering Temperature (5 seconds)

Maximum Power Dissipation (3)

DC or Average Output Current

ESD Input Protection Voltage (4)

Thermal Resistance (Jct-to-Case)

Junction Temperature

Min

-0.5

-65

Max

6.5

VDD+0.5

150

270

2.5

2000

175

(1) Stesses in excess of those listed above may result in permanent damage. These are stress ratings only, and

operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may

affect device reliability.

(2) Voltage referenced to VSS.

(3) FIFO power dissipation (IDDSB + IDDOP) plus FIFO output driver power dissipation due to external loading

must not exceed this specification.

(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC

certified lab.

RECOMMENDED OPERATING CONDITIONS

Description

Symbol

VDD

Parameter

Supply Voltage (referenced to VSS)

Ambient Temperature

Units

˚C

Min

4.5

-55

-0.3

Typ

5.0

Max

5.5

125

VPIN

Voltage on Any Pin (referenced to VSS)

VDD+0.3

CAPACITANCE (1)

Worst Case

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Conditions

VI=VDD or VSS, f=1 MHz

VIO=VDD or VSS, f=1 MHz

Units

Typical ₍₁₎

Min

Max

(1) This parameter is tested during design characterization only.

DATA RETENTION CHARACTERISTICS

Worst Case ₍₂₎

Symbol

Parameter

Typical (1)

Units Test Conditions

Min

Max

VDR

IDR

Data Retention Voltage

Data Retention Current

2.5

µA

ENW = ENR = VDR

500

(1) Typical operating conditions: TA=25ºC, pre-radiation.

(2) Worst case operating conditions: TC=-55ºC to +125ºC, post total dose at 25ºC.

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FIFO – HX6409/HX6218/HX6136

DC ELECTRICAL CHARACTERISTICS

Worst Case (1)

Units

Symbol

VIH

Test Parameters

Conditions

VDD=5.5V

VDD=4.5V

Min

Max

Input High Voltage

CMOS

TTL

CMOS

TTL

0.7xVDD

2.2

Input Low Voltage

0.3xVDD

VIL

0.8

0.4

+1.0

VOH1

VOH2

VOL

High Output Voltage

Low Output Voltage

Input Leakage Current

3.5

VDD-0.4

VDD=4.5V, IOH=-4.0mA

VDD=4.5V, IOH=-100µA

VDD=4.5V, IOL=4.0mA

VDD=5.5V. VIN=0V or VDD

TC=-55ºC to +125ºC

OE ≥VIH,

-1.0

µA

Output OFF, High Z Current

-10.0

+10.0

IOZL

IOZH

VSS<VO<VDD

Standby Power Supply Current (2)

4kx9, 1kx36, 2kx18

Operating Power Supply Current (2)

VIN=0V or VDD

mA CLK(s)=1 MHz

IDDSB

IDDOP

IDDSB

IDDOP

4kx9

2kx18

1kx36

mA VIN=0V or VDD

mA CLK(s)=1MHz

VIN=0V or VDD

mA CLK(s)=27MHz

Standby Power Supply Current (2)

4kx9, 2kx18, 1kx36

Operating Power Supply Current (2)

4kx9

2kx18

1kx36

280

330

500

VIN=0V or VDD

CLK(s)=27MHz

(1) Worst case operating conditions: VDD=4.5 to 5.5V, TC=-55°C to +125°C, post total dose at 25°C.

(2) Standby current for the device includes the Read Clock (CKR) and Write Clock (CKW) only. Both the Read

Enable (ENR) and Write Enable (ENW) are disabled (ENR, ENW = vdd). For operating currents, ENR and ENW

are enabled (=0.0V) and data inputs are switching at one half the clock speed between 0.0V and VDD.

Valid High

Output

2.9V

249 Ω

Valid Low

Output

DUT

Output

C_L> 50 pF

C_L> 5pF (for QZ measurements only)

Tester Equivalent Load Circuit

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FIFO – HX6409/HX6218/HX6136

AC TIMING CHARACTERISTICS (1)

Worst Case ₍₂₎

-55°C to 125°C

Symbol

Test Parameter

Units

Min

Max

TCKW

TCKR

TCKH

TCKL

TOH

TFH

TSD

THD

TSEN

THEN

TOE

TOLZ

TOHZ

TFD

Write Clock Cycle (6)

Read Clock Cycle

Clock High Read

Clock High Write

Clock Low

Data Access Time

Previous Output Data Hold After Rd High

Previous Flag Hold After Rd/Wr High

Data Set-UP

Data Hold

Enable Set-UP

Enable Hold

OE Low to Output Data Valid

OE Low to Output Data in Low Z

OE High to Output Data in High Z

Flag Delay

19.5

TSKEW1 Opposite Clock after Clock (3)

TSKEW2 Opposite Clock before Clock (4)

TPMR

Master Reset Pulse Width (Low)

TOHMR

TMRR

TMRF

TAMR

TSMRP

THMRP

TAP

Data Hold from Master Reset Low

Master Reset Recovery

Master Reset High to Flags Valid

Master Reset High to Data Outputs Low

Parity Program Mode – MR low Set-up to CKW High

Parity Program Mode – MR High Hold from CKW High

Parity Program Mode – Data Access Time

Parity Program Mode – Data Hold Time from MR High

TOHP

(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and

fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing characteristics Table,

capacitive output loading C_L=50pF. For C_L>50pF, derate access times by 0.02 ns/pF (typical).

(2) Worst case operating conditions: VDD=4.5V to 5.5V, TC=-55°C to +125°C, post total dose at 25°C.

(3) For flag updates tskew1 is the minimum time an opposite clock can occur after a clock and still not be included

in the current clock cycle. At less than tskew1, inclusion of the opposite clock is arbitrary.

(4) For flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in

the current clock cycle. At less than tskew2, inclusion of the opposite clock is arbitrary.

(5) Timing parameters are defined in Figures 1 through 6

(6) This parameter is tested during design characterization only.

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FIFO – HX6409/HX6218/HX6136

AC TIMING WAVEFORMS

Figure 1: Write Timing

Tckw

Tckh

Tckl

Enabled WR

Thd

Disabled WR

Then

CKW

Data

Tsd

Tsen

Then

ENW

Flags

Tfh

Tfd

Figure 2: Read Timing

Tckr

Tckh

Tckl

Enabled RD

Disabled RD

CKR

Data

Toh

Tsen

Then

Tsen

Then

ENR

Flags

Tfh

Tfd

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FIFO – HX6409/HX6218/HX6136

Tpmr

Figure 3. Master Reset Timing

Tmrr

First

Write

CKW

ENW

CKR

ENR

See Note (1)

Tohmr

Tamr

All Data

Outputs Low

See Note (2)

Data

Valid Data

Tmrf

Other

Flags

(1) If ENW is held during Master Reset, the parity is disabled.

(2) Outputs will be low after time Tohmr unless in parity programming mode. See figure 7.

Figure 4: Read Flag Update Timing

Latent Cycle

Flag

Update

Enable

Read

Enable

Read

CKR

ENR

Tskew2

Tskew1

Enable

Write

CKW

ENW

high

Tfd

Flags

NOTE: When an empty condition occurs, the empty flag is set. The performance of another

read requires at least one write, on read clock to reset the empty flag and then an enabled

read clock.

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FIFO – HX6409/HX6218/HX6136

Figure 5: Write Flag Update Timing

Latent Cycle

Flag

Update

Enable

Write

Enable

CKW

Write

Tskew2

ENW

Tskew1

Enable

Read

CKR

ENR

Tfd

Flags

NOTE: When a flag condition occurs, the full flag is set. The performance of another write

requires at least one read, one write clock to reset the full flag and then one enabled write

clock.

Figure 6: Output Enable Timing

Read M+1

CKR

ENR

Low

Tohz

Toe

Valid Data Word M

Valid Data Word M+1

Data

Tolz

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FIFO – HX6409/HX6218/HX6136

Figure 7. Parity Programming Mode

Tsmrp

Thrmp

Tckh

Tmrr

Parity

Write

First

Write

CKW

ENW

Tsd

Thd

Data In Last Word

Parity Word

Word

Tap

Tohmr

Valid Data

Tohp

Data Out

Parity Word

TESTER AC TIMING CHARACTERISTICS

TTL I/O Configuration

CMOS I/O Configuration

Input Levels *

VDD-0.5V

1.5V

VDD/2

0.5V

* Input rise and fall

times <1 ns/V.

Output Sense

Levels

VDD/2

VDD – 0.4V

0.4V

VDD – 0.4V

0.4V

High Z

3.4V

2.4V

3.4V

2.4V

High Z

High Z = 2.9V

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FIFO – HX6409/HX6218/HX6136

RELIABILITY

QUALIFICATION AND SCREENING

Since 1990 Honeywell has been producing

integrated circuits that meet the stringent

reliability requirements of space and defense

systems. Honeywell has delivered thousands of

QML parts since first becoming QML qualified in

1990.

The SOI CMOS technology was qualified by Honeywell after

meeting the criteria of the General Manufacturing Standards.

This approval is the culmination of years of development and

requires a considerable amount of testing, documentation,

and review. The SRAM is also QML Certified, which required

additional testing, documentation, and DLA Land and

Maritime approval.

Using this proven approach Honeywell will

assure the reliability of the products

manufactured with the SOI CMOS process

technology. This approach includes adhering to

Honeywell’s General Manufacturing Standards

for:

The test flow includes screening units with the defined flow

(Class V and Q equivalent) and the appropriate periodic or

lot conformance testing (Groups B, C, D, and E). Both the

SOI CMOS process and the SRAM products are subject to

period or lot based Technology Conformance Inspection

(TCI) and Quality Conformance Inspection (QCI) tests,

respectively.

• Designing in reliability by establishing

electrical rules based on wear out mechanism

characterization performed on specially

designed test structures (electromigration,

TDDB, hot carriers, negative bias temperature

instability, radiation)

• Utilizing a structured and controlled design

process

• A statistically controlled wafer fabrication

process with a continuous defect reduction

process

• Individual wafer lot acceptance through

process monitor testing (includes radiation

testing)

• The use of characterized and qualified

packages

Group A

Group B

General Electrical Tests

Mechanical - Bond strength, solvents, die

shear, solderability (1)

Group C

Group D

Life Tests - 1000 hours at 125^OC or

equivalent

Package related mechanical tests –

Dimensions (1), shock, vibration, lead

integrity, seal, acceleration, lead finish

adhesion (1), thermal shock, temperature

cycling, moisture resistance

Group E

Note

Radiation Tests

(1) Test performed by package supplier.

• A thorough product testing program based on

MIL-PRF-38535 and MIL-STD 883.

Honeywell delivers products that are tested to meet your

requirements. Products can be screened to several levels

including Proof of Design (POD), Engineering Models, and

Flight Units. PODs and EMs are available with limited

screening for prototype development and evaluation testing.

Pin List for HX6409

Signal Pin

Signal

Pin Signal Pin Signal Pin Signal

VSS

QF / TQF

ENR

CKW

ENW

VDD

E / F

VSS

VDD

CKR

EF _Fault

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FIFO – HX6409/HX6218/HX6136

Pin List for HX6218

Pin Signal

Signal

D17

D16

D15

D14

VDD

VSS

D13

D12

D11

D10

Pin Signal

Signal Pin

Signal

VSS

CKR

ENR

VSS

Q11

Q12

Q13

VDD

VSS

Q14

Q15

Q16

Q17

VDD

CKW

ENW

EF _Fault

QF / TQF

VDD

VSS

VDD

E / F

VDD

VSS

VDD

Q10

Pin List for HX6136

Signal

VSS

Signal

Pin Signal

Signal

Q19

Q20

CKW

VSS

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

D25

ENW

D24

VSS

VDD

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Q21

VDD

VSS

Q22

Q23

Q24

Q25

Q26

Q27

Q28

EF _Fault

QF / TQF

E / F

VSS

VDD

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

VSS

VDD

100

101

102

103

104

105

106

107

108

109

110

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q18

Q29

Q30

Q31

Q32

Q33

Q34

Q35

VDD

VSS

VDD

VSS

VDD

CKR

ENR

VDD

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FIFO – HX6409/HX6218/HX6136

PACKAGING

The FIFO is offered in a 32-lead, 68-lead and a 132-

lead flat pack, depending on the configuration. These

packages are constructed of multilayer ceramic (Al2O3)

and features internal power and ground planes. The flat

packs also feature non-conductive ceramic tie bars.

The tie bars allows electrical testing of the device, while

preserving the lead integrity during shipping and

handling, up to the point of lead forming and insertion.

Package Drawing For 6409 (22020651-001)

Package Drawing For 6218 (22019075-001)

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FIFO – HX6409/HX6218/HX6136

Package Drawing for 6136 (22018696-001)

ORDERING INFORMATION

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FIFO – HX6409/HX6218/HX6136

ORDERING INFORMATION

6409

PART NUMBER

6409 = 4K X 9

6218 = 2K X 18

6136 = 1K X 36

SCREEN LEVEL

S=QML V Equivalent (3)

B= QML Q Equivalent (3)

E=Engr Device (2)

INPUT

BUFFER TYPE

C=CMOS Level

T=TTL Level

Process

X=SOI

TOTAL DOSE

HARDNESS

Source

H=Honeywell

PACKAGE DESIGN

D=68-Lead CQFP

F=132-Lead CQFP

T=32-Lead CQFP

R=1X10⁵rad(Si0₂)

F=3x10⁵rad(Si0₂)

H=1x10⁶rad(Si0₂)

N=No Level Guaranteed

(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Department at 763-954-2888 for

further information.

(2) Engineering Device description: Parameters are tested from -55 to 12˚5 C, 24 hr burn -in, no radiation

guaranteed. Contact Factory with other needs.

(3) Screening Level S indicates class level V (space level) screening in accordance with MIL PRF 38535.

Screening Level B indicates class level Q screening in accordance with MIL PRF 38535. Screening for both is

also in accordance with approved Manufacturing Quality Management Plan.

QCI TESTING (1)

QML Q Equivalent:

QML V Equivalent:

No lot specific testing performed. (2)

Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.

(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell QM Plan. Quarterly testing is

done in accordance with the Honeywell QM Plan.

(2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.

Find out more

For more information about Honeywell’s family of radiation hardened products and technology, visit

www.honeywell.com/radhard.

Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability

arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Honeywell

12001 Highway 55

Plymouth, MN 55441

1-800-323-8295

www.honeywell.com/radhard

Form #900157

February 2011

www.honeywell.com/radhard

HX6136FSNC [HONEYWELL]

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