HXNV0100AYN [HONEYWELL]
Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64;
| 型号： | HXNV0100AYN |
| 厂家： | 
Honeywell |
| 描述： | Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64 内存集成电路 |
| 文件： | 总12页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HXNV0100
HXNV0100 1Megabit
64K x 16 Non-Volatile Magneto-Resistive RAM
Features
■
Fabricated on S150 Silicon On
Insulator (SOI) CMOS Underlayer
Technology
■
■
■
150 nm Process (Leff = 130 nm)
Total Dose Hardness ≥ 1x106 rad (Si)
Dose Rate Upset Hardness ≥ 1x109
rad(Si)/s
■
■
Dose Rate Survivability ≥1x1012
rad(Si)/s
Soft Error Rate ≤1x10-10
upsets/bit-day
■
■
■
■
■
■
■
■
■
■
Neutron Hardness ≥�1x1014 N/cm2
No Latchup
Read Access Time ≤� 80 ns
Read Cycle Time ≤� 110 ns
Write Cycle Time ≤ 140 ns
Typical Operating Power ≤500 mW
Unlimited Read (>1x1015 Cycles)
> 15 years Data Retention
Synchronous Operation
Single-Bit Error Detection &
Correction (ECC)
■
■
■
■
Dual Power Supplies
1.8 V ± 0.15V, 3.3 V ± 0.3V
3.3V CMOS Compatible I/O
The 64K x 16 radiation hardened low power non-volatile Magneto-Resistive Random
Access Memory (MRAM) is a high performance 65,536 word x 16-bit Magneto-Resistive
RAM with industry-standard functionality.
Standard Operating Temperature
Range is -40°C to +105°C
■
Package: 64 Lead Shielded
Ceramic Quad Flat Pack
The MRAM is designed for very high
reliability. Redundant write control lines,
error correction coding and low-voltage
write protection ensure the correct
operation of the memory and protection
from inadvertent writes.
fabricated with Honeywell’s radiation
hardened Silicon On Insulator (SOI)
technology, and is designed for use in
low-voltage systems operating in radiation
environments. The MRAM operates over
a temperature range of -40°C to +105°C
and is operated with 3.3 ± 0.3V and
1.8 ± 0.15V power supplies.
Integrated Power Up and Power Down
circuitry controls the condition of the
device during power transitions. It is
Functional
Block Diagram
Digit Line Drivers
A(7:15)
Q
D
C
CS
Row
Decoder
Data Array
65,536 x 16
ECC Array
65,536 x 5
ECC Logic
WE
Q
D
C
NWI
Bit Line Drivers
OE
Q
D
C
A(0:6)
Column Decoder
Data Input/Output
Read Circuit
Q
D
C
DQ(0:15)
Signal Description
Signal
A(0:6)
A(7:15)
DQ(0:15)
CS
Definition
Column Select Address Input. Signals which select a column within the memory array.
Row Select Address Input. Signals which select a row within the memory array.
Data Input/Output Signals. Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation.
Chip select. The rising edge of CS will clock in the address and WE signals and latch the DQ outputs.
Write Enable. Active high write enable. High state at rising edge of CS initiates a write cycle. Low state at rising edge of CS initiates a read cycle.
Output Enable. Active high output enable.
WE
OE
NWI0
NWI1
Not Write Inhibit – When set low, these signals inhibit writes to the memory. A high level allows the memory to be written.
NWI0 controls lower order 32K A(15)=0.
NWI1 controls the upper order 32K A(15)=1.
(Note the VIL and VIH requirements for NWI)
TESTOUT
TESTIN1
TESTIN2
TESTIN3
VDD1
This output signal is for Honeywell test purposes only. It must be left floating.
These signals are for Honeywell test purposes only. These must be grounded. (Failure to hold these pins low may result in
permanent loss of functionality)
DC Power Source Input: 1.8V
VDD2
DC Power Source Input: 3.3V
N/C
No Connect, (can be tied to any supply)
2
Package
Pinout
VDD1
GND
1
2
3
4
5
6
7
8
9
48 VSS
47 VDD2
46 ADDR(6)
45 ADDR(15)
44 WE
DQ(1)
DQ(0)
CS
NWI(0)
VDD2
VDD1
VSS
43 N/C
42 OE
41 VDD2
40 VDD1
39 VSS
HXNV0100
NWI(1) 10
TESTIN3 11
TESTOUT 12
DQ(8) 13
38 ADDR(14)
37 ADDR(13)
36 ADDR(12)
35 ADDR(11)
34 VSS
DQ(9) 14
VDD2 15
VSS 16
33 VDD1
Signal Description
Function Truth Table
NWI
CS
OE
WE
Data Outputs
Function
1
_/
X
1
X
1
Hi Z
Write cycle
(rising edge)
X
0
_/
(rising edge)
X
0
X
Lo Z
Read Cycle
Dependent on controls
Writes inhibited
Output Driver Truth Table
NWI
CS
0
OE
X
WE(1)
Data Outputs
Hi Z
Function
X
X
X
X
X
X
1
0
Outputs Disabled
Outputs Disabled
Outputs Disabled
Outputs Enabled
X
0
Hi Z
X
X
Hi Z
1
1
Low Z
(1) Latched by rising edge of CS
3
Radiation Characteristics
RAM and ROM Functional Capability
Total Ionizing Radiation Dose
This MRAM incorporates two write control signals allowing the two
sections of the memory to be controlled independently. The two
NOT WRITE INHIBIT signals, NWI(0) and NWI(1), allow one section
of the device to operate as a RAM and the other to operate as a
ROM at the full control of the user. These signals should be hard
wired to VDD2 or ground if active control is not needed. If control
is desired, maximum 5K ohms pull up or down resistor should be
used with care taken to insure that the VIH and VIL for the NWI
pins are met.
The MRAM will meet all stated functional and electrical
specifications after the specified total ionizing radiation dose.
All electrical and timing performance parameters will remain
within specifications, post rebound, after an operational period
of 15 years. Total dose hardness is assured by wafer level
testing of process monitor transistors using 10 KeV X-ray.
Parameter correlations have been made between 10 KeV X-rays
applied at a dose rate of 5x105 rad(SiO2)/min at T= 25°C and
gamma rays (Cobalt 60 source) to ensure that wafer level
X-ray testing is consistent with standard military radiation
test environments.
SOI and Magnetic Memory Technology
Transient Pulse Ionizing Radiation
The MRAM is capable of writing, reading, and retaining stored
data during and after exposure to a transient ionizing radiation
pulse, up to the specified transient dose rate upset specification,
when applied under recommended operating conditions.
To ensure validity of all specified performance parameters
before, during, and after radiation (timing degradation during
transient pulse radiation is ±10%), it is suggested that stiffening
capacitance be placed near the package VDD2 and ground
(GND) and near the package VDD1 and ground (GND).
Honeywell’s S150 Silicon On Insulator (SOI) CMOS is radiation
hardened through the use of advanced and proprietary design,
layout and process hardening techniques. The 150 nm process
is a technology with a 31Å gate oxide for 1.8 V transistors and
59Å gate oxide for 3.3 V transistors. The memory element is
a magnetic tunnel junction (MTJ) that is non-volatile and
composed of a magnetic storage layer structure and a magnetic
pinned layer structure separated by an insulating tunnel barrier.
During a write cycle, the storage layer is written by the
application of two orthogonal currents using row-and-column
addressing. The resistance of the MTJ depends on the magnetic
state of the storage layer structure, which uses the pinned layer
structure as a reference, and which enables signal sensing,
amplification, and readback. The resistance change from
the memory element is a result of the change in Tunneling
Magneto-Resistance (TMR) between the storage and pinned
layers that depends on the magnetic state of the storage
layer. The HXNV0100 is not subject to memory related wear
out mechanisms.
It is also recommended that the inductance between the MRAM
package leads and the stiffening capacitance be less that 1.0 nH.
If there are no operate through or valid stored-data requirements,
typical circuit board mounted de-coupling capacitors are
recommended. The MRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to the
transient dose rate survivability specification, when applied
under recommended operating conditions. Note that the current
conducted during the pulse by the MRAM inputs, outputs, and
power supply may significantly exceed the normal operating levels.
The application design must accommodate these effects.
Neutron Radiation
The MRAM will meet any functional or timing specification after
exposure to the specified neutron fluence under recommended
operating or storage conditions. This assumes equivalent neutron
energy of 1 MeV.
Error Correction Code (ECC)
Hamming 5-Bit ECC
A 5-bit Hamming ECC is generated for all data written into
memory. This code allows for the correction of all single-bit errors
per address. On a read cycle, a data word is read from memory
and corrected, if necessary, before being placed on the output
data bus.
There is no change made to the actual data in the memory cells
based on the ECC results. Actual data in memory are changed
only upon writing new values.
4
Soft Error Rate
Radiation-Hardness Ratings
The MRAM is capable of meeting the
specified Soft Error Rate (SER) under
recommended operating conditions.
This hardness level is defined by the
Adams 90% worst case cosmic ray
environment for geosynchronous orbits.
Parameter
Limits
Units
Test Conditions
VDD1 = 1.65 TO 1.95 VOLTS
VDD2 = 3.00 TO 3.60 VOLTS
TC = -40 TO 105 °C
6
Total Dose: H-Level
≥ 1 x 10
≤ 1 x 10
≥ 1 x 10
≥ 1 x 10
Rads(Si)
TA =25°C, X-Ray or Co60
-10
9
Soft Error Rate:
Upsets/bit-day (1)
Rads(Si)/s
Read or Write
Transient Dose Rate Upset
Transient Dose Rate Survivability
Neutron Fluence
Pulse Width = 20ns +/- 5ns FWHM, X-Ray
Pulse Width = 18-52ns FWHM, X-Ray
1 MeV equivalent energy
12
Rads(Si)/s
14
2
1x10
N/cm
Latchup
(1) Adams 90% Worst-Case environment under worst-case operating conditions for voltage, temperature and memory
operating conditions (e.g. static or dynamic operation).
The MRAM will not latch up under any
of the above radiation exposure condi-
tions when applied under recommended
operating conditions. Fabrication with SOI
substrate material provides oxide isolation
between adjacent PMOS and NMOS
transistors and eliminates any potential
SCR-type latchup structures. Sufficient
transistor body tie connections to the
p-channel and n-channel substrates
are made to ensure no source/drain
snapback occurs.
Magnetic Field Characteristics
The MRAM will meet all stated functional and electrical specifications over the entire
operating temperature range when exposed to magnetic fields up to the rating supplied
below. Exposure to larger magnetic fields may permanently affect functionality.
Magnetic Field Rating
Parameter
Limits
Units
Test Conditions
Magnetic Field
50
Oe
VDD1 = 1.8 Volts, VDD2 = 3.3 Volts
TC = -40°C to 105°C
Recommended Operating Conditions (1)
Limits
Symbol
VDD1
Parameter
Min
1.65
3.0
Typical
1.80
3.3
Max
1.95
Units
Volts
Volts
°C
Positive Supply Voltage
Positive Supply Voltage
External Package Temperature
Voltage On Any Pin
VDD2
3.6
T
-40
25
105
C
V
-0.3
VDD2+0.3
Volts
PIN
(1) Voltages referenced to GND
Electrical Specifications
Absolute Maximum Ratings (1)
Ratings
Symbol
VDD1
Parameter
Min
Max
2.5
Units
Volts
Volts
Volts
°C
Positive Supply Voltage (2)
Positive Supply Voltage (2)
Voltage on Any Pin (2)
-0.5
-0.5
-0.5
VDD2
4.6
V
VDD2+ 0.5
PIN
T
Maximum Junction Temperature for Sustained Exposure
Soldering Temperature
125 (6)
260°C
2.5
Exp
T
°C *sec(5)
W
SOLDER
P
P
Package Power Dissipation (3)
D
Package Thermal Resistance (Junction to Case)
Electrostatic Discharge Protection Voltage (4)
Junction Temperature Silicon
4.0
°C /W
V
JC
V
2000
PROT
T
175
160
°C
J
T
MTJ Temperature
°C
MTJ
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and operation at these levels is not implied.
Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS
(3) MRAM power dissipation due to IDDS, IDDOP, and IDDSEI, plus MRAM output driver power dissipation due to external loading must not exceed this specification
(4) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015
(5) Maximum soldering temp of 260°C can be maintained for no more than 180 seconds over the lifetime of the part.
(6) Not to exceed 24 hours duration (or equivalent at temperature using Ea = 1.235 eV)
Capacitance
Limits
Symbol
Parameter
Min
Max
Units
pF
Test Conditions
C
Data I/O Capacitance
Input Capacitance
15
Vio = VDD2 or VSS, f=1 MHz
VI = VDD2 or VSS, f=1 MHz
IO
C
12
pF
I
C
Not Write Inhibit Capacitance
100
pF
NWI
5
DC Electrical Characteristics (1)
Parameter
VIL
Symbol
Min
Max
Units
Comments
Low Level Input Voltage
High-level Input Voltage
Low Level Input Voltage (NWI Signals)
High-level Input Voltage (NWI Signals)
Low-level Output Voltage
High-level Output Voltage
Output Leakage Current
0.3*VDD2
V
V
V
All inputs except NWI
All inputs except NWI
NWI Inputs
VIH
0.7*VDD2
0.9*VDD2
VIL (NWI)
VIH (NWI)
VOL
0.5
0.5
100
10
NWI Inputs
V
V
IOL = 6 mA
VOH
VDD2-0.5
-100
IOH = -6 mA
IOZ
µA
Chip deselected or output disabled
(CS=0V, OE=0V)
II
Input Leakage Current
-10
µA
IIL : Vin=0V, IIH : Vin=VDD2
All inputs except TEST pins
IDDSB
Standby Current
VDD1 (1.95V)
12
2
mA
mA
mA
VDD2 (3.60V)
IDDOPWR1
IDDOPWR7
IDD2OPWR1
IDD2OPWR7
IDDOPR1
VDD1 current at 1 MHZ write frequency
(frequency of CS rising edges)
15
This is the average current comprised of 30 ma during
each 140 ns internal MRAM write, and 12 ma standby
in between each write
VDD1 current at 7 MHZ write frequency
(frequency of CS rising edges)
30
30
196
14
30
8
mA
mA
mA
mA
mA
mA
This is the average current comprised of 30 ma during
each 140 ns internal MRAM write, and 12 ma standby
in between each write
VDD2 current at 1 MHZ of write frequency
(frequency of CS rising edges)
This is the average current comprised of 200 ma during
each 140 ns internal MRAM write and 2 ma standby in
between each write.
VDD2 current at 7 MHZ of write frequency
(frequency of CS rising edges)
This is the average current comprised of 200 ma during
each 140 ns internal MRAM write and 2 ma standby in
between each write.
VDD1 current at 1 MHZ of read frequency
(frequency of CS rising edges)
This is the average current comprised of 30 ma during
each 110 ns internal MRAM read, and 12 ma standby in
between each read
IDDOPR9
VDD1 current at 9 MHZ of read frequency
(frequency of CS rising edges)
This is the average current comprised of 30 ma during
each 110 ns internal MRAM read, and 12 ma standby in
between each read
IDD2OPR1
VDD2 current at 1 MHZ of read frequency
(frequency of CS rising edges)
Dynamic current is due to driving load capacitance,
assumes all 16 outputs switching every read cycle
I = 16 * C * V * F + standby current with 70 pF load
per output
IDD2OPR9
VDD2 current at 9 MHZ of read frequency
(frequency of CS rising edges)
54
mA
Dynamic current is due to driving load capacitance,
assumes all 16 outputs switching every read cycle
I = 16 * C * V * F + standby current
with 70 pF load per output
(1) Post-radiation performance guaranteed at 25°C per MIL-STD-883 method 1019 up to 1MRad(Si) total dose
6
Max Write Cycle IDDOP
Max Read Cycle IDDOP
250
200
150
100
50
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0
IDDRD
IDD2RD
Total Read
IDDWR
IDDRWR
Total Write
0
0
2
4
6
8
0
2
4
6
8
10
Frequency (MHz)
Frequency (MHz)
Data Endurance
Ratings
Parameter
Min
Max
Units
Cycles
Cycles
Test Conditions
15
Data Read Endurance
Data Write Endurance
1x10
1x10
12
Data Retention
Ratings
Parameter
Min
Max
Units
Test Conditions
Data Retention
>15
years
Chip Power On or Off
7
Read Cycle
The MRAM is synchronous in operation relative to the rising edge
of the Chip Select (CS) signal. With the initiation of a CS signal,
the address and the Write Enable (WE) signal are latched into the
device and the read operation begins. The memory locations are
read and compared with the ECC values. Any single bit errors are
detected and corrected.
If WE was low when latched in, the data word is sent to the output
drivers. In addition to WE low being latched, Output Enable (OE)
must be set to a high value to enable the DQ output buffers. OE
is not latched, and may be set high before or after the rising edge
of CS.
Read Cycle AC Timing Characteristics
Tminr
CS
Tcspi
Tadsu
Tadhd
Twehd
ADDR
Don’t Care
Don’t Care
Don’t Care
ADDR Valid
Twesu
WE
Don’t Care
Tcsdv
DQ = HiZ or Prev. Read Data
Tcshz
DQ = HiZ
DQ Valid
DQ = HiZ
Toencbrcs
Toencarcs
Toedv
Toehz
See Note 1
OE
Don’t Care
(1) If OE is held high during no change window (Toencbrcs+Toencarcs), the DQ pins will drive the previously read data after rising CS.
If OE is held low during no change window, the DQ pins will remain at HiZ.
Name
TADSU
Description
Min
5
Max
Units
ns
Address Setup Time
–
–
TADHD
Address Hold Time
15
5
ns
TWESU
TWEHD
TCSDV
WE Setup Time
–
ns
WE Hold Time
15
–
–
ns
DQ valid with respect to rising edge of CS
OE access time
80
15
15
20
–
ns
TOEDV
–
ns
TOEHZ
OE de-asserted to outputs Hi z
CS de-asserted to outputs Hi z
Read Cycle Time
–
ns
TCSHZ
–
ns
TMINR
110
–
ns
TCSPI
CS ignored pulse width (glitch tolerance)
OE rising or falling edge to rising CS time
CS rising edge to OE rising or falling edge
4
ns
TOENCBRCS
TOENCARCS
15
65
–
ns
–
ns
8
Write Cycle
The MRAM is synchronous in operation relative to the rising edge
of the Chip Select (CS) signal. With the initiation of a CS signal,
the address and the Write Enable (WE) signal are latched into
the device.
The bit cell construction of this device does not provide a method
of simply writing a “1” or a “0” to match the data. The “write” to
a bit can only change its state, thus the need to read the bit
locations first. Only the bits which need to “change state” are
actually written.
The WRITE CYCLE begins by reading the currently addressed
value in memory. The current memory data are compared to
the data to be written. If the location needs to change value,
the data are then written.
Write Cycle AC Timing Characteristics
Tminw
Tcspw, Tcspi
CS
Tdqsu
Tdqhd
DQ Valid
Data Written
DQ = HiZ
ADDR
WE
Tadsu
Tadhd
Twehd
ADD Valid
Twesu
Tnwisu
Tnwi, Tnwihd
NWI
Name
TADSU
Description
Min
5
Max
Units
ns
Address Setup Time
Address Hold Time
WE Setup Time
WE Hold Time
–
–
TADHD
TWESU
TWEHD
TCSPW
TCSPI
15
5
ns
–
ns
15
10
–
–
ns
CS Pulse Width (for valid write)
–
ns
CS ignored pulse width (glitch tolerance)
Data Setup Time (relative to CS rising edge)
Data Hold Time (relative to CS rising edge)
4
–
ns
TDQSU
TDQHD
TNWI
5
ns
15
–
–
ns
NWI falling edge with respect to CS rising edge to inhibit write
Write Cycle Time
40
–
ns
TMINW
140
ns
9
Power Up Timing
During power-up there are no restrictions on which supply
comes up first provided NWI is asserted (low). NWI is de-asserted
within 1us of both supplies reaching their 90% values.
• Utilizing a structured and controlled design process
• A statistically controlled wafer fabrication process with
a continuous defect reduction process
• Individual wafer lot acceptance through process monitor testing
(includes radiation testing)
POWER UP SEQUENCE
VDD1
• The use of characterized and qualified packages
• A thorough product testing program based on MIL-PRF-38535
and MIL-STD 883.
VDD2
1us
NWI
Qualification and Screening
The SOI CMOS technology is qualified by Honeywell after
meeting the criteria of the General Manufacturing Standards
and is also QML Qualified. This qualification is the culmination
of years of development, testing, documentation, and on-going
process control.
Power Down Timing
POWER DOWN SEQUENCE
The test flow includes screening units with the defined flow
(Class V and Q+ equivalent) and the appropriate periodic or lot
conformance testing (Groups B, C, D, and E). Both the process
and the products are subject to period or lot based Technology
Conformance Inspection (TCI) and Quality Conformance
Inspection (QCI) tests, respectively, as defined by Honeywell’s
Quality Management Plan.
VDD1
VDD2
100ns
NWI
Reliability
For many years Honeywell has been producing integrated circuits
that meet the stringent reliability requirements of space and
defense systems. Honeywell has delivered hundreds of thousands
of QML parts since first becoming QML qualified in 1990. Using
this proven approach Honeywell will assure the reliability of the
products manufactured with the SOI CMOS process technology.
This approach includes adhering to Honeywell’s General
Manufacturing Standards for:
Group A
Group B
Final Lot Acceptance Electrical Tests
Mechanical – Dimensions (1), Bond Strength, Solvents, Die Shear,
Solderability, Lead Integrity, Seal, Acceleration
Life Tests – 1000 hours at 105°C or equivalent
Package related mechanical tests – Shock, Vibration, Accel, Salt (1),
Seal, Lead Finish Adhesion, Lid Torque, Thermal Shock, Temp Cycle,
Moisture Resistance
Group C
Group D
Group E
Radiation Tests
• Designing in reliability by establishing electrical rules based
on wear out mechanism characterization performed on
specially designed test structures (electro migration, TDDB,
hot carriers, negative bias temperature instability, radiation)
(1) Testing performed by package supplier.
10
Package Outline
The 64 Lead Shielded Ceramic QFP Package, including
external capacitors. Magnetic shielding is tied to ground
on the package.
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1. Controlling dimensions are in millimeters.
Common Dimensions - Millimeters
Common Dimensions - Inches
Symbol
Min
3.86
1.44
0.41
0.10
22.63
18.92
---
Nom
4.29
1.60
0.46
0.15
22.86
19.05
1.27
5.08
---
Max
4.75
1.76
0.51
0.20
23.09
19.18
---
Min
.152
.057
.016
.004
.891
.745
---
Nom
.169
.063
.018
.006
.900
.750
.050
.200
---
Max
.187
.070
.020
.008
.909
.755
---
2
A1 is the total thickness of the top shield,
lid, sear ring, ceramic body, bottom
shield, and shield adhesives.
A
A1
b
c
3
Lead frame corners are trimmed to fit
into carriers.
D1/E1
D2/E2
e
F
4.44
---
5.72
52.58
30.86
---
.175
---
.225
2.070
1.215
---
L1
L2
R
30.10
8.03
30.48
---
1.185
.316
1.200
---
11
Ordering Information (1)
H
X
NV
0100
A
Z
H
Source
H = Honeywell
Process
X = SOI
Part Type
NV = Non Volatile
Package Designation
Total Dose Hardness
6
A = 64 Lead QFP
H = 1x10 rad (Si)
N = No Level Guaranteed
Part Number
0100 = 1 Meg
Screen Level
Z = Class V Equivalent
Y = Class Q+ Equivalent
E = Eng. Model (2)
(1) To order parts or obtain technical assistance, call 1-800-323-8295
(2) Engineering Model Description: Parameters are tested from -40°C to 105°C, 24-hour burn-in, no radiation guarantee.
QCI Testing (1)
Classification
QML Q+ Equivalent
V Equivalent
QCI Testing
No lot specific testing performed. (2)
Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.
(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell QM Plan. Quarterly testing is done in accordance with the Honeywell QM Plan.
(2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.
This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR)
22 CFR 120-130 and may not be exported, as defined by the ITAR, without the appropriate prior authorization from the Directorate of
Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and regulations is prohibited.
Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights
nor the rights of others.
Find out more
To learn more about Honeywell’s radiation hardened
integrated circuit products and technologies, visit
www.honeywell.com/microelectronics.
Honeywell Aerospace
Honeywell
1944 E. Sky Harbor Circle
Phoenix, AZ 85034
Telephone: 1.800.601.3099
N61-0995-000-000
June 2010
International: 602.365.3099
www.honeywell.com
© 2010 Honeywell International Inc.
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