RFM75-D [HOPERF]
Low Power High Performance GFSK Transceiver;
| 型号： | RFM75-D |
| 厂家： | 
HOPERF |
| 描述： | Low Power High Performance GFSK Transceiver |
| 文件： | 总28页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFM75 V2.0
Low Power High Performance
2.4 GHz GFSK Transceiver
Features
*
*
2400-2483.5 MHz ISM band operation
Support 250Kbps, 1Mbps and 2 Mbps air
data rate
*
*
*
*
*
*
Programmable output power
Tolerate +/- 60ppm 16 MHz crystal
Variable payload length from 1 to 32bytes
Automatic packet processing
6 data pipes for 1:6 star networks
1.9V to 3.6V power supply
*
4-pin SPI interface with maximum 8 MHz
clock rate
RFM75C
RFM75-S
*
20-pin 4x4mm QFN package
Applications
*
*
*
*
*
Wireless PC peripherals
Wireless gamepads
Wireless audio
Remote controls
Home automation
* Toys
RFM75-D
Block Diagram
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RFM75 V2.0
Table of Contents
1
2
General Description ......................................................................................................... 3
Abbreviations ....................................................................................................................4
3
4
Pin Information .................................................................................................................5
State Control .....................................................................................................................6
State Control Diagram ......................................................................................................6
Power Down Mode........................................................................................................... 7
Standby-I Mode ............................................................................................................... 7
Standby-II Mode............................................................................................................... 7
TX Mode .......................................................................................................................... 7
RX Mode .......................................................................................................................... 8
Packet Processing ............................................................................................................ 8
Packet Format ................................................................................................................... 8
4.1
4.2
4.3
4.4
4.5
4.6
5
5.1
5.1.1 Preamble........................................................................................................................... 9
5.1.2 Address............................................................................................................................. 9
5.1.3 Packet Control .................................................................................................................. 9
5.1.4 Payload ........................................................................................................................... 10
5.1.5 CRC ................................................................................................................................ 10
5.2
6
6.1
6.2
6.3
Packet Handling ............................................................................................................. 10
Data and Control Interface ............................................................................................. 11
TX/RX FIFO ................................................................................................................... 11
Interrupt ........................................................................................................................... 11
SPI Interface .................................................................................................................... 12
6.3.1 SPI Command ................................................................................................... .. ........... 12
6.3.2 SPI Timing ......................................................................................................... ............. 13
7
Register Map ................................................................................................................... 15
Register Bank 0 ................................................................................................................ 15
Register Bank 1 ................................................................................................................ 21
Electrical Specifications ....................................................................................... ........... 22
Typical Application Schematic ............................................................................ ........... 23
Package and Die Bonding Information.............................................................................. 24
Package Information ..........................................................................................................24
Die Bonding Information ................................................................................................... 25
PCB Bonding diagram .......................................................................................................27
Order Information ..............................................................................................................28
Contact Information ........................................................................................................... 29
Update History ................................................................................................................... 30
7.1
7.2
8
9
10
10.1
10.2
10.3
11
12
13
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RFM75 V2.0
1 General Description
RFM75 is a GFSK transceiver operating in
the world wide ISM frequency band at 2400-
2483.5 MHz. Burst mode transmission and up
to 2Mbps air data rate make them suitable for
applications requiring ultra low power
resolution of the RF channel frequency is
1MHz.
A
transmitterand
a
receiver must be
programmed with the same RF channel
frequency to be able to communicate with
each other.
consumption.
The
embedded
packet
processing engines enable their full operation
with a very simple MCU as a radio system.
Auto re-transmission and auto acknowledge
give reliable link without any MCU
interference.
The output power of RFM75 is set by the
RF_PWR bits in the RF_SETUP register.
Demodulation is done with embedded data
slicer and bit recovery logic. The air data rate
can be programmed to 250Kbps, 1Mbps or
2Mbps by RF_DR_HIGH and RF_DR_LOW
register. A transmitter and a receiver must be
programmed with the same setting.
RFM75 operates in TDD mode, either as a
transmitter or as a receiver.
The RF channel frequency determines the
center of the channel used by RFM75. The
frequency is set by the RF_CH register in
register bank 0 according to the following
formula: F0= 2400 + RF_CH (MHz). The
In the following chapters, all registers are in
register bank 0 except with explicit claim.
Figure 1 RFM75 Chip Block Diagram
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RFM75 V2.0
2 Abbreviations
ACK
ARC
ARD
CD
Acknowledgement
Auto Retransmission Count
Auto Retransmission Delay
Carrier Detection
Chip Enable
CE
CRC
CSN
Cyclic Redundancy Check
Chip Select Not
DPL
Dynamic Payload Length
First-In-First-Out
Gaussian Frequency Shift Keying
Gigahertz
FIFO
GFSK
GHz
LNA
IRQ
ISM
Low Noise Amplifier
Interrupt Request
Industrial-Scientific-Medical
Least Significant Bit
Maximum Retransmit
Megabit per second
Microcontroller Unit
Megahertz
Master In Slave Out
Master Out Slave In
Most Significant Bit
Power Amplifier
LSB
MAX_RT
Mbps
MCU
MHz
MISO
MOSI
MSB
PA
PID
PLD
Packet Identity Bits
Payload
PRX
Primary RX
PTX
Primary TX
PWD_DWN
PWD_UP
RF_CH
RSSI
RX
Power Down
Power Up
Radio Frequency Channel
Received Signal Strength Indicator
Receive
RX_DR
SCK
Receive Data Ready
SPI Clock
SPI
TDD
TX
Serial Peripheral Interface
Time Division Duplex
Transmit
TX_DS
XTAL
Transmit Data Sent
Crystal
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RFM75 V2.0
3 Pin Information
Figure 2 RFM75C / RFM75 pin assignments (top view)
Table 1 RFM75C/RFM75 pin functions
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RFM75 V2.0
4 State Control
4.1 State Control Diagram
RFM75 has built-in state machines that
control the state transition between different
modes.
*
*
Pin signal: VDD, CE
SPI register: PWR_UP, PRIM_RX,
EN_AA, NO_ACK, ARC, ARD
System information: Time out, ACK
received, ARD elapsed, ARC_CNT, TX
FIFO empty, ACK packet transmitted,
Packet received
*
When auto acknowledge feature is disabled,
state transition will be fully controlled by
MCU.
Figure 3 PTX (PRIM_RX=0) state control diagram
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RFM75 V2.0
Figure 4 PRX (PRIM_RX=1) state control diagram
4.2 Power Down Mode
4.4 Standby-II Mode
In power down mode RFM75 is in sleep
mode with minimal current consumption. SPI
interface is still active in this mode, and all
register values are available by SPI. Power
down mode is entered by setting the PWR_UP
bit in the CONFIG register to low.
In standby-II mode more clock buffers are
active than in standby-I mode and much more
current is used. Standby-II occurs when CE is
held high on a PTX device with empty TX
FIFO. If a new packet is uploaded to the TX
FIFO in this mode, the device will
automatically enter TX mode and the packet is
transmitted.
4.3 Standby-I Mode
By setting the PWR_UP bit in the CONFIG
register to 1 and de-asserting CE to 0, the
device enters standby-I mode. Standby-I mode
is used to minimize average current
consumption while maintaining short start-up
time. In this mode, part of the crystal oscillator
is active. This is also the mode which the
RFM75 returns to from TX or RX mode when
CE is set low.
4.5 TX Mode
*
PTX device (PRIM_RX=0)
The TX mode is an active mode where the
PTX device transmits a packet. To enter this
mode from power down mode, the PTX device
must have the PWR_UP bit set high,
PRIM_RX bit set low, a payload in the TX
FIFO, and a high pulse on the CE for more
than 10µs.
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The PTX device stays in TX mode until it
finishes transmitting the current packet. If CE
= 0 it returns to standby-I mode. If CE = 1, the
next action is determined by the status of the
TX FIFO. If the TX FIFO is not empty the
PTX device remains in TX mode, transmitting
the next packet. If the TX FIFO is empty the
PTX device goes into standby-II mode. It is
important to never stay in TX mode for more
than 4ms at one time.
high, PRIM_RX bit set high and the CE pin
set high. Or PRX device can enter this mode
from TX mode after transmitting an
acknowledge packet when EN_AA=1 and
NO_ACK=0 in received packet.
In this mode the receiver demodulates the
signals from the RF channel, constantly
presenting the demodulated data to the packet
processing engine. The packet processing
engine continuously searches for
packet. If a valid packet is found (by a
matching address and valid CRC) the
a valid
If the auto retransmit is enabled (EN_AA=1)
and
auto
acknowledge
is
required
a
(NO_ACK=0), the PTX device will enter TX
mode from standby-I mode when ARD
elapsed and number of retried is less than
ARC.
payload of the packet is presented in a vacant
slot in the RX FIFO. If the RX FIFO is full,
the received packet is discarded.
The PRX device remains in RX mode until the
MCU configures it to standby-I mode or
power down mode.
*
PRX device (PRIM_RX=1)
The PRX device will enter TX mode from RX
mode only when EN_AA=1 and NO_ACK=0
in received packet to transmit acknowledge
packet with pending payload in TX FIFO.
In RX mode a carrier detection (CD) signal is
available. The CD is set to high when a RF
signal is detected inside the receiving
frequency channel. The internal CD signal is
filtered before presented to CD register. The
RF signal must be present for at least 128 µs
before the CD is set high.
4.6 RX Mode
*
PRX device (PRIM_RX=1)
*
PTX device (PRIM_RX=0)
The RX mode is an active mode where the
RFM75 radio is configured to be a receiver.
To enter this mode from standby-I mode, the
PRX device must have the PWR_UP bit set
The PTX device will enter RX mode from TX
mode only when EN_AA=1 and NO_ACK=0
to receive acknowledge packet.
5 Packet Processing
5.1 Packet Format
The packet format has a preamble, address, packet control, payload and CRC field.
Preamble1byte Address3~5byte PacketControl 9/0bit
Payload0~32byte
CRC2/1byte
PayloadLength6bit
PID2bit
NO_ACK1bit
Figure 5 Packet Format
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No other data pipe can receive data until a
complete packet is received by a data pipe that
has detected its address. When multiple PTX
devices are transmitting to a PRX, the ARD
can be used to skew the auto retransmission so
that they only block each other once.
5.1.1 Preamble
The preamble is a bit sequence used to detect 0
and 1 levels in the receiver. The preamble is
one byte long and is either 01010101 or
10101010. If the first bit in the address is 1 the
preamble is automatically set to 10101010 and
if the first bit is
0
the preamble is
5.1.3 Packet Control
automatically set to 01010101. This is done to
ensure there are enough transitions in the
preamble to stabilize the receiver.
When Dynamic Payload Length function is
enabled, the packet control field contains a 6
bit payload length field, a 2 bit PID (Packet
Identity) field and, a 1 bit NO_ACK flag.
5.1.2 Address
*
Payload length
This is the address for the receiver. An address
ensures that the packet is detected by the target
receiver. The address field can be configured
to be 3, 4, or 5 bytes long by the AW register.
The payload length field is only used if the
Dynamic Payload Length function is enabled.
*
PID
The 2 bit PID field is used to detect whether
the received packet is new or retransmitted.
PID prevents the PRX device from presenting
the same payload more than once to the MCU.
The PID field is incremented at the TX side
for each new packet received through the SPI.
The PID and CRC fields are used by the PRX
device to determine whether a packet is old or
new. When several data packets are lost on the
link, the PID fields may become equal to the
last received PID. If a packet has the same PID
as the previous packet, RFM75 compares the
CRC sums from both packets. If the CRC
sums are also equal, the last received packet is
considered a copy of the previously received
packet and discarded.
The PRX device can open up to six data pipes
to support up to six PTX devices with unique
addresses. All six PTX device addresses are
searched simultaneously. In PRX side, the data
pipes are enabled with the bits in the
EN_RXADDR register. By default only data
pipe 0 and 1 are enabled.
Each data pipe address is configured in the
RX_ADDR_PX registers.
Each pipe can have up to 5 bytes configurable
address. Data pipe 0 has a unique 5 byte
address. Data pipes 1-5 share the 4 most
significant address bytes. The LSB byte must
be unique for all 6 pipes.
*
NO_ACK
To ensure that the ACK packet from the PRX
is transmitted to the correct PTX, the PRX
takes the data pipe address where it received
the packet and uses it as the TX address when
transmitting the ACK packet.
The NO_ACK flag is only used when the auto
acknowledgement feature is used. Setting the
flag high, tells the receiver that the packet is
not to be auto acknowledged.
The PTX can set the NO_ACK flag bit in the
Packet Control Field with the command:
W_TX_PAYLOAD_NOACK. However, the
function must first be enabled in the
On the PRX, the RX_ADDR_Pn, defined as
the pipe address, must be unique. On the PTX
the TX_ADDR must be the same as the
RX_ADDR_P0 on the PTX, and as the pipe
address for the designated pipe on the PRX.
FEATURE
register
by setting the
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EN_DYN_ACK bit. When you use this option,
the PTX goes directly to standby-I mode after
transmitting the packet and the PRX does not
transmit an ACK packet when it receives the
packet.
5.1.5 CRC
The CRC is the error detection mechanism in
the packet. The number of bytes in the CRC is
set by the CRCO bit in the CONFIG register.
It may be either 1 or 2 bytes and is calculated
over the address, Packet Control Field, and
Payload.
5.1.4 Payload
The payload is the user defined content of the
packet. It can be 0 to 32 bytes wide, and it is
transmitted on-air as it is uploaded
(unmodified) to the device.
The polynomial for 1 byte CRC is X8 + X2 +
X + 1. Initial value is 0xFF.
The polynomial for 2 byte CRC is X16 + X12
X5 + 1. Initial value is 0xFFFF.
+
The RFM75 provides two alternatives for
handling payload lengths, static and dynamic
payload length. The static payload length of
each of six data pipes can be individually set.
No packet is accepted by receiver side if the
CRC fails.
The default alternative is static payload length.
With static payload length all packets between
a transmitter and a receiver have the same
length. Static payload length is set by the
RX_PW_Px registers. The payload length on
the transmitter side is set by the number of
bytes clocked into the TX_FIFO and must
equal the value in the RX_PW_Px register on
the receiver side. Each pipe has its own
payload length.
5.2 Packet Handling
RFM75 uses burst mode for payload
transmission and receive.
The transmitter fetches payload from TX FIFO,
automatically assembles it into packet and
transmits the packet in a very short burst
period with 1Mbps or 2Mbps air data rate.
After transmission, if the PTX packet has the
NO_ACK flag set, RFM75 sets TX_DS and
gives an active low interrupt IRQ to MCU. If
the PTX is ACK packet, the PTX needs
receive ACK from the PRX and then asserts
the TX_DS IRQ.
Dynamic Payload Length (DPL) is an
alternative to static payload length. DPL
enables the transmitter to send packets with
variable payload length to the receiver. This
means for a system with different payload
lengths it is not necessary to scale the packet
length to the longest payload.
The receiver automatically validates and
disassembles received packet, if there is a
valid packet within the new payload, it will
write the payload into RX FIFO, set RX_DR
and give an active low interrupt IRQ to MCU.
With DPL feature the RFM75 can decode the
payload length of the received packet
automatically instead of using the RX_PW_Px
registers. The MCU can read the length of the
received payload by using the command:
R_RX_PL_WID.
When auto
(EN_AA=1),
acknowledge
the PTX
is enabled
devicewill
automatically wait for acknowledge packet
after transmission, and re-transmit original
packet with the delay of ARD until an
acknowledge packet is received or the number
of re-transmission exceeds a threshold ARC. If
the later one happens, RFM75 will set
MAX_RT and give an active low interrupt
In order to enable DPL the EN_DPL bit in the
FEATURE register must be set. In RX mode
the DYNPD register has to be set. A PTX that
transmits to a PRX with DPL enabled must
have the DPL_P0 bit in DYNPD set.
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RFM75 V2.0
IRQ to MCU. Two packet loss counters
(ARC_CNT and PLOS_CNT) are incremented
each time a packet is lost. The ARC_CNT
counts the number of retransmissions for the
current transaction. The PLOS_CNT counts
the total number of retransmissions since the
last channel change. ARC_CNT is reset by
initiating a new transaction. PLOS_CNT is
reset by writing to the RF_CH register. It is
possible to use the information in the
OBSERVE_TX register to make an overall
assessment of the channel quality.
accessible through the SPI by using dedicated
SPI commands. A TX FIFO in PRX can store
payload for ACK packets to three different
PTX devices. If the TX FIFO contains more
than one payload to a pipe, payloads are
handled using the first in first out principle.
The TX FIFO in a PRX is blocked if all
pending payloads are addressed to pipes where
the link to the PTX is lost. In this case, the
MCU can flush the TX FIFO by using the
FLUSH_TX command.
The RX FIFO in PRX may contain payload
from up to three different PTX devices.
The PTX device will retransmit if its RX FIFO
is full but received ACK frame has payload.
A TX FIFO in PTX can have up to three
payloads stored.
As an alternative for PTX device to auto
retransmit it is possible to manually set the
RFM75 to retransmit a packet a number of
times. This is done by the REUSE_TX_PL
command.
The TX FIFO can be written to by three
commands,
W_TX_PAYLOAD
and
W_TX_PAYLOAD_NO_ACK in PTX mode
and W_ACK_PAYLOAD in PRX mode. All
three commands give access to the TX_PLD
register.
When auto acknowledge is enabled, the PRX
device will automatically check the NO_ACK
field in received packet, and if NO_ACK=0, it
will automatically send an acknowledge
packet to PTX device. If EN_ACK_PAY is set,
and the acknowledge packet can also include
pending payload in TX FIFO.
The RX FIFO can be read by the command
R_RX_PAYLOAD in both PTX and PRX
mode. This command gives access to the
RX_PLD register.
The payload in TX FIFO in a PTX is NOT
removed if the MAX_RT IRQ is asserted.
6 Data and Control Interface
In the FIFO_STATUS register it is possible to
read if the TX and RX FIFO are full or empty.
The TX_REUSE bit is also available in the
FIFO_STATUS register. TX_REUSE is set by
the SPI command REUSE_TX_PL, and is
6.1 TX/RX FIFO
The data FIFOs are used to store payload that
is to be transmitted (TX FIFO) or payload that
is received and ready to be clocked out (RX
FIFO). The FIFO is accessible in both PTX
mode and PRX mode.
reset
by
the
SPI
command:
W_TX_PAYLOAD or FLUSH TX.
6.2 Interrupt
There are three levels 32 bytes FIFO for both
TX and RX, supporting both acknowledge
mode or no acknowledge mode with up to six
pipes.
In RFM75 there is an active low interrupt
(IRQ) pin, which is activated when TX_DS
IRQ, RX_DR IRQ or MAX_RT IRQ are set
high by the state machine in the STATUS
register. The IRQ pin resets when MCU writes
'1' to the IRQ source bit in the STATUS
register. The IRQ mask in the CONFIG
*
*
TX three levels, 32 byte FIFO
RX three levels, 32 byte FIFO
Both FIFOs have
a controller and are
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register is used to select the IRQ sources that
are allowed to assert the IRQ pin. By setting
one of the MASK bits high, the corresponding
IRQ source is disabled. By default all IRQ
sources are enabled.
to low transition on CSN.
In parallel to the SPI command word applied
on the MOSI pin, the STATUS register is
shifted serially out on the MISO pin.
The 3 bit pipe information in the STATUS
register is updated during the IRQ pin high to
low transition. If the STATUS register is read
during an IRQ pin high to low transition, the
pipe information is unreliable.
The serial shifting SPI commands is in the
following format:
*
*
<Command word: MSB bit to LSB bit
(one byte)>
<Data bytes: LSB byte to MSB byte,
MSB bit in each byte first> for all
registers at bank 0 and register 9 to
register 14 at bank 1
6.3 SPI Interface
*
<Data bytes: MSB byte to LSB byte,
MSB bit in each byte first> for register 0
to register 8 at bank 1
6.3.1 SPI Command
The SPI commands are shown in Table 3.
Every new command must be started by a high
Command
# Data
Command name
word
Operation
bytes
(binary)
Read command and status registers. AAAAA =
5 bit Register Map Address
1 to 5
LSB byte first
R_REGISTER
W_REGISTER
000A AAAA
001A AAAA
Write command and status registers. AAAAA = 5
bit Register Map Address
Executable in power down or standby modes only.
1 to 5
LSB byte first
Read RX-payload: 1 – 32 bytes. A read operation
always starts at byte 0. Payload is deleted from FIFO
after it is read. Used in RX mode.
1 to 32
LSB byte first
R_RX_PAYLOAD
0110 0001
Write TX-payload: 1 – 32 bytes. A write operation
always starts at byte 0 used in TX payload.
1 to 32
LSB byte first
W_TX_PAYLOAD
FLUSH_TX
1010 0000
1110 0001
Flush TX FIFO, used in TX mode
0
Flush RX FIFO, used in RX mode
Should not be executed during transmission of
acknowledge, that is, acknowledge package will not
be completed.
FLUSH_RX
1110 0010
0
Used for a PTX device
Reuse last transmitted payload. Packets are repeatedly
retransmitted as long as CE is high.
TX payload reuse is active until
REUSE_TX_PL
1110 0011
0
W_TX_PAYLOAD or FLUSH TX is executed. TX
payload reuse must not be activated or deactivated
during package transmission
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This write command followed by data 0x73 activates
the following features:
• R_RX_PL_WID
• W_ACK_PAYLOAD
• W_TX_PAYLOAD_NOACK
A new ACTIVATE command with the same data
deactivates them again. This is executable in power
down or stand by modes only.
The R_RX_PL_WID, W_ACK_PAYLOAD, and
W_TX_PAYLOAD_NOACK features registers are
initially in a deactivated state; a write has no effect, a
read only results in zeros on MISO. To activate these
registers, use the ACTIVATE command followed by
data 0x73. Then they can be accessed as any other
register. Use the same command and data to
deactivate the registers again.
ACTIVATE
0101 0000
1
This write command followed by data 0x53 toggles
the register bank, and the current register bank
number can be read out from REG7 [7]
Read RX-payload width for the top
R_RX_PAYLOAD in the RX FIFO.
R_RX_PL_WID
0110 0000
1010 1PPP
Used in RX mode.
Write Payload to be transmitted together with ACK
packet on PIPE PPP. (PPP valid in the range from 000
to 101). Maximum three ACK packet payloads can be
pending. Payloads with same PPP are handled using
first in - first out principle. Write payload: 1– 32
bytes. A write operation always starts at byte 0.
1 to 32
LSB byte first
W_ACK_PAYLOAD
Used in TX mode. Disables AUTOACK on this
specific packet.
W_TX_PAYLOAD_NO
ACK
1 to 32
LSB byte first
1011 0000
1111 1111
No Operation. Might be used to read the STATUS
register
NOP
0
Table 2 SPI command
6.3.2 SPI Timing
SCK
CSN
Write to SPI register:
x
x
MOSI
MISO
x
C7
C6
C5
C4
C3
C2
C1
S1
C0
S0
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
HI-Z
S7
S6
S5
S4
S3
S2
0
Hi-Z
Read from SPI register:
x
C7
C6
C5
C4
C3
C2
C1
S1
C0
S0
x
MOSI
MISO
x
x
S7
S6
S5
S4
S3
S2
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6 SPI timing
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Cn: SPI command bit
Sn: STATUS register bit
Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)
Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte
order is inversed that the MSB byte is R/W before LSB byte.
Figure 7 SPI NOP timing diagram
Symbol
Tdc
Parameters
Min
10
Max
Units
ns
ns
Data to SCK Setup
SCK to Data Hold
CSN to Data Valid
SCK to Data Valid
SCK Low Time
Tdh
20
Tcsd
Tcd
38
55
ns
ns
Tcl
40
40
0
ns
Tch
SCK High Time
ns
MHz
ns
Fsck
Tr,Tf
Tcc
SCK Frequency
8
SCK Rise and Fall
CSN to SCK Setup
SCK to CSN Hold
CSN Inactive time
CSN to Output High Z
100
2
2
ns
Tcch
Tcwh
Tcdz
ns
50
ns
38
ns
Table 3 SPI timing parameter
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RFM75 V2.0
7 Register Map
There are two register banks, which can be toggled by SPI command “ACTIVATE” followed with
0x53 byte, and bank status can be read from Bank0_REG7 [7].
7.1 Register Bank 0
Address
(Hex)
Reset
Value
Mnemonic
Bit
Type
Description
00
CONFIG
Configuration Register
Reserved
7
6
0
0
R/W
Only '0' allowed
MASK_RX_DR
MASK_TX_DS
MASK_MAX_RT
R/W
R/W
R/W
Mask interrupt caused by RX_DR
1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt
on the IRQ pin
Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt
on the IRQ pin
Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low
interrupt on the IRQ pin
5
4
0
0
Enable CRC. Forced high if one of the bits
in the EN_AA is high
CRC encoding scheme
EN_CRC
CRCO
3
2
1
0
R/W
R/W
'0' - 1 byte
'1' - 2 bytes
PWR_UP
PRIM_RX
1
0
0
0
R/W
R/W
1: POWER UP, 0:POWER DOWN
RX/TX control,
1: PRX, 0: PTX
01
EN_AA
Enable „Auto Acknowledgment‟ Function
Reserved
7:6
5
4
3
2
00
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Only '00' allowed
ENAA_P5
ENAA_P4
ENAA_P3
ENAA_P2
ENAA_P1
ENAA_P0
Enable auto acknowledgement data pipe 5
Enable auto acknowledgement data pipe 4
Enable auto acknowledgement data pipe 3
Enable auto acknowledgement data pipe 2
Enable auto acknowledgement data pipe 1
Enable auto acknowledgement data pipe 0
1
0
1
1
02
EN_RXADDR
Reserved
ERX_P5
ERX_P4
ERX_P3
ERX_P2
ERX_P1
ERX_P0
Enabled RX Addresses
Only '00' allowed
7:6
5
4
3
2
00
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable data pipe 5.
Enable data pipe 4.
Enable data pipe 3.
Enable data pipe 2.
Enable data pipe 1.
Enable data pipe 0.
1
0
1
1
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RFM75 V2.0
03
SETUP_AW
Setup of Address Widths
(common for all data pipes)
Only '000000' allowed
Reserved
AW
7:2
1:0
000000
11
R/W
R/W
RX/TX Address field width
'00' - Illegal
'01' - 3 bytes
'10' - 4 bytes
'11' - 5 bytes
LSB bytes are used if address width is
below 5 bytes
04
SETUP_RETR
ARD
Setup of Automatic Retransmission
Auto Retransmission Delay
„0000‟ – Wait 250 us
7:4
0000
R/W
„0001‟ – Wait 500 us
„0010‟ – Wait 750 us
……..
„1111‟ – Wait 4000 us
(Delay defined from end of transmission to
start of next transmission)
Auto Retransmission Count
„0000‟ –Re-Transmit disabled
„0001‟ – Up to 1 Re-Transmission on fail
of AA
ARC
3:0
0011
R/W
……
„1111‟ – Up to 15 Re-Transmission on fail
of AA
05
06
RF_CH
Reserved
RF_CH
RF Channel
Only '0' allowed
Sets the frequency channel
7
6:0
0
R/W
R/W
0000010
RF_SETUP
Reserved
RF Setup Register
Only '00' allowed
Set Air Data Rate. See RF_DR_HIGH for
encoding.
Force PLL lock signal. Only used in test
Set Air Data Rate.
7:6
5
0
0
0
R/W
R/W
R/W
RF_DR_LOW
PLL_LOCK
4
Encoding: RF_DR_LOW, RF_DR_HIGH:
„00‟ – 1Mbps
RF_DR_HIGH
3
1
R/W
„01‟ – 2Mbps (default)
„10‟ – 250Kbps
„11‟ – 2Mbps
Set RF output power in TX mode
RF_PWR[1:0]
RF_PWR[1:0]
LNA_HCURR
2:1
0
11
1
R/W
R/W
Setup LNA gain
0:Low gain(20dB down)
1:High gain
Status Register (In parallel to the SPI
command word applied on the MOSI pin,
the STATUS register is shifted serially out
on the MISO pin)
Register bank selection states. Switch
register bank is done by SPI command
“ACTIVATE” followed by 0x53
0: Register bank 0
07
STATUS
RBANK
7
0
R
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RFM75 V2.0
1: Register bank 1
RX_DR
TX_DS
6
5
0
0
R/W
R/W
Data Ready RX FIFO interrupt
Asserted when new data arrives RX FIFO
Write 1 to clear bit.
Data Sent TX FIFO interrupt
Asserted when packet transmitted on TX.
If AUTO_ACK is activated, this bit is set
high only when ACK is received.
Write 1 to clear bit.
Maximum number of TX retransmits
interrupt
Write 1 to clear bit. If MAX_RT is
asserted it must be cleared to enable
further communication.
Data pipe number for the payload
available for reading from RX_FIFO
000-101: Data Pipe Number
110: Not used
MAX_RT
RX_P_NO
4
0
R/W
R
3:1
111
111: RX FIFO Empty
TX_FULL
0
0
R
R
R
TX FIFO full flag.
1: TX FIFO full
0: Available locations in TX FIFO
08
OBSERVE_TX
PLOS_CNT
Transmit observe register
Count lost packets. The counter is
overflow protected to 15, and discontinues
at max until reset. The counter is reset by
writing to RF_CH.
7:4
3:0
0000
0000
Count retransmitted packets. The counter
is reset when transmission of a new packet
starts.
ARC_CNT
09
CD
Reserved
CD
7:1
0
000000
0
R
R
Carrier Detect
Receive address data pipe 0. 5 Bytes
maximum length. (LSB byte is written
first. Write the number of bytes defined by
SETUP_AW)
Receive address data pipe 1. 5 Bytes
maximum length. (LSB byte is written
first. Write the number of bytes defined by
SETUP_AW)
0A
0B
RX_ADDR_P0
RX_ADDR_P1
39:0
39:0
0xE7E7E
7E7E7
R/W
R/W
0xC2C2C
2C2C2
Receive address data pipe 2. Only LSB
MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 3. Only LSB
MSB bytes is equal to
RX_ADDR_P1[39:8]
0C
0D
0E
RX_ADDR_P2
RX_ADDR_P3
RX_ADDR_P4
7:0
7:0
7:0
0xC3
0xC4
0xC5
R/W
R/W
R/W
Receive address data pipe 4. Only LSB.
MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 5. Only LSB.
MSB bytes is equal to
RX_ADDR_P1[39:8]
Transmit address. Used for a PTX device
only.
0F
10
RX_ADDR_P5
TX_ADDR
7:0
0xC6
R/W
R/W
39:0
0xE7E7E
7E7E7
Page 17 of 27
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RFM75 V2.0
(LSB byte is written first)
Set RX_ADDR_P0 equal to this address to
handle automatic acknowledge if this is a
PTX device
11
12
13
14
15
RX_PW_P0
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 0 (1 to 32 bytes).
0: not used
1 = 1 byte
RX_PW_P0
000000
…
32 = 32 bytes
RX_PW_P1
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 1 (1 to 32 bytes).
0: not used
1 = 1 byte
RX_PW_P1
000000
…
32 = 32 bytes
RX_PW_P2
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 2 (1 to 32 bytes).
0: not used
1 = 1 byte
RX_PW_P2
000000
…
32 = 32 bytes
RX_PW_P3
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 3 (1 to 32 bytes).
0: not used
1 = 1 byte
000000
RX_PW_P3
…
32 = 32 bytes
RX_PW_P4
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 4 (1 to 32 bytes).
0: not used
1 = 1 byte
RX_PW_P4
000000
…
32 = 32 bytes
16
RX_PW_P5
Reserved
7:6
5:0
00
R/W
R/W
Only '00' allowed
Number of bytes in RX payload in data
pipe 5 (1 to 32 bytes).
0: not used
1 = 1 byte
RX_PW_P5
000000
…
32 = 32 bytes
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RFM75 V2.0
17
FIFO_STATUS
Reserved
FIFO Status Register
Only '0' allowed
Reuse last transmitted data packet if set
high.
The packet is repeatedly retransmitted as
long as CE is high. TX_REUSE is set by
the SPI command REUSE_TX_PL, and is
reset by the SPI command
7
6
0
0
R/W
R
TX_REUSE
W_TX_PAYLOAD or FLUSH TX
TX FIFO full flag
1: TX FIFO full; 0: Available locations in
TX FIFO
TX_FULL
5
0
R
TX FIFO empty flag.
TX_EMPTY
Reserved
4
1
00
0
R
1: TX FIFO empty
0: Data in TX FIFO
Only '00' allowed
RX FIFO full flag
3:2
1
R/W
R
RX_FULL
1: RX FIFO full
0: Available locations in RX FIFO
RX FIFO empty flag
RX_EMPTY
ACK_PLD
0
1
R
1: RX FIFO empty
0: Data in RX FIFO
Written by separate SPI command ACK
packet payload to data pipe number PPP
given in SPI command
N/A
255:0
X
W
Used in RX mode only
Maximum three ACK packet payloads can
be pending. Payloads with same PPP are
handled first in first out.
Written by separate SPI command TX data
pay-load register 1 - 32 bytes. This register
is implemented as a FIFO with three
levels.
N/A
N/A
TX_PLD
RX_PLD
255:0
255:0
X
X
W
R
Used in TX mode only
Read by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO
with three levels.
All RX channels share the same FIFO.
1C
DYNPD
Reserved
Enable dynamic payload length
Only „00‟ allowed
Enable dynamic payload length data pipe
5.
(Requires EN_DPL and ENAA_P5)
Enable dynamic payload length data pipe
4.
(Requires EN_DPL and ENAA_P4)
Enable dynamic payload length data pipe
3.
(Requires EN_DPL and ENAA_P3)
Enable dynamic payload length data pipe
2.
7:6
5
0
0
R/W
R/W
DPL_P5
DPL_P4
DPL_P3
DPL_P2
4
3
2
0
0
0
R/W
R/W
R/W
(Requires EN_DPL and ENAA_P2)
Enable dynamic payload length data pipe
1.
(Requires EN_DPL and ENAA_P1)
Enable dynamic payload length data pipe
0.
DPL_P1
DPL_P0
1
0
0
0
R/W
R/W
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RFM75 V2.0
(Requires EN_DPL and ENAA_P0)
1D
FEATURE
Reserved
EN_DPL
R/W
R/W
R/W
R/W
Feature Register
Only „00000‟ allowed
Enables Dynamic Payload Length
Enables Payload with ACK
Enables the W_TX_PAYLOAD_NOACK
command
7:3
2
1
0
0
0
EN_ACK_PAY
EN_DYN_ACK
0
0
R/W
Note: Don’t write reserved registers and registers at other addresses in register bank 0
Table 4 Register Bank 0
Page 20 of 27
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RFM75 V2.0
7.2 Register Bank 1
Address
Reset
(Hex)
Mnemonic
Bit
Value
Type
Description
00
01
02
31:0
0
W
Must write with 0x404B01E2
Must write with 0xC04B0000
Must write with 0xD0FC8C02
31:0
31:0
0
0
0x
W
W
03
31:0
03001200
W
Must write with 0x99003921
Must write with
：
1Msps 0x
F996821B
2Msps: 0xF99682DB
：
250ksps 0xF9968ADB
04
05
31:0
31:0
0
0
W
W
For single carrier mode:0x
Must write with
F9968221
：
1Msps 0x24060FA6(Disable RSSI)
2Msps：0x 24060FB6(Disable RSSI)
250ksps:0x24060FB6(Disable RSSI)
RSSI measurement:
0:Enable
RSSI_EN
18
31:0
31:0
0
0
0
W
W
W
1:Disable
Reserved
Reserved
06
07
Register bank selection states. Switch
register bank is done by SPI command
“ACTIVATE” followed by 0x53
0: Register bank 0
RBANK
Chip ID
7
R
R
1: Register bank 1
BEKEN Chip ID:
0x00000063(RFM75)
Reserved
Reserved
Reserved
08
09
0A
0B
31:0
0
0
0
0
Please initialize with 0x05731200
For 120us mode:0x00731200
PLL Settling time:
101:130us
0C
31:0
26:24
0
101
W
000:120us
9
1
Compatible mode:
0:Static compatible
1:Dynamic compatible
Please initialize with 0x0080B436
Ramp curve
0D
0E
NEW_FEATURE 31:0
RAMP 87:0
0
NA
W
Please write with
0x FFFFFEF7CF208104082041
Note: Don’t write reserved registers and no definition registers in register bank 1
Table 5 Register Bank 1
Page 21 of 27
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RFM75 V2.0
8 Electrical Specifications
Name
Parameter (Condition)
Min
Typical
Max
Unit
Comment
Operating Condition
VDD
Voltage
1.9
3.0
3.6
V
TEMP
Temperature
-40
+27
+85
ºC
Digital input Pin
VIH
VIL
High level
Low level
0.7VDD
VSS
VDD+0.7
0.3VDD
V
V
Digital output Pin
High level (IOH=-0.25mA)
Low level(IOL=0.25mA)
Normal condition
Power Down current
Standby-I current
Standby-II current
Normal RF condition
Operating frequency
Crystal frequency
VOH
VOL
VDD- 0.3
0
VDD
0.3
V
V
IVDD
IVDD
IVDD
3
50
300
uA
uA
uA
FOP
FXTAL
RFSK
2400
250
2527
2000
MHz
MHz
Kbps
16
Air data rate
Transmitter
PRF
Output power
4
dBm
MHz
MHz
KHz
mA
PBW
PBW
PBW
IVDD
Modulation 20 dB bandwidth(2Mbps)
Modulation 20 dB bandwidth (1Mbps)
Modulation 20 dB bandwidth (250Kbps)
TBD
TBD
TBD
9.8
Current at -25dBm output power
Current at -18dBm output power
Current at -12dBm output power
Current at -7dBm output power
IVDD
IVDD
IVDD
IVDD
IVDD
10.2
10.8
11.6
13.4
18
mA
mA
mA
mA
mA
Current at -1dBm output power
Current at 4 dBm output power
Receiver
IVDD
IVDD
IVDD
Current (2Mbps)
Current (1Mbps)
Current (250Kbps)
16.5
16
16
mA
mA
mA
Max Input 1 E-3 BER
10
dBm
dBm
dBm
dBm
RXSENS
RXSENS
RXSENS
1 E-3 BER sensitivity (2Mbps)
1 E-3 BER sensitivity (1Mbps)
1 E-3 BER sensitivity (250Kbps)
-88
-91
-96
Table 6 Electrical Specifications
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RFM75 V2.0
9 Typical Application Schematic
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RFM75 V2.0
10 Package Information
Figure 9 RFM75C SMD PACKAGE
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RFM75 V2.0
Figure 10 RFM75 SMD PACKAGE
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RFM75 V2.0
Figure 10 RFM75 DIP PACKAGE
Page 26 of 27
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RFM75 V2.0
11 Order Information
Part Number
RFM75C
Packag
SMD
SMD
DIP
e
RFM75-S
RFM75-D
12 Solder Information
*
Solder Method: Not supported reflow soldering, recommend to use hand solder .
*
The Selection of Soldering tools
According to both our soldering experiment and customers‟
feedback, we don‟t find that it results in obvious effect on soldering
and products‟ fuctions by using open soldering pens(i.e. common
soldering pens without closed-loop temperature control). However,
considering the requirements of lead-free soldering and its
productivity improvement, we suggest that you should use
thermostatic soldering pen with closed-loop temperature control and
select appropriate solder tip. Please kindly note that big solder tips,
according to the feedback from customers, obviously bring about
low efficiency of soldering and increase the possibility of short-
circuit.
*
The Selection of Soldering Materials
——Sn96.5%/Ag3.0%/Cu0.5%
——Sn96.5%/Ag3.5%
The wireless modules we provide are green products in complete
accordance with the lead-free requirement; therefore, we suggest
you should use environment-friendly lead-free soldering tin. We
recommend two alloyed soldering tins as below to match the no-
clean rosin(core and additive rosin):
——Sn96.5%/Ag3.0%/Cu0.5%
——Sn96.5%/Ag3.5%
Page 27 of 27
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RFM75 V2.0
13 Contact Information
HOPE MICROELECTRONICS CO.,LTD
Add: 2/F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town,
Nanshan District, Shenzhen, Guangdong, China
Tel: 86-755-82973805
Fax: 86-755-82973550
Email: sales@hoperf.com
Website: http://www.hoperf.com
This document may contain preliminary information and is subject to
change by Hope Microelectronics without notice. Hope Microelectronics
assumes no responsibility or liability for any use of the information
contained herein. Nothing in this document shall operate as an express or
implied license or indemnity under the intellectual property rights of Hope
Microelectronics or third parties. The products described in this document
are not intended for use in implantation or other direct life support
applications where malfunction may result in the direct physical harm or
injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY
OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS
DOCUMENT.
HOPE MICROELECTRONICS CO.,LTD Add:
2/F, Building 3, Pingshan Private
Enterprise Science and Technology
Park, Lishan Road, XiLi Town, Nanshan
District, Shenzhen, Guangdong, China
Tel: 86-755-82973805
Fax: 86-755-82973550
Email: sales@hoperf.com
Website: http://www.hoperf.com
©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.
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