GM71CS18163CLJ-5 [HYNIX]

x16 EDO Page Mode DRAM ; X16 EDO页模式DRAM\n


型号：	GM71CS18163CLJ-5
厂家：	HYNIX SEMICONDUCTOR
描述：	x16 EDO Page Mode DRAM X16 EDO页模式DRAM\n 动态存储器
文件：	总11页 (文件大小：114K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GM71C18163C

GM71CS18163CL

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

Description

Features

The GM71C(S)18163C/CL is the new

generation dynamic RAM organized 1,048,576

x 16 bit. GM71C(S)18163C/CL has realized

higher density, higher performance and various

functions by utilizing advanced CMOS process

technology. The GM71C(S)18163C/CL offers

Extended Data out(EDO) Mode as a high speed

access mode. Multiplexed address inputs permit

the GM71C(S)18163C/CL to be packaged in

standard 400 mil 42pin plastic SOJ, and standard

400mil 44(50)pin plastic TSOP II. The package

size provides high system bit densities and is

compatible with widely available automated

testing and insertion equipment.

* 1,048,576 Words x 16 Bit Organization

* Extended Data Out Mode Capability

* Single Power Supply (5V+/-10%)

* Fast Access Time & Cycle Time

(Unit: ns)

tRAC

tCAC

tRC

tHPC

15 104

18 124

GM71C(S)18163C/CL-5

GM71C(S)18163C/CL-6

GM71C(S)18163C/CL-7

* Low Power

Active : 1045/935/825mW (MAX)

Standby : 11mW (CMOS level : MAX)

0.83mW (L-version : MAX)

* RAS Only Refresh, CAS before RAS Refresh,

Hidden Refresh Capability

* All inputs and outputs TTL Compatible

* 1024 Refresh Cycles/16ms

* 1024 Refresh Cycles/128ms (L-version)

* Self Refresh Operation (L-version)

* Battery Back Up Operation (L-version)

* 2 CAS byte Control

Pin Configuration

42 SOJ

44(50) TSOP II

VSS

VCC

VSS

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

I/O15

I/O14

I/O13

I/O15

40 I/O14

39 I/O13

46 I/O12

⁴⁵VSS

I/O12

VSS

I/O11

I/O4

I/O5

I/O6

I/O7

43 I/O10

42 I/O9

⁴¹I/O8

I/O10

I/O9

I/O8

LCAS

UCAS

RAS

³⁶NC

LCAS

UCAS

RAS

A11

A10

26 A7

28 A5

27 A4

23 A4

VCC

VSS

VCC

VSS

(Top View)

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Pin Description

A0-A9

Function

Read/Write Enable

Output Enable

Power (+5V)

Address Inputs

A0-A9

Refresh Address Inputs

Data Input/Data Output

Row Address Strobe

I/O0-I/O15

RAS

Ground

UCAS, LCAS

Column Address Strobe

No Connection

Ordering Information

Type No.

Access Time

Package

GM71C(S)18163CJ/CLJ -5

GM71C(S)18163CJ/CLJ -6

GM71C(S)18163CJ/CLJ -7

50ns

60ns

70ns

400 Mil

42 Pin

Plastic SOJ

GM71C(S)18163CT/CLT -5

GM71C(S)18163CT/CLT -6

GM71C(S)18163CT/CLT -7

50ns

60ns

70ns

400 Mil

44(50) Pin

Plastic TSOP II

Absolute Maximum Ratings*

Symbol

Parameter

Rating

0 ~ +70

Unit

Ambient Temperature under Bias

TSTG

VIN/OUT

VCC

Storage Temperature

-55 ~ +125

-1.0 ~ +7.0V

Voltage on any Pin Relative to VSS

Supply voltage Relative to VSS

Short Circuit Output Current

-1.0 ~ +7.0V

IOUT

1.0

Power Dissipation

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Recommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol

VCC

Parameter

Min

4.5

Typ

Max

5.5

Unit

Supply Voltage

5.0

VIH

Input High Voltage

Input Low Voltage

2.4

6.0

VIL

-1.0

0.8

Note: All voltage referred to Vss.

The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be

on the same level.

Truth Table

Output

Open

Operation

RAS

LCAS UCAS

Notes

1,3

Standby

Valid

Lower byte

1,3

Valid

Read cycle

Upper byte

Valid

Word

Open

Lower byte

Open

Early write cycle

Upper byte

1,2,3

1,3

Open

Word

Undefined

Lower byte

Upper byte

Delayed Write

cycle

Undefined

Valid

Word

Lower byte

H to L L to H

Read-modify

-write cycle

Upper byte

Valid

Open

Word

H to L

CBR Refresh

Self Refresh

(L-series)

Open

Word

1,3

RAS-only

Refresh cycle

Open

Word

1,3

Read cycle

(Output disabled)

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tWCS >= 0ns Early write cycle

tWCS <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS,LCAS.

ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)

Symbol

Parameter

Min Max Unit Note

Output Level

Output "H" Level Voltage (IOUT = -2mA)

2.4

Output Level

Output "L" Level Voltage (IOUT = 2mA)

0.4

Operating Current

Average Power Supply Operating Current

(RAS, UCAS or LCAS Cycling: tRC = tRC min)

CC1

50ns

60ns

70ns

190

170

1, 2

150

CC2

CC3

Standby Current (TTL)

Power Supply Standby Current

(RAS, UCAS, LCAS = VIH, DOUT = High-Z)

50ns

190

170

150

185

RAS Only Refresh Current

Average Power Supply Current

RAS Only Refresh Mode

(tRC = tRC min)

60ns

70ns

50ns

CC4

EDO Page Mode Current

Average Power Supply Current

EDO Page Mode

1, 3

60ns

70ns

165

145

(tHPC = tHPC min)

Standby Current (CMOS)

Power Supply Standby Current

(RAS, UCAS or LCAS >=VCC - 0.2V, DOUT = High-Z)

CC5

CC6

150

50ns

60ns

70ns

190

170

CAS-before-RAS Refresh Current

(tRC = tRC min)

150

500

Battery Back Up Operating Current(Standby with CBR Ref.)

(CBR refresh, tRC=125us, tRAS<=0.3us,

CC7

CC8

4,5

OUT=High-Z, CMOS interface)

Standby Current RAS = VIH

UCAS, LCAS = VIL

OUT = Enable

Self-Refresh Mode Current

(RAS, UCAS or LCAS <=0.2V, DOUT=High-Z, CMOS interface)

CC9

300

L(I)

Input Leakage Current

Any Input (0V<=VIN<= 6V)

-10

Output Leakage Current

(DOUT is Disabled, 0V<=VOUT<= 6V)

L(O)

Note: 1. ICC depends on output load condition when the device is selected.

CC(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL

3. Address can be changed once or less while UCAS and LCAS = VIH

4. CAS = L (<=0.2V) while RAS = L (<=0.2V).

5. L-version.

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Capacitance (VCC = 5V+/ - 10%, TA = 25C)

Symbol

CI1

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

Min

Max

Unit

Note

CI2

1, 2

CI/O

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. LCAS and UCAS = VIH to disable DOUT

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20)

Test Conditions

Input rise and fall times : 2 ns

Input levels : VIL = 0V, VIH = 3V

Input timing reference levels : 0.8V, 2.4V

Output timing reference levels : 0.8V, 2.0V

Output load : 1TTL gate + CL (100 pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5

C/CL-6

C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

RAS Precharge Time

104

124

tRP

CAS Precharge Time

RAS Pulse Width

50 10,000

7 10,000

10,000

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

ODD

DZO

DZC

CAS Pulse Width

10 10,000 13 10,000

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

11 37

14 45

12 30

14 52

12 35

CAS Hold Time

CAS to RAS Precharge Time

OE to DIN Delay Time

OE Delay Time from DIN

CAS Delay Time from DIN

Transition Time (Rise and Fall)

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Read Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Access Time from RAS

8,9

9,10,17

9,11,17

RAC

CAC

OAC

RCS

RCH

Access Time from CAS

Access Time from Address

Access Time from OE

Read Command Setup Time

Read Command Hold Time to CAS

12,22

Read Command Hold Time to RAS

Column Address to RAS Lead Time

RRH

RAL

CAL

CLZ

OHO

OFF

OEZ

CDD

RCHR

Column Address to CAS Lead Time

CAS to Output in Low-Z

Output Data Hold Time

Output Data Hold Time from OE

Output Buffer Turn-off Time

Output Buffer Turn-off Time to OE

CAS to DIN Delay Time

13,27

Read Command Hold Time from RAS

Output Data hold Time from RAS

Output Buffer turn off to RAS

Output Buffer turn off to WE

OHR

OFR

WEZ

WDD

WE to DIN Delay Time

RAS to DIN Delay Time

RDD

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Write Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Write Command Setup Time

Write Command Hold Time

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Setup Time

14,21

WCS

tWCH

RWL

CWL

15,23

tDS

Data-in Hold Time

tDH

Read- Modify-Write Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

RWC

RWD

CWD

AWD

OEH

Read-Modify-Write Cycle Time

RAS to WE Delay Time

111

136

161

CAS to WE Delay Time

Column Address to WE Delay Time

OE Hold Time from WE

Refresh Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

tCSR

CAS Setup Time

(CAS-before-RAS Refresh Cycle)

CHR

CAS Hold Time

(CAS-before-RAS Refresh Cycle)

RAS Precharge to CAS Hold Time

tRPC

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

EDO Page Mode Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

HPC

EDO Page Mode Cycle Time

100,000

EDO Page Mode RAS Pulse Width

Access Time from CAS Precharge

RAS Hold Time from CAS Precharge

tRASP

9,17,22

tACP

tRHCP

tDOH

Output data Hold Time from CAS low

CAS Hold Time referred OE

CAS to OE Setup Time

COL

COP

Read command Hold Time

from CAS Precharge

RCHP

EDO Page Mode Read-Modify-Write Cycle

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

HPRWC

EDO Page Mode Read-Modify-Write

Cycle Time

14,22

tCPW

WE Delay Time from CAS Precharge

Refresh

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

1024

cycles

REF

Refresh period

1024

cycles

REF

Refresh period (L -Series)

128

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Self Refresh Mode ( L-version )

GM71CS18163

CL-5

GM71CS18163

CL-6

GM71CS18163

CL-7

Symbol

Parameter

Unit Note

Min Max Min Max Min Max

RASS

RAS Pulse Width(Self-Refresh)

100

110

-50

100

130

-50

tRPS

RAS Precharge Time(Self-Refresh)

CAS Hold Time(Self-Refresh)

-50

tCHS

Notes :

1. AC measurements assume tT = 2 ns.

2. An initial pause of 200us is required after power followed by a minimum of eight initializa-

tion cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS

refresh).

3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is

specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then

access time is controlled exclusively by tCAC.

4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is

specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then

access time is controlled exclusively by tAA.

5. Either tODD or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH (min) and VIL (max).

8. Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max). If tRCD or tRAD is greater than the

maximum recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 1TTL loads and 100pF.

10. Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max).

11. Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condi-

tion and are not referred to output voltage levels.

14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only; if tWCS >= tWCS (min), the cycle is an early

write cycle and the data out pin will remain open circuit(high impedance) throughout the

entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min)

tAWD >= tAWD (min) and tCPW >= tCPW (min), the cycle is a read-modify-write and the data out-

put will contain data read from the selected cell; if neither of the above sets of conditions is

satisfied, the condition of the data out (at access time) is indeterminate.

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to

WE leading edge in delayed write or read-modify-write cycles.

16. tRASP defines RAS pulse width in EDO mode cycles.

17. Access time is determined by the longer of tAA or tCAC or tACP.

18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high

impedance): if tOEH<=tCWL, invalid data will be out at each I/O.

19. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the

device. LCAS and UCAS cannot be staggered within the same write/read cycles.

20. All the Vcc and Vss pins shall be supplied with the same voltages.

21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS

or LCAS.

22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.

23. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.

24. tCP is determined by the time that both UCAS and LCAS are high.

25. tHPC(min) can be achieved during a series of EDO page made write cycles or EDO mode

write cycles. It both write and read operation are mixed in a EDO mode RAS cycle(EDO

mode mix cycle (1),(2)) minimum Value of CAS cycle (tCAS+tCP+2tT) becomes greater than

the specified tHPC (min) value. The value of CAS cycle time of mixed EDO mode is shown

in EDO mode mix cycle (1) and (2).

26. When output buffers are enabled once, sustain the low impedance state until valid data

is obtained. When output buffer is turned on and off within a very short time , generally

it causes large Vcc/Vss line noise, which causes to degrade VIH min/VIL max level.

27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.

Hold time and turn off time are specified by the timing specification of later rising edge of

RAS and CAS between tOHR and tOH, and between tOFR and tOFF.

28. EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high

during CAS high, the data will not come out until next CAS access. When WE goes low

during CAS high, the data will not come out until next CAS access.

29.

Please do not use tRASS timing, 10us<=tRASS<=100us. During this period, the device is in

transition state from normal operation mode to self refresh mode. If tRASS>=100us, then

RAS

precharge time should use tRPS instead of tRP.

H or L ( H : VIH(min) <= VIN <= VIH(max), L : VIL(min) <= VIN <= VIL(max) )

30.

Rev 0.1 / Apr’01

GM71C18163C

GM71CS18163CL

Unit: Inches (mm)

Package Dimension

42 SOJ

0.025(0.64)

MIN

0.093(2.38)

MIN

1.058(26.89) MAX

1.072(27.23) MAX

0.128(3.25) MIN

0.148(3.75) MAX

0.050(1.27)

TYP

0.026(0.66) MIN

0.032(0.81) MAX

0.015(0.38) MIN

0.020(0.50) MAX

44(50) TSOP-II

0.016(0.40) MIN

0.024(0.60) MAX

_{0 ~ 5}¡ £

0.004(0.12) MIN

0.008(0.21) MAX

0.820(20.82) MIN

0.830(21.08) MAX

0.037(0.95) MIN

0.041(1.05) MAX

0.047(1.20)

MAX

0.012(0.30) MIN

0.017(0.45) MAX

0.031(0.80)

TYP

0.002(0.05) MIN

0.006(0.15) MAX

Rev 0.1 / Apr’01

GM71CS18163CLJ-5 [HYNIX]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E