H5TC4G43AFR-H9A [HYNIX]
4Gb DDR3L SDRAM; 4GB DDR3L SDRAM型号: | H5TC4G43AFR-H9A |
厂家: | HYNIX SEMICONDUCTOR |
描述: | 4Gb DDR3L SDRAM |
文件: | 总35页 (文件大小:497K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
4Gb DDR3L SDRAM
4Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC4G43AFR-xxA
H5TC4G83AFR-xxA
H5TC4G63AFR-xxA
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 / Apr. 2013
1
Revision History
Revision No.
History
Draft Date
Oct. 2012
Apr. 2013
Remark
0.1
1.0
Initial Release
1.0 version release
Rev. 1.0 / Apr. 2013
2
Description
The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate
III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward
compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD infor-
mation for details.)
4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the
CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• AverageRefreshCycle (Tcaseof0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16
• Driver strength selected by EMRS
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13
supported
• 8 bit pre-fetch
• Programmable additive latency 0, CL-1, and CL-2
• This product in compliance with the RoHS directive.
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
Rev. 1.0 / Apr. 2013
3
ORDERING INFORMATION
Part No.
Configuration
Package
H5TC4G43AFR-*xxA
H5TC4G83AFR-*xxA
H5TC4G63AFR-*xxA
1G x 4
78ball FBGA
96ball FBGA
512M x 8
256M x 16
* xx means Speed Bin Grade
OPERATING FREQUENCY
Frequency [MHz]
Grade
Remark
CL5
CL6
CL7
CL8
CL9
CL10
CL11
CL12
CL13
-G7
-H9
-PB
-RD
667
667
667
800
800
800
800
1066
1066
1066
1066
1066
1066 1333
1066 1333
1066 1333
1333
1333
1333
1600
1600
1866
Rev. 1.0 / Apr. 2013
4
Package Ballout/Mechanical Dimension
x4 Package Ball out (Top view): 78ball FBGA Package
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
VSS
VDD
VSSQ
DQ2
NF
NC
DQ0
DQS
DQS
NF
NF
DM
VSS
VSSQ
DQ3
VSS
NF
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
A
B
C
D
E
F
VDDQ
VSSQ
VREFDQ
NC
DQ1
VDD
NF
VDDQ
VSS
VDD
CS
RAS
CAS
WE
BA2
A0
CK
VSS
VDD
ZQ
G
H
J
ODT
CK
CKE
NC
G
H
J
NC
A10/AP
A15
VSS
BA0
A3
VREFCA
BA1
A4
VSS
K
L
VDD
VSS
A12/BC
A1
VDD
VSS
K
L
A5
A2
M
N
VDD
VSS
A7
A9
A11
A6
VDD
VSS
M
N
RESET
A13
A14
A8
1
2
3
4
5
6
7
8
9
Note: NF (No Function) - This is applied to balls only used in x4 configuration.
1
2 3
7
8 9
A
B
C
D
E
F
(Top View: See the balls through the Package)
G
H
J
Populated ball
Ball not populated
K
L
M
N
Rev. 1.0 / Apr. 2013
5
x8 Package Ball out (Top view): 78ball FBGA Package
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
VSS
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
CS
NC
DQ0
DQS
DQS
DQ4
RAS
CAS
WE
NF/TDQS
DM/TDQS
DQ1
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
A
B
C
D
E
F
VDDQ
VSSQ
VREFDQ
NC
VDD
DQ7
CK
G
H
J
ODT
NC
CK
CKE
NC
G
H
J
A10/AP
A15
VSS
BA0
A3
BA2
A0
VREFCA
BA1
A4
VSS
K
L
VDD
VSS
A12/BC
A1
VDD
VSS
K
L
A5
A2
M
N
VDD
VSS
A7
A9
A11
A6
VDD
VSS
M
N
RESET
A13
A14
A8
1
2
3
4
5
6
7
8
9
1
2 3
7
8 9
A
B
C
D
E
F
(Top View: See the balls through the Package)
G
H
J
Populated ball
Ball not populated
K
L
M
N
Rev. 1.0 / Apr. 2013
6
x16 Package Ball out (Top view): 96ball FBGA Package
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQU5
VDD
DQU3
VDDQ
VSSQ
DQL2
DQL6
VDDQ
VSS
DQU7
VSS
DQU1
DMU
DQL0
DQSL
DQSL
DQL4
RAS
CAS
WE
DQU4
DQSU
DQSU
DQU0
DML
DQL1
VDD
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
A
B
C
D
E
F
VDDQ
VSSQ
VREFDQ
NC
G
H
J
G
H
J
DQL7
CK
DQL5
VSS
K
L
ODT
VDD
CS
CK
VDD
CKE
NC
K
L
NC
A10/AP
NC
ZQ
M
N
P
R
T
VSS
BA0
BA2
A0
VREFCA
BA1
VSS
M
N
P
R
T
VDD
A3
A12/BC
A1
VDD
VSS
VSS
A5
A2
A4
VDD
A7
A9
A11
A6
VDD
VSS
VSS
RESET
A13
A14
A8
1
2
3
4
5
6
7
8
9
1
2 3
7
8 9
A
B
C
D
E
F
G
H
J
(Top View: See the balls through the Package)
Populated ball
Ball not populated
K
L
M
N
P
R
T
Rev. 1.0 / Apr. 2013
7
Pin Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK.
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank).
CKE, (CKE0),
(CKE1)
Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS is registered HIGH.
CS provides for external Rank selection on systems with multiple Ranks.
CS is considered part of the command code.
CS, (CS0),
(CS1), (CS2),
(CS3)
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8
configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,
DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable
ODT.
ODT, (ODT0),
(ODT1)
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
RAS.
CAS. WE
Input
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access. DM is sampled
on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by
Mode Register A11 setting in MR1.
DM, (DMU),
(DML)
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge
BA0 - BA2
A0 - A15
Input command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective
bank. (A10/AP and A12/BC have additional functions, see below).
Input
The address inputs also provide the op-code during Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
A10 / AP
A12 / BC
Input
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst
Input chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Rev. 1.0 / Apr. 2013
8
Symbol
Type
Function
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
RESET
Input
Input /
Output
DQ
Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
DQU, DQL,
DQS, DQS,
DQSU, DQSU, Output
DQSL, DQSL
Input /
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
TDQS, TDQS Output function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
NC
NF
No Connect: No internal electrical connection is present.
No Function
VDDQ
VSSQ
VDD
Supply DQ Power Supply: 1.35 V +0.100/- 0.067 V
Supply
Supply
Supply
Supply
Supply
Supply
DQ Ground
Power Supply: 1.35 V +0.100/- 0.067 V
Ground
VSS
Reference voltage for DQ
Reference voltage for CA
Reference Pin for ZQ calibration
VREFDQ
VREFCA
ZQ
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
Rev. 1.0 / Apr. 2013
9
ROW AND COLUMN ADDRESS TABLE
4Gb
Configuration
# of Banks
1Gb x 4
512Mb x 8
256Mb x 16
8
8
8
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9,A11
1 KB
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
1 KB
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9
2 KB
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Rev. 1.0 / Apr. 2013
10
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
Notes
VDD
- 0.4 V ~ 1.80 V
V
1,3
VDDQ
VIN, VOUT
TSTG
- 0.4 V ~ 1.80 V
- 0.4 V ~ 1.80 V
-55 to +100
V
1,3
1
V
oC
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
Parameter
Rating
Units
Notes
0 to 85
oC
1,2
Normal Operating Temperature Range
Extended Temperature Range (Optional)
TOPER
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Man-
ual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b). DDR3
SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the DIMM
SPD for tREFI requirements in the EXtended Temperature Range.
Rev. 1.0 / Apr. 2013
11
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
1.283
1.35
1.45
V
V
1,2,3,4
1,2,3,4
Supply Voltage
Supply Voltage for Output
VDDQ
1.283
1.35
1.45
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - DDR3 (1.5V) operation
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
1.425
1.5
1.575
V
V
1,2,3
1,2,3
Supply Voltage
Supply Voltage for Output
VDDQ
1.425
1.5
1.575
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.0 / Apr. 2013
12
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
tCKSRX
Tmin = 10ns
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
Tmin = 10ns
CKE
VALID
VALID
tDLLK
tIS
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
1)
COMMAND
BA
READ
READ
1)
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
VALID
tIS
tIS
ODT
RTT
READ
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
DON’T CARE
TIME BREAK
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 1.0 / Apr. 2013
13
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
•
”0” and “LOW” is defined as VIN <= V
ILAC(max).
”1” and “HIGH” is defined as VIN >= V
IHAC(max).
•
•
•
•
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0 (Output Buffer enabled in MR1);
B
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.0 / Apr. 2013
14
IDDQ (optional)
IDD
VDD
RESET
CK/CK
VDDQ
DDR3L
SDRAM
RTT = 25 Ohm
CKE
CS
DQS, DQS
DQ, DM,
VDDQ/2
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 1.0 / Apr. 2013
15
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Symbol
Unit
7-7-7
1.875
7
9-9-9
1.5
9
11-11-11
13-13-13
1.07
13
tCK
1.25
11
11
39
28
11
24
32
5
ns
CL
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nRCD
nRC
nRAS
nRP
7
9
13
27
20
7
33
24
9
45
32
13
1KB page size
2KB page size
1KB page size
2KB page size
20
27
4
20
30
4
26
nFAW
33
5
nRRD
6
5
6
6
nRFC -512Mb
nRFC-1 Gb
nRFC- 2 Gb
nRFC- 4 Gb
nRFC- 8 Gb
48
59
86
139
187
60
74
107
174
234
72
88
128
208
280
85
103
150
243
328
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
IDD0
Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table
IDD1
4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 4.
Rev. 1.0 / Apr. 2013
16
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
IDD2N
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable
at 0; Pattern Details: see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;
IDD2NT
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: tog-
gling according to Table 6; Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
IDD2P0
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
IDD2P1
IDD2Q
IDD3N
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Fast Exitc)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable
at 0; Pattern Details: see Table 5.
Rev. 1.0 / Apr. 2013
17
Symbol
IDD3P
Description
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer
IDD4R
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-
IDD4W
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-
mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM:
stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in
IDD5B
Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,
Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-
put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-
IDD6ET
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
MID_LEVEL
Rev. 1.0 / Apr. 2013
18
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a), f); AL: CL-
1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord-
ing to Table 10; Data IO: read data burst with different data between one burst and the next one
according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0,
IDD7
1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Apr. 2013
19
Table 3 - IDD0 Measurement-Loop Patterna)
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
-
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
20
Table 4 - IDD1 Measurement-Loop Patterna)
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD 00
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRCD
...
0
1
0
1
0
0
0
0
0
0
0
0
00000000
-
nRAS
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD 00
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRCD
...
0
1
0
1
0
0
0
0
F
0
00110011
-
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.0 / Apr. 2013
21
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
0
1
0
0
0
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
22
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
Datab)
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
-
2,3
D,D
RD
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
23
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
0
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
-
2,3
D,D
WR
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 9 - IDD5B Measurement-Loop Patterna)
Datab)
0
1
0
REF
D, D
D, D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
1.2
00
00
3,4
5...8
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC-1
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
24
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
1
0
1
2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
repeat above D Command until nRRD - 1
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
D
1
0
0
0
0
3
00
0
0
F
0
-
-
4
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
0
F
0
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
2*nFAW+nRRD+1 RDA
ACT
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
11
D
2&nFAW+nRRD+
2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
0
0
-
14 2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
15 3*nFAW
16 3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
-
19 3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
25
IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.
IDD Specification
Speed Grade DDR3L - 1066 DDR3L - 1333 DDR3L - 1600 DDR3L - 1866
Bin
7-7-7
9-9-9
11-11-11
13-13-13
Unit
Notes
Symbol
30
41
37
51
8
32
42
39
53
8
33
43
40
53
8
34
44
41
54
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
x4/x8
x16
IDD0
IDD01
IDD2P0
IDD2P1
IDD2N
IDD2NT
IDD2Q
IDD3P
IDD3N
IDD4R
x4/x8
x16
x4/x8
x16
12
9
12
10
14
16
20
20
24
17
21
17
18
25
27
75
110
80
120
200
12
15
16
18
130
195
12
10
14
17
22
21
27
17
23
18
19
26
29
85
125
90
135
200
12
15
16
18
135
200
13
11
15
18
23
22
29
17
24
18
20
27
29
95
140
100
155
200
12
15
16
18
145
205
x4/x8
x16
14
15
20
18
23
16
20
17
18
24
26
65
90
70
100
200
12
15
16
18
110
170
x4/x8
x16
x4/x8
x16
x4/x8
x16
x4/x8
x16
x4/x8
x16
x4/x8
x16
x4/x8
x16
IDD4w
IDD5B
IDD6
x4/x8/x16
x4/x8, 1
x16, 1
x4/x8, 2
x16, 2
x4/x8
x16
IDD6ET
IDD7
Notes:
1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC.
2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC.
Rev. 1.0 / Apr. 2013
26
Input/Output Capacitance
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameter
Symbol
Units Notes
Min
Max
Min
Max Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS,
TDQS, TDQS)
CIO
1.4
2.5
1.4
2.5
1.4
2.3
1.4
2.2
1.4
2.1
pF
1,2,3
Input capacitance, CK and
CK
Input capacitance delta
CK and CK
Input capacitance delta,
DQS and DQS
Input capacitance
(All other input-only pins)
Input capacitance delta
(All CTRL input-only pins)
CCK
CDCK
CDDQS
CI
0.8
0
1.6
0.15
0.20
1.3
0.8
0
1.6
0.15
0.20
1.3
0.8
0
1.4
0.15
0.15
1.3
0.8
0
1.4
0.15
0.15
1.2
0.8
0
1.3
0.15
0.15
1.2
pF
pF
pF
pF
pF
2,3
2,3,4
2,3,5
2,3,6
2,3,7,8
0
0
0
0
0
0.75
-0.5
0.75
-0.5
0.75
-0.4
0.75
-0.4
0.75
-0.4
CDI_CTR
0.3
0.3
0.2
0.2
0.2
L
Input capacitance delta
(All ADD/CMD input-only
pins)
CDI_ADD
_CMD
-0.5
0.5
-0.5
0.5
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF 2,3,9,10
Input/output capacitance
delta
(DQ, DM, DQS, DQS)
Input/output capacitance
of ZQ pin
CDIO
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
2,3,12
CZQ
Notes:
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK.
5. Absolute value of CIO(DQS)-CIO(DQS).
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTR applies to ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance an ZQ pin: 5 pF.
Rev. 1.0 / Apr. 2013
27
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3L-800E
6-6-6
Unit
Notes
CL - nRCD - nRP
Parameter
Symbol
min
max
tAA
15
20
ns
ns
ns
ns
ns
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tRCD
15
15
—
—
tRP
tRC
52.5
37.5
—
ACT to ACT or REF command period
ACT to PRE command period
tRAS
9 * tREFI
tCK(AVG)
tCK(AVG)
3.0
2.5
3.3
3.3
ns
ns
CL = 5
CL = 6
CWL = 5
CWL = 5
1,2,3,4,11,12
1,2,3
12
nCK
nCK
5, 6
5
Supported CL Settings
Supported CWL Settings
Rev. 1.0 / Apr. 2013
28
DDR3L-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3L-1066F
7-7-7
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ns
ns
ns
ns
ACT to internal read or
write delay time
tRCD
13.125
13.125
50.625
—
—
—
tRP
PRE command period
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
37.5
3.0
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
ns
ns
1,2,3,4,6,11,12
CWL = 6
Reserved
4
1,2,3,6
1,2,3,4
4
CWL = 5
CL = 6
2.5
3.3
ns
CWL = 6
Reserved
Reserved
ns
CWL = 5
CL = 7
ns
CWL = 6
1.875
1.875
< 2.5
< 2.5
ns
1,2,3,4
4
CWL = 5
CL = 8
Reserved
ns
CWL = 6
ns
1,2,3
12
nCK
nCK
Supported CL Settings
Supported CWL Settings
5, 6, 7, 8
5, 6
Rev. 1.0 / Apr. 2013
29
DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3L-1333H
Unit
Note
CL - nRCD - nRP
9-9-9
Parameter
Symbol
min
13.5
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,10
13.5
(13.125)5,10
ACT to internal read or
write delay time
—
—
—
13.5
(13.125)5,10
PRE command period
49.5
(49.125)5,10
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
36
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
3.0
ns
ns
ns
ns
ns
ns
1,2,3,4,7,11,12
CWL = 6, 7
Reserved
4
CWL = 5
2.5
3.3
1,2,3,7
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,7
4
4
1.875
1.875
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,7
(Optional)5,10
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 5
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
4
Reserved
CWL = 6
< 2.5
1,2,3,7
1,2,3,4
4
CWL = 7
Reserved
Reserved
CWL = 5, 6
CWL = 7
CL = 9
1.5
1.5
<1.875
<1.875
1,2,3,4
4
CWL = 5, 6
Reserved
(Optional)
CL = 10
ns
ns
1,2,3
5
tCK(AVG)
CWL = 7
nCK
Supported CL Settings
Supported CWL Settings
5, 6, 7, 8, 9, 10
5, 6, 7
nCK
Rev. 1.0 / Apr. 2013
30
DDR3L-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3L-1600K
11-11-11
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.75
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,10
13.75
(13.125)5,10
ACT to internal read or
write delay time
—
—
—
13.75
(13.125)5,10
PRE command period
48.75
(48.125)5,10
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
35
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
3.0
ns
ns
ns
ns
ns
ns
1,2,3,4,8,11,12
CWL = 6, 7
Reserved
4
CWL = 5
2.5
3.3
1,2,3,8
CL = 6
CL = 7
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,8
4
4
1.875
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,8
(Optional)5,10
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
Reserved
4
4
Reserved
1.875
1.5
< 2.5
1,2,3,8
1,2,3,4,8
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
<1.875
tCK(AVG)
CWL = 7
ns
1,2,3,4,8
(Optional)5,10
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
ns
ns
1,2,3,4
4
CWL = 5, 6
Reserved
CL = 10 CWL = 7
CWL = 8
1.5
<1.875
<1.5
ns
1,2,3,8
1,2,3,4
4
Reserved
Reserved
ns
CWL = 5, 6,7
CL = 11
ns
CWL = 8
1.25
ns
1,2,3
nCK
nCK
Supported CL Settings
Supported CWL Settings
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Rev. 1.0 / Apr. 2013
31
DDR3L-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3L-1866M
13-13-13
Unit
Note
CL - nRCD - nRP
Parameter
Internal read command
to first data
Symbol
min
max
13.91
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,13
13.91
(13.125)5,13
13.91
ACT to internal read or
write delay time
—
—
PRE command period
(13.125)5,13
ACT to PRE command
period
tRAS
tRC
34
9 * tREFI
47.91
(47.125)5,13
3.0
ACT to ACT or PRE
command period
-
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
3.3
ns
ns
ns
ns
ns
ns
1, 2, 3, 4, 9
CWL = 6,7,8,9
Reserved
4
CWL = 5
2.5
1.875
1.875
1.5
3.3
1, 2, 3, 9
1, 2, 3, 4, 9
CL = 6
CL = 7
CWL = 6
CWL = 7,8,9
CWL = 5
Reserved
Reserved
Reserved
4
4
< 2.5
< 2.5
<1.875
tCK(AVG)
CWL = 6
ns
1, 2, 3, 4, 9
(optional)
Reserved
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7,8,9
CWL = 5
ns
ns
ns
ns
ns
ns
4
4
CWL = 6
CWL = 7
CWL = 8,9
CWL = 5, 6
1, 2, 3, 9
1, 2, 3, 4, 9
CL = 8
CL = 9
Reserved
Reserved
Reserved
4
4
tCK(AVG)
CWL = 7
ns
1, 2, 3, 4, 9
(optional)
Reserved
Reserved
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
CWL = 9
ns
ns
ns
ns
ns
ns
1, 2, 3, 4, 9
4
4
CWL = 5, 6
CWL = 7
CWL = 8
CL = 10
CL = 11
1.5
<1.875
<1.5
1, 2, 3, 9
1, 2, 3, 4, 9
4
Reserved
Reserved
CWL = 5,6,7
1.25
tCK(AVG)
CWL = 8
ns
1, 2, 3, 4, 9
(optional)
Reserved
Reserved
Reserved
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 9
CWL = 5,6,7,8
CWL = 9
CWL = 5,6,7,8
CWL = 9
ns
ns
ns
ns
ns
1, 2, 3, 4
4
1,2,3,4
4
CL = 12
CL = 13
1.07
<1.25
1, 2, 3
nCK
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8, 9, 10, 11, 13
5, 6, 7, 8, 9
Rev. 1.0 / Apr. 2013
32
Speed Bin Table Notes
Absolute Specification (T
; V
= V = 1.35V +0.100/- 0.067 V);
OPER
DDQ DD
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-
tory in SPD coding.
13. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin
must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866M devices sup-
porting down binning to DDR3-1600K or DDR3-1333H or 1066F should program 13.125ns in SPD
bytes for tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRC-
min(byte 21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin
= 34ns + 13.125ns)
Rev. 1.0 / Apr. 2013
33
Package Dimensions
Package Dimension(x4/x8): 78Ball Fine Pitch Ball Grid Array Outline
9.0000.100
A1 INDEX MARK
TOP VIEW
SIDE VIEW
0.800 X 8 = 6.400
0.800
1.3000.100
A1 BALL MARK
9
8
7
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
78x0.4500.050
1.600 1.600
BOTTOM VIEW
Rev. 1.0 / Apr. 2013
34
Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline
9.0000.100
A1 INDEX MARK
TOP VIEW
SIDE VIEW
0.800 X 8 = 6.400
0.800
1.3000.100
9
8
7
3
2
1
A1 BALL MARK
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.600 1.600
96x0.4500.050
BOTTOM VIEW
Rev. 1.0 / Apr. 2013
35
相关型号:
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