HMA425U6AFR6N-UH [HYNIX]
DDR4 SDRAM Unbuffered DIMM Based on 4Gb A-die;
| 型号： | HMA425U6AFR6N-UH |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR4 SDRAM Unbuffered DIMM Based on 4Gb A-die 动态存储器 双倍数据速率 |
| 文件： | 总75页 (文件大小：1340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
288pin DDR4 SDRAM Unbuffered DIMM
DDR4 SDRAM Unbuffered DIMM
Based on 4Gb A-die
HMA425U6AFR6N
HMA451U6AFR8N
HMA451U7AFR8N
HMA41GU6AFR8N
HMA41GU7AFR8N
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.7 / Mar.2016
1
Revision History
Revision No.
History
Draft Date
Dec.2014
Jan.2015
Remark
0.1
0.2
1.0
Initial Release
Changed development plan
IDD Specification update
May.2015
Changed maximum VDDSPD from 2.75V to 3.6
Module dimension update(PCB)
Corrected Pin Assignments
1.1
1.2
1.3
1.4
1.5
Jun.2015
Jul.2015
Aug.2015
Oct.2015
Dec.2015
Added development plan (1Rx16)
Changed Module Dimension
Updated JEDEC Specification
Deleted Speed Grade Table
1.6
1.7
Updated IDD Specification(1Rx16)
Dec.2015
Mar.2016
Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns)
Updated JEDEC Specification
Rev. 1.7 / Mar.2016
2
Description
SK hynix Unbuffered DDR4 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices.
These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as
PCs and workstations.
Features
• Power Supply: VDD=1.2V (1.14V to 1.26V)
• VDDQ = 1.2V (1.14V to 1.26V)
• VPP - 2.5V (2.375V to 2.75V)
• VDDSPD=2.25V to 3.6V
• Functionality and operations comply with the DDR4 SDRAM datasheet
• 16 internal banks
• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-
ferent bank group accesses are available
• Data transfer rates: PC4-2400, PC4-2133, PC4-1866, PC4-1600
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
• Per DRAM Addressability is supported
• Internal Vref DQ level generation is available
Ordering Information
# of
ranks
Part Number
Density
Organization
Component Composition
HMA425U6AFR6N-TF/UH
HMA451U6AFR8N-TF/UH
HMA451U7AFR8N-TF/UH
HMA41GU6AFR8N-TF/UH
HMA41GU7AFR8N-TF/UH
2GB
4GB
4GB
8GB
8GB
256Mx64
512Mx64
512Mx72
1Gx64
256Mx16(H5AN4G6NAFR)*4
512Mx8(H5AN4G8NAFR)*8
512Mx8(H5AN4G8NAFR)*9
512Mx8(H5AN4G8NAFR)*16
512Mx8(H5AN4G8NAFR)*18
1
1
1
2
2
1Gx72
Rev. 1.7 / Mar.2016
3
Key Parameters
CAS
Latency
(tCK)
tCK
(ns)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
MT/s
Grade
CL-tRCD-tRP
13.75
13.75
48.75
(48.50)*
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
-PB
-RD
-TF
1.25
1.071
0.937
0.833
11
13
15
17
35
34
33
32
11-11-11
13-13-13
15-15-15
17-17-17
(13.50)* (13.50)*
13.92 13.92
(13.50)* (13.50)*
14.06 14.06
(13.50)* (13.50)*
14.16 14.16
(13.75)* (13.75)*
47.92
(47.50)*
47.06
(46.50)*
46.16
(45.75)*
-UH
*SK hynix DRAM devices support optional downbinning to CL15, CL13 and CL11. SPD setting is programmed to match.
Address Table
2GB(1Rx16) 4GB(1Rx8) 8GB(2Rx8) 4GB(1Rx8) 8GB(2Rx8)
# of Bank Groups
Bank Address BG Address
Bank Address in a BG
4
4
4
4
4
BG0
BG0~BG1
BA0~BA1
A0~A14
A0~ A9
1 KB
BG0~BG1
BA0~BA1
A0~A14
A0~ A9
1 KB
BG0~BG1
BA0~BA1
A0~A14
A0~ A9
1 KB
BG0~BG1
BA0~BA1
A0~A14
A0~ A9
1 KB
BA0~BA1
A0~A14
A0~ A9
2 KB
Row Address
Column Address
Page size
Rev. 1.7 / Mar.2016
4
Pin Descriptions
Pin Name
Description
Pin Name
Description
A0-A171
BA0, BA1
BG0, BG1
I2C serial bus clock for SPD-TSE
I2C serial bus line for SPD-TSE
I2C slave address select for SPD-TSE
SDRAM parity input
SDRAM address bus
SDRAM bank select
SCL
SDA
SDRAM bank group select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SA0-SA2
PARITY
VDD
RAS_n2
CAS_n3
WE_n4
SDRAM I/OO and core power supply
Chip ID lines
C0, C1, C2
Optional power Supply on socket but
not used on UDIMM
CS0_n, CS1_n, DIMM Rank Select Lines
12V
VREFCA
VSS
SDRAM command/address reference
supply
CKE0, CEK1
ODT0, ODT1
SDRAM clock enable lines input
SDRAM on-die termination control lines
input
Power supply return (ground)
ACT_n
DQ0-DQ63
CB0-CB7
SDRAM activate
VDDSPD
ALERT_n
VPP
Serial SPD-TSE positive power supply
SDRAM ALERT_n output
SDRAM Supply
DIMM memory data bus
DIMM ECC check bits
Dummy loads for mixed populations of
x4 based and x8 based RDIMMs.
TDQS0_t-TDQS8_t
TDQS0_c-TDQS8_c
Not used on UDIMMs.
SDRAM data strobes
DQS0_t-DQS8_t
DQS0_c-DQS8_c
(positive line of differential pair)
SDRAM data strobes
RESET_n
Set DRAMs to a Known State
(negative line of differential pair)
SDRAM data masks/data bus inersion
(x8-based x72 DIMMs)
DM0_n-DM8_n,
DBI0_n-DBI8_n
SPD signals a thermal event has
occurred
EVENT_n
VTT
SDRAM clock (positive line of differen-
tial pair)
CK0_t, CK1_t
CK0_c, CK1_c
SDRAM I/O termination supply
Reserved for future use
SDRAM clock (positive line of differen-
tial pair)
RFU
1. Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs, this connection pin is NC.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.7 / Mar.2016
5
Input/Output Functional Descriptions
Symbol
Type
Function
CK0_t, CK0_c,
CK1_t, CK1_c
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
device input buffers and output drivers. Taking CKE LOW provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in
any bank). CKE is aynchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref
CKE0, CKE1
Input have become stable during the power on and initialization sequence, they must be
maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE,
are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-
Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
CS0_n, CS1_n,
CS2_n, CS3_n
external Rank selection on systems with multiple Ranks. CS_n is considered part of the
command code.
Input
CS2_n and CS_3_n are not used on UDIMMs.
Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of
Input stacked component. Chip ID is considered part of the command code.
Not used on UDIMMs.
C0, C1, C2
ODT0, ODT1
ACT_n
On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,
DQS_c and DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. For x16 configuration, ODT is
Input
applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal.
The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
Input with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as
Row Address A16, A15 and A14.
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. Those pins have multi function. For example, for activation
Input with ACT_n Low, these are Addresses like A16, A15, and A14. But for non-activation
command with ACT_n High, these are Command pins for Read, Write, and other
commands defined in command truth table.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
Input data is masked when DM_n is sampled LOW coincident with that input data during
a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function
by Mode Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or
TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output
identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data
will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is
HIGH. TDQS is only supported in x8 SDRAM configurations.
DM_n/DBI_n/
TDQS_t,
(DMU_n/DBIU_n), Output
(DML_n/DBIL_n)
Input/
TDQS is not valid for UDIMMs.
Rev. 1.7 / Mar.2016
6
Symbol
Type
Function
Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write, or
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle. x4/x8 SDRAM configurations have BG0 and BG1. x16
based SDRAMs only have BG0.
BG0, BG1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
BA0, BA1
A0 - A17
Input Precharge command is being applied. Bank address also determines which mode
register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions. See other rows. The address inputs also provide the op-code during
Input
Mode Register Set commands.
A17 is only defined for the x4 SDRAM configuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
A10 / AP
Input
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if
Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
A12 / BC_n
RESET_n
CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
Input/ CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the
Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor
specific data sheets to determine which DQ is used.
DQ
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7;
Input/ DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and
Output DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively,
to provide differential pair signaling to the system during reads and writes. DDR4
SDRAM supports differential data strobe only and does not support single-ended.
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
TDQS_t, TDQS_c Output Termination Data Strobe: TDQS_t/TDQS_c are not valid for UDIMMs.
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
PARITY
Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity
should be maintained at the rising edge of the clock and at the same time with
command & address with CS_n LOW.
Rev. 1.7 / Mar.2016
7
Symbol
Type
Function
Alert: It has multiple functions, such as CRC error flag, Command and Address Parity
error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for
the period time interval and goes back HIGH. If there is an error in Command Address
ALERT_n
Output Parity Check, then ALERT_n goes LOW for a relatively long period until on going DRAM
internal recovery transaction is complete. During Connectivity Test mode, this pin
functions as an input.
Using this signal or not is dependent on the system.
RFU
NC
Reserved for Future Use. No on DIMM electrical connection is present.
No Connect: No on DIMM electrical connection is present.
VDD1
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Power Supply: 1.2 V +/- 0.06 V
Ground
VSS
DRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)
Power Supply for termination of Address, Command and Control, VDD/2.
12V supply not used on UDIMMs.
VPP
VTT2
12V
Power supply used to power the I2C bus on the SPD-TSE
Reference voltage for CA
VDDSDP
VREFCA
Note:
1. For PC4 VDD 1.2V. For PC4L VDD is TBD.
2. For PC4 VTT is 0.60V. For PC4L VTT is TBD.
Rev. 1.7 / Mar.2016
8
Pin Assignments
Front Side
Pin
Back Side
Pin Label
Front Side
Pin Label
Back Side
Pin Label
Pin
Pin
Pin
Pin Label
1
NC
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
NC
VREFCA
VSS
74
75
76
77
CK0_t
CK0_c
VDD
218
219
220
221
CK1_t
CK1_c
VDD
2
VSS
3
DQ4
4
VSS
DQ5
VTT
VTT
5
DQ0
VSS
KEY
6
VSS
DQ1
7
DM0_n, DBI0_n, NC
VSS
78
79
EVENT_n
A0
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
PARITY
VDD
BA1
8
NC
DQS0_c
DQS0_t
VSS
9
VSS
80
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DQ6
81
BA0
A10/AP
VDD
RFU
VSS
DQ7
82
RAS_n/A16
VDD
DQ2
VSS
83
VSS
DQ3
84
CS0_n
VDD
WE_n/A14
VDD
NC
DQ12
VSS
85
VSS
DQ13
VSS
86
CAS_n/A15
ODT0
VDD
DQ8
87
VDD
A13
VSS
DQ9
88
DM1_n, DBI1_n, NC
VSS
89
CS1_n
VDD
VDD
NC
NC
VSS
DQS1_c
DQS1_t
VSS
90
91
ODT1
NC
DQ14
VSS
92
VDD
VDD
NC
DQ15
VSS
93
NC
DQ10
VSS
94
VSS
SA2
DQ11
VSS
95
DQ36
VSS
VSS
DQ20
VSS
96
DQ37
VSS
DQ21
VSS
97
DQ32
DQ16
VSS
98
VSS
DQ33
VSS
DQ17
VSS
99
DM4_n, DBI4_n, NC
NC
DM2_n, DBI2_n, NC
NC
100
101
102
103
104
105
106
107
108
109
DQS4_c
DQS4_t
VSS
DQS2_c
DQS2_t
VSS
VSS
VSS
DQ38
VSS
DQ22
VSS
DQ39
VSS
DQ23
VSS
DQ34
VSS
DQ18
VSS
DQ35
VSS
DQ19
VSS
DQ44
DQ28
VSS
VSS
DQ45
VSS
DQ29
VSS
DQ40
VSS
DQ24
DQ41
Rev. 1.7 / Mar.2016
9
Front Side
Pin Label
Back Side
Pin Label
Front Side
Pin Label
Back Side
Pin Label
Pin
Pin
Pin
Pin
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
VSS
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
213
214
215
215
216
217
DQ25
VSS
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DM5_n, DBI5_n, NC
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
VSS
DM3_n, DBI3_n, NC
NC
DQS5_C
NC
VSS
DQS3_c
DQS3_t
VSS
VSS
DQS5_t
VSS
DQ46
DQ30
VSS
VSS
DQ47
VSS
DQ31
VSS
DQ42
DQ26
VSS
VSS
DQ43
VSS
DQ27
VSS
DQ52
CB4, NC
VSS
VSS
DQ53
VSS
CB5, NC
VSS
DQ48
CB0, NC
VSS
VSS
DQ49
VSS
CB1, NC
VSS
DM6_n, DBI6_n, NC
DM8_n, DBI8_n, NC
NC
NC
DQS6_c
DQS6_t
VSS
DQS8_c
DQS8_t
VSS
VSS
VSS
DQ54
CB6, NC
VSS
VSS
DQ55
VSS
CB7, NC
VSS
DQ50
CB2, NC
VSS
VSS
DQ51
VSS
CB3, NC
VSS
DQ60
RESET_n
VDD
VSS
DQ61
VSS
CKE1
VDD
DQ56
CKE0
VDD
VSS
DQ57
VSS
RFU
DM7_n, DBI7_n, NC
ACT_n
BG0
VDD
NC
VSS
DQ62
VSS
DQ58
VSS
SA0
SA1
SCL
DQS7_c
DQS7_t
VSS
BG1
VDD
ALERT_n
VDD
A12/BC_n
A9
DQ63
VSS
A11
VDD
A7
DQ59
VSS
A8
VDD
A6
A5
VDDSPD
SDA
VDD
A4
A3
VDD
VPP
VPP
RFU
VPP
A1
A2
VPP
VDD
VDD
VPP
Rev. 1.7 / Mar.2016
10
Functional Block Diagram
2GB, 256Mx64 Module(1Rank of x16)
CK0_t, CK0_c
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
ZQ
VSS
ZQ
VSS
DQS0_t
DQS0_c
DQ [7:0]
DQL_t
DQL_c
DQL [7:0]
DQS2_t
DQS2_c
DQ [23:16]
DQL_t
DQL_c
DQL [7:0]
D0
D1
DM0_n/DBI0_n
DM0_n/DBI0_n
DM2_n/DBI2_n
DM0_n/DBI0_n
DQS1_t
DQS1_c
DQU_t
DQU_c
DQS3_t
DQS3_c
DQU_t
DQU_c
DQ [15:8]
DQU [7:0]
DQ [31:24]
DQU [7:0]
DM1_n/DBI1_n
DM1_n/DBI1_n
DM3_n/DBI3_n
DM1_n/DBI1_n
ZQ
VSS
ZQ
VSS
DQS4_t
DQS4_c
DQ [39:32]
DQL_t
DQL_c
DQL [7:0]
DQS6_t
DQS6_c
DQ [55:48]
DQL_t
DQL_c
DQL [7:0]
D2
D3
DM4_n/DBI4_n
DM0_n/DBI0_n
DM6_n/DBI6_n
DM0_n/DBI0_n
DQS5_t
DQS5_c
DQU_t
DQU_c
DQS7_t
DQS7_c
DQU_t
DQU_c
DQ [47:40]
DQU [7:0]
DQ [63:56]
DQU [7:0]
DM5_n/DBI5_n
DM1_n/DBI1_n
DM7_n/DBI7_n
DM1_n/DBI1_n
VDDSPD
SPD
VPP
D0–D3
D0–D3
SCL
SDA
SA0 SA1 SA2
VDD
VTT
SA0 SA1
Serial PD with Thermal sensor
SA2
D0–D3
D0–D3
VREFCA
VSS
Note:
1. Unless otherwize noted, resistor values are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
Rev. 1.7 / Mar.2016
11
4GB, 512Mx64 Module(1Rank of x8)
CK0_t, CK0_c
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
DQS0_t
DQS0_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS4_t
DQS4_c
DQ [39:32]
DQS_t
DQS_c
DQ [7:0]
D0
D1
D2
D3
D4
D5
D6
D7
DM0_n/DBI0_n
DM_n/DBI_n
DM4_n/DBI4_n
DM_n/DBI_n
DQS1_t
DQS1_c
DQ [15:8]
DQS_t
DQS_c
DQ [7:0]
DQS5_t
DQS5_c
DQ [47:40]
DQS_t
DQS_c
DQ [7:0]
DM1_n/DBI1_n
DM_n/DBI_n
DM5_n/DBI5_n
DM_n/DBI_n
DQS2_t
DQS2_c
DQ [23:16]
DQS_t
DQS_c
DQ [7:0]
DQS6_t
DQS6_c
DQ [55:48]
DQS_t
DQS_c
DQ [7:0]
DM2_n/DBI2_n
DM_n/DBI_n
DM6_n/DBI6_n
DM_n/DBI_n
DQS3_t
DQS3_c
DQ [31:24]
DQS_t
DQS_c
DQ [7:0]
DQS7_t
DQS7_c
DQ [63:56]
DQS_t
DQS_c
DQ [7:0]
DM3_n/DBI3_n
DM_n/DBI_n
DM7_n/DBI7_n
DM_n/DBI_n
VDDSPD
SPD
SCL
SDA
VPP
D0–D7
D0–D7
SA0 SA1 SA2
VDD
VTT
SA0 SA1
Serial PD with Thermal sensor
SA2
D0–D7
D0–D7
VREFCA
VSS
Note:
1. Unless otherwize noted, resistor values are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
3. For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 or 2
4. EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
Rev. 1.7 / Mar.2016
12
4GB, 512Mx72 Module(1Rank of x8)
CK0_t, CK0_c
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
DQS0_t
DQS0_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS4_t
DQS4_c
DQ [39:32]
DQS_t
DQS_c
DQ [7:0]
D0
D1
D2
D3
D4
D5
D6
D7
DM0_n/DBI0_n
DM_n/DBI_n
DM4_n/DBI4_n
DM_n/DBI_n
DQS1_t
DQS1_c
DQ [15:8]
DQS_t
DQS_c
DQ [7:0]
DQS5_t
DQS5_c
DQ [47:40]
DQS_t
DQS_c
DQ [7:0]
DM1_n/DBI1_n
DM_n/DBI_n
DM5_n/DBI5_n
DM_n/DBI_n
DQS2_t
DQS2_c
DQ [23:16]
DQS_t
DQS_c
DQ [7:0]
DQS6_t
DQS6_c
DQ [55:48]
DQS_t
DQS_c
DQ [7:0]
DM2_n/DBI2_n
DM_n/DBI_n
DM6_n/DBI6_n
DM_n/DBI_n
DQS3_t
DQS3_c
DQ [31:24]
DQS_t
DQS_c
DQ [7:0]
DQS7_t
DQS7_c
DQ [63:56]
DQS_t
DQS_c
DQ [7:0]
DM3_n/DBI3_n
DM_n/DBI_n
DM7_n/DBI7_n
DM_n/DBI_n
ZQ
VSS
DQS3_t
DQS3_c
CB [7:0]
DQS_t
DQS_c
DQ [7:0]
D8
DM8_n/DBI8_n
DM_n/DBI_n
VDDSPD
SPD
SCL
VPP
D0–D8
D0–D8
SDA
EVENT_n
EVENT_n
SA0 SA1 SA2
VDD
VTT
SA0 SA1
Serial PD with Thermal sensor
SA2
D0–D8
D0–D8
VREFCA
VSS
Note:
1. Unless otherwize noted, resistor values are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
3. For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 or 2
4. EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
Rev. 1.7 / Mar.2016
13
8GB, 1Gx64 Module(2Rank of x8) - page1
CK0_t, CK0_c
CK1_t, CK1_c
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
CS1_n
ODT1
CKE1
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
DQS0_t
DQS0_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
D0
D1
D2
D3
D15
D14
D13
D12
DM0_n/DBI0_n
DM_n/DBI_n
DM_n/DBI_n
DQS1_t
DQS1_c
DQ [15:8]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DM1_n/DBI1_n
DM_n/DBI_n
DM_n/DBI_n
DQS2_t
DQS2_c
DQ [23:16]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DM2_n/DBI2_n
DM_n/DBI_n
DM_n/DBI_n
DQS3_t
DQS3_c
DQ [31:24]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DM3_n/DBI3_n
DM_n/DBI_n
DM_n/DBI_n
Note:
1. Unless otherwize noted, resistor values are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
Rev. 1.7 / Mar.2016
14
8GB, 1Gx64 Module(2Rank of x8) - page2
CK0_t, CK0_c
CK1_t, CK1_c
A[16:0], BA[1:0]
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
CS1_n
ODT1
CKE1
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
DQS4_t
DQS4_c
DQ [39:32]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
D4
D5
D6
D7
D11
D10
D9
DM4_n/DBI4_n
DM_n/DBI_n
DM_n/DBI_n
DQS5_t
DQS5_c
DQ [47:40]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DM5_n/DBI5_n
DM_n/DBI_n
DM_n/DBI_n
DQS6_t
DQS6_c
DQ [55:48]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DM6_n/DBI6_n
DM_n/DBI_n
DM_n/DBI_n
DQS7_t
DQS7_c
DQ [63:56]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
D8
DM7_n/DBI7_n
DM_n/DBI_n
DM_n/DBI_n
VDDSPD
VPP
SPD
SCL
SDA
D0–D15
D0–D15
SA0 SA1 SA2
VDD
VTT
SA0 SA1
Serial PD with Thermal sensor
SA2
D0–D15
D0–D15
VREFCA
VSS
Note:
1. Unless otherwize noted, resistor values are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
3. EVENT_n is not wired on this design.
Rev. 1.7 / Mar.2016
15
8GB, 1Gx72 Module(2Rank of x8)
A[16:0],BA[1:0],BG[1:0]
ACT_n, PARITY
CK0_t,CK0_c
CS0_n
ODT0
CKE0
CK1_t,CK1_c
CS1_n
ODT1
CKE1
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
VSS
DQS4_t
DQS4_c
DQ [39:32]
DQS_t
DQS_c
DQ [7:0]
DQS0_t
DQS0_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
D5
D0
D14
D9
DM0_n/DBI0_n
DM_n/DBI_n
DM0_n/DBI0_n
DM_n/DBI_n
DM_n/DBI_n
DM_n/DBI_n
VSS
DQS5_t
DQS5_c
DQ [47:40]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS1_t
DQS1_c
DQ [15:8]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
D6
D1
D15
D10
DM5_n/DBI5_n
DM1_n/DBI1_n
VSS
DQS6_t
DQS6_c
DQ [55:48]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS2_t
DQS2_c
DQ [23:16]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
D7
D2
D16
D11
DM5_n/DBI5_n
DM2_n/DBI2_n
VSS
DQS7_t
DQS7_c
DQ [63:56]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS3_t
DQS3_c
DQ [31:24]
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
D8
D3
D17
D12
DM7_n/DBI7_n
DM3_n/DBI3_n
VSS
DQS8_t
DQS8_c
CB [7:0]
DQS_t
DQS_c
DQ [7:0]
DQS_t
DQS_c
DQ [7:0]
D4
D13
DM8_n/DBI8_n
DM_n/DBI_n
DM_n/DBI_n
VDDSPD
VPP
SPD
SCL
EVENT_n
D0–D17
D0–D17
SDA
EVENT_n
SA0 SA1 SA2
VDD
VTT
SA0 SA1
Serial PD with Thermal sensor
SA2
D0–D17
D0–D17
VREFCA
VSS
Note:
1. Unless otherwize noted resistors are 15Ω±5%.
2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.
Rev. 1.7 / Mar.2016
16
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
NOTE
VDD
-0.3 ~ 1.5
-0.3 ~ 1.5
-0.3 ~ 3.0
-0.3 ~ 1.5
-55 to +100
V
1,3
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VPP pin relative to Vss
Voltage on any pin except VREFCA relative to Vss
Storage Temperature
VDDQ
VPP
V
V
1,3
4
V
IN, VOUT
TSTG
V
1,3,5
1,2
°C
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
5. Overshoot area above 1.5V is specified in DDR4 Device Operation.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
Parameter
Rating
Units
oC
oC
Notes
0 to 85
1,2
Normal Operating Temperature Range
Extended Temperature Range
TOPER
85 to 95
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 1.7 / Mar.2016
20
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Typ.
1.2
Symbol
Parameter
Unit
NOTE
Min.
1.14
Max.
1.26
VDD
VDDQ
VPP
Supply Voltage
V
V
V
1,2,3
1,2,3
3
Supply Voltage for Output
1.14
1.2
1.26
2.75
Supply Voltage for DRAM Activating
2.375
2.5
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Rev. 1.7 / Mar.2016
21
AC & DC Input Measurement Levels
AC & DC Logic input levels for single-ended signals
Single-ended AC & DC input levels for Command and Address
DDR4-1600/1866/2133/
DDR4-2666/3200
2400
Symbol
Parameter
Unit NOTE
Min.
Max.
Min.
Max.
VREFCA
0.075
+
VIH.CA(DC75)
DC input logic high
DC input logic low
VDD
TBD
TBD
V
V
VREFCA
0.075
-
V
IL.CA(DC75)
VSS
TBD
TBD
VIH.CA(AC100)
VIL.CA(AC100)
VREF + 0.1
Note 2
AC input logic high
AC input logic low
Note 2
TBD
TBD
TBD
TBD
V
V
1
1
VREF - 0.1
Reference Voltage for
ADD, CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
TBD
TBD
V
2,3
NOTE :
1. See “Overshoot and Undershoot Specifications”
2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for
reference : approx. ± 12mV)
3. For reference : approx. VDD/2 ± 12mV
Rev. 1.7 / Mar.2016
22
AC and DC Input Measurement Levels: V
Tolerances
REF
The DC-tolerance limits and ac-noise limits for the reference voltages V
is illustrated in Figure below.
REFCA
It shows a valid reference voltage V (t) as a function of time. (V
stands for V
).
REF
REF
REFCA
V
(DC) is the linear average of V
(t) over a very long period of time (e.g. 1 sec). This average has to
REF
REF
meet the min/max requirement in Table X. Furthermore V
(t) may temporarily deviate from V
(DC) by
REF
REF
no more than ± 1% V
.
DD
voltage
VDD
VSS
time
Illustration of V
(DC) tolerance and V
AC-noise limits
REF
REF
The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are
IH
IH
IL
IL
dependent on V
.
REF
"V " shall be understood as V (DC), as defined in Figure above.
REF
REF
This clarifies, that DC-variations of V
affect the absolute voltage a signal has to reach to achieve a valid
REF
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for V (DC) deviations from the optimum position within the data-eye of the
REF
input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with V
AC-noise. Timing and voltage effects due to AC-noise on V
up to the spec-
REF
REF
ified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.
DD
Rev. 1.7 / Mar.2016
23
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
NOTE:
1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
Definition of differential ac-swing and “time above ac-level” t
DVAC
Rev. 1.7 / Mar.2016
24
Differential swing requirements for clock (CK_t - CK_c)
Differential AC and DC Input Levels
DDR4 -1600,1866,2133
DDR4 -2400,2666 & 3200
Symbol
Parameter
unit NOTE
min
+0.150
max
NOTE 3
-0.150
min
TBD
max
NOTE 3
TBD
VIHdiff
VILdiff
differential input high
differential input low
V
V
1
1
NOTE 3
NOTE 3
2 x (VIH(AC) -
2 x (VIH(AC) -
VIHdiff(AC)
differential input high ac
differential input low ac
NOTE 3
NOTE 3
V
V
2
2
VREF
)
VREF
)
2 x (VIL(AC) -
2 x (VIL(AC) -
VILdiff(AC)
NOTE 3
NOTE 3
VREF
)
VREF)
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA
;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits
(VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Allowed time before ringback (tDVAC) for CK_t - CK_c
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV tDVAC [ps] @ |VIH/Ldiff(AC)| = TBDmV
Slew Rate [V/ns]
min
120
115
110
105
100
95
max
min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
90
1.2
85
1.0
80
< 1.0
80
Rev. 1.7 / Mar.2016
25
Single-ended requirements for differential signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain require-
ments for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different
value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for
the single-ended signals CK_t and CK_c
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Single-ended requirement for differential signals
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components
of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transi-
tion of single-ended signals through the ac-levels is used to measure setup time. For single-ended compo-
nents of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Rev. 1.7 / Mar.2016
26
Single-ended levels for CK_t, CK_c
DDR4-1600/1866/2133 DDR4-2400/2666/3200
Symbol
VSEH
Parameter
Unit NOTE
Min
Max
Min
Max
Single-ended high-level for
CK_t , CK_c
Single-ended low-level for
CK_t , CK_c
(VDD/2)
+0.100
NOTE3
TBD
NOTE3
V
V
1, 2
1, 2
(VDD/2)-
0.100
VSEL
NOTE3
NOTE3
TBD
NOTE :
1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA
;
3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits
(VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Rev. 1.7 / Mar.2016
27
Address and Control Overshoot and Undershoot specifications
AC overshoot/undershoot specification for Address, Command and Control pins
Specification
Parameter
Unit
DDR4-
1600
DDR4-
1866
DDR4-
2133
DDR4-
2400
DDR4-
2666
Maximum peak amplitude above VDD Absolute Max
allowed for overshoot area
0.06
0.06
0.06
0.06
TBD
V
Delta value between VDD Absolute Max and VDD Max
allowed for overshoot area
0.24
0.3
0.24
0.3
0.24
0.3
0.24
0.3
TBD
TBD
TBD
V
Maximum peak amplitude allowed for undershoot area
V-ns
V-ns
Maximum overshoot area per 1tCK Above Absolute
Max
0.0083
0.0071
0.0062
0.0055
Maximum overshoot area per 1tCK Between Absolute
Max
0.2550
0.2644
0.2185
0.2265
0.1914
0.1984
0.1699
0.1762
TBD
TBD
V-ns
V-ns
Maximum undershoot area per 1tCK Below VSS
(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
Overshoot Area above VDD Absolute Max
VDD Absolute Max
Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
VSS
Volts
(V)
1 tCK
Undershoot Area below VSS
Address,Command and Control Overshoot and Undershoot Definition
Rev. 1.7 / Mar.2016
28
Clock Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Clock
Specification
Parameter
Unit
DDR4-
1600
DDR4-
1866
DDR4-
2133
DDR4-
2400
DDR4-
2666
Maximum peak amplitude above VDD Absolute Max
allowed for overshoot area
0.06
0.06
0.24
0.06
0.24
0.06
0.24
TBD
TBD
V
V
Delta value between VDD Absolute Max and VDD Max
allowed for overshoot area
0.24
0.3
Maximum peak amplitude allowed for undershoot area
0.3
0.3
0.3
TBD
TBD
V
Maximum overshoot area per 1UI Above Absolute Max 0.0038
0.0032
0.0028
0.0025
V-ns
Maximum overshoot area per 1UI Between Absolute
Max
0.1125
0.0964
0.0980
0.0844
0.0858
0.0750
0.0762
TBD
TBD
V-ns
V-ns
Maximum undershoot area per 1UI Below VSS
0.1144
(CK_t, Ck_c)
Overshoot Area above VDD Absolute Max
Overshoot Area Between
VDD Absolute Max
VDD Absolute Max and VDD Max
VDD
Volts
(V)
1 UI
VSS
Undershoot Area below VSS
Clock Overshoot and Undershoot Definition
Rev. 1.7 / Mar.2016
29
Data, Strobe and Mask Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Data, Strobe and Mask
Specification
Parameter
Unit
DDR4-
1600
DDR4-
1866
DDR4-
2133
DDR4-
2400
DDR4-
2666
Maximum peak amplitude above Max absolute level of
Vin,Vout
0.16
0.24
0.16
0.24
0.16
0.24
0.16
0.24
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
V
Overshoot area Between Max Absolute level of Vin,
Vout and VDDQ Max
Undershoot area Between Min absolute level of
Vin,Vout and VDDQ
0.30
0.30
0.30
0.30
V
Maximum peak amplitude below Min absolute level of
Vin,Vout
0.10
0.10
0.10
0.10
V
Maximum overshoot area per 1UI Above Max absolute
level of Vin,Vout
0.0150
0.1050
0.1050
0.0150
0.0129
0.0900
0.0900
0.0129
0.0113
0.0788
0.0788
0.0113
0.0100
0.0700
0.0700
0.0100
V-ns
V-ns
V-ns
V-ns
Maximum overshoot area per 1UI Between Max abso-
lute level of Vin,Vout and VDDQ Max
Maximum undershoot area per 1UI Between Min abso-
lute level of Vin,Vout and VSSQ
Maximum undershoot area per 1UI Below Min abso-
lute level of Vin,Vout
(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)
Overshoot Area above Max absolute level of Vin,Vout
Max absolute level of Vin,Vout
Overshoot Area Between
Max absolute level of Vin,Vout and VDDQ
VDDQ
VSSQ
Volts
(V)
1 UI
Undershoot Area Between
Min absolute level of Vin,Vout and VSSQ
Min absolute level of Vin,Vout
Undershoot Area below Min absolute level of Vin, Vout
Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.7 / Mar.2016
30
Slew Rate Definitions
Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Fig-
ure below.
Differential Input Slew Rate Definition
Description
Defined by
from
to
V
V
V
V
V
V
V
Differential input slew rate for rising edge(CK_t - CK_c)
Differential input slew rate for falling edge(CK_t - CK_c)
[
[
ILdiffmax ] / DeltaTRdiff
ILdiffmax
IHdiffmin
IHdiffmin -
V
ILdiffmax ] / DeltaTFdiff
IHdiffmin
ILdiffmax
IHdiffmin -
NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Delta TRdiff
V
IHdiffmin
0
V
ILdiffmax
Delta TFdiff
Differential Input Slew Rate Definition for CK_t, CK_c
Rev. 1.7 / Mar.2016
31
Slew Rate Definition for Single-ended Input Signals (CMD/ADD)
Delta TRsingle
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
V
ILCA(AC) Max
Delta TFsingle
Single-ended Input Slew Rate definition for CMD and ADD
NOTE :
1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single
2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single
3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope
Rev. 1.7 / Mar.2016
32
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each
cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The dif-
ferential input cross point voltage VIX is measured from the actual cross point of true and complement sig-
nals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEL
VSEH
VSS
Vix Definition (CK)
Cross point voltage for differential input signals (CK)
DDR4-1600/1866/2133
Symbol
Parameter
min
max
VDD/2 - 145mV VDD/2 + 100mV
VSEL =<
VDD/2 - 145mV
VDD/2 + 145mV
=< VSEH
-
Area of VSEH, VSEL
=< VSEL =<
=< VSEH =<
VDD/2 - 100mV VDD/2 + 145mV
Differential Input Cross Point
VlX(CK) Voltage relative to VDD/2 for
CK_t, CK_c
- (VDD/2 - VSEL) (VSEH - VDD/2)
-120mV
120mV
+ 25mV
- 25mV
DDR4-2400/2666/3200
Symbol
Parameter
min
max
-
Area of VSEH, VSEL
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Differential Input Cross Point
VlX(CK) Voltage relative to VDD/2 for
CK_t, CK_c
Rev. 1.7 / Mar.2016
33
CMOS rail to rail Input Levels
CMOS rail to rail Input Levels for RESET_n
CMOS rail to rail Input Levels for RESET_n
Parameter
Symbol
Min
0.8*VDD
0.7*VDD
VSS
Max
VDD
Unit
V
NOTE
AC Input High Voltage
DC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Rising time
VIH(AC)_RESET
VIH(DC)_RESET
VIL(DC)_RESET
VIL(AC)_RESET
TR_RESET
6
2
VDD
V
0.3*VDD
0.2*VDD
1.0
V
1
VSS
V
7
-
us
us
4
RESET pulse width
tPW_RESET
1.0
-
3,5
NOTE :
1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,
otherwise, SDRAM may not be reset.
2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM
operation will not be guaranteed until it is reset asserting RESET_n signal LOW.
3. RESET is destructive to data contents.
4. No slope reversal(ringback) requirement during its level transition from Low to High.
5. This definition is applied only “Reset Procedure at Power Stable”.
6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
RESET_n Input Slew Rate Definition
Rev. 1.7 / Mar.2016
34
AC and DC Logic Input Levels for DQS Signals
Differential signal definition
Definition of differential DQS Signal AC-swing Level
Differential swing requirements for DQS (DQS_t - DQS_c)
Differential AC and DC Input Levels for DQS
DDR4-1600,1866,2133
DDR4-2400
DDR4-2666,3200
Symbol
Parameter
Unit Note
Min
186
Max
Note2
-186
Min
Max
TBD
TBD
Min
TBD
TBD
Max
TBD
TBD
VIHDiffPeak VIH.DIFF.Peak Voltage
VILDiffPeak VIL.DIFF.Peak Voltage
TBD
TBD
mV
mV
1
1
Note2
NOTE :
1. Used to define a differential signal slew-rate.
2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective
limits Overshoot, Undershoot Specification for single-ended signals.
Rev. 1.7 / Mar.2016
35
Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the
exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.
Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling
Rev. 1.7 / Mar.2016
36
Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the
cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel
below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured
from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.
VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals,
and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above
VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the tran-
sitioning DQS signals.
A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent
provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t
rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage
and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back
transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal
tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ring-
back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is
not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope
to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its neg-
ative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.
Vix Definition (DQS)
Rev. 1.7 / Mar.2016
37
Cross point voltage for differential input signals
DDR4-
1600,1866,2133,2400
DDR4-2666,2933,3200
Symbol
Parameter
Unit Note
Min
Max
Min
Max
DQS_t and DQS_c crossing relative
to the midpoint of the DQS_t and
DQS_c signal swings
Vix_DOS_
ratio
-
25
TBD
TBD
%
1,2
NOTE :
1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the
difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest
horizontal tangent below VDQSmid of the transitioning DQS signals.
2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs
drivers and paths are matched.
Rev. 1.7 / Mar.2016
38
Differential Input Slew Rate Definition
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure
below.
NOTE :
1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
Differential Input Slew Rate Definition for DQS_t, DQS_c
Differential Input Slew Rate Definition for DQS_t, DQS_c
Description
Defined by
From
To
Differential input slew rate for
rising edge(DQS_t - DQS_c)
VILDiff_DQS
VIHDiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff
Differential input slew rate for
falling edge(DQS_t - DQS_c)
VIHDiff_DQS
VILDiff_DQS
Differential Input Level for DQS_t, DQS_c
DDR4-1600,1866,2133
DDR4-2400
DDR4-2666,3200
Symbol
Parameter
Unit Note
Min
136
-
Max
-
Min
Max
-
Min
TBD
TBD
Max
TBD
TBD
VIHDiff_DQS Differential Input High
VILDiff_DQS Differential Input Low
130
-
mV
mV
-136
-130
Rev. 1.7 / Mar.2016
39
Differential Input Slew Rate for DQS_t, DQS_c
DDR4-1600,1866,2133
DDR4-2400
DDR4-2666,3200
Symbol
SRIdiff
Parameter
Unit Note
Min
Max
Min
Max
Min
Max
Differential Input
Slew Rate
3
18
3
18
TBD
TBD
V/ns
Rev. 1.7 / Mar.2016
40
AC and DC output Measurement levels
Single-ended AC & DC Output Levels
Single-ended AC & DC output levels
DDR4-1600/1866/2133/
2400/2666/3200
Symbol Parameter
OH(DC) DC output high measurement level (for IV curve linearity)
Units NOTE
V
1.1 x VDDQ
0.8 x VDDQ
V
V
V
VOM(DC) DC output mid measurement level (for IV curve linearity)
VOL(DC) DC output low measurement level (for IV curve linearity)
VOH(AC) AC output high measurement level (for output SR)
VOL(AC) AC output low measurement level (for output SR)
0.5 x VDDQ
(0.7 + 0.15) x VDDQ
(0.7 - 0.15) x VDDQ
V
V
1
1
NOTE :
1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing
with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ
.
Differential AC & DC Output Levels
Differential AC & DC output levels
DDR4-1600/1866/
2133/2400/2666/3200
Symbol Parameter
Units NOTE
V
OHdiff(AC) AC differential output high measurement level (for output SR)
+0.3 x VDDQ
-0.3 x VDDQ
V
V
1
1
VOLdiff(AC) AC differential output low measurement level (for output SR)
NOTE :
1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with
a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs.
Rev. 1.7 / Mar.2016
40
Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between V
and V
for single ended signals as shown in Table and Figure below.
OL(AC)
OH(AC)
Single-ended output slew rate definition
Measured
Description
Defined by
From
To
[VOH(AC)-VOL(AC)] /
Delta TRse
VOL(AC)
VOH(AC)
Single ended output slew rate for rising edge
[VOH(AC)-VOL(AC)] /
Delta TFse
VOH(AC)
VOL(AC)
Single ended output slew rate for falling edge
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
V
OH(AC)
V
OL(AC)
delta TFse
delta TRse
Single-ended Output Slew Rate Definition
Single-ended output slew rate
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200
Min Max Min Max Min Max Min Max Min Max Min Max
Parameter
Symbol
Units
Single ended output slew rate SRQse
Description: SR: Slew Rate
4
9
4
9
4
9
4
9
TBD TBD TBD TBD V/ns
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE:
1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or
low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction
(i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction,
the regular maximum limit of 9 V/ns applies
Rev. 1.7 / Mar.2016
41
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure
below.
Differential output slew rate definition
Measured
Description
Defined by
From
To
[VOHdiff(AC)-VOLdiff(AC)] /
Delta TRdiff
VOLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
[VOHdiff(AC)-VOLdiff(AC)] /
Delta TFdiff
VOHdiff(AC)
VOLdiff(AC)
Differential output slew rate for falling edge
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
V
(AC)
OHdiff
V
(AC)
OLdiff
delta TFdiff
delta TRdiff
Differential Output Slew Rate Definition
Differential output slew rate
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200
Min Max Min Max Min Max Min Max Min Max Min Max
Parameter
Symbol
Units
Differential output slew rate SRQdiff
8
18
8
18
8
18
8
18
TBD TBD TBD TBD V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
Rev. 1.7 / Mar.2016
42
Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test
Mode.
Single-ended AC & DC output levels of Connectivity Test Mode
DDR4-1600/1866/2133/
Symbol Parameter
Unit Note
2400/2666/3200
V
OH(DC) DC output high measurement level (for IV curve linearity)
OM(DC) DC output mid measurement level (for IV curve linearity)
VOL(DC) DC output low measurement level (for IV curve linearity)
OB(DC) DC output below measurement level (for IV curve linearity)
1.1 x VDDQ
V
V
V
V
V
V
V
0.8 x VDDQ
0.5 x VDDQ
0.2 x VDDQ
V
VOH(AC) AC output high measurement level (for output SR)
VOL(AC) AC output below measurement level (for output SR)
VTT + (0.1 x VDDQ
VTT - (0.1 x VDDQ
)
1
1
)
NOTE :
1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.
VOH(AC)
VTT
0.5 * VDDQ
VOL(AC)
TF_output_CT
TR_output_CT
Differential Output Slew Rate Definition of Connectivity Test Mode
Single-ended output slew rate of Connectivity Test Mode
DDR4-1600/1866/2133/2400/2666/3200
Parameter
Symbol
Unit Note
Min
Max
10
Output signal Falling time TF_output_CT
Output signal Rising time TR_output_CT
-
-
ns/V
ns/V
10
Rev. 1.7 / Mar.2016
43
Standard Speed Bins
DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600K
11-11-11
CL-nRCD-nRP
Unit NOTE
Parameter
Symbol
min
max
Internal read command to first
data
13.75
tAA
18.00
ns
ns
ns
10
10
10
(13.50)5,10
Internal read command to first
data with read DBI enabled
tAA_DBI
tRCD
tAA(min) + 2nCK
tAA(max) +2nCK
-
13.75
(13.50)5,10
ACT to internal read or write
delay time
13.75
PRE command period
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.50)5,10
ACT to PRE command period
35
9 x tREFI
-
48.75
(48.50)5,10
ACT to ACT or REF command
period
Normal Read DBI
1,2,3,4,9,
12
CL = 9
tCK(AVG)
1.5
1.6
ns
CL = 11
CWL = 9
CL = 10 CL = 12 tCK(AVG)
CL = 10 CL = 12 tCK(AVG)
Reserved
ns 1,2,3,4,9
Reserved
ns
ns
1,2,3,4
1,2,3,4
1,2,3
11,12
11
CWL = 9,11 CL = 11 CL = 13 tCK(AVG)
CL = 12 CL = 14 tCK(AVG)
Supported CL Settings
1.25
1.25
<1.5
<1.5
ns
9,11,12
11,13,14
9,11
nCK
nCK
nCK
Supported CL Settings with read DBI
Supported CWL Settings
Rev. 1.7 / Mar.2016
42
DDR4-1866 Speed Bins and Operations
Speed Bin
DDR4-1866M
13-13-13
CL-nRCD-nRP
Unit NOTE
Parameter
Symbol
min
max
Internal read command to first
data
13.9212
tAA
18.00
ns
ns
ns
10
10
10
(13.50)5,10
Internal read command to first
data with read DBI enabled
tAA_DBI
tRCD
tAA(min) + 2nCK
tAA(max) +2nCK
-
13.92
(13.50)5,10
ACT to internal read or write delay
time
13.92
PRE command period
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.50)5,10
ACT to PRE command period
34
9 x tREFI
-
47.92
(47.50)5,10
ACT to ACT or REF command
period
Normal Read DBI
1,2,3,4,9,
10
CL = 9
tCK(AVG)
1.5
1.6
ns
CL = 11
CWL = 9
CL = 10 CL = 12 tCK(AVG)
CL = 10 CL = 12 tCK(AVG)
Reserved
ns 1,2,3,4,9
ns
ns 1,2,3,4,6
Reserved
4
CWL = 9,11 CL = 11 CL = 13 tCK(AVG)
CL = 12 CL = 14 tCK(AVG)
CL = 12 CL = 14 tCK(AVG)
CWL = 10,12 CL = 13 CL = 15 tCK(AVG)
CL = 14 CL = 16 tCK(AVG)
Supported CL Settings
1.25
1.25
<1.5
<1.5
ns
ns
1,2,3,6
1,2,3,4
1,2,3,4
1,2,3
Reserved
1.071
1.071
<1.25
<1.25
ns
ns
9,11,12,13,14
11,13,14 ,15,16
9,10,11,12
nCK
nCK
nCK
11,12
12
Supported CL Settings with read DBI
Supported CWL Settings
Rev. 1.7 / Mar.2016
43
DDR4-2133 Speed Bins and Operations
Speed Bin
DDR4-2133P
15-15-15
CL-nRCD-nRP
Unit
NOTE
Parameter
Symbol
min
max
14.0612
Internal read command to first data
tAA
18.00
ns
ns
ns
10
10
10
(13.50)5,10
Internal read command to first data
with read DBI enabled
tAA_DBI
tRCD
tAA(min)+3nCK
tAA(max)+3nCK
-
14.06
(13.50)5,10
ACT to internal read or write delay
time
14.06
PRE command period
ACT to PRE command period
ACT to ACT or REF command period
Normal Read DBI
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.50)5,10
33
9 x tREFI
-
47.06
(46.50)5,10
1,2,3,4,9,1
2
CL = 9
tCK(AVG)
1.5
1.6
ns
CL = 11
CWL = 9
CL = 10 CL = 12 tCK(AVG)
CL = 11 CL = 13 tCK(AVG)
CL = 12 CL = 14 tCK(AVG)
CL = 13 CL = 15 tCK(AVG)
CL = 14 CL = 16 tCK(AVG)
CL = 14 CL = 17 tCK(AVG)
Reserved
ns
ns
1,2,3,9
1,2,3,4,7
1,2,3,7
1,2,3,4,7
1,2,3,7
1,2,3,4
1,2,3,4
1,2,3
1.25
1.25
<1.5
<1.5
CWL = 9,11
ns
1.071
1.071
<1.25
<1.25
ns
CWL = 10,12
ns
Reserved
ns
CWL = 11,14 CL = 15 CL = 18 tCK(AVG)
CL = 16 CL = 19 tCK(AVG)
Supported CL Settings
0.937
0.937
<1.071
<1.071
ns
ns
9,11,12,13,14,15,16
11,13,14,15,16,18,19
9,10,11,12,14
nCK
nCK
nCK
11,12
Supported CL Settings with read DBI
Supported CWL Settings
Rev. 1.7 / Mar.2016
44
DDR4-2400 Speed Bins and Operations
Speed Bin
DDR4-2400T
17-17-17
CL-nRCD-nRP
Unit
NOTE
Parameter
Symbol
min
max
14.16
Internal read command to first data
tAA
18.00
ns
ns
ns
10
10
10
(13.75)5,10
Internal read command to first data
with read DBI enabled
tAA_DBI
tRCD
tAA(min)+3nCK
tAA(max)+3nCK
-
14.16
(13.75)5,10
ACT to internal read or write delay
time
14.16
PRE command period
ACT to PRE command period
ACT to ACT or REF command period
Normal Read DBI
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.75)5,10
32
9 x tREFI
-
46.16
(45.75)5,10
CL = 9
tCK(AVG)
Reserved
ns
ns
1,2,3,4,9
1,2,3,4,9
4
CL = 11
CWL = 9
1.6
CL = 10 CL = 12 tCK(AVG)
CL = 10 CL = 12 tCK(AVG)
1.5
Reserved
Reserved
Reserved
ns
CWL = 9,11 CL = 11 CL = 13 tCK(AVG)
CL = 12 CL = 14 tCK(AVG)
1.25
1.25
<1.5
<1.5
ns
1,2,3,4,8
1,2,3,8
4
ns
CL = 12 CL = 14 tCK(AVG)
ns
CWL = 10,12 CL = 13 CL = 15 tCK(AVG)
CL = 14 CL = 16 tCK(AVG)
1.071
1.071
<1.25
<1.25
ns
1,2,3,4,8
1,2,3,8
4
ns
CL = 14 CL = 17 tCK(AVG)
ns
CWL = 11,14 CL = 15 CL = 18 tCK(AVG)
CL = 16 CL = 19 tCK(AVG)
0.937
0.937
<1.071
<1.071
ns
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4
ns
CL = 15 CL = 18 tCK(AVG)
Reserved
Reserved
ns
CL = 16 CL = 19 tCK(AVG)
CWL = 12,16
ns
CL = 17 CL = 20 tCK(AVG)
0.833
0.833
<0.937
<0.937
ns
CL = 18 CL = 21 tCK(AVG)
Supported CL Settings
ns
1,2,3
11
10,11,12,13,14,15,16,17,18
12,14,16,18,19,20,21
9,10,11,12,14,16
nCK
nCK
nCK
Supported CL Settings with read DBI
Supported CWL Settings
Rev. 1.7 / Mar.2016
45
Speed Bin Table Notes
Absolute Specification
- VDDQ = VDD = 1.20V +/- 0.06 V
- VPP = 2.5V +0.25/-0.125 V
- The values defined with above-mentioned table are DLL ON case.
- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making
a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use
the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating
CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next ‘Supported CL’, where tAA = 12.5ns and
tCK(avg) = 1.3 ns should only be used for CL = 10 calculation.
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg)
down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result
is tCK(avg).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a
mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this
setting is supported.
6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
10. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as
stated in the Speed Bin Tables.
11. CL number in parentheses, it means that these numbers are optional.
12. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).
13. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to
be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given
speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.
Rev. 1.7 / Mar.2016
46
IDD and IDDQ Specification Parameters and Test Conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
Figure shows the setup and test load for IDD, IPP and IDDQ measurements.
•
IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,
IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,
IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the
DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.
•
•
IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD, IPP and IDDQ measurements, the following definitions apply:
•
•
•
•
•
•
•
“0” and “LOW” is defined as VIN <= VILAC(max).
“1” and “HIGH” is defined as VIN >= VIHAC(min).
“MID-LEVEL” is defined as inputs are VREF = VDD / 2.
Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.
IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
RTT_NOM = RZQ/6 (40 Ohm in MR1);
RTT_WR = RZQ/2 (120 Ohm in MR2);
RTT_PARK = Disable;
Qoff = 0 (Output Buffer enabled) in MR1;
B
TDQS_t disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear down mode disabled in MR3
Read/Write DBI disabled in MR5;
DM disabled in MR5
•
•
•
Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA
changes when directed.
Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply
invert of BG/BA changes when directed above.
Rev. 1.7 / Mar.2016
50
I
I
I
DDQ
DD
PP
V
V
V
DDQ
DD
PP
RESET
CK_t/CK_c
DDR4 SDRAM
CKE
CS
C
DQS_t/DQS_c
DQ
DM
ACT,RAS,CAS,WE
A,BG,BA
ODT
V
V
SSQ
SS
ZQ
NOTE:
1. DIMM level Output test load condition may be different from above
Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Application specific
IDDQ
TestLad
memory channel
environment
Channel
IO Powe
Simulatin
IDDQ
Simuaion
IDDQ
Measurement
Correlation
X
X
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement
Rev. 1.7 / Mar.2016
51
Table 1 -Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Symbol
Unit
11-11-11
13-13-13
15-15-15
17-17-17
tCK
CL
1.25
11
11
11
39
28
11
16
20
28
4
1.071
13
12
13
45
32
13
16
22
28
4
0.937
15
14
15
51
36
15
16
23
32
4
0.833
17
17
17
56
39
17
16
26
36
4
ns
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
CWL
nRCD
nRC
nRAS
nRP
x4
nFAW x8
x16
x4
nRRDS x8
x16
4
4
4
4
5
5
6
7
x4
5
5
6
6
nRRDL x8
x16
5
5
6
6
6
6
7
8
tCCD_S
tCCD_L
tWTR_S
tWTR_L
nRFC 2Gb
nRFC 4Gb
nRFC 8Gb
nRFC 16Gb
4
4
4
4
5
5
6
6
2
3
3
3
6
7
8
9
128
208
280
TBD
150
243
327
TBD
171
278
374
TBD
193
313
421
TBD
Rev. 1.7 / Mar.2016
52
Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode
IDD0
Registers2; ODT Signal: stable at 0; Pattern Details: see Table 3
Operating One Bank Active-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD0
IDD0A
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,
Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode
IDD1
Registers2; ODT Signal: stable at 0; Pattern Details: see Table 4
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD1
IDD1A
IPP1
Operating One Bank Active-Read-Precharge IPP Current
Same condition with IDD1
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
IDD2N
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Precharge Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD2N
IDD2NA
IPP2N
Precharge Standby IPP Current
Same condition with IDD2N
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD2NT Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data
IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Standby Current with CAL enabled
IDD2NL
Same definition like for IDD2N, CAL enabled3
Precharge Standby Current with Gear Down mode enabled
IDD2NG
Same definition like for IDD2N, Gear Down mode enabled3
Precharge Standby Current with DLL disabled
IDD2ND
Same definition like for IDD2N, DLL disabled3
Rev. 1.7 / Mar.2016
53
Precharge Standby Current with CA parity enabled
IDD2N_par
IDD2P
Same definition like for IDD2N, CA parity enabled3
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at
0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: stable at 0
Precharge Power-Down IPP Current
Same condition with IDD2P
IPP2P
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0
IDD2Q
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Active Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD3N
IDD3NA
IPP3N
Active Standby IPP Current
Same condition with IDD3N
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0
IDD3P
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
Table 7; Data IO: seamless read data burst with different data between one burst and the next one
according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0; Pattern Details: see Table 7
IDD4R
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RA
IDD4RB
IPP4R
Operating Burst Read Current with Read DBI
Read DBI enabled3, Other conditions: see IDD4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Rev. 1.7 / Mar.2016
54
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
IDD4W Table 8; Data IO: seamless write data burst with different data between one burst and the next one
according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through
banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at HIGH; Pattern Details: see Table 8
Operating Burst Write Current (AL=CL-1)
IDD4WA
AL = CL-1, Other conditions: see IDD4W
Operating Burst Write Current with Write DBI
IDD4WB
Write DBI enabled3, Other conditions: see IDD4W
Operating Burst Write Current with Write CRC
IDD4WC
Write CRC enabled3, Other conditions: see IDD4W
Operating Burst Write Current with CA Parity
IDD4W_par
CA Parity enabled3, Other conditions: see IDD4W
Operating Burst Write IPP Current
IPP4W
Same condition with IDD4W
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
IDD5B
Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see
Table 9
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
IPP5B
Burst Refresh Current (2X REF)
IDD5F2
tRFC=tRFC_x2, Other conditions: see IDD5B
Burst Refresh Write IPP Current (2X REF)
IPP5F2
Same condition with IDD5F2
Burst Refresh Current (4X REF)
IDD5F4
tRFC=tRFC_x4, Other conditions: see IDD5B
Burst Refresh Write IPP Current (4X REF)
IPP5F4
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:
IDD6N
IPP6N
IDD6E
IPP6E
Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Normal Temperature Range
Same condition with IDD6N
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:
Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Extended Temperature Range
Same condition with IDD6E
Rev. 1.7 / Mar.2016
55
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: MID-LEVEL
IDD6R
Self Refresh IPP Current: Reduced Temperature Range
Same condition with IDD6R
IPP6R
IDD6A
IPP6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;
CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Auto Self-Refresh IPP Current
Same condition with IDD6A
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address
Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between
one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times
interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and
RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10
IDD7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
IPP7
IDD8
IPP8
Maximum Power Down Current
TBD
Maximum Power Down IPP Current
Same condition with IDD8
Rev. 1.7 / Mar.2016
56
NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pulse(NOP) input.
Rev. 1.7 / Mar.2016
57
Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
Data4
0
0
ACT
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
1,2
D, D
D_#,
D_#
32
3,4
1
1
1
1
1
0
0
3
0
0
0
7
F
0
-
...
nRAS
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat pattern 1...4 until nRC - 1, truncate if necessary
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
-
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
1
2
1*nRC
2*nRC
3*nRC
4*nRC
5*nRC
6*nRC
7*nRC
8*nRC
9*nRC
10*nRC
11*nRC
12*nRC
13*nRC
14*nRC
15*nRC
3
4
5
6
7
8
9
10
11
12
13
14
15
For x4
and x8
only
NOTE:
1 .DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.7 / Mar.2016
58
Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Patterna)
Data4
0 0
1, 2
ACT
D, D
D#, D#
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
3b
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
-
-
-
3, 4
...
repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary
nRCD -AL
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1
1*nRC + 0
1*nRC + 1, 2 D, D
1*nRC + 3, 4 D#, D#
ACT
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
1
0
3b
1
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
-
-
-
...
repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC + nRCD RD
- AL
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
...
1*nRC + nRAS PRE
... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary
repeat pattern 1...4 until nRAS - 1, truncate if necessary
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
-
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
2 2*nRC
3 3*nRC
4 4*nRC
5 5*nRC
6 6*nRC
8 7*nRC
9 9*nRC
10 10*nRC
11 11*nRC
12 12*nRC
13 13*nRC
14 14*nRC
15 15*nRC
16 16*nRC
For x4 and x8 only
NOTE:
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
Rev. 1.7 / Mar.2016
59
Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,
IDD3NA and IDD3P
Measurement-Loop Pattern1
Data4
0 0
D, D
D, D
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
32
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
0
1
2
0
0
D#,
D#
32
3
D#,
D#
1
1
1
1
1
0
0
3
0
0
0
7
F
0
0
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-27
7 28-31
8 32-35
9 36-39
10 40-43
11 44-47
12 48-51
13 52-55
14 56-59
15 60-63
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.7 / Mar.2016
60
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1
Data4
0 0
D, D
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
32
32
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
-
-
-
1
2
D, D
D#, D#
3
D#, D#
1
1
1
1
1
0
0
3
0
0
0
7
F
0
-
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 0 instead
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-27
7 28-31
8 32-35
9 36-39
10 40-43
11 44-47
12 48-51
13 52-55
14 56-59
15 60-63
For x4
andx8
only
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.7 / Mar.2016
61
Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
Data4
0
1
0
RD
0
1
1
0
1
0
0
0
0
32
1
0
0
0
0
0
0
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1
D
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
2,3
D#, D#
4
RD
0
1
1
0
1
0
0
1
0
0
0
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5
D
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
32
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
6,7
D#, D#
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
2
3
4
5
6
7
8
9
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
10 40-43
11 44-47
12 48-51
13 52-55
14 56-59
15 60-63
For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. Burst Sequence driven on each DQ signal by Read Command.
Rev. 1.7 / Mar.2016
62
Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
Data4
0
1
0
WR
0
1
1
0
1
1
0
0
0
32
1
0
0
0
0
0
0
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1
D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
2,3
D#, D#
4
WR
0
1
1
0
1
1
0
1
0
0
0
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5
D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
32
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
6,7
D#, D#
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
2
3
4
5
6
7
8
9
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
10 40-43
11 44-47
12 48-51
13 52-55
14 56-59
15 60-63
For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.7 / Mar.2016
63
Table 9 - IDD4WC Measurement-Loop Pattern1
Datad
0 0
WR
0
1
1
0
1
1
0
0
0
32
1
0
0
0
0
0
0
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
D8=CRC
1,2
D, D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
3,4
5
D#, D#
WR
0
1
1
0
1
1
0
1
0
0
0
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
D8=CRC
6,7
8,9
D, D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
32
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
D#, D#
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
2 10-14
3 15-19
4 20-24
5 25-29
6 30-34
7 35-39
8 40-44
9 45-49
10 50-54
11 55-59
12 60-64
13 65-69
14 70-74
15 75-79
For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.7 / Mar.2016
64
Table 10 - IDD5B Measurement-Loop Pattern1
Data4
0 0
1 1
2
REF
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
32
32
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
0
F
0
0
0
0
-
-
-
-
D
D
3
D#, D#
4
D#, D#
1
1
1
1
1
0
0
3
0
0
0
7
F
0
-
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead
4-7
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
40-43
44-47
48-51
52-55
56-59
60-63
For x4 and x8
only
2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. DQ signals are VDDQ.
Rev. 1.7 / Mar.2016
65
Table 11 - IDD7 Measurement-Loop Pattern1
Data4
0 0
1
ACT
RDA
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
-
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
-
2
3
D
D#
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
32
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
...
1 nRRD
nRRD + 1
repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
ACT
RDA
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
-
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
...
repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
2 2*nRRD
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary
3 3*nRRD
4 4*nRRD
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
5 nFAW
6 nFAW + nRRD
7 nFAW + 2*nRRD
8 nFAW + 3*nRRD
9 nFAW + 4*nRRD repeat Sub-Loop 4
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
10 2*nFAW
11 2*nFAW + nRRD
12 2*nFAW + 2*nRRD
13 2*nFAW + 3*nRRD
14 2*nFAW + 4*nRRD repeat Sub-Loop 4
For x4 and x8
only
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
15 3*nFAW
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
16 3*nFAW + nRRD
17 3*nFAW + 2*nRRD
18 3*nFAW + 3*nRRD
19 3*nFAW + 4*nRRD repeat Sub-Loop 4
20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Rev. 1.7 / Mar.2016
66
IDD Specifications (Tcase: 0 to 95oC)
2GB, 256M x 64 U-DIMM: HMA425U6AFR6N
2133
2400
Symbol
unit
note
IDD
164
164
224
224
68
76
64
68
52
IPP
12
12
10
10
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
5
5
5
138
141
102
16
10
8
5
57
9
IDD
176
180
236
240
72
84
68
76
56
IPP
12
12
10
10
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
5
5
5
138
142
103
16
10
8
5
57
9
IDD0
IDD0A
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2NP
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WP
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
72
84
48
68
76
92
52
72
136
140
112
586
597
590
626
643
626
559
688
728
800
600
48
148
152
120
656
668
660
701
720
701
626
791
728
800
600
48
64
32
88
724
28
64
32
88
752
28
IDD6R
IDD6A
IDD7
IDD8
Rev. 1.7 / Mar.2016
64
4GB, 512M x 64 U-DIMM: HMA451U6AFR8N
2133
2400
Symbol
unit
note
IDD
219
219
264
267
109
154
142
73
113
103
109
72
106
197
197
144
663
679
667
712
732
712
632
712
1457
1597
1202
77
IPP
13
14
11
11
5
6
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
254
282
203
13
15
10
20
77
14
IDD
232
234
282
286
117
169
156
80
122
109
117
79
114
213
213
156
742
760
747
798
820
798
708
798
1457
1597
1202
77
IPP
14
14
11
11
5
6
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
254
284
205
13
15
10
20
77
14
IDD0
IDD0A
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2NP
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WP
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
97
61
107
963
30
97
61
107
991
30
IDD6R
IDD6A
IDD7
IDD8
Rev. 1.7 / Mar.2016
65
4GB, 512M x 72 U-DIMM: HMA451U7AFR8N
2133
2400
Symbol
unit
note
IDD
261
264
317
321
132
190
175
90
137
123
132
89
128
239
240
176
835
855
841
898
922
898
796
898
1639
1797
1352
86
IPP
15
15
12
12
6
7
6
6
6
6
6
6
6
8
8
8
8
8
8
8
8
8
8
8
286
317
229
15
16
11
22
87
16
IDD
274
276
329
336
143
199
188
93
146
133
143
93
131
255
255
182
909
932
916
986
1013
986
867
986
1639
1797
1352
86
IPP
16
16
13
13
6
7
6
6
6
6
6
6
6
8
8
8
8
8
8
8
8
8
8
8
286
320
231
15
16
11
22
87
16
IDD0
IDD0A
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2NP
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WP
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
109
68
120
1115
34
109
68
120
1159
34
IDD6R
IDD6A
IDD7
IDD8
Rev. 1.7 / Mar.2016
66
8GB, 1G x 64 U-DIMM: HMA41GU6AFR8N
2133
2400
Symbol
unit
note
IDD
329
373
373
421
219
307
283
146
226
206
219
143
212
394
395
289
772
832
777
822
886
822
741
822
1566
1707
1311
153
193
122
213
1072
60
IPP
19
19
16
17
11
12
11
11
11
11
11
11
11
14
14
14
12
13
12
12
13
12
12
12
259
287
209
26
29
19
40
83
28
IDD
350
403
399
455
234
338
312
160
244
218
234
158
227
426
426
312
859
929
864
915
989
915
825
915
1574
1715
1319
153
193
122
213
1109
60
IPP
19
20
17
17
11
12
11
11
11
11
11
11
11
14
14
15
12
13
12
13
13
12
12
13
259
290
211
26
29
19
40
83
28
IDD0
IDD0A
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2NP
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WP
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
IDD6R
IDD6A
IDD7
IDD8
Rev. 1.7 / Mar.2016
67
8GB, 1G x 72 U-DIMM: HMA1GU7AFR8N
2133
2400
Symbol
unit
note
IDD
370
419
420
473
246
346
319
165
254
231
246
161
239
443
444
325
869
936
874
925
996
925
834
925
1762
1920
1475
172
217
137
240
1206
68
IPP
21
22
18
19
12
13
12
12
12
12
12
12
12
16
16
16
14
15
14
14
15
14
14
14
292
323
235
30
33
22
45
93
32
IDD
393
454
449
512
264
380
351
180
274
245
264
177
256
479
479
351
967
1045
972
1029
1112
1030
928
1030
1770
1929
1484
172
217
137
240
1247
68
IPP
22
23
19
19
12
13
12
12
12
12
12
12
12
16
16
16
14
15
14
14
15
14
14
14
292
326
237
30
33
22
45
93
32
IDD0
IDD0A
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2NP
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WP
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
IDD6R
IDD6A
IDD7
IDD8
Rev. 1.7 / Mar.2016
68
Module Dimensions
256Mx64 - HMA425U6AFR6N
Front
133.35
129.55
2.10
SPD/TS
3.00
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.18mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
69
512Mx64 - HMA451U6AFR8N
Front
133.35
129.55
2.10
SPD/TS
3.00
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.18mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
70
512Mx72 - HMA451U7AFR8N
Front
133.35
129.55
2.10
SPD/TS
3.00
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.18mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
71
1Gx64 - HMA41GU6AFR8N-TF
Front
133.35
129.55
2.10
3.00
SPD/TS
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.78mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
72
1Gx64 - HMA41GU6AFR8N-UH
Front
133.35
129.55
2.10
3.00
SPD/TS
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.78mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
73
1Gx72 - HMA41GU7AFR8N-TF
Front
133.35
129.55
2.10
SPD/TS
3.00
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.78mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
74
1Gx72 - HMA41GU7AFR8N-UH
Front
133.35
129.55
2.10
SPD/TS
3.00
Detail A
Detail B
Detail D
Detail E
Detail C
Detail F
Pin 35
Pin 47
Pin 105
Pin 117
Pin 1
3.35
64.60
56.10
Back
2x R0.60 Max
Side
Detail of Contacts A, F
± 0.03
Detail of Contacts B
Detail of Contacts C
3.78mm max
0.60
Pin 35
Pin 47
Pin 105
Pin 117
Max 0.30
9.35
9.35
10.20
10.20
Non-matarized keep out area
Max 0.35
Detail of Contacts D
± 0.03
0.85
Detail of Contacts E
4.30
Max 0.25
0.60
1.40±0.1mm
max
Max 0.30
0.20
±0.15
Non-matarized keep out area
Max 0.35
0.85
Max 0.25
1.50
5.95
±0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.7 / Mar.2016
75
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