HMA81GS6CJR8N-WM_技术文档

260pin DDR4 SDRAM SODIMM

DDR4 SDRAM SO-DIMM

Based on 8Gb C-die

HMA851S6CJR6N

HMA81GS6CJR8N

HMA81GS7CJR8N

HMA82GS6CJR8N

HMA82GS7CJR8N

*SK hynix reserves the right to change products or specifications without notice.

Rev. 1.6 / Jan.2020

1

Revision History

Revision No.

History

Draft Date

Jul.2017

Remark

0.1

1.0

Initial Release

IDD spec update

Aug.2017

Sep.2017

1.1

Changed features (Temperature sensor with integrated SPD

for ECC SODIMM)

CS released for 2666 non-ECC SODIMM

1.2

1.3

1.4

1.5

Corrected module dimensions P/N

Updated JEDEC Specification

Speed bin table note update

Feb.2018

Apr.2018

Jun.2018

Define IDD specification(2666)

Modify IDD specification table /

Updated JEDEC specification

1.6

Define IDD/IPP Value for 2933, 3200Mbps

Jan.2020

Rev. 1.6 / Jan.2020

2

Description

SK hynix Unbuffered Small Outline DDR4 SDRAM DIMMs (Unbuffered Small Outine Double Data Rate Syn-

chronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules

that use DDR4 SDRAM devices. These DDR4 SDRAM Unbuffered Small Outline DIMMs are intended for use

as main memory when installed in systems such as micro servers and mobile personal computres.

Features

• Power Supply: VDD=1.2V (1.14V to 1.26V)

• VDDQ = 1.2V (1.14V to 1.26V)

• VPP - 2.5V (2.375V to 2.75V)

• VDDSPD=2.25V to 3.6V

• Functionality and operations comply with the DDR4 SDRAM datasheet

• 16 internal banks

• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-

ferent bank group accesses are available

• Data transfer rates: PC4-3200, PC4-2933, PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600

• Bi-Directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)

• Supports ECC error correction and detection

• On-Die Termination (ODT)

• Temperature sensor with integrated SPD for ECC SODIMM

• This product is in compliance with the RoHS directive.

• Per DRAM Addressability is supported

• Internal Vref DQ level generation is available

Ordering Information

# of

ranks

Part Number

Density

Organization

Component Composition

HMA851S6CJR6N- UH/VK/WM/XN

HMA81GS6CJR8N-UH/VK/WM/XN

HMA81GS7CJR8N-UH/VK/WM/XN

HMA82GS6CJR8N-UH/VK/WM/XN

HMA82GS7CJR8N-UH/VK/WM/XN

4GB

8GB

512Mx64

1Gx64

1Gx72

2Gx64

2Gx72

512Mx16(H5AN8G6NCJR)*4

1Gx8(H5AN8G8NCJR)*8

1Gx8(H5AN8G8NCJR)*9

1Gx8(H5AN8G8NCJR)*16

1Gx8(H5AN8G8NCJR)*18

1

2

8GB

16GB

Rev. 1.6 / Jan.2020

3

Key Parameters

CAS

Latency

(tCK)

tCK

(ns)

tRCD

(ns)

tRP

(ns)

tRAS

(ns)

tRC

(ns)

MT/s

Grade

CL-tRCD-tRP

13.75

48.75

(48.50)*

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

-PB

-RD

-TF

-UH

-VK

1.25

1.071

0.937

0.833

0.75

11

13

15

17

19

35

34

33

32

11-11-11

13-13-13

15-15-15

17-17-17

19-19-19

(13.50)* (13.50)*

13.92 13.92

(13.50)* (13.50)*

14.06 14.06

(13.50)* (13.50)*

14.16 14.16

(13.75)* (13.75)*

14.25 14.25

(13.75)* (13.75)*

14.32 14.32

(13.75)* (13.75)*

13.75 13.75

47.92

(47.50)*

47.06

(46.50)*

46.16

(45.75)*

46.25

(45.75)*

46.32

(45.75)*

DDR4-2933

DDR4-3200

-WM

-XN

0.682

0.625

21

22

32

21-21-21

22-22-22

47.0

*SK hynix DRAM devices support optional downbinning to CL21, CL19, CL17, CL15, CL13 and CL11. SPD setting is pro-

grammed to match.

Address Table

4GB(1Rx16)

8GB(1Rx8)

16GB(2Rx8)

# of Bank Groups

Bank Address BG Address

Bank Address in a BG

2

4

BG0

BG0~BG1

BA0~BA1

A0~A15

A0~ A9

1 KB

BG0~BG1

BA0~BA1

A0~A15

A0~ A9

1 KB

BA0~BA1

A0~A15

A0~ A9

2KB

Row Address

Column Address

Page size

Rev. 1.6 / Jan.2020

4

Pin Descriptions

Pin Name

Description

Pin Name

Description

SDRAM address bus

SDRAM bank select

SCL

SDA

A0-A16

BA0, BA1

BG0, BG1

I²C serial bus clock for SPD/TS

I²C serial bus data line for SPD/TS

I²C slave address select for SPD/TS

SDRAM parity input

SDRAM bank group select

SDRAM row address strobe

SDRAM column address strobe

SDRAM write enable

SA0-SA2

PARITY

VDD

RAS_n¹

CAS_n²

WE_n³

SDRAM I/O & core power supply

SDRAM activating power supply

VPP

CS0_n, CS1_n,

CS2_n, CS3_n

Rank Select Lines

C0, C1

Chip ID lines for 3DS components

SDRAM command/address reference

supply

CKE0, CEK1

SDRAM clock enable lines

VREFCA

ODT0, ODT1

ACT_n

SDRAM on-die termination control lines

SDRAM activate

VSS

Power supply return (ground)

Serial SPD/TS positive power supply

SDRAM ALERT_n

VDDSPD

ALERT_n

DQ0-DQ63

CB0-CB7

DIMM memory data bus

DIMM ECC check bits

SDRAM data strobes

DQS0_t-DQS8_t

DQS0_c-DQS8_c

RESET_n

EVENT_n

VTT

Set SDRAMs to a Known State

(positive line of differential pair)

SDRAM data strobes

SPD signals a thermal event has

occurred

(negative line of differential pair)

SDRAM data masks/data bus inversion

(x8-based x72 DIMMs)

DM0_n-DM8_n,

DBI0_n-DBI8_n

Termination supply for the Address,

Command and Control bus

SDRAM clocks (positive line of differen-

tial pair)

CK0_t, CK1_t

CK0_c, CK1_c

NC

No connection

SDRAM clocks (negative line of differ-

ential pair)

1. RAS_n is a multiplexed function with A16.

2. CAS_n is a multiplexed function with A15.

3. WE_n is a multiplexed function with A14.

Rev. 1.6 / Jan.2020

5

Input/Output Functional Descriptions

Symbol

Type

Function

CK0_t, CK0_c,

CK1_t, CK1_c

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and

device input buffers and output drivers. Taking CKE LOW provides Precharge Power-

Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in

any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref

CKE0, CKE1

Input have become stable during the power on and initialization sequence, they must be

maintained during all operations (including Self-Refresh). CKE must be maintained high

throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE,

are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-

Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for

Input external Rank selection on systems with multiple Ranks. CS_n is considered part of the

command code.

CS0_n, CS1_n,

CS2_n, CS3_n

Chip ID: Chip ID is only used for 3DS for 2 and 4 high stack via TSV to select each slice

of stacked component. Chip ID is considered part of the command code.

C0, C1

Input

On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance

internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,

DQS_c and DM_n/DBI_n, signal. The ODT pin will be ignored if MR1 is programmed to

ODT0, ODT1

Input

disable RTT_NOM.

Activation Command Input: ACT_n defines the Activation command being entered along

Input with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as

Row Address A16, A15, and A14.

ACT_n

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the

command being entered. Those pins have multi function. For example, for activation

Input with ACT_n Low, these are Addresses like A16, A15, and A14 but for non-activation

command with ACT_n High, these are Command pins for Read, Write, and other

command defined in command truth table.

RAS_n/A16,

CAS_n/A15,

WE_n/A14

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during

Input/ a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function.

Output DBI_n is an input/output identifying wherther to store/output the true or inverted data.

If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM

and not inverted if DBI_n is HIGH.

DM_n/DBI_n

BG0-BG1

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write, or

Precharge command is being applied. BG0 also determines which mode register is to be

accessed during a MRS cycle. For x4/8 based SDRAMs, BG0 and BG1 are valid. For x16

Input

based SDRAM components, only BG0 is valid.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write, or

Input Precharge command is being applied. Bank address also determines which mode

register is to be accessed during a MRS cycle.

BA0-BA1

Rev. 1.6 / Jan.2020

6

Symbol

Type

Function

Address Inputs: Provide the row address for ACTIVATE Commands and the column

address for Read/Write commands to select one location out of the memory array in the

A0 - A16

Input respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 have

additional functions. See other rows. The address inputs also provide the op-code during

Mode Register Set commands.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write

operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a

Precharge command to determine whether the Precharge applies to one bank (A10

A10 / AP

Input

LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected

by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if

Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).

See command truth table for details.

A12 / BC_n

RESET_n

CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive

Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then

Input/ CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the

Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor

specific data sheets to determine which DQ is used.

DQ

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. DDR4 SDRAMs support differential data strobe only and does not

support single-ended.

Input/

Output

DQS_t, DQS_c,

Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with

MR setting. Once it’s enabled via Register in MR5, then DSRAM calculates Parity with

Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity

should be maintained at the rising edge of the clock and at the same time with

command & address with CS_n LOW.

PARITY

ALERT: It has multiple functions, such as CRC error flag or Command and Address Parity

error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for

the period time interval and goes back HIGH. If there is an error in Command Address

Output Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM

internal recovery transaction is complete.

ALERT_n

During Connectivity Test mode, this pin functions as an input.

Use of this signal or not is dependent on the system.

SA0-SA1

RFU

Input Device address for the SPD.

Reserved for Future Use. No on DIMM electrical connection is present.

No Connect: No on DIMM electrical connection is present.

NC

VDD¹

Supply

Power Supply: 1.2 V +/- 0.06 V

Ground

VSS

VTT²

Power Supply : 0.6V

Rev. 1.6 / Jan.2020

7

Symbol

Type

Function

Supply

DRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)

Reference voltage for CA

VPP

VREFCA

VDDSPD

Power supply used to power the I2C bus on the SPD.

Note:

1. For PC4, VDD 1.2V. For PC4L VDD is TBD.

2. For PC4, VTT is 0.6V. For PC4L VTT is TBD.

Rev. 1.6 / Jan.2020

8

Pin Assignments

Front Side

Back Side

Pin Label

Front Side

Pin Label

Back Side

Pin Label

1

VSS

DQ5

VSS

2

VSS

DQ4

131

133

135

137

139

141

143

A3

A1

132

134

136

138

140

142

144

A2

3

4

EVENT_

n

5

6

VSS

VDD

7

DQ1

VSS

8

DQ0

CK0_t

CK0_c

VDD

CK1_t

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

VSS

CK1_C

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

DQS0_

C

DM0_n, DBI0_n

VSS

VDD

A0

DQS0_t

VSS

PARITY

DQ6

KEY

DQ7

VSS

DQ2

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

BA1

VDD

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

A10/AP

VDD

DQ3

VSS

DQ12

VSS

CS0_n

A14/WE_n

VDD

BA0

DQ13

VSS

A16/RAS_n

VDD

DQ8

DQ9

VSS

ODT0

CS1_n

VDD

A15/CAS_n

A13

VSS

DQS1_C

DM1_n, DBI1_n

VSS

DQS1_t

VSS

VDD

ODT1

VDD

C0, CS2_n, NC

VREFCA

SA2

DQ15

VSS

DQ14

VSS

C1, CS3_n, NC

VSS

DQ10

VSS

DQ11

VSS

DQ37

VSS

DQ36

DQ21

VSS

DQ20

VSS

DQ33

VSS

DQ32

VSS

DQ17

VSS

DQ16

VSS

DQS4_

C

DM4_n, DBI4_n

VSS

DQS2_c

DQS2_t

VSS

DM2_n, DBI2_n

VSS

DQS4_t

VSS

DQ39

DQ22

VSS

DQ38

VSS

DQ23

VSS

DQ35

VSS

DQ18

DQ34

VSS

DQ19

VSS

DQ45

VSS

DQ28

VSS

DQ44

VSS

DQ29

VSS

DQ41

DQ24

VSS

DQ40

VSS

DQ25

VSS

DQS5_c

DQS5_t

VSS

DQS3_c

DQS3_t

DM5_n, DBI5_n

VSS

DM3_n, DBI3_n

Rev. 1.6 / Jan.2020

9

Front Side

Pin Label

Back Side

Pin Label

Front Side

Pin Label

Back Side

Pin Label

77

79

VSS

DQ30

VSS

78

80

VSS

DQ31

203

205

207

209

211

213

215

217

219

221

223

225

227

229

231

233

235

237

239

241

243

245

247

249

251

253

255

257

259

DQ46

VSS

204

206

208

210

212

214

216

218

220

222

224

226

228

230

232

234

236

238

240

242

244

246

248

250

252

254

256

258

260

DQ47

VSS

81

82

VSS

DQ42

VSS

DQ43

VSS

83

DQ26

VSS

84

DQ27

VSS

85

86

DQ52

VSS

DQ53

VSS

87

CB5, NC

VSS

88

CB4, NC

VSS

89

90

DQ49

VSS

DQ48

VSS

91

CB1, NC

VSS

92

CB0, NC

VSS

93

94

DQS6_

C

DM6_n, DBI6_n

VSS

95

DQS8_c

DQS8_t

VSS

96

DM8_n, DBI8_n

VSS

DQS6_t

VSS

97

98

DQ54

VSS

99

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

CB6, NC

VSS

DQ55

VSS

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

CB2, NC

VSS

DQ50

VSS

CB7, NC

VSS

DQ51

VSS

CB3, NC

VSS

DQ60

VSS

RESET_n

CKE1

VDD

DQ61

VSS

CKE0

VDD

DQ57

VSS

DQ56

VSS

BG1

ACT_n

ALERT_n

VDD

DQS7_c

DQS7_t

VSS

BG0

DM7_n, DBI7_n

VSS

VDD

A12

A11

DQ62

VSS

DQ63

VSS

A9

A7

VDD

DQ58

VSS

DQ59

VSS

A8

A5

A6

A4

SCL

SDA

VDD

VDDSPD

VPP

SA0

VTT

VPP

SA1

Rev. 1.6 / Jan.2020

10

Functional Block Diagram

4GB, 512Mx64 Module(1Rank of x16)

CK0_t, CK0_c

A[16:0], BA[1:0]

ACT_n, PARITY,BG[0]

CS0_n

ODT0

CKE0

ZQ

VSS

DQS0_t

DQS0_c

DQ [7:0]

DQS1_t

DQS1_c

DQSL_t

DQSL_c

DQL[7:0]

DQSU_t

DQSU_c

DQU[7:0]

D0

D1

D2

D3

Serial PD

DQ [15:8]

DM0_n/DBI0_n

DM1_n/DBI1_n

DM_n/DBI_n

SCL

SDA

NC

A0

A1

A2

DQS2_t

DQS2_c

DQ [23:16]

DQS3_t

DQS3_c

DQ [15:8]

DQSL_t

DQSL_c

DQL[7:0]

DQSU_t

DQSU_c

DQU[7:0]

SA0 SA1 SA2

DM2_n/DBI2_n

DM3_n/DBI3_n

DM_n/DBI_n

V_DDSPD

SPD

V_PP

D0–D4

DQS4_t

DQS4_c

DQ [39:32]

DQS5_t

DQS5_c

DQ [47:40]

DQSL_t

DQSL_c

DQL[7:0]

DQSU_t

DQSU_c

DQU[7:0]

V_DD

V_TT

D0–D4

VREFCA

VSS

DM4_n/DBI4_n

DM5_n/DBI5_n

DM_n/DBI_n

DQS6_t

DQS6_c

DQ [55:48]

DQSL_t

DQSL_c

DQL[7:0]

DQS7_t

DQS7_c

DQ [63:56]

DQSU_t

DQSU_c

DQU[7:0]

DM6_n/DBI6_n

DM7_n/DBI7_n

DM_n/DBI_n

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. CK1_t, CK1_c terminated with 75Ω±5% resistor.

Rev. 1.6 / Jan.2020

11

8GB, 1Gx64 Module(1Rank of x8)

CK0_t, CK0_c

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

CS0_n

ODT0

CKE0

ZQ

VSS

ZQ

VSS

DQS2_t

DQS2_c

DQ [23:16]

DQS_t

DQS_c

DQ [7:0]

DQS4_t

DQS4_c

DQ [39:32]

DQS_t

DQS_c

DQ [7:0]

D1

D0

D7

D6

D5

D4

D3

D2

DM2_n/DBI2_n

DM_n/DBI_n

DM4_n/DBI4_n

DM_n/DBI_n

ZQ

DQS0_t

DQS0_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DQS6_t

DQS6_c

DQ [55:48]

DQS_t

DQS_c

DQ [7:0]

DM0_n/DBI0_n

DM_n/DBI_n

DM6_n/DBI6_n

DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQS_t

DQS_c

DQ [7:0]

DQS7_t

DQS7_c

DQ [63:56]

DQS_t

DQS_c

DQ [7:0]

DM1_n/DBI1_n

DM_n/DBI_n

DM7_n/DBI7_n

DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t

DQS_c

DQ [7:0]

DQS5_t

DQS5_c

DQ [47:40]

DQS_t

DQS_c

DQ [7:0]

DM3_n/DBI3_n

DM_n/DBI_n

DM5_n/DBI5_n

DM_n/DBI_n

Serial PD

V_DDSPD

SPD

SCL

EVENT_n

V_PP

D0–D7

SDA

R1

NC

A0

A1

A2

V_DD

V_TT

SA2 (pin 166)

VSS

SA0 SA1

D0–D7

VREFCA

R2

VSS

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. To connect the SPD A2 input to the edge connector pin 166 install R1. To tie the SPD input A2 to ground install R2.

Do not install both R1 and R2. The values for R1 and R2 are not critical. Any value less than 100 Ohms may be used.

Rev. 1.6 / Jan.2020

12

8GB, 1Gx72 Module(1Rank of x8)

CK1_t, CK1_c

CK0_t, CK0_c

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

CS0_n

ODT0

CKE0

CS0_n

ODT0

CKE0

ZQ

VSS

ZQ

VSS

DQS8_t

DQS8_c

CB[7:0]

DQS_t

DQS_c

DQ [7:0]

DQS2_t

DQS2_c

DQ [23:16]

DQS_t

DQS_c

DQ [7:0]

D6

D5

D4

D3

D1

D0

D8

D7

DM8_n/DBI8_n

DM_n/DBI_n

DM2_n/DBI2_n

DM_n/DBI_n

ZQ

DQS4_t

DQS4_c

DQ [39:32]

DQS_t

DQS_c

DQ [7:0]

DQS0_t

DQS0_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM4_n/DBI4_n

DM_n/DBI_n

DM0_n/DBI0_n

DM_n/DBI_n

DQS6_t

DQS6_c

DQ [55:48]

DQS_t

DQS_c

DQ [7:0]

DQS1_t

DQS1_c

DQ [15:8]

DQS_t

DQS_c

DQ [7:0]

DM6_n/DBI6_n

DM_n/DBI_n

DM1_n/DBI1_n

DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQS_t

DQS_c

DQ [7:0]

DQS3_t

DQS3_c

DQ [31:24]

DQS_t

DQS_c

DQ [7:0]

DM7_n/DBI7_n

DM_n/DBI_n

DM3_n/DBI3_n

DM_n/DBI_n

ZQ

VSS

DQS5_t

DQS5_c

DQ [47:40]

DQS_t

DQS_c

DQ [7:0]

D2

DM5_n/DBI5_n

DM_n/DBI_n

Serial PD with Thermal sensor

EVENT_n/NC

V_DDSPD

SPD

V_PP

D0–D8

SCL

V_DD

V_TT

SDA

EVENT_n

A0

A1

A2

R1

D0–D8

VREFCA

pin 166

VSS

SA0 SA1

VSS

R2

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. To connect the SPD A2 input to the edge connector pin 166 install R1. To tie the SPD input A2 to ground install R2.

Do not install both R1 and R2. The values for R1 and R2 are not critical. Any value less than 100 Ohms may be used.

Rev. 1.6 / Jan.2020

13

16GB, 2Gx64 Module(2Rank of x8) - page1

CK0_t, CK0_c

CK1_t, CK1_c

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

CS0_n

ODT0

CKE0

CS1_n

ODT1

CKE1

ZQ

VSS

ZQ

VSS

DQS2_t

DQS2_c

DQ [23:16]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D5

D4

D0

D1

D14

D15

D11

D10

DM2_n/DBI2_n

DM_n/DBI_n

DQS0_t

DQS0_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM0_n/DBI0_n

DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM1_n/DBI1_n

DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM3_n/DBI3_n

DM_n/DBI_n

Rev. 1.6 / Jan.2020

14

16GB, 2Gx64 Module(2Rank of x8) - page2

CK0_t, CK0_c

CK1_t, CK1_c

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

A[16:0], BA[1:0]

ACT_n, PARITY,BG[1:0]

CS0_n

ODT0

CKE0

CS1_n

ODT1

CKE1

ZQ

VSS

ZQ

VSS

DQS4_t

DQS4_c

DQ [39:32]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D2

D3

D7

D6

D9

DM4_n/DBI4_n

DM_n/DBI_n

DQS6_t

DQS6_c

DQ [55:48]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D8

DM6_n/DBI6_n

DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D12

D13

DM7_n/DBI7_n

DM_n/DBI_n

DQS5_t

DQS5_c

DQ [47:40]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM5_n/DBI5_n

DM_n/DBI_n

Serial PD

V_DDSPD

V_PP

SPD

SCL

SDA

D0–D15

A0

A1

A2

V_DD

V_TT

SA0 SA1 SA2

D0–D15

VREFCA

VSS

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. SDRAMs for ODD ranks (D8 to D15), which are placed on the back side of the module use the address mirroing for A4-A3, A6-A5, A8-A7,

A13-A11, BA1-BA0 and BG1-BG0. More detail can be found in the DDR4 SODIMM Common Section of the Design Specification.

Rev. 1.6 / Jan.2020

15

16GB, 2Gx72 Module(2Rank of x8)

CK0_t, CK0_c

CK1_t, CK1_c

PARITY

A[16:0],BA[1:0],BG[1:0],ACT_n

CS0_n

CS1_n

ODT1

CKE1

ODT0

CKE0

DQS0_t

DQS0_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D1

D2

D0

D3

D5

D8

D6

D7

D4

D10

D11

D9

DM0_n/DBI0_n

DM_n/DBI_n

ZQ

VSS

ZQ

VSS

DQS1_t

DQS1_c

DQ [15:8]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM1_n/DBI1_n

DM_n/DBI_n

DQS2_t

DQS2_c

DQ [23:16]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM2_n/DBI2_n

DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D12

D14

D17

D15

D16

D13

DM3_n/DBI3_n

DM_n/DBI_n

ZQ

VSS

ZQ

VSS

DQS4_t

DQS4_c

DQ [39:32]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM4_n/DBI4_n

DM_n/DBI_n

DQS5_t

DQS5_c

DQ [47:40]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

V_DDSPD

V_PP

SPD

DM5_n/DBI5_n

DM_n/DBI_n

D0–D17

V_DD

V_TT

DQS6_t

DQS6_c

DQ [55:48]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

D0–D17

VREFCA

VSS

DM6_n/DBI6_n

DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

DM7_n/DBI7_n

DM_n/DBI_n

Serial PD with Thermal sensor

SCL

DQS8_t

DQS8_c

CB [7:0]

DQS_t

DQS_c

DQ [7:0]

DQS_t

DQS_c

DQ [7:0]

SDA

EVENT_n

VSS

EVENT_n

A0 A1

A2

DM8_n/DBI8_n

DM_n/DBI_n

SA0 SA1 SA2

Note:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. Unless otherwize noted, resistor values are 15Ω±5%.

3. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

4. ZQ resistors are 240 Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

Rev. 1.6 / Jan.2020

16

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

NOTE

VDD

-0.3 ~ 1.5

-0.3 ~ 3.0

-0.3 ~ 1.5

-55 to +100

V

1,3

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VPP pin relative to Vss

Voltage on any pin except VREFCA relative to Vss

Storage Temperature

VDDQ

VPP

V

1,3

4

V_IN,V_OUT

T_STG

V

1,3,5

1,2

°C

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indi-

cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement

conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x

VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times

5. Overshoot area above 1.5V is specified in DDR4 Device Operation.

DRAM Component Operating Temperature Range

Temperature Range

Symbol

Parameter

Rating

Units

^oC

Notes

0 to 85

1,2

Normal Operating Temperature Range

Extended Temperature Range

T_OPER

85 to 95

1,3

NOTE:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-

ment conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.

During operation, the DRAM case temperature must be maintained between 0 - 85^oC under all operating condi-

tions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85^oC and 95^oC

case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is

also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.

Please refer to the DIMM SPD for option availability

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use

the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)

or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

Rev. 1.6 / Jan.2020

17

AC & DC Operating Conditions

Recommended DC Operating Conditions

Rating

Typ.

1.2

Symbol

Parameter

Unit

NOTE

Min.

1.14

Max.

1.26

VDD

VDDQ

VPP

Supply Voltage

V

1,2,3

3

Supply Voltage for Output

1.2

1.26

2.75

Supply Voltage for DRAM Activating 2.375

2.5

NOTE:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. DC bandwidth is limited to 20MHz.

Rev. 1.6 / Jan.2020

18

AC & DC Input Measurement Levels

AC & DC Logic input levels for single-ended signals

Single-ended AC & DC input levels for Command and Address

DDR4-1600/1866/2133/

DDR4-2666/3200

2400

Symbol

Parameter

Unit NOTE

Min.

Max.

Min.

Max.

V_REFCA

0.075

+

V_REFCA+

0.065

DC input logic

high

V_IH.CA(DC75)

V_IL.CA(DC75)

VDD

V

V_REFCA

0.075

-

V_REFCA

0.065

-

DC input logic low

VSS

AC input logic

high

V_IH.CA(AC100)

V_IL.CA(AC100)

V_REF+ 0.1

Note 2

V_REF+ 0.09

Note 2

V

1

V_REF- 0.1

V_REF- 0.09

AC input logic low

Reference Volt-

age for ADD, CMD

inputs

V_REFCA(DC)

0.49*VDD

0.51*VDD

0.49*VDD

0.51*VDD

V

2,3

NOTE :

1. See “Overshoot and Undershoot Specifications”

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1%

VDD (for reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

Rev. 1.6 / Jan.2020

19

AC and DC Input Measurement Levels: V_REFTolerances

The DC-tolerance limits and ac-noise limits for the reference voltages V

is illustrated in Figure below.

REFCA

It shows a valid reference voltage V (t) as a function of time. (V

stands for V

).

REFCA

REF

V

(DC) is the linear average of V

(t) over a very long period of time (e.g. 1 sec). This average has to

REF

meet the min/max requirement in Table X. Furthermore V

(t) may temporarily deviate from V

(DC) by

REF

no more than ± 1% V

.

DD

voltage

V_DD

V_SS

time

Illustration of V

(DC) tolerance and V

AC-noise limits

REF

The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are

IH

IL

dependent on V

.

REF

"V " shall be understood as V (DC), as defined in Figure above.

REF

This clarifies, that DC-variations of V

affect the absolute voltage a signal has to reach to achieve a valid

REF

high or low level and therefore the time to which setup and hold is measured. System timing and voltage

budgets need to account for V (DC) deviations from the optimum position within the data-eye of the

REF

input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and

voltage associated with V

AC-noise. Timing and voltage effects due to AC-noise on V

up to the spec-

REF

ified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.

DD

Rev. 1.6 / Jan.2020

20

AC and DC Logic Input Levels for Differential Signals

Differential signal definition

tDVAC

V_IH.DIFF.AC.MIN

V_IH.DIFF.MIN

0.0

half cycle

V_IL.DIFF.MAX

V_IL.DIFF.AC.MAX

tDVAC

time

NOTE:

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

Definition of differential ac-swing and “time above ac-level” t

DVAC

Rev. 1.6 / Jan.2020

21

Differential swing requirements for clock (CK_t - CK_c)

Differential AC and DC Input Levels

DDR4 -

1600,1866,21 DDR4 -2400 DDR4 -2666 DDR4 -2933 DDR4 -3200

un NO

it TE

Symbol Parameter

33

min

+0.150 NOTE3 +0.135 NOTE3 +0.135 NOTE3 +0.125 NOTE3 +0.110 NOTE3 V

NOTE 3 -0.150 NOTE3 -0.135 NOTE3 -0.135 NOTE3 -0.125 NOTE3 -0.110

max

min

max

min

max

min

max

min

max

differential

V_IHdiff

1

input high

differential

V_ILdiff

V

input low

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V /V (AC) of ADD/CMD and V

;

REFCA

IH.CA IL.CA

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the

respective limits (V (DC) max, V (DC)min) for single-ended signals as well as the limitations for

IH.CA

IL.CA

overshoot and undershoot.

Allowed time before ringback (tDVAC) for CK_t - CK_c

tDVAC [ps] @ |V_IH/Ldiff(AC)| = 200mV tDVAC [ps] @ |V_IH/Ldiff(AC)| = TBDmV

Slew Rate [V/ns]

min

120

115

110

105

100

95

max

min

TBD

max

> 4.0

4.0

-

3.0

2.0

1.8

1.6

1.4

90

1.2

85

1.0

80

< 1.0

80

Rev. 1.6 / Jan.2020

22

Single-ended requirements for differential signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain require-

ments for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels

(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different

value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for

the single-ended signals CK_t and CK_c

V_DDor V_DDQ

V_SEHmin

V_SEH

V

_DD/2 or V_DDQ/2

CK

V_SELmax

V_SEL

V_SSor V_SSQ

time

Single-ended requirement for differential signals

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components

of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transi-

tion of single-ended signals through the ac-levels is used to measure setup time. For single-ended compo-

nents of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but

adds a restriction on the common mode characteristics of these signals.

Rev. 1.6 / Jan.2020

23

Single-ended levels for CK_t, CK_c

DDR4-1600/

1866/2133

U

ni

t

DDR4-2400

DDR4-2666

DDR4-2933

DDR4-3200

Sym

bol

NO

TE

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Single-ended (VDD/

(VDD/

2)

(VDD/

2)

(VDD/

2)

(VDD/

2)

V_SEH

high-level for

2)

NOTE3

NOTE3 V 1, 2

CK_t , CK_c +0.100

+0.095

+0.085

Single-ended

low-level for NOTE3

CK_t , CK_c

(VDD/

2)-

0.100

(VDD/

2)-

0.095

(VDD/

2)-

0.095

(VDD/

2)-

0.085

(VDD/

2)-

0.085

V_SEL

NOTE3

V 1, 2

NOTE :

1. For CK_t - CK_c use V

/V

(AC) of ADD/CMD;

IH.CA IL.CA

2. V (AC)/V (AC) for ADD/CMD is based on V ;

REFCA

IH

IL

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the

respective limits (V (DC) max, V (DC)min) for single-ended signals as well as the limitations for

IH.CA

IL.CA

overshoot and undershoot.

Rev. 1.6 / Jan.2020

24

Address and Control Overshoot and Undershoot specifications

AC overshoot/undershoot specification for Address, Command and Control pins

Specification

Uni

t

Parameter

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-

1600

1866

2133

2400

2666

2933

3200

Maximum peak amplitude above VDD Abso-

lute Max allowed for overshoot area

0.06

V

Delta value between VDD Absolute Max and

VDD Max allowed for overshoot area

VDD + 0.24

0.30

VDD + 0.24

0.30

Maximum peak amplitude allowed for under-

shoot area

V-

ns

Maximum overshoot area per 1tCK Above

Absolute Max

V-

ns

0.0083 0.0071 0.0062 0.0055

0.2550 0.2185 0.1914 0.1699

0.2644 0.2265 0.1984 0.1762

0.0055

0.1699

0.1762

Maximum overshoot area per 1tCK Between

Absolute Max

V-

ns

Maximum undershoot area per 1tCK Below

VSS

V-

ns

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

Overshoot Area above VDD Absolute Max

VDD Absolute Max

Overshoot Area Between

VDD Absolute Max and VDD Max

V_DD

V_SS

Volts

(V)

1 tCK

Undershoot Area below VSS

Address,Command and Control Overshoot and Undershoot Definition

Rev. 1.6 / Jan.2020

25

Clock Overshoot and Undershoot Specifications

AC overshoot/undershoot specification for Clock

Specification

Uni

t

Parameter

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-

1600

1866

2133

2400

2666

2933

3200

Maximum peak amplitude above VDD Abso-

lute Max allowed for overshoot area

0.06

V

Delta value between VDD Absolute Max and

VDD Max allowed for overshoot area

VDD + 0.24

0.30

VDD + 0.24

0.30

Maximum peak amplitude allowed for under-

shoot area

Maximum overshoot area per 1UI Above

Absolute Max

V-

ns

0.0038 0.0032 0.0028 0.0025

0.1125 0.0964 0.0844 0.0750

0.0025

0.0750

0.0762

Maximum overshoot area per 1UI Between

Absolute Max

V-

ns

Maximum undershoot area per 1UI Below

VSS

V-

ns

0.1144 0.0980 0.0858 0.0762

(CK_t, Ck_c)

Overshoot Area above VDD Absolute Max

Overshoot Area Between

VDD Absolute Max

VDD Absolute Max and VDD Max

V_DD

Volts

(V)

1 UI

V_SS

Undershoot Area below VSS

Clock Overshoot and Undershoot Definition

Rev. 1.6 / Jan.2020

26

Data, Strobe and Mask Overshoot and Undershoot Specifications

AC overshoot/undershoot specification for Data, Strobe and Mask

Specification

Uni

t

Parameter

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-

1600

1866

2133

2400

2666

2933

3200

Maximum peak amplitude above Max abso-

lute level of Vin,Vout

0.16

V

Overshoot area Between Max Absolute level

of Vin, Vout and VDDQ Max

VDDQ + 0.24

VDDQ+0.24

0.30

Undershoot area Between Min absolute level

of Vin,Vout and VDDQ Max

0.30

0.10

0.30

0.10

0.30

0.10

0.30

0.10

Maximum peak amplitude below Min absolute

level of Vin,Vout

0.10

Maximum overshoot area per 1UI Above Max

absolute level of Vin,Vout

V-

ns

0.0150 0.0129 0.0113 0.0100

0.1050 0.0900 0.0788 0.0700

0.0100

Maximum overshoot area per 1UI Between

Max absolute level of Vin,Vout and VDDQ

Max

V-

ns

0.0700

Maximum undershoot area per 1UI Between

Min absolute level of Vin,Vout and VSSQ

V-

ns

0.1050 0.0900 0.0788 0.0700

0.0150 0.0129 0.0113 0.0100

0.0700

0.0100

Maximum undershoot area per 1UI Below Min

absolute level of Vin,Vout

V-

ns

(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)

Overshoot Area above Max absolute level of Vin,Vout

Max absolute level of Vin,Vout

Overshoot Area Between

Max absolute level of Vin,Vout and VDDQ

VDDQ

VSSQ

Volts

(V)

1 UI

Undershoot Area Between

Min absolute level of Vin,Vout and VSSQ

Min absolute level of Vin,Vout

Undershoot Area below Min absolute level of Vin, Vout

Data, Strobe and Mask Overshoot and Undershoot Definition

Rev. 1.6 / Jan.2020

27

Slew Rate Definitions

Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Fig-

ure below.

Differential Input Slew Rate Definition

Description

Defined by

from

to

V

Differential input slew rate for rising edge(CK_t -

CK_c)

[

] / DeltaTR-

IHdiffmin - ILdiffmax

V

IHdiffmin

ILdiffmax

diff

V

Differential input slew rate for falling edge(CK_t -

CK_c)

] / DeltaTF-

IHdiffmin - ILdiffmax

V

ILdiffmax

IHdiffmin

diff

NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

Delta TRdiff

V

IHdiffmin

0

V

ILdiffmax

Delta TFdiff

Differential Input Slew Rate Definition for CK_t, CK_c

Rev. 1.6 / Jan.2020

28

Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

Delta TRsingle

V

IHCA(AC) Min

V

IHCA(DC) Min

VREFCA(DC)

V

ILCA(DC) Max

V

ILCA(AC) Max

Delta TFsingle

Single-ended Input Slew Rate definition for CMD and ADD

NOTE :

1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single

2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single

3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope

Rev. 1.6 / Jan.2020

29

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each

cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The dif-

ferential input cross point voltage VIX is measured from the actual cross point of true and complement sig-

nals to the midlevel between of VDD and VSS.

VDD

CK_t

Vix

VDD/2

Vix

CK_c

VSEL

VSEH

VSS

Vix Definition (CK)

Cross point voltage for differential input signals (CK)

DDR4-1600/1866/2133

Symbol

Parameter

min

max

VDD/2 -

VDD/2 + 100mV

=< VSEH =<

VDD/2 + 145mV

VDD/2 +

145mV =<

VSEH

VSEL =<

145mV =<

VSEL =< VDD/

2 - 100mV

-

Area of VSEH, VSEL

Differential Input Cross

VDD/2 - 145mV

(VSEH - VDD/2)

- 25mV

- (VDD/2 -

VSEL) + 25mV

VlX(CK) Point Voltage relative to

VDD/2 for CK_t, CK_c

-120mV

120mV

Rev. 1.6 / Jan.2020

30

DDR4-2400/2666/3200

Symbol

Parameter

min

max

VDD/2 -

145mV =<

VSEL =< VDD/

2 - 100mV

VDD/2 + 100mV

=< VSEH =<

VDD/2 + 145mV

VDD/2 +

145mV =<

VSEH

VSEL =<

-

Area of VSEH, VSEL

Differential Input Cross

VDD/2 - 145mV

(VSEH - VDD/2)

- 25mV

- (VDD/2 -

VSEL) + 25mV

VlX(CK) Point Voltage relative to

VDD/2 for CK_t, CK_c

-120mV

120mV

Rev. 1.6 / Jan.2020

31

CMOS rail to rail Input Levels

CMOS rail to rail Input Levels for RESET_n

Parameter

Symbol

Min

0.8*VDD

0.7*VDD

VSS

Max

VDD

Unit

V

NOTE

AC Input High Voltage

DC Input High Voltage

DC Input Low Voltage

AC Input Low Voltage

Rising time

VIH(AC)_RESET

VIH(DC)_RESET

VIL(DC)_RESET

VIL(AC)_RESET

TR_RESET

6

2

VDD

V

0.3*VDD

0.2*VDD

1.0

V

1

VSS

V

7

-

us

4

RESET pulse width

tPW_RESET

1.0

-

3,5

NOTE :

1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,

otherwise, SDRAM may not be reset.

2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM

operation will not be guaranteed until it is reset asserting RESET_n signal LOW.

3. RESET is destructive to data contents.

4. No slope reversal(ringback) requirement during its level transition from Low to High.

5. This definition is applied only “Reset Procedure at Power Stable”.

6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.

7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings

tPW_RESET

0.8*VDD

0.7*VDD

0.3*VDD

0.2*VDD

TR_RESET

RESET_n Input Slew Rate Definition

Rev. 1.6 / Jan.2020

32

AC and DC Logic Input Levels for DQS Signals

Differential signal definition

Definition of differential DQS Signal AC-swing Level

Differential swing requirements for DQS (DQS_t - DQS_c)

Differential AC and DC Input Levels for DQS

DDR4-1600,1866,2133

DDR4-2400

DDR4-2666,3200

Symbol

Parameter

Unit Note

Min

186

Max

Note2

-186

Min

Max

Note2

-160

Min

140

Max

Note2

-140

VIHDiffPeak VIH.DIFF.PeakVoltage

VILDiffPeak VIL.DIFF.Peak Voltage

160

mV

1

Note2

NOTE :

1. Used to define a differential signal slew-rate.

2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective

limits Overshoot, Undershoot Specification for single-ended signals.

Rev. 1.6 / Jan.2020

33

Peak voltage calculation method

The peak voltage of Differential DQS signals are calculated in a following equation.

VIH.DIFF.Peak Voltage = Max(f(t))

VIL.DIFF.Peak Voltage = Min(f(t))

f(t) = VDQS_t - VDQS_c

The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the

exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.

Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling

Rev. 1.6 / Jan.2020

34

Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the

cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel

below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured

from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.

VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals,

and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above

VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the tran-

sitioning DQS signals.

A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent

provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t

rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage

and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back

transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal

tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ring-

back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is

not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope

to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its neg-

ative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.

Vix Definition (DQS)

Rev. 1.6 / Jan.2020

35

Cross point voltage for differential input signals

DDR4-

1600,1866,2133,2400

DDR4-

2666,2933,3200

Symbol

Parameter

Unit Note

Min

Max

Min

Max

DQS_t and DQS_c crossing relative

to the midpoint of the DQS_t and

DQS_c signal swings

Vix_DOS_

ratio

-

25

-

25

%

1,2

VDQSmid_to_ VDQSmid offset relative to

min(VIH-

diff, 50)

min(VIH-

diff, 50)

-

mV 3,4,5

Vcent

Vcent_DQ(midpoint)

NOTE :

1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the

difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest

horizontal tangent below VDQSmid of the transitioning DQS signals.

2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs

drivers and paths are matched.

3. Teh maximum limite shall not exceed the smaller of VIHdiff minimum limit or 50mV.

4. VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and

high-z states are not applicable conditions.

5. The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a

system.



Rev. 1.6 / Jan.2020

36

Differential Input Slew Rate Definition

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure

below.

NOTE :

1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.

2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.

Differential Input Slew Rate Definition for DQS_t, DQS_c

Description

Defined by

From

To

Differential input slew rate for

rising edge(DQS_t - DQS_c)

VILDiff_DQS

VIHDiff_DQS

|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff

|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff

Differential input slew rate for

falling edge(DQS_t - DQS_c)

VIHDiff_DQS

VILDiff_DQS

Rev. 1.6 / Jan.2020

37

Differential Input Level for DQS_t, DQS_c

DDR4-

1600,1866,

2133

U

ni ot

t

N

DDR4-2400

DDR4-2666

DDR4-2933

DDR4-3200

Symbol Parameter

e

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

VIHDif- Differential

m

V

136

-

130

-

130

-

115

-

110

-

f_DQS

Input High

VILDif-

f_DQS

Differential

Input Low

m

V

-

-136

-

-130

-

-130

-

-115

-

-110

Differential Input Slew Rate for DQS_t, DQS_c

DDR4-

U

ni

t

1600,1866,21 DDR4-2400

33

DDR4-2666

DDR4-2933

DDR4-3200

No

te

Symbol Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Differential

SRIdiff Input Slew

Rate

V/

ns

3

18

3

18

2.5

18

2.5

18

2.5

18

Rev. 1.6 / Jan.2020

38

AC and DC output Measurement levels

Single-ended AC & DC Output Levels

Single-ended AC & DC output levels

DDR4-1600/1866/2133/

2400/2666/3200

Symbol Parameter

Units NOTE

V

_OH(DC) DC output high measurement level (for IV curve linearity)

_OM(DC) DC output mid measurement level (for IV curve linearity)

V_OL(DC) DC output low measurement level (for IV curve linearity)

_OH(AC) AC output high measurement level (for output SR)

1.1 x V_DDQ

0.8 x V_DDQ

V

0.5 x V_DDQ

V

(0.7 + 0.15) x V_DDQ

(0.7 - 0.15) x V_DDQ

V

1

V_OL(AC) AC output low measurement level (for output SR)

NOTE :

1. The swing of ± 0.15 × V

is based on approximately 50% of the static single-ended output peak-to-

DDQ

peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to V = V

.

TT

DDQ

Differential AC & DC Output Levels

Differential AC & DC output levels

DDR4-1600/1866/

2133/2400/2666/3200

Symbol Parameter

Units NOTE

V

_OHdiff(AC) AC differential output high measurement level (for output SR)

_OLdiff(AC) AC differential output low measurement level (for output SR)

NOTE :

+0.3 x V_DDQ

-0.3 x V_DDQ

V

1

V

1. The swing of ± 0.3 × V_DDQis based on approximately 50% of the static differential output peak-to-peak swing with

a driver impedance of RZQ/7Ω and an effective test load of 50Ω to V_TT= V_DDQat each of the differential outputs.

Rev. 1.6 / Jan.2020

39

Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between V

and V

for single ended signals as shown in Table and Figure below.

OL(AC)

OH(AC)

Single-ended output slew rate definition

Measured

Description

Defined by

From

To

[V_OH(AC)-V_OL(AC)] /

Delta TRse

V_OL(AC)

V_OH(AC)

Single ended output slew rate for rising edge

[V_OH(AC)-V_OL(AC)] /

Delta TFse

V_OH(AC)

V_OL(AC)

Single ended output slew rate for falling edge

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

V

OH(AC)

V

OL(AC)

delta TFse

delta TRse

Single-ended Output Slew Rate Definition

Single-ended output slew rate

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Parameter

Symbol

Units

Single ended output slew rate SRQse

4

9

4

9

4

9

4

9

4

9

4

9

4

9

V/ns

Description: SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

NOTE:

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or

low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction

(i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction,

the regular maximum limit of 9 V/ns applies

Rev. 1.6 / Jan.2020

40

Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure

below.

Differential output slew rate definition

Measured

Description

Defined by

From

To

[V_OHdiff(AC)-V_OLdiff(AC)] /

Delta TRdiff

V_OLdiff(AC)

V_OHdiff(AC)

Differential output slew rate for rising edge

[V_OHdiff(AC)-V_OLdiff(AC)] /

Delta TFdiff

V_OHdiff(AC)

V_OLdiff(AC)

Differential output slew rate for falling edge

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

V

(AC)

OHdiff

V

(AC)

OLdiff

delta TFdiff

delta TRdiff

Differential Output Slew Rate Definition

Differential output slew rate

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Parameter

Symbol

Units

Differential output slew rate SRQdiff

Description:

8

18

8

18

8

18

8

18

8

18

8

18

8

18

V/ns

SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

diff: Differential Signals

For Ron = RZQ/7 setting

Rev. 1.6 / Jan.2020

41

Single-ended AC & DC Output Levels of Connectivity Test Mode

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test

Mode.

Single-ended AC & DC output levels of Connectivity Test Mode

DDR4-1600/1866/2133/

Symbol Parameter

_OH(DC) DC output high measurement level (for IV curve linearity)

Unit Note

2400/2666/3200

V

1.1 x V_DDQ

V

V_OM(DC) DC output mid measurement level (for IV curve linearity)

V_OL(DC) DC output low measurement level (for IV curve linearity)

V_OB(DC) DC output below measurement level (for IV curve linearity)

0.8 x V_DDQ

0.5 x V_DDQ

0.2 x V_DDQ

V

_OH(AC) AC output high measurement level (for output SR)

VTT + (0.1 x V_DDQ

)

1

V_OL(AC) AC output below measurement level (for output SR)

VTT - (0.1 x V_DDQ

)

NOTE :

1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.

VOH(AC)

VTT

0.5 * VDDQ

VOL(AC)

TF_output_CT

TR_output_CT

Differential Output Slew Rate Definition of Connectivity Test Mode

Single-ended output slew rate of Connectivity Test Mode

DDR4-1600/1866/2133/2400/2666/3200

Parameter

Symbol

Unit Note

Min

Max

10

Output signal Falling time TF_output_CT

Output signal Rising time TR_output_CT

-

ns/V

10

Rev. 1.6 / Jan.2020

42

Standard Speed Bins

DDR4-1600 Speed Bins and Operations

Speed Bin

DDR4-1600K

CL-nRCD-nRP

11-11-11

Unit NOTE

Parameter

Symbol

min

max

Internal read command to first

data

13.75¹⁴

(13.50)^5,12

tAA

18.00

ns

12

Internal read command to first

data with read DBI enabled

tAA_DBI

tRCD

tAA(min) + 2nCK

tAA(max) +2nCK

-

13.75

(13.50)^5,12

ACT to internal read or write

delay time

13.75

(13.50)^5,12

PRE command period

tRP

tRAS

tRC

-

ns

12

ACT to PRE command period

35

9 x tREFI

-

48.75

(48.50)^5,12

ACT to ACT or REF command

period

Normal

Read DBI

CL = 11

1,2,3,4,

11,14

CL = 9

tCK(AVG)

1.5

1.6

ns

(Optional)

5

CWL= 9

1,2,3,4,

11

CL = 10

CL = 12 tCK(AVG)

Reserved

CL = 10

CL = 11

CL = 12

CL = 12 tCK(AVG)

CL = 13 tCK(AVG)

CL = 14 tCK(AVG)

ns 1,2,3,4

CWL =

9,11

1.25

<1.5

ns

1,2,3

Supported CL Settings

(9),11,12

(11),13,14

9,11

nCK 13,14

Supported CL Settings with read DBI

Supported CWL Settings

nCK

13

Rev. 1.6 / Jan.2020

43

DDR4-1866 Speed Bins and Operations

Speed Bin

DDR4-1866M

CL-nRCD-nRP

13-13-13

Unit NOTE

Parameter

Symbol

min

max

14

Internal read command to first

data

13.92

tAA

18.00

ns

12

5,12

(13.50)

Internal read command to first

data with read DBI enabled

tAA_DBI

tRCD

tAA(min) + 2nCK

tAA(max) +2nCK

-

ACT to internal read or write

delay time

13.92

5,12

(13.50)

13.92

-

ns

PRE command period

tRP

tRAS

tRC

12

5,12

(13.50)

34

9 x tREFI

-

ACT to PRE command period

ACT to ACT or REF command

period

47.92

5,12

(47.50)

Normal Read DBI

1,2,3,4,

11,14

CL = 11

CL = 9

1.5

ns

tCK(AVG)

1.6

(Optional)⁵

CWL = 9

1,2,3,4,

11

Reserved

ns

CL = 10

CL = 11

CL = 12 tCK(AVG)

CL = 13 tCK(AVG)

4

CWL =

9,11

1,2,3,4,

6

1.25

<1.5

1,2,3,6

1,2,3,4

1,2,3

ns

CL = 12

CL = 13

CL = 14

CL = 14 tCK(AVG)

CL = 15 tCK(AVG)

CL = 16 tCK(AVG)

Reserved

CWL =

10,12

1.071

<1.25

ns

13,14

13

9,11,12,13,14

11,13,14 15,16

9,10,11,12

nCK

Supported CL Settings

Supported CL Settings with read DBI

Supported CWL Settings

Rev. 1.6 / Jan.2020

44

DDR4-2133 Speed Bins and Operations

Speed Bin

DDR4-2133P

CL-nRCD-nRP

15-15-15

Unit NOTE

Parameter

Symbol

min

max

Internal read command to first

data

14.06¹⁴

(13.50)^5,12

tAA

18.00

ns

12

Internal read command to first

data with read DBI enabled

tAA_DBI

tRCD

tAA(min) + 3nCK

tAA(max) + 3nCK

-

14.06

(13.50)^5,12

ACT to internal read or write delay

time

14.06

(13.50)^5,12

PRE command period

tRP

tRAS

tRC

-

ns

12

ACT to PRE command period

33

9 x tREFI

-

47.06

(46.50)^5,12

ACT to ACT or REF command

period

Normal Read DBI

1,2,3,4,

11,14

CL = 9

CL = 10

CL = 11

CL = 12

CL = 13

CL = 11

CL = 12

CL = 13

CL = 14

CL = 15

tCK(AVG)

1.5

1.6

ns

CWL = 9

Reserved

ns 1,2,3,11

1,2,3,4,

1.25

<1.5

ns

7

CWL = 9,11

ns

1,2,3,7

1,2,3,4,

7

1.071

<1.25

CWL =

10,12

CL = 14

CL = 15

CL = 16

CL = 17

CL = 18

CL = 19

tCK(AVG)

ns

1,2,3,7

1,2,3,4

1,2,3

Reserved

CWL =

11,14

0.937

<1.071

Supported CL Settings

(9),(11),12,(13),14,15,16

(11),(13),14,(15),16,18,19

9,10,11,12,14

nCK 13,14

nCK

Supported CL Settings with read DBI

Supported CWL Settings

ns

12

Rev. 1.6 / Jan.2020

45

DDR4-2400 Speed Bins and Operations

Speed Bin

DDR4-2400T

CL-nRCD-nRP

17-17-17

Unit

NOTE

Parameter

Symbol

min

max

14.16

(13.75)^5,12

Internal read command to first

data

tAA

18.00

ns

12

Internal read command to first

data with read DBI enabled

tAA_DBI

tRCD

tAA(min) + 3nCK

tAA(max) + 3nCK

-

14.16

(13.75)^5,12

ACT to internal read or write

delay time

14.16

(13.75)^5,12

PRE command period

tRP

tRAS

tRC

-

ns

12

ACT to PRE command period

32

9 x tREFI

-

46.16

(45.75)^5,12

ACT to ACT or REF command

period

Normal Read DBI

CL = 11

1,2,3,4,11

CL = 9

Reserved

ns

5

(Optional)

CWL = 9

tCK(AVG)

CL = 10

CL = 11

CL = 12

CL = 13

CL = 14

CL = 15

CL = 16

CL = 15

CL = 16

CL = 17

CL = 18

CL = 12

1.5

1.6

ns 1,2,3,4,11

ns

4

CWL = 9,11

CL = 13 tCK(AVG)

1.25

<1.5

1,2,3,4,8

1,2,3,8

4

CL = 14

tCK(AVG)

Reserved

CWL =

10,12

CL = 15 tCK(AVG)

1.071

<1.25

1,2,3,4,8

1,2,3,8

4

CL = 16

CL = 17

tCK(AVG)

CWL =

11,14

CL = 18 tCK(AVG)

0.937

<1.071

1,2,3,4,8

1,2,3,8

1,2,3,4

CL = 19

CL = 18

CL = 19

CL = 20

CL = 21

tCK(AVG)

Reserved

CWL =

12,16

0.833

<0.937

ns

1,2,3

13

Supported CL Settings

10,11,12,13,14,15,16,17,18

12,13,14,15,16,18,19,20,21

9,10,11,12,14,16

nCK

Supported CL Settings with read DBI

Supported CWL Settings

Rev. 1.6 / Jan.2020

46

DDR4-2666 Speed Bins and Operations

Speed Bin

DDR4-2666V

CL-nRCD-nRP

19-19-19

Unit

NOTE

Parameter

Symbol

min

max

14.25¹⁴

Internal read command to

first data

tAA

18.00

ns

12

(13.75)^5,12

Internal read command to

first data with read DBI

enabled

tAA_DBI

tAA(min) + 3nCK

tAA(max) + 3nCK

ACT to internal read or write

delay time

14.25

tRCD

tRP

-

ns

12

(13.75)^5,12

PRE command period

14.25

(13.75)^5,12

-

ACT to PRE command

period

tRAS

tRC

32

9 x tREFI

-

ACT to ACT or REF com-

mand period

46.25

(45.75)^5,12

Normal Read DBI

CWL= 9 CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG)

Reserved

ns 1,2,3,4,11

1.5

1.6

ns

1,2,3,11

4

CWL = CL = 10 CL = 12 tCK(AVG)

9,11

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG)

1.25

<1.5

ns

1,2,3,4,9

1,2,3,9

4

ns

CWL = CL = 12 CL = 14 tCK(AVG)

10,12

Reserved

ns

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG)

1.071

<1.25

ns

1,2,3,4,9

1,2,3,9

4

ns

CWL = CL = 14 CL = 17 tCK(AVG)

ns

11,14

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG)

0.937

<1.071

ns

1,2,3,4,9

1,2,3,9

4

ns

CWL = CL = 15 CL = 18 tCK(AVG)

12.16

Reserved

ns

CL = 16 CL = 19 tCK(AVG)

CL = 17 CL = 20 tCK(AVG)

CL = 18 CL = 21 tCK(AVG)

ns

1,2,3,4,9

1,2,3

0.833

<0.937

ns

CWL = CL = 17 CL = 20 tCK(AVG)

Reserved

ns

1,2,3,4

1,2,3

14,18

CL = 18 CL = 21 tCK(AVG)

CL = 19 CL = 22 tCK(AVG)

CL = 20 CL = 23 tCK(AVG)

Supported CL Settings

ns

0.75

<0.833

ns

10,(11),12,(13),14,(15),16,(17),18,19,20

12,(13),14,(15),17,(18),19,(20),21,22,23

9,10,11,12,14,16,18

nCK

13

Supported CL Settings with read DBI

Supported CWL Settings

Rev. 1.6 / Jan.2020

47

DDR4-2933 Speed Bins and Operations

Speed Bin

DDR4-2933Y

CL-nRCD-nRP

21-21-21

Unit

NOTE

Parameter

Symbol

min

max

14.32¹⁴

(13.75)^5,12

Internal read command to

first data

tAA

18.00

ns

12

Internal read command to

first data with read DBI

enabled

tAA_DBI

tAA(min) + 4nCK

tAA(max) + 4nCK

ns

12

14.32

(13.75)^5,12

14.32

ACT to internal read or write

delay time

tRCD

tRP

-

ns

12

PRE command period

-

(13.75)^5,12

ACT to PRE command

period

tRAS

tRC

32

9 x tREFI

-

46.32

(45.75)^5,12

ACT to ACT or REF com-

mand period

Read

Normal

DBI

CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG)

Reserved

ns

1,2,3,4,11

1,2,3,11

1,2,3,4

CWL =

9

1.5

1.6

CWL = CL = 10 CL = 12 tCK(AVG)

9,11

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG)

1.25

<1.5

ns 1,2,3,4,13

ns

1,2,3,15

1,2,3,4

CWL = CL = 12 CL = 14 tCK(AVG)

10,12

Reserved

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG)

1.071

<1.25

ns 1,2,3,4,15

ns

1,2,3,15

1,2,3,4

CWL = CL = 14 CL = 17 tCK(AVG)

11,14

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG)

0.937

<1.071

ns 1,2,3,4,15

ns

1,2,3,15

1,2,3,4

CWL = CL = 15 CL = 18 tCK(AVG)

12.16

Reserved

CL = 16 CL = 19 tCK(AVG)

CL = 17 CL = 20 tCK(AVG)

CL = 18 CL = 21 tCK(AVG)

ns 1,2,3,4,15

0.833

0.937

ns

1,2,3,15

1,2,3,4

CWL = CL = 17 CL = 20 tCK(AVG)

14,18

Reserved

CL = 18 CL = 21 tCK(AVG)

CL = 19 CL = 22 tCK(AVG)

CL = 20 CL = 23 tCK(AVG)

ns 1,2,3,4,15

0.75

<0.833

ns

1,2,3,15

1,2,3,4

1,2,3

CWL = CL = 19 CL = 23 tCK(AVG)

16,20

Reserved

CL = 20 CL = 24 tCK(AVG)

CL = 21 CL = 26 tCK(AVG)

CL = 22 CL = 26 tCK(AVG)

Supported CL Settings

ns

0.682

<0.75

ns

10,(11),12,(13),14,(15),16,(17),18,(19),20,

21,22

nCK

13

Supported CL Settings with read DBI

Supported CWL Settings

12,(13),14,(15),16,(18),19,(20),21,(22),23,

25,26

nCK

13

9,10,11,12,14,15,16,18,20



Rev. 1.6 / Jan.2020

48

DDR4-3200 Speed Bins and Operations

Speed Bin

DDR4-3200AA

CL-nRCD-nRP

22-22-22

Unit

NOTE

Parameter

Symbol

min

max

Internal read command to

first data

tAA

13.75

18.00

ns

12

Internal read command to

first data with read DBI

enabled

tAA(min)

+ 4nCK

tAA_DBI

tAA(max) + 4nCK

ACT to internal read or

write delay time

tRCD

tRP

13.75

32

-

ns

12

PRE command period

-

ACT to PRE command

period

tRAS

9 x tREFI

ACT to ACT or REF com-

mand period

tRC

45.75

-

ns

12

Read

Normal

DBI

CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG)

Reserved

ns

nCK

1,2,3,4,11

1,2,3,4

CWL =

9

CWL = CL = 10 CL = 12 tCK(AVG)

9,11

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG)

1.25

<1.5

1,2,3,4,10

1,2,3,10

1,2,3,4

CWL = CL = 12 CL = 14 tCK(AVG)

Reserved

10,12

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG)

1.071

<1.25

1,2,3,4,10

1,2,3,10

1,2,3,4

CWL = CL = 14 CL = 17 tCK(AVG)

11,14

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG)

0.937

<1.071

1,2,3,4,10

1,2,3,10

1,2,3,4

CWL = CL = 15 CL = 18 tCK(AVG)

Reserved

12.16

CL = 16 CL = 19 tCK(AVG)

CL = 17 CL = 20 tCK(AVG)

CL = 18 CL = 21 tCK(AVG)

1,2,3,4,10

1,2,3,10

1,2,3,4

0.833

<0.937

CWL = CL = 17 CL = 20 tCK(AVG)

Reserved

14,18

CL = 18 CL = 21 tCK(AVG)

CL = 19 CL = 22 tCK(AVG)

CL = 20 CL = 23 tCK(AVG)

1,2,3,4,10

1,2,3,10

1,2,3,4

0.75

<0.833

CWL = CL = 20 CL = 24 tCK(AVG)

Reserved

16,20

CL = 22 CL = 26 tCK(AVG)

CL = 24 CL = 28 tCK(AVG)

Supported CL Settings

0.625

<0.75

1,2,3,4

1,2,3

10,11,12,13,14,15, 16,17,18,19,20,22,

24

13

Supported CL Settings with read DBI

Supported CWL Settings

12,13,14,15,16,18, 19,20,21,22,23,24,

26, 28

nCK

9,10,11,12,14,16,

18,20



Rev. 1.6 / Jan.2020

49

Speed Bin Table Note

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133, 2400, 2933 and 3200 Speed Bin Tables are valid only when Geardown Mode is

disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection

of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL

- all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following

rounding algorithm defined in Section 13.5.

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the

next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.937 ns or 0.833 ns). This result is tCK(avg).MAX corre-

sponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory fea-

ture. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

10. Any DDR4-3200 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

11. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

12. DDR4-2400,2666,2933 and 3200Mbps speed bin support CL=10 if DRAM operate at 1333MT/s data rate.

13. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the

Speed Bin Tables.

14. CL number in parentheses, it means that these numbers are optional.

15. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

16. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC

compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance

requires meeting the parameters for a least one of the listed speed bins.

Rev. 1.6 / Jan.2020

50

IDD and IDDQ Specification Parameters and Test Conditions

IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.

Figure shows the setup and test load for IDD, IPP and IDDQ measurements.

•

IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,

IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,

IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the

DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

•

IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all

VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-

rents.

Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can

be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In

DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one

merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

•

“0” and “LOW” is defined as VIN <= VILAC(max).

“1” and “HIGH” is defined as VIN >= VIHAC(min).

“MID-LEVEL” is defined as inputs are VREF = VDD / 2.

Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.

Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.

Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.

IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-

ited to setting 

RON = RZQ/7 (34 Ohm in MR1); 

RTT_NOM = RZQ/6 (40 Ohm in MR1);

RTT_WR = RZQ/2 (120 Ohm in MR2);

RTT_PARK = Disable;

Qoff = 0 (Output Buffer enabled) in MR1;

B

TDQS_t disabled in MR1;

CRC disabled in MR2;

CA parity feature disabled in MR5;

Gear down mode disabled in MR3

Read/Write DBI disabled in MR5;

DM disabled in MR5

•

Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time

before actual IDD or IDDQ measurement is started.

Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA

changes when directed.

Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply

invert of BG/BA changes when directed above.

Rev. 1.6 / Jan.2020

51

I

DDQ

DD

PP

V

DDQ

DD

PP

RESET

CK_t/CK_c

DDR4 SDRAM

CKE

CS

C

DQS_t/DQS_c

DQ

DM

ACT,RAS,CAS,WE

A,BG,BA

ODT

V

SSQ

SS

ZQ

NOTE:

1. DIMM level Output test load condition may be different from above

Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements

Application specific

IDDQ

TestLad

memory channel

environment

Channel

IO Powe

Simulatin

IDDQ

Simuaion

IDDQ

Measurement

Correlation

X

Channel IO Power

Number

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ

Measurement

Rev. 1.6 / Jan.2020

52

Table 1-Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Symbol

Unit

11-11-11

1.25

11

39

28

11

16

20

28

4

13-13-13

15-15-15

17-17-17

19-19-19

0.75

19

18

19

62

43

19

16

28

40

4

21-21-21

0.682

21

20

21

68

47

21

16

31

44

4

22-22-22

0.625

22

20

22

74

52

22

16

34

48

4

tCK

CL

1.071

13

12

13

45

32

13

16

22

28

4

0.937

15

14

15

51

36

15

16

23

32

4

0.833

17

16

17

56

39

17

16

26

36

4

ns

nCK

CWL

nRCD

nRC

nRAS

nRP

x4

x8

nFAW

nRRDS

nRRDL

x16

x4

x8

4

x16

x4

5

6

7

8

9

5

6

7

8

x8

5

6

7

8

x16

6

7

8

9

10

4

11

tCCD_S

4

tCCD_L

tWTR_S

5

6

7

8

2

3

4

tWTR_L

6

7

8

9

10

214

347

467

734

11

12

256

416

560

880

nRFC 2Gb

nRFC 4Gb

nRFC 8Gb

nRFC 16Gb

TBD

128

208

280

440

150

243

327

514

171

278

374

587

193

313

421

661

235

382

514

807

Rev. 1.6 / Jan.2020

53

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8¹; AL: 0; CS_n: High

between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially

toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-

IDD0

ters²; ODT Signal: stable at 0; Pattern Details: see Table 3

Operating One Bank Active-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD0

IDD0A

IPP0

Operating One Bank Active-Precharge IPP Current

Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8¹; AL: 0; CS_n: High

between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,

Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Regis-

IDD1

ters²; ODT Signal: stable at 0; Pattern Details: see Table 4

Operating One Bank Active-Read-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD1

IDD1A

IPP1

Operating One Bank Active-Read-Precharge IPP Current

Same condition with IDD1

Precharge Standby Current (AL=0)

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data

IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

IDD2N

Mode Registers²; ODT Signal: stable at 0; Pattern Details: see Table 5

Precharge Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD2N

IDD2NA

IPP2N

Precharge Standby IPP Current

Same condition with IDD2N

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: stable at 1; Command,

IDD2NT Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data

IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers²; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6

IDDQ2NT Precharge Standby ODT IDDQ Current

(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

IDD2NL

Same definition like for IDD2N, CAL enabled³

Precharge Standby Current with Gear Down mode enabled

IDD2NG

Same definition like for IDD2N, Gear Down mode enabled^3,5

Precharge Standby Current with DLL disabled

IDD2ND

Same definition like for IDD2N, DLL disabled³

Rev. 1.6 / Jan.2020

54

Precharge Standby Current with CA parity enabled

IDD2N_par

IDD2P

Same definition like for IDD2N, CA parity enabled³

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL:

0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at

0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:

Enabled in Mode Registers²; ODT Signal: stable at 0

Precharge Power-Down IPP Current

Same condition with IDD2P

IPP2P

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers²; ODT

Signal: stable at 0

IDD2Q

IDD3N

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data

IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in

Mode Registers²; ODT Signal: stable at 0; Pattern Details: see Table 5

Active Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD3N

IDD3NA

IPP3N

Active Standby IPP Current

Same condition with IDD3N

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal:

stable at 0

IDD3P

IPP3P

Active Power-Down IPP Current

Same condition with IDD3P

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8²; AL: 0; CS_n: High between RD;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Table 7; Data IO: seamless read data burst with different data between one burst and the next one

according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through

banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal:

stable at 0; Pattern Details: see Table 7

IDD4R

Operating Burst Read Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD4R

IDD4RA

IDD4RB

IPP4R

Operating Burst Read Current with Read DBI

Read DBI enabled³, Other conditions: see IDD4R

Operating Burst Read IPP Current

Same condition with IDD4R

IDDQ4R Operating Burst Read IDDQ Current

(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

IDDQ4RB Operating Burst Read IDDQ Current with Read DBI

(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Rev. 1.6 / Jan.2020

55

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8¹; AL: 0; CS_n: High between WR;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

IDD4W Table 8; Data IO: seamless write data burst with different data between one burst and the next one

according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through

banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal:

stable at HIGH; Pattern Details: see Table 8

Operating Burst Write Current (AL=CL-1)

IDD4WA

AL = CL-1, Other conditions: see IDD4W

Operating Burst Write Current with Write DBI

IDD4WB

Write DBI enabled³, Other conditions: see IDD4W

Operating Burst Write Current with Write CRC

IDD4WC

Write CRC enabled³, Other conditions: see IDD4W

Operating Burst Write Current with CA Parity

IDD4W_par

CA Parity enabled³, Other conditions: see IDD4W

Operating Burst Write IPP Current

IPP4W

Same condition with IDD4W

Burst Refresh Current (1X REF)

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8¹; AL: 0; CS_n: High between REF;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

IDD5B

Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);

Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal: stable at 0; Pattern Details: see

Table 9

Burst Refresh Write IPP Current (1X REF)

Same condition with IDD5B

IPP5B

Burst Refresh Current (2X REF)

IDD5F2

tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF)

IPP5F2

Same condition with IDD5F2

Burst Refresh Current (4X REF)

IDD5F4

tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF)

IPP5F4

Same condition with IDD5F4

Self Refresh Current: Normal Temperature Range

T_CASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal⁴; CKE: Low; External clock:

IDD6N

IPP6N

IDD6E

IPP6E

Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 8¹; AL: 0; CS_n#, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;

Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Normal Temperature Range

Same condition with IDD6N

Self-Refresh Current: Extended Temperature Range⁾

T_CASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended⁴; CKE: Low; External clock:

Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 8¹; AL: 0; CS_n, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature

Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Extended Temperature Range

Same condition with IDD6E

Rev. 1.6 / Jan.2020

56

Self-Refresh Current: Reduced Temperature Range

T_CASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced⁴; CKE: Low;

External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 8¹; AL: 0; CS_n#, Command,

Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:

Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers²;

ODT Signal: MID-LEVEL

IDD6R

Self Refresh IPP Current: Reduced Temperature Range

Same condition with IDD6R

IPP6R

IDD6A

IPP6A

Auto Self-Refresh Current

T_CASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto⁴; CKE: Low; External clock: Off;

CK_t and CK_c#: LOW; CL: see Table 1; BL: 8¹; AL: 0; CS_n#, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh

operation; Output Buffer and RTT: Enabled in Mode Registers²; ODT Signal: MID-LEVEL

Auto Self-Refresh IPP Current

Same condition with IDD6A

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 8¹; AL:

CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address

Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between

one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times

interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and

RTT: Enabled in Mode Registers²; ODT Signal: stable at 0; Pattern Details: see Table 10

IDD7

Operating Bank Interleave Read IPP Current

Same condition with IDD7

IPP7

IDD8

IPP8

Maximum Power Down Current

TBD

Maximum Power Down IPP Current

Same condition with IDD8

Rev. 1.6 / Jan.2020

57

NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7

RTT_Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s

010] : 1866MT/s, 2133MT/s

011] : 2400MT/s

Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate

DLL disabled : set MR1 [A0 = 0]

CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s

010] : 2400MT/s

Read DBI enabled : set MR5 [A12 = 1]

Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal

01] : Reduced Temperature range

10] : Extended Temperature range

11] : Auto Self Refresh

5. IDD2NG should be measured after sync pulse(NOP) input.

Rev. 1.6 / Jan.2020

58

Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern¹

Data⁴

0

ACT

0

1

0

-

1,2

D, D

D_#,

D_#

3²

3,4

1

0

3

0

7

F

0

-

...

nRAS

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

0

1

0

1

0

-

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 0 instead

1

2

1*nRC

2*nRC

3*nRC

4*nRC

5*nRC

6*nRC

7*nRC

8*nRC

9*nRC

10*nRC

11*nRC

12*nRC

13*nRC

14*nRC

15*nRC

3

4

5

6

7

8

9

10

11

12

13

14

15

For x4

and x8

only

NOTE:

1 .DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

Rev. 1.6 / Jan.2020

59

Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Pattern^a)

Data⁴

0

1

0

WR

0

1

0

1

0

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

1

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

3²

1

2,3

D#, D#

4

WR

0

1

0

1

0

1

0

7

F

0

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

5

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

3²

6,7

D#, D#

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 0 instead

2

3

4

5

6

7

8

9

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

For x4 and x8 only

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE:

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

Rev. 1.6 / Jan.2020

60

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,

IDD3NA and IDD3P

Measurement-Loop Pattern¹

Data⁴

0

1

2

D, D

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

D#,

D#

3²

3

D#,

D#

1

0

3

0

7

F

0

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 3, BA[1:0] = 0 instead

1

2

3

4

5

6

7

8

9

4-7

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

Rev. 1.6 / Jan.2020

61

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern¹

Data⁴

0 0

D, D

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

1

2

D, D

D#, D#

3

D#, D#

1

0

3

0

7

F

0

-

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 1, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]²= 3, BA[1:0] = 0 instead

1 4-7

2 8-11

3 12-15

4 16-19

5 20-23

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

For x4

andx8

only

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

Rev. 1.6 / Jan.2020

62

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern¹

Data⁴

0

1

0

RD

0

1

0

1

0

3²

1

0

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

1

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2,3

D#, D#

4

RD

0

1

0

1

0

1

0

7

F

0

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

5

D

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

6,7

D#, D#

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 0 instead

2

3

4

5

6

7

8

9

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

For x4 and x8 only

NOTE :

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Read Command.

Rev. 1.6 / Jan.2020

63

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern¹

Data⁴

0

1

0

WR

0

1

0

1

0

3²

1

0

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

1

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2,3

D#, D#

4

WR

0

1

0

1

0

1

0

7

F

0

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

5

D

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

6,7

D#, D#

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 0 instead

2

3

4

5

6

7

8

9

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

For x4 and x8 only

NOTE :

1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Write Command.

Rev. 1.6 / Jan.2020

64

Table 9 - IDD4WC Measurement-Loop Pattern¹

Data^d

0 0

WR

0

1

0

1

0

3²

1

0

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

D8=CRC

1,2

D, D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

3,4

5

D#, D#

WR

0

1

0

1

0

1

0

7

F

0

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

D8=CRC

6,7

8,9

D, D

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

D#, D#

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 0 instead

2 10-14

3 15-19

4 20-24

5 25-29

6 30-34

7 35-39

8 40-44

9 45-49

10 50-54

11 55-59

12 60-64

13 65-69

14 70-74

15 75-79

For x4 and x8 only

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Write Command.

Rev. 1.6 / Jan.2020

65

Table 10 - IDD5B Measurement-Loop Pattern¹

Data⁴

0 0

1 1

2

REF

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

D

3

D#, D#

4

D#, D#

1

0

3

0

7

F

0

-

repeat pattern 1...4, use BG[1:0]²= 1, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]²= 0, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat pattern 1...4, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat pattern 1...4, use BG[1:0]²= 1, BA[1:0] = 0 instead

repeat pattern 1...4, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat pattern 1...4, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]²= 3, BA[1:0] = 3 instead

repeat pattern 1...4, use BG[1:0]²= 2, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat pattern 1...4, use BG[1:0]²= 3, BA[1:0] = 0 instead

4-7

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

For x4 and x8

only

2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. DQ signals are VDDQ.

Rev. 1.6 / Jan.2020

66

Table 11 - IDD7 Measurement-Loop Pattern¹

Data⁴

0 0

1

ACT

RDA

0

1

0

1

0

1

0

1

0

-

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

-

2

3

D

D#

1

0

1

0

1

0

1

0

1

0

3²

0

3

0

7

0

F

0

-

...

1 nRRD

nRRD + 1

repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

ACT

RDA

0

1

0

1

0

1

0

1

0

1

0

-

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

...

repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 2 instead

2 2*nRRD

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 3 instead

repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary

3 3*nRRD

4 4*nRRD

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 1, BA[1:0] = 0 instead

5 nFAW

6 nFAW + nRRD

7 nFAW + 2*nRRD

8 nFAW + 3*nRRD

9 nFAW + 4*nRRD repeat Sub-Loop 4

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 3 instead

10 2*nFAW

11 2*nFAW + nRRD

12 2*nFAW + 2*nRRD

13 2*nFAW + 3*nRRD

14 2*nFAW + 4*nRRD repeat Sub-Loop 4

For x4 and x8

only

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 1 instead

15 3*nFAW

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]²= 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]²= 3, BA[1:0] = 0 instead

16 3*nFAW + nRRD

17 3*nFAW + 2*nRRD

18 3*nFAW + 3*nRRD

19 3*nFAW + 4*nRRD repeat Sub-Loop 4

20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ

Rev. 1.6 / Jan.2020

67

IDD Specifications (Tcase: 0 to 95^oC)

4GB, 512Mx 64 SO-DIMM: HMA851S6CJR6N

IDD

2666

180

184

244

256

112

132

84

IPP

2666

38

42

13

64

88

uni not

uni no

t

e

t

te

Symbol 2400

2933

188

192

248

264

116

136

88

116

112

116

84

100

160

128

872

892

884

672

728

660

676

772

792

584

524

84

3200

188

200

252

272

120

140

92

120

116

120

88

100

164

132

940

964

956

716

780

708

724

856

796

592

532

84

Symbol 2400

2933

38

42

13

64

88

252

168

140

20

28

16

28

96

13

3200

38

42

13

64

88

252

172

140

20

28

16

28

96

13

IDD0

IDD0A

IDD1

176

236

248

108

128

80

108

104

108

76

mA

IPP0

IPP1

38

42

mA

IPP2N

IPP2P

IPP3N

IPP3P

IPP4R

IPP4W

IPP5B

IPP5F2

IPP5F4

IPP6N

IPP6E

IPP6R

IPP6A

IPP7

13

64

88

252

160

140

20

IDD1A

IDD2N

IDD2NA

IDD2NT

IDD2NL

IDD2NG

IDD2ND

IDD2NP

IDD2P

88

112

108

112

80

252

164

140

20

28

20

28

96

13

IDD2Q

IDD3N

IDD3NA

IDD3P

IDD4R

IDD4RA

IDD4RB

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4WP

IDD5B

IDD5F2

IDD5F4

IDD6N

IDD6E

IDD6R

IDD6A

IDD7

100

148

120

736

756

588

608

560

580

648

784

568

508

84

100

152

124

800

816

812

640

664

604

628

708

788

576

516

84

28

16

28

92

IPP8

13

112

56

112

736

48

112

56

112

756

48

112

56

112

768

48

112

56

112

788

48

IDD8

Rev. 1.6 / Jan.2020

68

8GB, 1Gx 64 SO-DIMM: HMA81GS6CJR8N

IDD

2666

296

304

376

400

224

264

168

224

216

224

160

200

304

248

1008

1032

1024

864

896

816

848

1000

1576

1152

1032

168

224

112

224

1168

96

IPP

2666

44

52

26

uni not

uni no

t

e

t

te

Symbol 2400

2933

312

320

392

416

232

272

176

232

224

232

168

200

320

256

1096

1128

1112

944

976

896

928

1088

1584

1168

1048

168

224

112

224

1176

96

3200

312

336

400

432

240

280

184

240

232

240

176

200

328

264

Symbol 2400

2933

44

52

26

128

152

504

336

280

40

3200

44

52

26

128

152

504

344

280

40

IDD0

IDD0A

IDD1

288

360

384

216

256

160

216

208

216

152

200

296

240

928

952

800

824

760

784

920

1568

1136

1016

168

224

112

224

1120

96

mA

IPP0

IPP1

44

52

mA

IPP2N

IPP2P

IPP3N

IPP3P

IPP4R

IPP4W

IPP5B

IPP5F2

IPP5F4

IPP6N

IPP6E

IPP6R

IPP6A

IPP7

26

IDD1A

IDD2N

IDD2NA

IDD2NT

IDD2NL

IDD2NG

IDD2ND

IDD2NP

IDD2P

26

128

152

504

320

280

40

56

33

56

136

26

128

152

504

328

280

40

56

33

56

144

26

IDD2Q

IDD3N

IDD3NA

IDD3P

56

33

56

144

26

56

33

56

144

26

IDD4R

IDD4RA

IDD4RB

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4WP

IDD5B

1176 mA

1208 mA

1192 mA

mA

1048 mA

mA

1208 mA

1592 mA

1184 mA

1064 mA

IPP8

992

952

992

IDD5F2

IDD5F4

IDD6N

IDD6E

168

224

112

224

mA

IDD6R

IDD6A

IDD7

1200 mA

96 mA

IDD8

Rev. 1.6 / Jan.2020

69

8GB, 1Gx 72 SO-DIMM: HMA81GS7CJR8N

IDD

IPP

2400

50

59

29

unit note

Symbol

IDD0

IDD0A

IDD1

2400

324

405

432

243

288

180

243

234

243

171

225

333

270

1044

1071

900

927

855

882

1035

1764

1278

1143

189

252

126

252

1260

108

2666

333

342

423

450

252

297

189

252

243

252

180

225

342

279

Symbol

IPP0

IPP1

2666

50

59

29

144

171

567

369

315

45

mA

IPP2N

IPP2P

IPP3N

IPP3P

IPP4R

IPP4W

IPP5B

IPP5F2

IPP5F4

IPP6N

IPP6E

IPP6R

IPP6A

IPP7

IDD1A

IDD2N

IDD2NA

IDD2NT

IDD2NL

IDD2NG

IDD2ND

IDD2NP

IDD2P

IDD2Q

IDD3N

IDD3NA

IDD3P

IDD4R

IDD4RA

IDD4RB

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4WP

IDD5B

IDD5F2

IDD5F4

IDD6N

IDD6E

29

144

171

567

360

315

45

63

37

63

153

29

63

37

63

162

29

1134

1161

1152

972

1008

918

IPP8

954

1125

1773

1296

1161

189

252

126

252

1314

108

IDD6R

IDD6A

IDD7

IDD8

Rev. 1.6 / Jan.2020

70

16GB, 2Gx 64 SO-DIMM: HMA82GS6CJR8N

IDD

2666

520

528

600

624

448

528

336

448

432

448

320

400

608

IPP

2666

70

78

51

uni not

uni no

t

e

t

te

Symbol 2400

2933

544

552

624

648

464

544

352

464

448

464

336

400

640

512

1328

1360

1344

1176

1208

1128

1160

1320

1816

1400

1280

336

448

224

448

1408

192

3200

552

576

640

672

480

560

368

480

464

480

352

400

656

528

Symbol 2400

2933

70

78

51

3200

70

78

51

IDD0

IDD0A

IDD1

504

576

600

432

512

320

432

416

432

304

400

592

480

1144

1168

1016

mA

IPP0

IPP1

70

78

mA

IPP2N

IPP2P

IPP3N

IPP3P

IPP4R

IPP4W

IPP5B

IPP5F2

IPP5F4

IPP6N

IPP6E

IPP6R

IPP6A

IPP7

51

IDD1A

51

IDD2N

IDD2NA

IDD2NT

IDD2NL

IDD2NG

IDD2ND

IDD2NP

IDD2P

IDD2Q

IDD3N

IDD3NA

IDD3P

256

178

530

346

306

80

112

66

112

162

51

256

178

530

354

306

80

112

66

112

170

51

256

178

530

362

306

80

112

66

112

170

51

256

178

530

370

306

80

112

66

112

170

51

496

IDD4R

IDD4RA

IDD4RB

IDD4W

1232

1256

1248

1088

1120

1040

1072

1224

1800

1376

1256

336

448

224

448

1392

192

1416 mA

1448 mA

1432 mA

1232 mA

1288 mA

1192 mA

1232 mA

1448 mA

1832 mA

1424 mA

1304 mA

IPP8

IDD4WA 1040

IDD4WB 976

IDD4WC 1000

IDD4WP

IDD5B

IDD5F2

IDD5F4

IDD6N

IDD6E

IDD6R

IDD6A

IDD7

1136

1784

1352

1232

336

448

224

448

1336

192

336

448

224

448

mA

1440 mA

192 mA

IDD8

Rev. 1.6 / Jan.2020

71

16GB, 2Gx 72 SO-DIMM: HMA82GS7CJR8N

IDD

2400

567

IPP

2400

78

unit note

Symbol

IDD0

IDD0A

IDD1

2666

585

Symbol

IPP0

2666

78

mA

567

648

675

486

576

360

486

468

486

342

450

666

540

1287

1314

1143

1170

1098

1125

1278

2007

1521

1386

378

504

252

504

1503

216

594

675

702

504

594

378

504

486

504

360

450

684

558

1386

1413

1404

1224

1260

1170

1206

1377

2025

1548

1413

378

504

252

504

1566

216

IPP1

87

58

87

58

IPP2N

IPP2P

IPP3N

IPP3P

IPP4R

IPP4W

IPP5B

IPP5F2

IPP5F4

IPP6N

IPP6E

IPP6R

IPP6A

IPP7

IDD1A

IDD2N

IDD2NA

IDD2NT

IDD2NL

IDD2NG

IDD2ND

IDD2NP

IDD2P

IDD2Q

IDD3N

IDD3NA

IDD3P

IDD4R

IDD4RA

IDD4RB

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4WP

IDD5B

IDD5F2

IDD5F4

IDD6N

IDD6E

288

200

596

389

344

90

126

74

126

182

58

288

200

596

398

344

90

126

74

126

191

58

IPP8

IDD6R

IDD6A

IDD7

IDD8

Rev. 1.6 / Jan.2020

72

Module Dimensions

512Mx64 - HMA851S6CJR6N

Front

Side

3.5mm max

69.60mm

1.75

4.000.10

SPD

Detail-A

pin 1

pin 260

1.425

2.50

1.675

1.20±0.10

35.50

28.50

2X1.800.10

Back

Detail - A

1.00

±0.05

0.50

0.35±0.03

Note-metalized

keep out area Max 0.30

Max 0.25

0.20±0.15

Note:

1. 0.13 tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 1.6 / Jan.2020

73

1Gx64 - HMA81GS6CJR8N

Front

Side

69.60mm

3.7mm max

1.75

4.000.10

SPD

Detail-A

pin 1

pin 260

1.425

2.50

1.675

1.20±0.10

35.50

28.50

2X1.800.10

Back

Detail - A

±0.05

1.00

0.50

0.35±0.03

Note-metalized

keep out area Max 0.30

Max 0.25

0.20±0.15

Note:

1. 0.13 tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 1.6 / Jan.2020

74

1Gx72 - HMA81GS7CJR8N

Front

Side

69.60mm

3.7mm max

1.75

4.000.10

SPD/TS

Detail-A

pin 1

pin 260

1.425

2.50

1.675

1.20±0.10

35.50

28.50

2X1.800.10

Back

Detail - A

1.00

±0.05

0.50

0.35±0.03

Note-metalized

keep out area Max 0.30

Max 0.25

0.20±0.15

Note:

1. 0.13 tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 1.6 / Jan.2020

75

2Gx64 - HMA82GS6CJR8N

Front

Side

3.7mm max

69.60mm

1.75

4.000.10

SPD

Detail-A

pin 1

pin 260

1.425

2.50

1.675

1.20±0.10

35.50

28.50

2X1.800.10

Back

Detail - A

1.00

±0.05

0.50

0.35±0.03

Note-metalized

keep out area Max 0.30

Max 0.25

0.20±0.15

Note:

1. 0.13 tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 1.6 / Jan.2020

76

2Gx72 - HMA82GS7CJR8N

Front

Side

3.7mm max

69.60mm

1.75

4.000.10

SPD/TS

Detail-A

pin 1

pin 260

1.425

2.50

1.675

1.20±0.10

35.50

28.50

2X1.800.10

Back

Detail - A

1.00

±0.05

0.50

0.35±0.03

Note-metalized

keep out area Max 0.30

Max 0.25

0.20±0.15

Note:

1. 0.13 tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 1.6 / Jan.2020

77


型号：	HMA81GS6CJR8N-WM
厂家：	HYNIX SEMICONDUCTOR
描述：	DDR4 SDRAM SO-DIMM Based on 8Gb C-die 动态存储器双倍数据速率
文件：	总77页 (文件大小：1670K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HMA81GS6CJR8N-WM [HYNIX]

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