HMS81C4260_技术文档

HYNIX SEMICONDUCTOR INC.

8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS81C4x60

User’s Manual (Ver. 1.1)

Version 1.1

Published by MCU Application Team

Heung-il Bae(hibae@hynix.com), Byoung-jin Lim( bjinlim@hynix.com)

Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Repre-

sentatives listed at address directory.

Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

HMS81C4x60

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

FOR TELEVISION

1. OVERVIEW

1.1 Description

The HMS81C4x60 is an advanced CMOS 8-bit microcontroller with 60K bytes of ROM. This is one of the HMS800 family.

This is a powerful microcontroller which provides a high flexibility and cost effective solution to many TV applications. The

HMS81C4x60 provides following standard features: 60K bytes of ROM, 1024 bytes of RAM, 8/16-bit timer/counter, on-

chip PLL oscillator and clock circuitry. In addition, there are other package types, HMS81C4360(32PDIP),

HMS81C4360SK(32SKDIP), HMS81C4460(42SDIP).

This document is explained for the base of HMS81C4x60, the eliminated functions are same as below.

Device name

HMS81C4260

HMS87C4260

ROM Size

EPROM Size

RAM Size

1024bytes

I/O

31

Package

52SDIP

60K bytes

-

60K bytes

1.2 Features

• 60K Bytes of On-chip Program Memory

• 1024 Bytes of On-chip Data RAM

- Watch Dog Timer

• Number of Interrupt Source

- 16 Interrupts

- 3 External Interrupts

• Minimum Instruction Cycle Time

- 256ns (NOP operation)

• On Screen Display

- 512 character fonts pattern

• PLL Oscillator for OSD and System Clock

- External 4MHz Crystal Input

- Character Size : 1.0, 1.5, 2.0 times

- Character Pixel size : 12 × 10, 12 × 12, 12 × 14,

12 × 16, 16 × 18

• 31 Programmable I/O pins

- 26 Input/Output and 5 Input pins

- Display Capability : 48 Characters × 16 Lines

- Character, Background color : 512 colors, 8 pal-

let

• I²C Bus Interface

- Multimaster (2 Pairs interface pins)

• A/D Converter

- 8-bit × 5 ch

- Special functions : Rounding, Outline, Shadow,

Underline, Double scanned line OSD

• Pulse Width Modulation

- 14-bit × 1 ch

• Buzzer Driving Port

- 500Hz ~ 250KHz @4MHz (Duty 50%)

- 8-bit × 5 ch

• Vertical Blanking Interveral Information cap-

ture for EIA-608(Closed Caption) or VPS, etc

• Timer

- Timer/Counter : 8-bit × 4 ch(16-bit × 2 ch)

- Basic interval timer

November 2001 Ver 1.1

1

HMS81C4x60

1.3 Development Tools

Note: There are several setting switches in the Emulator.

User should read carefully and do setting properly before

developing the program. Otherwise, the Emulator may not

work properly.

The HMS87C4x60 is supported by a full-featured macro assem-

bler, an in-circuit emulator CHOICE-Dr.^TMand EPROM pro-

grammers. There are two different type programmers such as

single type and gang type. For more detail, refer to EPROM Pro-

gramming chapter. Macro assembler operates under the MS-

Windows 95/98^TM

.

Please contact sales part of Hynix Semiconductor.

1.4 Ordering Information

Device name

ROM Size (bytes)

60K bytes

RAM size

1024 bytes

Package

52SDIP

Mask ROM version

OTP ROM version

Mask ROM version

OTP ROM version

Mask ROM version

OTP ROM version

Mask ROM version

OTP ROM version

HMS81C4260

HMS87C4260

HMS81C4360SK

HMS87C4360SK

HMS81C4360

HMS87C4360

HMS81C4460

HMS87C4460

60K bytes EPROM (OTP)

60K bytes

52SDIP

32SKDIP

32PDIP

42SDIP

60K bytes EPROM (OTP)

60K bytes

60K bytes EPROM (OTP)

60K bytes

60K bytes EPROM (OTP)

2

November 2001 Ver 1.1

HMS81C4x60

2. BLOCK DIAGRAM

YM

YS

PLL

R

OSD

G8MC

CORE

G

B

CLOCK

GENERATION

/ SYSTEM

CONTROLLER

CVBS

SCAP

DATA

SLICER

RAM ( 1024)

PRESCALER

/BIT

MASK ROM

( User ROM

: 60KB

Font ROM

: 32KB )

R10/AN0

R11/AN1

R12/AN2

R13/AN3

R14/AN4

ADC

WATCH DOG

TIMER

R30/PWM0

R31/PWM1

R32/PWM2

BUZZER

PWM

R33/PWM3

R34/PWM4

R35/PWM5

R40 ~ R43

R30 ~ R37

R20 ~ R25

R10 ~ R14

R00 ~ R07

R4 PORT

R3 PORT

R2 PORT

R1 PORT

R0 PORT

R36/BUZ

REMOCON

R40/SCL0

R41/SDA0

R42/SCL1

R43/SDA1

I²C

INTERRUPT

CONTROLLER

R24/EC2

R25/EC3

TIMER

R37/TMR1

Figure 2-1 Block Diagram

November 2001 Ver 1.1

3

HMS81C4x60

3. PIN ASSIGNMENT

R40/SCL0

R41/SDA0

R42/SCL1

R43/SDA1

R04

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

R30/PWM0

R31/PWM1

R32/PWM2

R33/PWM3

R34/PWM4

R35/PWM5

R36/BUZ

R37/TMR1

TEST

VSS

1

2

3

4

5

R05

6

R06

7

R07

8

VDD

9

HMS81C4260

R14/AD4

SCAP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

52SDIP

YM

CVBS

YS

VDD

B

VSS

G

R10/AD0

R11/AD1

R12/AD2

R13/AD3

HS

R

VDD

VSS

XIN

XOUT

RESET

R03

VS

R20

R21/INT1

R22/INT2

R23/INT3

R24/EC2

R25/EC3

R02

VDD

VSS

R01

R00

Figure 3-1 52SDIP

4

November 2001 Ver 1.1

HMS81C4x60

R40/SCL0

R41/SDA0

42

41

R31/PWM1

R32/PWM2

1

2

R42/SCL1

R43/SDA1

R04

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

R33/PWM3

R34PWM4

R35/PWM5

R36/BUZ

R37/TMR1

TEST

YM

3

4

5

VDD

6

R14/AD4

SCAP

7

8

CVBS

9

HMS81C4460

VDD

YS

10

11

12

13

14

42SDIP

VSS

B

R10/AD0

R11/AD1

R12/AD2

R13/AD3

HS

G

R

XIN

XOUT

RESET

R03

15

16

17

18

19

20

21

VS

R21/INT1

R22/INT2

R23/INT3

R24/EC2

R02

R01

R00

R25/EC3

Figure 3-2 42SDIP

November 2001 Ver 1.1

5

HMS81C4x60

R40/SCL0

R41/SDA0

R42/SCL1

R43/SDA1

VDD

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

R33/PWM3

R34/PWM4

R35/PWM5

R37/TMR1

TEST

1

2

3

4

5

R14/AD4

SCAP

YM

6

YS

7

HMS81C4360SK

32SKDIP

CVBS

B

8

VDD

G

9

VSS

R

10

11

12

13

14

15

16

R10/AD0

R13/AD3

HS

XIN

XOUT

RESET

R02

VS

R21/INT1

R22/INT2

R24/EC2

R23/INT3

Figure 3-3 32SKDIP

R40/SCL0

R41/SDA0

32

R34PWM4

R35PWM5

1

31

2

R42/SCL1

R43/SDA1

VDD

30

29

28

27

26

25

24

23

22

21

20

19

18

17

R37/TMR1

TEST

YM

3

4

5

R14/AD4

SCAP

YS

6

B

7

CVBS

G

8

HMS81C4360

VDD

R

32PDIP

9

VSS

XIN

10

11

12

13

14

15

16

R10/AD0

R11/AD1

R12/AD2

R13/AD3

HS

XOUT

RESET

R02

R24/EC2

R23/INT3

R21/INT1

VS

Figure 3-4 32PDIP

6

November 2001 Ver 1.1

HMS81C4x60

4. PACKAGE DIAGRAM

52

27

0 ~ 15

HYNIX

HMS81C4260

26

1

0.25 0.05

45.97 0.13

0.76 0.13

UNIT: mm

0.47 0.13

1.02 0.25

1.778 0.25

32

17

HYNIX

HMS81C4360

UNIT: inch

TYP 0.600 BSC

16

1

1.665

1.645

0.550

0.530

MIN 0.015

0.140

0.120

0.022

0.015

0 ~ 15°

0.1 BSC

0.065

0.045

November 2001 Ver 1.1

7

HMS81C4x60

42

22

0 ~ 15

HYNIX

HMS81C4460

21

1

0.25 0.05

36.83 0.13

0.76 0.13

UNIT: mm

0.47 0.13

1.02 0.25

1.778 0.25

32

17

0 ~ 15

HYNIX

HMS81C4360SK

16

1

0.25 0.05

27.68 0.13

0.76 0.13

UNIT: mm

0.47 0.13

1.02 0.25

1.778 0.25

Figure 4-1 Package Diagram

8

November 2001 Ver 1.1

HMS81C4x60

5. PIN FUNCTION

V_DD: Supply voltage.

R30~R37: R3 is 8-bit CMOS bidirectional I/O port. R0

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

V

_SS: Circuit ground.

TEST: Used for shipping inspection of the IC. For normal

operation, it should not be connected .

In addition, R3 serves the functions of the various follow-

ing special features.

RESET: Reset the MCU.

Port pin

Alternate function

X

_IN: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

R30

R31

R32

R33

R34

R35

PWM0 (Pulse Width Modulation output 0)

PWM1 (Pulse Width Modulation output 1)

PWM2 (Pulse Width Modulation output 2)

PWM3 (Pulse Width Modulation output 3)

PWM4 (Pulse Width Modulation output 4)

PWM5 (Pulse Width Modulation output 5)

with 14bit resolution

X

_OUT: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit bidirectional I/O port. R0 pins 1

or 0 written to the Port Direction Register can be used as

outputs or inputs.

R10~R14: R1 is a 5-bit read only port. R1 pins 1 or 0 writ-

ten to the Port Direction Register can be used as inputs.

R36

R37

BUZ (Buzzer output)

TMR1 (Timer Interrupt 1)

In addition, R1 serves the functions of the various follow-

ing special features.

R40~R43: R4 is a 4-bit open drain I/O port. Each pins 1 or

0 written to the their Port Direction Register can be used as

outputs or inputs.

Port pin

Alternate function

In addition, R4 serves the functions of the various follow-

ing special features.

R10

R11

R12

R13

R14

AD0 (A/D converter input 0)

AD1 (A/D converter input 1)

AD2 (A/D converter input 2)

AD3 (A/D converter input 3)

AD4 (A/D converter input 4)

Port pin

Alternate function

SCL0 (I²C Clock 0)

R40

R41

R42

R43

SDA0 (I²C Data0)

SCL1 (I²C Clock 1)

SDA1 (I²C Data 1)

R20~R25: R2 is a 6-bit CMOS bidirectional I/O port. Each

pins 1 or 0 written to the their Port Direction Register can

be used as outputs or inputs.

In addition, R2 serves the functions of the various follow-

ing special features.

R,G,B: R,G,B are output port. Each pins controls Red,

Green, Blue color control.

YM,YS: YM,YS are CMOS output port. Each pins con-

trols Background, Edge control.

Port pin

Alternate function

R21

R22

R23

R24

R25

INT1 (External interrupt input 1)

INT2 (External interrupt input 2)

INT3 (External interrupt input 3)

EC2 (Event counter input 2)

EC3 (Event counter input 3)

HS,VS: HS,VS are CMOS input port. Each pins Vertical

Sync. input and Horizaltal Sync. inputs.

CVBS: CVBS is a CVBS(Composit Video in) signal input

pin.

PIN NAME

V_DD

V_SS

Pin No.

In/Out

Function

9,13,30,

37

-

Supply voltage

Circuit ground

Table 5-1 Port Function Description

14,29,

36,43

-

November 2001 Ver 1.1

9

HMS81C4x60

PIN NAME

TEST

Pin No.

44

33

35

34

19

20

38

39

40

41

42

52

51

50

49

48

47

46

45

1

In/Out

I

Function

TEST signal input (internal pull up resister)

Reset signal input

RESET

X_IN

I

Main oscillation input

X_OUT

O

Main oscillation output

HS

I

Horisontal Sync. input

VS

I

Vertical Sync. input

Red signal output

Green signal output

Blue signal output

Edge signal output

Background signal output

8bit PWM (pull up)

8bit PWM

R

O

G

O

B

O

YS

O

YM

O

R30/PWM0

R31/PWM1

R32/PWM2

R33/PWM3

R34/PWM4

R35/PWM5

R36/BUZ

R37/TMR1

R40/SCL0

I/O

PWM functions

14bit PWM

Buzzer (pull up)

Timer Interrupt 1

I²C Serial clock 0

I²C Serial data 0

I²C Serial clock 1

R41/SDA0

R42/SCL1

2

3

I/O

I²C functions (open drain)

I²C Serial data 1

R43/SDA1

R20

4

I/O

21

22

23

24

25

26

(pull up)

R21/INT1

R22/INT2

R23/INT3

R24/EC2

R25/EC3

External interrupt input 1

External interrupt input 2 (pull up)

External interrupt input 3

Event counter input 2

Event counter input 3 (pull up)

External interrupt functions

Data slicer comparation reference

voltage

SCAP

11

I

R10/AD0

R11/AD1

R12/AD2

R13/AD3

R14/AD4

CVBS

15

16

17

18

10

12

I

Analog input 0

Analog input 1

Analog input 2

Analog input 3

Analog input 4

Composit video input

A/D conversion functions

Table 5-1 Port Function Description

10

November 2001 Ver 1.1

HMS81C4x60

PIN NAME

R00

Pin No.

In/Out

I/O

Function

(normal I/O, pull up)

27

28

31

32

5

R01

R02

R03

R04

R05

R06

R07

I/O

(normal I/O, pull up)

(normal I/O)

I/O

(normal I/O, pull up)

(open drain, pull up)

Digital I/O functions

I/O

6

I/O

7

I/O

8

I/O

Table 5-1 Port Function Description

November 2001 Ver 1.1

11

HMS81C4x60

6. PORT STRUCTURES

X_IN, X_OUT

R14~10, CVBS

V_DD

I

Data out

Out Enable

X_IN

V_DD

V_SS

Data in

X_OUT

Schmitt

STOP

Analog in

V_SS

Main frequency

clock

R03~R00,R37~R30,HS,VS,YS,YM

R07~R04, R43~R40, TEST

V_DD

I/O

Data out

Out Enable

V_SS

Data in

Schmitt

12

November 2001 Ver 1.1

HMS81C4x60

R,G,B

SCAP

V_DD

I/O

Data In

V_SS

V_DD

I/O

V_SS

R25~R20, RESET

V_DD

I/O

Data out

Out Enable

V_SS

Data in

Noise Filter

Schmitt

November 2001 Ver 1.1

13

HMS81C4x60

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage........................................... -0.3 to +6.0 V

Storage Temperature ................................-40 to +125 °C

Maximum current (ΣI_OL)....................................100 mA

Maximum current (ΣI_OH)......................................80 mA

Voltage on any pin with respect to Ground (V_SS

)

Note: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of

the device at any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

............................................................... -0.3 to V_DD+0.3

Maximum current out of Vss pin.........................160 mA

Maximum current into V_DDpin ..........................160 mA

Maximum current sunk by(I_OLper I/O Pin) .........20 mA

Maximum output current sourced by (I_OHper I/O Pin)

.................................................................................8 mA

7.2 Recommended Operating Conditions

Specifications

Unit

Parameter

Supply Voltage

Symbol

Condition

Min.

4.5

-

Max.

V_DD

f_XIN

V_DD=4.5~5.5V

f_XIN=4MHz

5.5

V

Operating Frequency

4.0(typical)

70

MHz

°C

T_OPR

Operating Temperature

-10

7.3 DC Electrical Characteristics

(T_A=-10~70°C, V_DD=4.5~5.5V),

Specifications

Typ.

Parameter

Symbol

Condition

Unit

Min.

Max.

TEST, RESET, Xin, R0, R1, R2, R3,

HS, VS

V_IH

V_IL

0.8 V_DD

V_DD

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

-

V

TEST, RESET, Xin, R0, R1, R2, R3,R4

HS, VS

0.12 V_DD

0

-

I_OH= -5mA

R0, R1, R2, R3, YS, YM

V_OH

V_OL

I_DD

V_DD- 1

-

V

I_OL= 5mA

R0, R1, R2, R4

-

1.0

80

v

Supply current in

ACTIVE mode

V_DD

-

40

mA

V_DD= 5.5v, V_PIN= 0.4V

TEST, R00, R01, R03, R04, R05, R06,

R07, R20, R22, R25, R30, R31, R32, R33

R36

I_RUP

pull-up lekage current

-1.5

-5

-400

5

µA

V_DD= 5.5V_,V_PIN= V_DD

All input, I/O pins except X_IN

High input leakage

current

I_IZH

-

14

November 2001 Ver 1.1

HMS81C4x60

Specifications

Typ.

Parameter

Symbol

Condition

V_DD= 5.5V_,V_PIN= 0V

Unit

Min.

Max.

Low input leakage

current

I_IZL

-5

-

5

-

µA

V

All input, I/O pins except X_IN, OSC1

RAM data retention

voltage

V_RAM

V_DD

1.2

1.0

1.2

-

Vt+ ~

Vt-

TEST, RESET, Xin, HS, VS, R07 ~ R00,

R21, R23, R24, R25, R37 ~ R30

Hysterisis

-

V

V_DD= 5V

CVBS pin

Comparator operating

range

V_rCVBS

V_aCVBS

RGB_R1

3.5

0.08

5

V

V_DD= 5V

CVBS pin

Comparator resolution

V

V_DD= 5V

No in/out current in R,G,B pin

RGB DAC

Resolution 1

-

%

RGB DAC On

No in/out current in R,G,B pin

3/40V_dd

5/40V_dd

Level 0

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

8/40V_dd

RGB DAC

Output voltage

V_RGB

V

12/40V_dd

17/40V_dd

23/40V_dd

30/40V_dd

38/40V_dd

V_DD= 5V

RGB DAC On

Level 7

I_OH= -3mA

RGB V_oh

RGB V_ol

V_ohrgb

3.1

0.4

3.5

0.6

3.9

0.8

V

V_DD= 5V

RGB DAC On

Level 0

V_olrgb

I_OL= 3mA

7.4 AC Characteristics

(T_A=-10~70°C, V_DD=5V±10%, V_SS=0V)

Specifications

Parameter

Symbol

Pins

Unit

Min.

3

Typ.

Max.

f_XIN

X_IN

Crystal oscillator Frequency

External Clock Pulse Width

4

-

5

MHz

nS

t_MCPW

t_SCPW

t_{MRCP, MFCP}

_SRCP,t_SFCP

180

0.5

-

350

S_CLK

X_IN

-

µS

t

-

20

nS

External Clock Transition Time

t

S_CLK

-

nS

November 2001 Ver 1.1

15

HMS81C4x60

Specifications

Parameter

Symbol

Pins

Unit

Min.

Typ.

Max.

t_ST

t_IW

X_IN, X_OUT

INT1~3

Oscillation Stabilizing Time

Interrupt Pulse Width

RESET Input Width

-

20

-

mS

1

2

8

t_SYS

1

t_RST

RESET

-

t_SYS

Event Counter Input Pulse

Width

1

t_ECW

EC2, EC3

2

-

t_SYS

nS

t_{REC, FEC}

t

Event Counter Transition Time

20

1. t

is one of 1/f

main clock operation mode,

XIN

SYS

t_MCPW

1/f_XIN

V_DD-0.5V

X_IN

0.5V

t_MRCP

t_MFCP

t_IW

INT1 ~ 3

0.8V_DD

0.2V_DD

t_RST

RESET

0.2V_DD

t_ECW

0.8V_DD

EC2, EC3

0.2V_DD

t_REC

t_FEC

Figure 7-1 Timing Chart

16

November 2001 Ver 1.1

HMS81C4x60

7.5 A/D Converter Characteristics

(TA=25°C, V_DD=5V, V_SS=0V)

Specifications

Typ.

Parameter

Symbol

Condition

Unit

Min.

Max.

V_AN

CAIN

V_SS-0.3

V_DD+0.3

±2.5

±2.0

±1.0

±2.0

15

Analog Input Voltage Range

Overall Accuracy

-

V

-

±1.5

±0.5

±0.75

±1.5

-

Non Linearity Error

Differential Non Linearity Error

Zero Offset Error

NNLE

NDNLE

NZOE

NFSE

NGE

-

LSB

µS

-

Full Scale Error

-

Gain Error

-

f

_MAIN=4MHz

Conversion Time

TCONV

November 2001 Ver 1.1

17

HMS81C4x60

7.6 Typical Characteristics

These graphs and tables are for design guidance only and

are not tested or guaranteed.

The data is a statistical summary of data collected on units

from different lots over a period of time. “Typical” repre-

sents the mean of the distribution while “max” or “min”

represents (mean + 3σ) and (mean − 3σ) respectively

where σ is standard deviation

In some graphs or tables, the datas presented are out-

side specified operating range (e.g. outside specified

V_DDrange). This is for information only and devices

are guaranteed to operate properly only within the

specified range.

I_OH−V_OH, V_DD=5.2V

I_OL−V_OL, V_DD=5.2V

I_OL

I_OH

(mA)

40

°

-20 C

(mA)

-16

-20°C

25°C

70°C

-14

-12

-10

-8

30

20

10

-6

-4

-2

0

V_OH

5.0 (V)

V_OL

(V)

2.0

3.0

4.0

1.0

2.0

3.0

4.0

V

_DD−V_IH

V

_DD−V_IH

Hysterisis

V_IH1

(V)

V_IH2

(V)

f_MAIN=4MHz

Ta=25°C

f_MAIN=4MHz

Ta=25 C

°

4

3

2

3

2

1

0

1

0

V_DD

(V)

V_DD

(V)

4

4.5

6

4

4.5

6

5

5.5

5

5.5

18

November 2001 Ver 1.1

HMS81C4x60

V

_DD−V_IL

V

_DD−V_IL

Hysterisis

V_IL1

(V)

V_IL1

(V)

f_MAIN=4MHz

Ta=25 C

f_MAIN=4MHz

Ta=25 C

°

3

2

1

2

1

V_DD

(V)

V_DD

(V)

4

4.5

6

5

5.5

4

4.5

6

5

5.5

Operating Area

Normal Mode (Main opr.)

_DD1−V_DD

I

f_MAIN

I_DD

Ta= -20~70 C

°

(MHz)

6

Ta=25 C

°

(Main-clock)

(mA)

f_MAIN=4MHz

60

5

4

3

2

50

40

30

20

1

0

V_DD

6.5

V_DD

(V)

4

4.5

5

5.5

6

(V)

4

4.5

5

5.5

6

November 2001 Ver 1.1

19

HMS81C4x60

8. MEMORY ORGANIZATION

The GMS81C4x60 has separate address spaces for Pro-

gram memory, Data Memory and Display memory. Pro-

gram memory can only be read, not written to. It can be up

to 60K bytes of Program memory. Data memory can be

read and written to up to 1024 bytes including the stack ar-

ea. Font memory has prepared 32K bytes for OSD.

8.1 Registers

This device has six registers that are the Program Counter

(PC), a Accumulator (A), two index registers (X, Y), the

Stack Pointer (SP), and the Program Status Word (PSW).

The Program Counter consists of 16-bit register.

Generally, SP is automatically updated when a subroutine

call is executed or an interrupt is accepted. However, if it

is used in excess of the stack area permitted by the data

memory allocating configuration, the user-processed data

may be lost.

ACCUMULATOR

X REGISTER

A

X

The stack can be located at any position within 00_Hto FF_H

of the internal data memory. The SP is not initialized by

hardware, requiring to write the initial value (the location

with which the use of the stack starts) by using the initial-

ization routine. Normally, the initial value of “FF_H”is

used.

Y

Y REGISTER

SP

STACK POINTER

PCH

PCL

PROGRAM COUNTER

Stack Address (00_H~ FF_H)

PROGRAM STATUS

WORD

PSW

15

8

7

0

1

SP

Figure 8-1 Configuration of Registers

Hardware fixed

Accumulator: The Accumulator is the 8-bit general pur-

pose register, used for data operation such as transfer, tem-

porary saving, and conditional judgement, etc.

Caution:

The Stack Pointer must be initialized by software be-

cause its value is undefined after RESET.

The Accumulator can be used as a 16-bit register with Y

Register as shown below.

Example: To initialize the SP

Y

LDX

TXSP

#0FFH

; SP ← FF_H

Y

A

Program Counter: The Program Counter is a 16-bit wide

which consists of two 8-bit registers, PCH and PCL. This

counter indicates the address of the next instruction to be

executed. In reset state, the program counter has reset rou-

tine address (PC_H:0FF_H, PC_L:0FE_H).

Two 8-bit Registers can be used as a “YA” 16-bit Register

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these

index registers, the register contents are added to the spec-

ified address, which becomes the actual address. These

modes are extremely effective for referencing subroutine

tables and memory tables. The index registers also have in-

crement, decrement, comparison and data transfer func-

tions, and they can be used as simple accumulators.

Program Status Word: The Program Status Word (PSW)

contains several bits that reflect the current state of the

CPU. The PSW is described in Figure 8-3. It contains the

Negative flag, the Overflow flag, the Break flag the Half

Carry (for BCD operation), the Interrupt enable flag, the

Zero flag, and the Carry flag.

[Carry flag C]

Stack Pointer: The Stack Pointer is an 8-bit register used

for occurrence interrupts and calling out subroutines. Stack

Pointer identifies the location in the stack to be accessed

(save or restore).

This flag stores any carry or borrow from the ALU of CPU

after an arithmetic operation and is also changed by the

Shift Instruction or Rotate Instruction.

20

November 2001 Ver 1.1

HMS81C4x60

[Zero flag Z]

or data transfer is “0” and is cleared by any other result.

This flag is set when the result of an arithmetic operation

MSB

LSB

N

V

G

B

H

I

Z

C

RESET VALUE : 00_H

CARRY FLAG RECEIVES

PSW

NEGATIVE FLAG

CARRY OUT

OVERFLOW FLAG

ZERO FLAG

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

INTERRUPT ENABLE FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

BRK FLAG

ADDITION OPERLANDS

Figure 8-3 PSW (Program Status Word) Register

This flag assigns RAM page for direct addressing mode. In

[Interrupt disable flag I]

the direct addressing mode, addressing area is from zero

page 00_Hto 0FF_Hwhen this flag is "0". If it is set to "1",

addressing area is assigned by RPR register (address

0F3_H). It is set by SETG instruction and cleared by CLRG.

This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All inter-

rupts are disabled when cleared to “0”. This flag immedi-

ately becomes “0” when an interrupt is served. It is set by

the EI instruction and cleared by the DI instruction.

[Overflow flag V]

[Half carry flag H]

This flag is set to “1” when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow

occurs when the result of an addition or subtraction ex-

ceeds +127 (7F_H) or −128 (80_H). The CLRV instruction

clears the overflow flag. There is no set instruction. When

the BIT instruction is executed, bit 6 of memory is copied

to this flag.

After operation, this is set when there is a carry from bit 3

of ALU or there is no borrow from bit 4 of ALU. This bit

can not be set or cleared except CLRV instruction with

Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector ad-

dress.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT in-

struction is executed, bit 7 of memory is copied to this flag.

[Direct page flag G]

November 2001 Ver 1.1

21

HMS81C4x60

At execution of a

CALL/TCALL/PCALL

At acceptance

of interrupt

At execution

of RET instruction

At execution

of RETI instruction

01BC

01BD

01BE

01BC

01BD

01BE

01BC

01BD

01BE

PSW

01BD

01BE

01BF

Push

down

Push

down

Pop

up

PCL

PCH

PCL

PCH

PCL

PCH

Pop

up

PCH

01BF

SP before

execution

01BF

01BD

01BF

01BC

01BD

01BF

01BC

01BF

SP after

execution

At execution

of PUSH instruction

PUSH A (X,Y,PSW)

of POP instruction

POP A (X,Y,PSW)

01BC

0100_H

Stack

depth

01BD

01BE

01BD

01BE

Push

down

Pop

up

A

01BF

01BF_H

SP before

01BF

01BE

01BF

execution

SP after

execution

Figure 8-4 Stack Operation

22

November 2001 Ver 1.1

HMS81C4x60

8.2 Program Memory

A 16-bit program counter is capable of addressing up to

64K bytes, but this device has 60K bytes program memory

space only physically implemented. Accessing a location

above FFFF_Hwill cause a wrap-around to 0000_H.

Example: Usage of TCALL

LDA

#5

1BYTE INSTRUCTION

TCALL 15

;

INSTEAD OF 2 BYTES

NORMAL CALL

:

Figure 8-5 shows a map of Program Memory. After reset,

the CPU begins execution from reset vector which is stored

in address FFFE_Hand FFFF_Has shown in Figure 8-6.

;

;TABLE CALL ROUTINE

;

FUNC_A: LDA

LRG0

RET

As shown in Figure 8-5, each area is assigned a fixed loca-

tion in Program Memory. Program Memory area contains

the user program.

;

FUNC_B: LDA

LRG1

2

1

RET

;

;TABLE CALL ADD. AREA

;

1000_H

TCALL ADDRESS AREA

;

ORG

DW

0FFC0H

FUNC_A

FUNC_B

DW

The interrupt causes the CPU to jump to specific location,

where it commences the execution of the service routine.

The External interrupt 1, for example, is assigned to loca-

tion 0FFF8_H. The interrupt service locations spaces 2-byte

interval: 0FFF6_Hand 0FFF7_Hfor External Interrupt 2,

0FFE8_Hand 0FFE9_Hfor External Interrupt 3, etc.

PROGRAM

MEMORY

FEFF_H

FF00_H

FFC0_H

TCALL

AREA

PCALL

AREA

FFDF_H

FFE0_H

INTERRUPT

VECTOR AREA

Any area from 0FF00_Hto 0FFFF_H, if it is not going to be

used, its service location is available as general purpose

Program Memory.

FFFF_H

Address

Vector Area Memory

Figure 8-5 Program Memory Map

I²C Bus Interface Interrupt Vector

-

0FFE0_H

E2

Page Call (PCALL) area contains subroutine program to

reduce program byte length by using 2 bytes PCALL in-

stead of 3 bytes CALL instruction. If it is frequently called,

it is more useful to save program byte length.

E4

Basic Interval Timer Interrupt Vector

Watchdog Timer Interrupt Vector

External Interrupt 3/4 Vector

E6

E8

EA

Timer/Counter 3 Interrupt Vector

Timer/Counter 1 Interrupt Vector

V-Sync Interrupt Vector

Table Call (TCALL) causes the CPU to jump to each

TCALL address, where it commences the execution of the

service routine. The Table Call service area spaces 2-byte

for every TCALL: 0FFC0_Hfor TCALL15, 0FFC2_Hfor

TCALL14, etc., as shown in Figure 8-7.

EC

EE

F0

Slicer Interrupt Vector

F2

F4

F6

F8

FA

FC

FE

Timer/Counter 2 Interrupt Vector

Timer/Counter 0 Interrupt Vector

External Interrupt 2 Vector

External Interrupt 1 Vector

On Screen Display Interrupt Vector

-

RESET Vector

NOTE:

"-" means reserved area.

Figure 8-6 Interrupt Vector Area

November 2001 Ver 1.1

23

HMS81C4x60

Address

Program Memory

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

0FFC0_H

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

Address

0FF00_H

PCALL Area Memory

PCALL Area

(256 Bytes)

TCALL 8

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

TCALL 7

TCALL 6

TCALL 5

TCALL 4

0FFFF_H

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

NOTE:

* means that the BRK software interrupt is using

same address with TCALL0.

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel

TCALL→ n

4F35

PCALL 35_H

4A

TCALL 4

4A

01001010

4F

35

Reverse

~

PC:

11111111

F_HF_H

11010110

D_H6_H

~

0FF00_H

~

0FF00_H

0FF35_H

Ã

À

0FFD7_H

25

0FFFF_H

D1

Ã : index address

0FFFF_H

24

November 2001 Ver 1.1

HMS81C4x60

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

DW

I2C_INT

NOT_USED

BIT_INT

WDT_INT

IR_INT

TIMER3

TIMER1

VSYNC_INT

SLICE_INT

T2_INT

T0_INT

EXT2_INT

EXT1_INT

OSD_INT

NOT_USED

RESET

ORG

0F000H

;********************************************

;

MAIN

PROGRAM

*

;********************************************

;

RESET:

DI

;Disable All Interrupts

CLRG

LDX

#0

RAM_CLR: LDA

;RAM Clear(!0000_H->!00BF_H)

STA

{X}+

#0C0H

RAM_CLR

CMPX

BNE

;

LDX

TXSP

;

#0FFH

;Stack Pointer Initialize

;16MHz system clock

LDM

PLLC,#0000_0101b

;

LDM

:

R0, #0FFh

R0DIR,#0FFh

;Normal Port 0

;Normal Port Direction

:

LDM

:

TM0,#0000_0000B

VRAM_CLR

;timer stop

;Clear VRAM

:

CALL

:

November 2001 Ver 1.1

25

HMS81C4x60

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-

ble. Data Memory is divided into four groups, a user RAM,

control registers, Stack, and OSD memory.

in each peripheral section.

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write instruc-

tion. Use byte manipulation instruction.

0000H

RAM (192 bytes)

Page0

00C0H

Peripheral Reg. (64 bytes)

0100H

Example; To write at CKCTLR

RAM (256 bytes)

Page1

Stack area

LDM

CKCTLR,#05H;Divide ratio ÷ 8

0200H

RAM (256 bytes)

Page2

Page3

Stack Area

0300H

The stack provides the area where the return address is

saved before a jump is performed during the processing

routine at the execution of a subroutine call instruction or

the acceptance of an interrupt.

0400H

0440H

RAM (64 bytes)

NOT USED

Page4

0500H

NOT USED

Page5

Page6

When returning from the processing routine, executing the

subroutine return instruction [RET] restores the contents of

the program counter from the stack; executing the interrupt

return instruction [RETI] restores the contents of the pro-

gram counter and flags.

0600H

RAM (Slicer RAM)

( 256 Byte)

0700H

0A00H

Not Used

OSD RAM (192 bytes)

PageA

PageB

The save/restore locations in the stack are determined by

the stack pointed (SP). The SP is automatically decreased

after the saving, and increased before the restoring. This

means the value of the SP indicates the stack location

number for the next save. Refer to Figure 8-4 on page 22.

0AC0H

0B00H

Peripheral Reg. (32 bytes)

OSD RAM (192 bytes)

0BC0H

0C00H

Peripheral Reg. (32 bytes)

NOT USED

0FFFH

Addressin

g mode

Address

Symbol

R/W Reset Value

00C0H

00C1H

00C2H

00C3H

00C4H

00C5H

00C6H

00C7H

00C8H

00C9H

00CAH

00CBH

00CCH

00CDH

00CEH

00CFH

R0

R0DD

R1

R1DD

R2

R2DD

R3

R3DD

R4

R4DD

reserved

FUNC

PLLC

R/W ???????? byte, bit¹

Figure 8-8 Data Memory Map

User Memory

byte²

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

-

W

R

W

00000000

????????

---00000

R/W ????????

--000000

R/W ????????

00000000

R/W ????????

The GMS81C4x60 has 1,024 × 8 bits for the user memory

(RAM) except Peripheral Reg. (64 bytes) .

W

Control Registers

The control registers are used by the CPU and Peripheral

function blocks for controlling the desired operation of the

device. Therefore these registers contain control and status

bits for the interrupt system, the timer/ counters, analog to

digital converters and I/O ports. The control registers are in

address range of 0C0_Hto 0FF_H.

W

-

----0000

-

W

0000000-

-0000000

byte

Note that unoccupied addresses may not be implemented

on the chip. Read accesses to these addresses will in gen-

eral return random data, and write accesses will have an in-

determinate effect.

Table 8-1Control registers

More detailed informations of each register are explained

26

November 2001 Ver 1.1

HMS81C4x60

0D0H

0D1H

0D2H

0D3H

0D4H

0D5H

0D6H

0D7H

0D8H

0D9H

0DAH

0DBH

0DCH

0DEH

0DFH

TM0

TM2

TDR0

TDR1

TDR2

TDR3

BITR

CKCTLR

WDTR

ICAR

ICDR

ICSR

ICCR

reserved

R/W -0000000

R/W ????????

byte

0AD0

0AD1

0AD2

0AD3

0AD4

0AD5

0AD6

0AD7

0AD8

0AD9

0ADA

0ADB

0ADC

0ADD

0ADE

0ADF

RED0

RED1

RED2

GREEN0

GREEN1

GREEN2

BLUE0

W

-

???????? byte, bit-

????????

byte, bit

byte

????????

byte, bit

????????

byte, bit

????????

byte, bit

????????

byte, bit

R

W

????????

--010111

-0111111

????????

byte, bit

byte

BLUE1

BLUE2

????????

byte, bit

????????

byte, bit

R/W 00000000

R/W 11111111

R/W 0001000-

R/W 00000000

byte, bit

-

reserved

-

0E0H

0E1H

0E2H

0E3H

0E4H

0E5H

0E6H

0E7H

0E8H

0E9H

0EAH

0EBH

0ECH

0EDH

0EEH

0EFH

PWMR0

PWMR1

PWMR2

PWMR3

PWMR4

PWMR5H

PWMR5L

reserved

PWMCR1

PWMCR2

reserved

AIPS

W

????????

byte

byte, bit

0AE0H OSDCON1 R/W 00000000

0AE1H OSDCON2 R/W 00000000

byte, bit

byte

byte, bit

byte

byte, bit

byte

0AE2H OSDCON3

0AE3H FDWSET

0AE4H EDGECOL

W

R

W

R

W

R

00000000

01111010

10000111

????????

---00000

????????

00000000

--000000

??????-?

---?????

????????

---?????

????????

R/W ????????

R/W --??????

-

R/W 00000000

R/W -----000

-

0AE5H

0AE6H

0AE7H

0AE8H

0AE9H

0AEAH

0AEBH

0AECH

0AEDH

0AEEH

0AEFH

0AF0H

0AF1H

0AF2H

0AF3H

0AF4H

0AF5H

0AF9H

CHEDCL

OSDLN

LHPOS

DLLMOD

DLLTST

L1ATTR

L1EATR

L1VPOS

L2ATTR

L2EATR

L2VPOS

WINSH

WINSY

WINEH

WINEY

VCNT

-

byte, bit

-

W

--000000

byte

0F0H

0F1H

0F2H

0F3H

0F4H

0F5H

0F6H

0F7H

0F8H

0F9H

0FAH

0FBH

0FCH

0FDH

0FEH

0FFH

ADCM

ADR

IEDS

IMOD

IENL

IRQL

R/W ????????

R

W

R/W --000000

R/W 00000000

byte, bit

byte

byte, bit

-

byte, bit

byte

byte, bit

byte

????????

--000000

HCNT

CULTAD

R

W

byte

IENH

IRQH

reversed

IDCR

IDFS

IDR

DPGR

TMR

reserved

0BE0H

0BE1H

0BE2H

0BE3H

0BE4H

0BE7H

0BE8H

SLCON

SLINF0

SLINF1

RIKST

RIKED

SNCST

SNCED

R/W 00000000

byte, bit

byte

-

W

00000000

????????

R/W 0000-000

R

R/W ----0000

W

-

1----001

????????

byte

-

Table 8-1Control registers

1. "byte, bit" means that register can be addressed by not only bit

but byte manipulation instruction.

Table 8-1Control registers

2. "byte" means that register can be addressed by only byte

manipulation instruction. On the other hand, do not use any

read-modify-write instruction such as bit manipulation for clear-

ing bit.

November 2001 Ver 1.1

27

HMS81C4x60

8.4 Addressing Mode

The GMS81C4x60 uses six addressing modes;

• Register addressing

(3) Direct Page Addressing → dp

In this mode, a address is specified within direct page.

Example; G=0

• Immediate addressing

• Direct page addressing

• Absolute addressing

E551: C535 LDA

35_H

;A ←RAM[35_H]

• Indexed addressing

35_H

data

• Register-indirect addressing

À

~

data → A

þ

(1) Register Addressing

0E550_H

0E551_H

C5

35

Register addressing accesses the A, X, Y, C and PSW.

þ : direct page

(2) Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data

immediately.

(4) Absolute Addressing → !abs

Example:

Absolute addressing sets corresponding memory data to

Data, i.e. second byte (Operand I) of command becomes

lower level address and third byte (Operand II) becomes

upper level address.

FE0435 ADC

#35_H

MEMORY

With 3 bytes command, it is possible to access to whole

memory area.

04

35

A+35_H+C → A

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,

LDY, OR, SBC, STA, STX, STY

Example;

F100: 0735F0 ADC !0F035_H;A ←ROM[0F035_H]

When G-flag is 1, then RAM address is defined by 16-bit

address which is composed of 8-bit RAM paging register

(RPR) and 8-bit immediate data.

Example: G=1, RPR=01_H

0F035_H

data

À

E45535 LDM

35_H,#55_H

~

A+data+C → A

þ

0F100_H

0F101_H

0F102_H

07

35

F0

address: 0F035

0135_H

data

data ← 55_H

~

þ

À

0F100_H

E4

55

35

0F101_H

0F102_H

28

November 2001 Ver 1.1

HMS81C4x60

The operation within data memory (RAM)

ASL, BIT, DEC, INC, LSR, ROL, ROR

X indexed direct page, auto increment→ {X}+

In this mode, a address is specified within direct page by

the X register and the content of X is increased by 1.

Example; Addressing accesses the address 0135_Hregard-

less of G-flag and RPR.

LDA, STA

F100: 981501 INC !0115_H;A ←ROM[115_H]

Example; G=0, X=35_H

F100: DB LDA

{X}+

115_H

data

Ã

À

~

35_H

~

data

DB

À

data+1 → data

data → A

36H → X

0F100_H

0F101_H

0F102_H

~

98

15

01

þ

address: 0115

(5) Indexed Addressing

X indexed direct page (8 bit offset) → dp+X

X indexed direct page (no offset) → {X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15_H, G=1, RPR=01_H

This address value is the second byte (Operand) of com-

mand plus the data of -register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA

STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

E550: D4 LDA {X}

;ACC←RAM[X].

Example; G=0, X=0F5_H

E550: C645 LDA 45_H+X

115_H

data

D4

À

data → A

~

3A_H

data

þ

Ã

0E550_H

data → A

~

À

~

0E550_H

0E551_H

C6

45

þ

45_H+0F5_H=13A_H

November 2001 Ver 1.1

29

HMS81C4x60

FA00: 3F35 JMP [35_H]

Y indexed direct page (8 bit offset) → dp+Y

This address value is the second byte (Operand) of com-

mand plus the data of Y-register, which assigns Memory in

Direct page.

35_H

36_H

0A

E3

This is same with above (2). Use Y register instead of X.

À ^{jump to address 0E30A}

H

Y indexed absolute → !abs+Y

~

Sets the value of 16-bit absolute address plus Y-register

data as Memory. This addressing mode can specify mem-

ory in whole area.

0E30A_H

0FA00_H

~

þ

Example; Y=55_H

3F

35

F100: D500FA LDA !0FA00_H+Y

0F100_H

0F101_H

0F102_H

D5

00

FA

þ

X indexed indirect → [dp+X]

0FA00_H+55_H=0FA55_H

Processes memory data as Data, assigned by 16-bit pair

memory which is determined by pair data

[dp+X+1][dp+X] Operand plus X-register data in Direct

page.

~

À

0FA55_H

data

data → A

Ã

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10_H

FA00: 1625 ADC [25_H+X]

(6) Indirect Addressing

Direct page indirect → [dp]

35_H

36_H

05

Assigns data address to use for accomplishing command

which sets memory data (or pair memory) by Operand.

Also index can be used with Index register X,Y.

E0

0E005_H

À

~

25 + X(10) = 35_H

þ

0E005_H

0FA00_H

data

JMP, CALL

~

Example; G=0

16

25

Ã ^{A + data + C → A}

30

November 2001 Ver 1.1

HMS81C4x60

Y indexed indirect → [dp]+Y

Absolute indirect → [!abs]

Processes memory data as Data, assigned by the data

[dp+1][dp] of 16-bit pair memory paired by Operand in Di-

rect page plus Y-register data.

The program jumps to address specified by 16-bit absolute

address.

JMP

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10_H

Example; G=0

FA00: 1F25E0 JMP [!0E025_H]

FA00: 1725 ADC [25_H]+Y

PROGRAM MEMORY

0E025_H

0E026_H

25

E7

25_H

26_H

05

E0

jump to

address 0E725_H

À

0E005_H+ Y(10) = 0E015_H

À

~

þ

0E725_H

0FA00_H

data

þ

~

1F

17

25

A + data + C → A

Ã

E0

November 2001 Ver 1.1

31

HMS81C4x60

9. I/O PORTS

The HMS81C4x60 has 5 ports (R0, R1, R2, R3 and R4)

and OSD ports (R,G,B,YS,YM). These ports pins may be

multiplexed with an alternatefunction for the peripheral

features on the device. In general, in an initial reset state,

R ports are used as a general purpose digital port.

9.1 Registers for Port

Port Data Registers

ister) during initial setting as shown in Figure 9-1.

The Port Data Registers (R0, R1, R2, R3, R4) are repre-

sented as a D-Type flip-flop, which will clock in a value

from the internal bus in response to a “write to data regis-

ter” signal from the CPU. The Q output of the flip-flop is

placed on the internal bus in response to a “read data reg-

ister” signal from the CPU. The level of the port pin itself

is placed on the internal bus in response to “read data reg-

ister” signal from the CPU. Some instructions that read a

port activating the “read register” signal, and others acti-

vating the “read pin” signal.

All the port direction registers in the HMS81C4x60 have

been written to zero by reset function. On the other hand,

its initial status is input.

WRITE “55_H” TO PORT R0 DIRECTION REGISTER

0C0_H

0C1_H

BIT

R0 DATA

0

7

1

6

0

5

1

4

0

3

1

2

0

1

0

R0 DIRECTION

~

0

7

1

6

0

5

1

4

0

3

1

2

0

1

0

Port Direction Registers

0C8_H

0C9_H

R4 DATA

All pins have data direction registers which can define

these ports as output or input. A “1” in the port direction

register configure the corresponding port pin as output.

Conversely, write “0” to the corresponding bit to specify it

as input pin. For example, to use the even numbered bit of

R0 as output ports and the odd numbered bits as input

ports, write “55_H” to address 0C1_H(R0 port direction reg-

R4 DIRECTION

I

O

6

I

O

4

I

O

2

I

O

0

PORT

7

5

3

1

I : INPUT PORT

O : OUTPUT PORT

Figure 9-1 Example of port I/O assignment

32

November 2001 Ver 1.1

HMS81C4x60

9.2 I/O Ports Configuration

R0 Ports

functions as following table.

R07 ~ R04 is an open drain bidirectional I/O port and R03

~ R00 is a CMOS bidirectional I/O port(address 0C0_H).

Each I/O pin can independently used as an input or an out-

put through the R0DD register (address 0C1_H).

Port Pin

Alternate Function

R10

R11

R12

R13

R14

AN0 (A/D input 0)

AN1 (A/D input 1)

AN2 (A/D input 2)

AN3 (A/D input 3)

AN4 (A/D input 4)

The control registers for R0 are shown below.

ADDRESS : 00C0_H

RESET VALUE : Undefined

R0 Data Register

R/W

R06

R/W

R05

R/W

R04

R/W

R03

R/W

R02

R/W

R01

R/W

R00

Port R1 is multiplexed with various special features.The

control registers controls the selection of alternate func-

tion. After reset, this value is “0”, port may be used as nor-

mal input port. The way to select alternate function such as

comparator input will be shown in each peripheral section.

R07

R0

ADDRESS : 00C1_H

RESET VALUE : 0000 0000_b

R0 Direction Register

W

In addition, R1 port is used as key scan function which op-

erate with normal input port.

R0DD

Port Direction

0: Input

1: Output

Input or output is configured automatically by each func-

tion register (KSMR) regardless of R1DD.

R2 Port

R1 Ports

R2 is a 6-bit CMOS bidirectional I/O port (address 0C4_H).

Each I/O pin can independently used as an input or an out-

put through the R2DD register (address 00C5_H).The con-

trol registers for R2 are shown below.

R1 is a 5-bit CMOS input port only(address 0C2_H). Each

pin can independently used as an input through the R1DD

register (address 0C3_H). User can use R0DD register when

its bit is 0 only. The control registers for R1 are shown be-

low.

ADDRESS : 00C4_H

R2 Data Register

RESET VALUE : Undefined

ADDRESS : 00C2_H

RESET VALUE : Undefined

R/W

R25

R/W

R24

R/W

R23

R/W

R22

R/W

R21

R/W

R20

R1 Data Register

R2

R

R14

R13

R12

R11

R10

R1

ADDRESS : 00C5_H

RESET VALUE : 0000 0000_b

R2 Direction Register

ADDRESS : 00C3_H

RESET VALUE : ---0 0000_b

W

R1 Direction Register

-

R2DD

W

Port Direction

0: Input

1: Output

-

R1DD

AIPS

Port Direction

0 : use Input only

ADDRESS: 00CE_H

INITIAL VALUE: 0000 0000_b

ADDRESS: 00EF_H

INITIAL VALUE: --00 0000_H

W

-

EC3S

EC2S INT3S INT2S INT1S

1

FUNC

W

MSB

LSB

-

AIPS5 AIPS4 AIPS3 AIPS2 AIPS1 AIPS0

FUNC.5 ~ FUNC.1

0 : R2 Port

1 : INT mode, EC mode

MSB

LSB

user must set 1

AIPS.5 ~ AIPS.0

0 : R0 Port

1 : ADC Input

R2 port also use the value bit5 ~ bit1 of FUNC register to

secondary function register. R2 port have secondary func-

R1 port also can use the value bit5 ~ bit0 of AIPS register

to secondary function register. R1 port have secondary

November 2001 Ver 1.1

33

HMS81C4x60

tions as following table.

R4 Port

R4 is a 4-bit open drain and bidirectional I/O port (address

0C8_H). Each I/O pin can independently used as an input or

an output through the R4DD register (address 0C9_H).

Port Pin

Alternate Function

R21

R22

R23

R24

R25

INT1 (External Interrupt 1)

INT2 (External Interrupt 2)

INT3 (External Interrupt 3)

EC2 (Event Counter 2)

EC3 (Event Counter 3)

The control registers for R4 are shown below.

ADDRESS : 00C8_H

RESET VALUE : Undefined

R4 Data Register

R/W

R43

R/W

R42

R/W

R41

R/W

R40

R4

R3 Port

R3 is a 8-bit CMOS bidirectional output port (address

0C6_H). Each I/O pin can independently used as an input or

an output through the R3DD register (address 0C7_H).

ADDRESS : 00C9_H

RESET VALUE : 0000 0000_b

R4 Direction Register

W

-

W

-

W

The control registers for R3 are shown below.

-

R4DD

ICCR

ADDRESS : 00C6_H

RESET VALUE : Undefined

Port Direction

0: Input

R3 Data Register

1: Output

R/W

R36

R/W

R35

R/W

R34

R/W

R33

R/W

R32

R/W

R31

R/W

R30

R37

R3

ADDRESS: 00DB_H

INITIAL VALUE: 0000 0000_b

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS : 00C7_H

RESET VALUE : 0000 0000_b

BSEL1 BSEL0 ACKb

ESO

CCR3 CCR2 CCR1 CCR0

R3 Direction Register

LSB

MSB

ICCR.7 ~ ICCR.6

W

00 : R4 Port

01 : SCL0, SDA0, R42, R43

10 : SCL1, SDA1, R40, R41

11 : SCL0, SDA0, SCL1, SDA1

R3DD

Port Direction

0: Input

1: Output

R4 port also use the value bit7 ~ bit6 of ICCR register to

secondary function register. R4 port have secondary func-

tions as following table.

ADDRESS: 00EA_H

INITIAL VALUE: 0000 0000_b

R/W

R/W R/W R/W R/W R/W R/W

R/W

TM R1

BUZ

EN5

EN4

EN3

EN2

EN1

EN0

PWMCR1

MSB

LSB

R40

R41

R42

R43

SCL0 (Serial Clock 0)

SDA0 (Serial Data 0)

SCL1 (Serial Clock 1)

SDA1 (Serial Data 1)

PWMCR.7 ~ PWMCR.0

0 : R3 Port

1 : PWM, BUZ, TMR1

R3 port also use the value bit7 ~ bit0 of PWMCR1 register

to secondary function register. R3 port have secondary

functions as following table.

R30

R31

R32

R33

R34

R35

R36

R37

PWM0 (Pulse Width Modulation 0)

PWM1 (Pulse Width Modulation 1)

PWM2 (Pulse Width Modulation 2)

PWM3 (Pulse Width Modulation 3)

PWM4 (Pulse Width Modulation 4)

PWM5 (Pulse Width Modulation 5 - 14bit)

BUZ (Buzzer Output)

TMR1 (Timer Interrup 1)

34

November 2001 Ver 1.1

HMS81C4x60

10. CLOCK GENERATOR

As shown in Figure 10-1, the clock generation Circuit con-

sist PLL that generate multiplicated frequency of Crystal

clock, Generation Circuit which create CPU clock, Pres-

caler which generate input clock of Basic Interval Timer

and variable hardware clock, Basic Interval timer which is

generate standard time, Watch Dog Timer which is protect

Software Overflow.

See “12.1 BASIC INTERVAL TIMER” on page for de-

tails.

Data Slicer Clock

OSD Clock

OSC

PLL

Clock Pulse Generator

Internal System Clock

(16MHz typical)

Circuit

PRESCALER (11)

ENPCK

11

Peripheral Circuit

IFBIT

8

0

7

0

5

MUX

Basic Interval Timer(8)

BTCL

Watch Dog Timer(6)

6

WDTCL

COMPARATOR

6

IFWDT

to RESET

WDTON

CIRCUIT

0

5

6

CKCTRL

0

1 2

3

4 5

WDTR

7

WDTCL

6

8

Internal DATA BUS

10.1 Clock Generation Circuit

The clock signal come from crystal oscillator or ceramic

via Xin and Xout or from external clock via Xin is supplied

to Clock Pulse Generator and Prescaler.

Generator, and several peripherial clock is divided by pres-

caler.

Clock Generation circuit of Crystal Oscillator or Ceramic

Resonator is shown as below.

Internal System Clock for CPU is made by Clock Pulse

November 2001 Ver 1.1

35

HMS81C4x60

Cout

Cin

Xout

Xin

Xout

Xin

Open

GND

External Clock

Figure 10-2 External Clock

Figure 10-1 Cristal Oscillator or Ceramic Resonator

10.2 Phase Locked Loop

PLL(Phase Locked Loop) from OSC 4MHz clock circuit

generate Internal System clock, Timer clock(PS0), Data

Slicer Clock, OSD clock, etc.

Figure 10-3 PLL Control Register

W

ADDRESS: 00CF_H

INITIAL VALUE: -000 0000_b

-

PCF2

PCF1

PCF0 PLLO N

PLLC

MSB

LSB

PLL clock frequency

0 : Off PLL

1 : On PLL, in the case system clock supply OSD circuit

PLL clock frequency

000 : 8MHz

001 : 12MHz

010 : 16MHz(typical)

011 : 24MHz

100 : 32Mhz

Test mode

10.3 PRESCALER

Prescaler consistor of 11-bit binary counter, and input

clock which is supplied by oscillation circuit. Frequency

divided by prescaler is used as a source clock for periphe-

rial hardwares.

f_ex

PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8

PS9 PS10 PS11

ENPCK

B.I.T

8

PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11

12

PERIPHERAL

Figure 10-4 Prescaler

36

November 2001 Ver 1.1

HMS81C4x60

Peripheral Clock supplied from prescaler can be stopped

by ENPCK. Peripheral clock is determined by CKCTLR

Register.(However, PS11 cannot be stopped by ENPCK)

W

ADDRESS: 00F6_H

INITIAL VALUE: --00 0000_b

-

W DTO N ENPCK BTCL

BTS2

BTS1

BTS0

CKCTLR

MSB

LSB

B.I.T input clock select

000 : PS4 (4 S)

µ

001 : PS5 (8 S)

µ

010 : PS6 (16 S)

µ

011 : PS7 (32 S)

µ

100 : PS8 (64 S)

µ

101 : PS9 (128 S)

µ

110 : PS10 (256 S)

µ

111 : PS11 (512 S)

µ

B.I.T clear (when write)

0 : B.I.T Free-run

1 : B.I.T clear (Auto reset when after 1 cycle)

Peripherial clock enable (when write)

0 : Peripherial clock stop

1 : Peripherial clock supply

WDT function control(when write)

0 : 6 bit TIMER

1 : WATCH-DOG TIMER

B.I.T value (when read)

data : 00h ~ FFh

Figure 10-5 Clock Control Register

November 2001 Ver 1.1

37

HMS81C4x60

11. INTERRUPTS

The HMS81C4x60 interrupt circuits consist of Interrupt

enable register (IENH, IENL), Interrupt request flags of

IRQH and IRQL, Priority circuit and Master enable flag

("I" flag of PSW). 16 interrupt sources are provided. The

configuration of interrupt circuit is shown in Figure 11-2.

Interrupt Mode Register

It controls interrupt priority. It takes only one specified in-

terrupt.

Of course, interrupt’s priority is fixed by H/W, but some-

times user want to get specified interrupt even if higher

priority interrupt was occured. Higher priority interrupt is

occured the next time.

Below table shows the Interrupt priority

Reset/Interrupt

Hardware Reset

Symbol

Priority

It contains 2bit data to enable priority selection and 4bit

data to select specified interrupt.

RESET

-

1

reserved

OSD Interrupt

OSD

INT1

INT2

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Bit No. Name

Value

Function

External Interrupt 1

External Interrupt 2

Timer/Counter 0

Timer/Counter 2

Slicer Interrupt

VSync Interrupt

Timer/Counter 1

Timer/Counter 3

Interrupt interval measure

Watchdog Timer

Basic Interval Timer

reserved

00

01

1X

Mode 0: H/W priority

Mode 1: S/W priority

Interrupt is disabled, even

if IE is set.

Timer 0

Timer 2

Slicer

VSync

Timer 1

Timer 3

INTV(INT3/4)

WDT

5,4

IM1~0

0000

0001 OSD

0010 INT1

0011 INT2

0100 Timer 0

0101 Timer 2

0110 Slicer

0111 VSync

1000 Timer 1

1001 Timer 3

1010 INTV(INT3/4)

1011 WDT

-

BIT

-

I2C

I²C Interrupt

3~0

IP3~0

The External Interrupts can be transition-activated (1-to-0

or 0-to-1 transition).

1100 BIT

When an external interrupt is generated, the flag that gen-

erated it is cleared by the hardware when the service rou-

tine is vectored to only if the interrupt was transition-

activated.

1101

-

1110 I2C

1111 Not used

Table 11-1 Bit function

The Timer/Counter Interrupts are generated by

TnIF(n=0~3), which is set by a match in their respective

timer/counter register.

ADDRESS : 00F3_H

RESET VALUE : Undefined

The Basic Interval Timer Interrupt is generated by BITIF

which is set by a overflow in the timer register.

Interrupt Mode Register

R/W

M1

R/W

M0

R/W

IP3

R/W

IP2

R/W

IP1

R/W

IP0

The interrupts are controlled by the interrupt master enable

flag I-flag (bit 2 of PSW), that is the interrupt enable reg-

ister (IENH, IENL) and the interrupt request flags (in

IRQH,IRQL) except Power-on reset and software BRK in-

terrupt.

IMOD

Figure 11-1 Interrupt Mode Register

38

November 2001 Ver 1.1

HMS81C4x60

Internal bus line

Interrupt Enable

Register (Higher byte)

IMOD [00F3 ]

IENH [00F6 ]

H

IRQH

Bit5

[0F7 ]

H

-

IFOSD

INT1

OSD

RESET

BRK

INT1

INT2

T0

INT2

Timer 0

To CPU

Timer 2

Slicer

T2

SLICE

VSync

IFVSync

I Flag

T1

T3

Timer 1

Timer 3

Interrupt Master

Enable Flag

I-flag is in PSW , it is cleared by "DI", set by

"EI" instruction. W hen it goes interrupt service,

I-flag is cleared by hardware, thus any other

interrupt are inhibited. W hen interrupt service is

com pleted by "RETI" instruction, I-flag is set to

INTV

WDT

BIT

-

Intr. interval

IFWDT

IFBIT

"1" by hardware.

I2C

Interrupt

Vector

Address

Generator

IFI2C

IRQL

[00F5 ]

H

Interrupt Enable

Register (Lower byte)

IENL [00F4 ]

H

Internal bus line

Figure 11-2 Block Diagram of Interrupt

November 2001 Ver 1.1

39

HMS81C4x60

Interrupt request flag registers are shown in Figure 11-3.

Interrupt request is generated when suitable bit is set, and

suitable request flag of accepted interrup is clear when in-

terrupt processing cycle. Suitable bit is set when interrupt

request is occured, but no accepted request flag is set to

hold when the interrupt is accepted. Also, interrupt request

flag register(IRQH, IRQL) is the register of read or write.

So, request flag can be changed by program.

R/W R/W R/W R/W

INT1

R/W R/W R/W R/W

T2 SLICE

ADDRESS: 00F7_H

INITIAL VALUE: 0000 0000_b

INT2

T0

-

OSD

VSync

LSB

IRQH

MSB

VSync interrupt request flag

Slicer interrupt request flag

Timer / Counter 2 interrupt request flag

Timer / Counter 0 interrupt request flag

External interrupt 2 interrupt request flag

External interrupt 1 interrupt request flag

On screen display interrupt request flag

R/W R/W R/W R/W R/W R/W R/W

ADDRESS: 00F5_H

INITIAL VALUE: 0000 000-_b

-

T1

MSB

T3

BIT

I2C

IRQL

INTV WDT

LSB

I²C interrupt request flag

Basic interval timer interrupt request flag

Watch-dog timer interrupt request flag

Interrupt interval measurement interrupt request flag (INT3/4)

Timer / Counter 3 interrupt request flag

Timer / Counter 1 interrupt request flag

Figure 11-3 Interrupt Request Flag Registers

40

November 2001 Ver 1.1

HMS81C4x60

Interrupt enable flag registers are shown in Figure 11-4.

These registers are composed of interrupt enable flags of

each interrupt source, these flags determines whether an

interrupt will be accepted or not. When enable flag is "0",

a corresponding interrupt source is prohibited. Note that

PSW contains also a master enable bit, I-flag, which dis-

ables all interrupts at once.

R/W R/W R/W R/W

INT1

R/W R/W R/W R/W

T2 SLICE

ADDRESS: 00F6_H

INITIAL VALUE: 0000 0000_b

INT2

T0

-

OSD

VSync

LSB

IENH

MSB

VSync interrupt enable flag

Slicer interrupt enable flag

Timer / Counter 2 interrupt enable flag

Timer / Counter 0 interrupt enable flag

External interrupt 2 interrupt enable flag

External interrupt 1 interrupt enable flag

On screen display interrupt enable flag

R/W R/W R/W R/W R/W R/W R/W

T1 T3 BIT I2C

MSB

ADDRESS: 00F4_H

INITIAL VALUE: 0000 000-_b

-

IENL

INTV WDT

-

LSB

I²C interrupt enable flag

Basic interval timer interrupt enable flag

Watch-dog timer interrupt enable flag

Interrupt interval measurement interrupt enable flag (INT3/4)

Timer / Counter 3 interrupt enable flag

Timer / Counter 1 interrupt enable flag

Figure 11-4 Interrupt Enable Flag Regesters

November 2001 Ver 1.1

41

HMS81C4x60

11.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted

or the interrupt latch is cleared to "0" by a reset or an in-

struction. Interrupt acceptance sequence requires 8 f_ex(2

µs at f_MAIN=4MHz) after the completion of the current in-

struction execution. The interrupt service task terminates

upon execution of an interrupt return instruction [RETI].

2. Interrupt request flag for the interrupt source accepted

is cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto

the stack area. The stack pointer decrements 3 times.

4. The entry address of the interrupt service program is

read from the vector table address, and the entry ad-

dress is loaded to the program counter.

Interrupt acceptance

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any fol-

lowing maskable interrupts. When a non-maskable in-

terrupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

System clock

Instruction Fetch

SP-2

PSW

V.L.

V.H.

New PC

OP code

SP

SP-1

PC

Address Bus

Data Bus

Not used

V.L.

ADL

ADH

PCH

PCL

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 11-5 Interrupt Service routine Entering Timing

42

November 2001 Ver 1.1

HMS81C4x60

General-purpose register save/restore using push and pop

instructions;

Basic Interval Timer

Vector Table Address

Entry Address

012_H

0E3_H

0FFE6_H

0FFE7_H

0E_H

2E_H

0E312_H

0E313_H

main task

acceptance of

interrupt

service task

saving

registers

Correspondence between vector table address for BIT interrupt

and the entry address of the interrupt service program.

restoring

registers

A maskable interrupt is not accepted until the I-flag is set

to "1" even if a maskable interrupt of higher priority than

that of the current interrupt being serviced.

interrupt return

When nested interrupt service is necessary, the I-flag is set

to "1" in the interrupt service program. In this case, accept-

able interrupt sources are selectively enabled by the indi-

vidual interrupt enable flags.

11.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,

which is the lowest priority order.

Interrupt vector address of BRK is shared with the vector

of TCALL 0 (Refer to Program Memory Section). When

BRK interrupt is generated, B-flag of PSW is set to distin-

guish BRK from TCALL 0.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program

counter and the program status word are automatically

saved on the stack, but not the accumulator and other reg-

isters. These registers are saved by the program if neces-

sary. Also, when nesting multiple interrupt services, it is

necessary to avoid using the same data memory area for

saving registers.

Each processing step is determined by B-flag as shown in

Figure 11-6.

=0

The following method is used to save/restore the general-

purpose registers.

B-FLAG

=1

BRK or

TCALL0

BRK

INTERRUPT

ROUTINE

Example: Register save using push and pop instructions

TCALL0

ROUTINE

INTxx: PUSH

A

;SAVE ACC.

;SAVE X REG.

;SAVE DPGR

; Direct page

; accessable reg.

;

PUSH

LDA

X

RETI

RET

DPGR

PUSH

A

:

interrupt processing

:

Figure 11-6 Execution of BRK/TCALL0

POP

STA

POP

RETI

A

DPGR

;RESTORE DPGR

;RESTORE X REG.

;RESTORE ACC.

;RETURN

X

A

November 2001 Ver 1.1

43

HMS81C4x60

11.3 Multi Interrupt

If two requests of different priority levels are received si-

multaneously, the request of higher priority level is ser-

viced. If requests of the same priority level are received

simultaneously, an internal polling sequence determines

by hardware which request is serviced.

However, multiple processing through software for special

features is possible. Generally when an interrupt is accept-

ed, the I-flag is cleared to disable any further interrupt. But

as user set I-flag in interrupt routine, some further interrupt

can be serviced even if certain interrupt is in progress.

Example: Even though Timer1 interrupt is in progress,

INT0 interrupt serviced without any suspend.

Main Program

service

TIMER 1

service

TIMER1: PUSH

A

PUSH

LDM

EI

X

INT0

service

Y

IENH,#20H

IENL,#0

;Enable INT1 only

;Disable other

;Enable Interrupt

enable INT0

disable other

EI

:

Occur

INT0

TIMER1 interrupt

:

enable INT0

enable other

LDM

POP

RETI

IENH,#FFH

;Enable all interrupts

IENL,#FEH

Y

X

A

In this example, the INT0 interrupt can be serviced without any

pending, even TIMER1 is in progress.

Because of re-setting the interrupt enable registers IENH,IENL

and master enable "EI" in the TIMER1 routine.

Figure 11-7 Execution of Multi Interrupt

44

November 2001 Ver 1.1

HMS81C4x60

11.4 External Interrupt

The external interrupt on INT1, INT2... pins are edge trig-

gered depending the edge selection register.

INT1, INT2 and INT3 are multiplexed with general I/O

ports. To use external interrupt pin, the bit of port function

register FUNC1 should be set to "1" correspondingly.

Refer to “6. PORT STRUCTURES” on page 12.

The edge detection of external interrupt has three transition

activated mode: rising edge, falling edge, both edge.

Response Time

The INT1, INT2 and INT3 edge are latched into INT1IF,

INT2IF and INT3IF at every machine cycle. The values

are not actually polled by the circuitry until the next ma-

chine cycle. If a request is active and conditions are right

for it to be acknowledged, a hardware subroutine call to the

requested service routine will be the next instruction to be

executed. For example, the DIV instruction takes twelve

machine cycles. Thus, a minimum of twelve complete ma-

chine cycles elapse between activation of an external inter-

rupt request and the beginning of execution of the first

instruction of the service routine

INT1 pin

INT2 pin

INT1IF

INT2IF

INT1 INTERRUPT

INT2 INTERRUPT

INT3 pin

INT3IF

INT3 INTERRUPT

IEDS

[00F2_H]

Figure 11-8 External Interrupt Block Diagram

System clock

Instruction Fetch

Last instruction execution (0~12cycle)

Interrupt request sampling

Enter interrupt service routine (8cycle)

1cycle

Interrupt overhaed (9~21cycle)

Figure 11-9 Interrupt Response Timing Diagram ( Interrupt overhead )

November 2001 Ver 1.1

45

HMS81C4x60

12. TIMER

12.1 Basic Interval Timer

The HMS81C4x60 has one 8-bit Basic Interval Timer that

is free-run and can not be stopped. Block diagram is shown

in Figure 12-1.

generated. The Basic Interval Timer is controlled by the

clock control register (CKCTLR) shown in Figure 12-2.

Source clock can be selected by lower 3 bits of CKCTLR.

The Basic Interval Timer generates the time base for

watchdog timer counting, and etc. It also provides a Basic

interval timer interrupt (BITIF). As the count overflow

from FF_Hto 00_H, this overflow causes the interrupt to be

BITR and CKCTLR are located at same address, and ad-

dress 00D6_His read as a BITR and written to CKCTLR..

f_ex2⁴

÷

PS4

PS5

PS6

PS7

PS8

PS9

f_ex2⁵

÷

8-bit up-counter

BITR

f_ex2⁶

÷

source

clock

overflow

f_ex2⁷

÷

BITIF

MUX

f_ex2⁸

Basic Interval Timer Interrupt

÷

f_ex2⁹

÷

[0D6_H]

f_ex2¹⁰

Watchdog timer clock (WDTCK)

÷

PS10

PS11

f_ex2¹¹

clear

BTCL

÷

BITCK

3

Select Input clock

Clock control register

[0D6_H]

WDT

ENPCK BTCL BTS2 BTS1 BTS0

CKCTLR

ON

Internal bus line

Figure 12-1 Block Diagram of Basic Interval Timer

W

ADDRESS: 00D6_H

INITIAL VALUE: --00 0000_b

-

W DTO N ENPCK BTCL

BTS2

BTS1

BTS0

CKCTLR

MSB

LSB

B.I.T Clock

B.I.T clear (when write)

0 : B.I.T Free-run

1 : B.I.T clear (Auto reset when after 1 cycle)

Peripherial clock enable (write time)

0 : Peripherial clock stop

1 : Peripherial clock supply

Caution:

WDT function control

0 : 6 bit TIMER

1 : WATCH-DOG TIMER

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

B.I.T value (when read)

R

ADDRESS: 00D6_H

BITR

INITIAL VALUE: Undefined

MSB

LSB

8-BIT BINARY COUNTER

Figure 12-2 BITR Basic Interval Timer Mode Register

46

November 2001 Ver 1.1

HMS81C4x60

12.2 Timer 0, 1

Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare

data register, 8-bit count register, Control register, and

Comparator as shown in Figure 12-3 and Figure 12-4.

Note: You can read Timer 0, Timer 1 value from TDR0 or

TDR1. But if you write data to TDR0 or TDR1, it changes

Timer 0 or Timer 1 modulo data, not Timer value.

These Timers can run separated 8bit timer or combined

16bit timer. These timers are operated by internal clock.

The content of TDR0, TDR1 must be initialized (by soft-

ware) with the value between 01_Hand FF_H,not to 00_H.

Or not, Timer 0 or Timer 1 can not count up forever.

The contents of TDR1 are compared with the contents of

up-counter T1. If a match is found, a timer/counter 1 inter-

rupt (T1IF) is generated, and the counter is cleared. Count-

ing up is resumed after the counter is cleared.

The control registers for Timer 0,1 are shown below.

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00D0_H

INITIAL VALUE: -000 0000_b

-

T1ST T1SL1 T1SL0 T0ST

T0CN T0SL1 T0SL0

TM0

MSB

LSB

T0 input clock select(f_ex=4MHz)

00 : PS2(1 S)

µ

01 : PS4(4 S)

µ

10 : PS6(16 S)

µ

11 : PS8(64 S)

µ

Timer 0 Continue/Hold control

0 : Count Hold

1 : Count Countinue

Timer 0 Start control

0 : Count Hold

1 : Count Clear and Start

Timer 1 input clock(f_ex=4MHz)

00 : Timer 0 overflow (16bit mode)

01 : PS2(1 S)

µ

10 : PS4(4 S)

µ

11 : PS6(16 S)

µ

Timer 1Start/Hold control

0 : Count Hold

0 : Count Clear and Start

ADDRESS: 00D2_H

INITIAL VALUE: Undefined

R/W R/W

R/W R/W R/W R/W R/W R/W

TDR0

TDR1

MSB

LSB

ADDRESS: 00D3_H

INITIAL VALUE: Undefined

R/W R/W

R/W R/W R/W R/W R/W R/W

MSB

LSB

Figure 12-3 Timer / Event Count 0,1

(Example) TIMER0 1mS TIME INTERVAL INTERRUPT

:

TDR_CNT: LDM

TDR0,#249

LDM

:

TDR1,#0

TM0,#0011_1101b

; 4uSEC PRESCALER FOR T0

:

November 2001 Ver 1.1

47

HMS81C4x60

.

Internal bus line

TM0

TDR0

TDR1

T0CN

8bit Comparator

T0IF

8bit Comparator

T1IF

Timer 0

Clock

Timer 1

Clock

PS2

PS4

PS6

PS8

MUX

Clear

T0ST

NC

PS2

PS4

PS6

T1ST

Figure 12-4 Simplified Block Diagram of 8bit Timer0, 1

TDR0

enable

disable

clear & start

stop

TIME

Timer 0 (T0IF)

Interrupt

Occur interrupt

T0ST

T0ST = 1

T0ST = 0

Start & Stop

T0CN

T0CN = 1

Control count

T0CN = 0

Figure 12-5 Count Example of Timer

48

November 2001 Ver 1.1

HMS81C4x60

Internal bus line

TM0

TDR0

TDR1

0

T0CN

16bit Comparator

T1IF

Timer 0

Clock

Timer 1

Clock

PS2

PS4

PS6

PS8

MUX

Clear

T0ST

Figure 12-6 Simplified Block Diagram of 16bit Timer0, 1

November 2001 Ver 1.1

49

HMS81C4x60

12.3 Timer / Event Counter 2, 3

Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare

data register, 8-bit count register, Control register, and

Comparator as shown in Figure 12-7 and Figure 12-8.

Note: You can read Timer 2, Timer 3 value from TDR2 or

TDR3. But if you write data to TDR2 or TDR3, it changes

Timer 2 or Timer 3 modulo data, not Timer value.

These Timers have two operating modes. One is the timer

mode which is operated by internal clock, other is event

counter mode which is operated by external clock from pin

R24/EC2, R25/EC3.

The content of TDR2, TDR3 must be initialized (by soft-

ware) with the value between 01_Hand FF_H,not to 00_H.

Or not, Timer 2 or Timer 3 can not count up forever.

These Timers can run separated 8bit timer or combined

16bit timer.

The control registers for Timer 2,3 are shown below

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00D1_H

INITIAL VALUE: -000 0000_b

-

T3ST T3SL1 T3SL0 T3ST

T3CN T3SL1 T3SL0

TM2

MSB

LSB

T2 input clock select

00 : External EVENT input(EC2)

01 : PS2(1 S)

µ

10 : PS4(4 S)

µ

11 : PS6(16 S)

µ

Timer 2 Continue/Hold control

0 : Count Hold

1 : Count Countinue

Timer 2 Start/Hold control

0 : Count Hold

1 : Count Clear and Start

Timer 3 input clock

00 : Connected to T2(16bit mode)

01 : External EVENT input(EC3)

10 : PS2 (1 S)

µ

11 : PS6 (16 S)

µ

Timer 3 Start/Hold control

0 : Count Hold

0 : Count Clear and Start

ADDRESS: 00D4_H

INITIAL VALUE: Undefined

R/W R/W

R/W R/W R/W R/W R/W R/W

TDR2

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1 TDR0

MSB

LSB

ADDRESS: 00D5_H

INITIAL VALUE: Undefined

R/W R/W

R/W R/W R/W R/W R/W R/W

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1 TDR0

TDR3

FUNC

LSB

MSB

W

ADDRESS: 00CE_H

INITIAL VALUE: 0000 000-_b

-

EC1S

EC0S INT3S INT2S INT1S

-

MSB

LSB

R24/EC2 Select

0 : R24

1 : EC2

R25/EC3 Select

0 : R25

1 : EC3

Figure 12-7 Timer / Event Count 2,3

50

November 2001 Ver 1.1

HMS81C4x60

.

Internal bus line

TM2

TDR2

TDR3

T2CN

8bit Comparator

T2IF

8bit Comparator

T3IF

Timer 2

Clock

Timer 3

Clock

EC2

PS2

PS4

PS6

MUX

Clear

T2ST

NC

EC3

PS2

PS4

T3ST

Figure 12-8 Simplified Block Diagram of 8bit Timer/Event Counter 2,3

TDR2

enable

disable

clear & start

stop

TIME

Timer 2 (T2IF)

Interrupt

Occur interrupt

T2ST

Start & Stop

T2ST = 1

T2ST = 0

T2CN

T2CN = 1

Control count

T2CN = 0

Figure 12-9 Count Example of Timer / Event counter

November 2001 Ver 1.1

51

HMS81C4x60

Internal bus line

TM2

TDR2

TDR3

0

T0CN

16bit Comparator

T3IF

Timer 2

Clock

Timer 3

Clock

EC2

PS4

PS6

PS8

MUX

Clear

T0ST

Figure 12-10 Simplified Block Diagram of 16bit Timer/Event Counter 2,3

n interrupt (TnIF) is generated and the up-counter is

Timer Mode

cleared to 0. Counting up is resumed after the up-counter

is cleared.

In the timer mode, the internal clock is used for counting

up. Thus, you can think of it as counting internal clock in-

put. The contents of TDRn (n=0~3) are compared with the

contents of up-counter, Timer n. If match is found, a timer

As the value of TDRn is changeable by software, time in-

terval is set as you want

Start count

Source clock

N-2

N-1

N

1

4

0

3

0

1

2

3

2

Up-counter

TDRn (n=0~3)

N

Match

Detect

Counter

Clear

TnIF (n=0~3) interrupt

Figure 12-11 Timer Mode Timing Chart

Event Counter Mode

put.

In event timer mode, counting up is started by an external

trigger. This trigger means falling edge of the ECn (n=0~1

) pin input. Source clock is used as an internal clock select-

ed with TM2. The contents of TDRn are compared with the

contents of the up-counter. If a match is found, an TnIF in-

terrupt is generated, and the counter is cleared to 00_H. The

counter is restarted by the falling edge of the ECn pin in-

The maximum frequency applied to the ECn pin is f_ex/2

[Hz] in main clock mode.

In order to use event counter function, the bit EC0S, EC1S

of the Port Function Select Register FUNC(address 0CE_H)

is required to be set to "1".

After reset, the value of TDRn is undefined, it should be

52

November 2001 Ver 1.1

HMS81C4x60

initialized to between 01_H~FF_Hnot to 00_H

Start count

ECn (n=2~3) pin

1

2

Up-counter

0

2

N-1

N

0

TDRn (n=2~3)

N

TnIF (n=2~3) interrupt

Figure 12-12 Event Counter Mode Timing Chart

The interval period of Timer is calculated as below equa-

tion.

1

f_ex

-----

Period=

× Prescaler ratio × TDRn

TDR2

TDR2=n

n

n-1

n-2

P_CP

8

7

6

5

4

3

2

1

0

TIME

Interrupt period

= P_CPx n

Timer 2 (T2IF)

Interrupt

Occur interrupt

Figure 12-13 Count Example of Timer / Event counter

November 2001 Ver 1.1

53

HMS81C4x60

TDR2

enable

disable

clear & start

stop

TIME

Timer 2 (T2IF)

Interrupt

Occur interrupt

T2ST

Start & Stop

T2ST = 1

T2ST = 0

T2CN

T2CN = 1

Control count

T2CN = 0

Figure 12-14 Count Operation of Timer / Event counter

54

November 2001 Ver 1.1

HMS81C4x60

13. A/D Converter

The A/D converter circuit is shown in Figure 13-1.

alog input. The ADCM register control A/D converter’s

activity. The ADR register stores A/D converted 8bit re-

sult. The more details are shown Figure 13-2.

The A/D converter circuit consists of the comparator and

control register AIPS(00EF_H), ADCM(00F0_H),

ADR(00F1_H). The AIPS register select normal port or an-

Data Bus

5

8

0

ADEN ADS2 ADS1 ADS0 ADST ADSF

0

1

2

3

4

5

6

7

ADCM [F0_H]

ADR [F1_H]

8

IFA

Control circuit

port

select

Comparator

AN0

AN1

AN2

AN3

AN4

S/H

Succesive

Approximation

Circuit

+

−

MUX

Vref

Register ladder

8

Figure 13-1 Block Diagram of A/D convertor circuit

BBC ADCM.ADSF,$

LDA ADR

Control

; or “SET1 ADST”

The HMS81C4x60 contains a A/D converter module

which has six analog inputs.

:

1. First of all, you have to select analog input pin by set the

ADCM and AIPS.

5. After A/D conversion is completed, ADSF bit and inter-

rupt flag IFA will be set. (A/D conversion takes 36 ma-

chine cycle : 18uS when f_ex=4MHz).

2. Set ADEN (A/D enable bit : ADCM bit5).

3. Set ADST (A/D start bit : ADCM bit1). We recommend

you do not set ADEN and ADST at once, it makes worse

A/D converted result.

Note: Make sure AIPS bits, if you using a port which is set

digital input by AIPS, analog voltage will be flow into MCU

internal logic not A/D converter. Sometimes device or port

is damaged permanently.

4. ADST bit will be cleared 1 cycle automatically after you

set this.

[Example]

;Set AIPS, change ? to what you want

;

0 : digital port

1 : analog port

AIPS,#0000_1000b

;

LDM

; Set ADEN, xxx is analog port number

LDM

ADCM,#0010_1100b

; or “SET1 ADEN”

; Set ADST, xxx is analog port number

LDM

ADCM,#0010_11110b

November 2001 Ver 1.1

55

HMS81C4x60

R/W

R

R/W R/W R/W R/W R/W R/W

ADDRESS: 00F0_H

INITIAL VALUE: --01 1101_b

-

ADEN ADS2

ADS1

ADS0 ADST ADSF

ADCM

MSB

LSB

A/D Converter Status bit

0 : Busy

1 : A/D conversion completed

A/D Converter Start bit

0 : Ignore

1 : A/D start (‘0’ after 1 cycle)

Analog Port Select

000 : AN0 select

001 : AN1 select

010 : AN2 select

011 : AN3 select

100 : AN4 select

101 : Default

110 : Default

111 : Default

A/D Converter Enable bit

0 : Disable

1 : Enable

ADDRESS: 00F1_H

INITIAL VALUE: Undefined

R

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1

TDR0

ADR

MSB

LSB

ADDRESS: 00EF_H

INITIAL VALUE: ---0 0000_H

W

AIPS

-

AIPS4 AIPS3 AIPS2 AIPS1 AIPS0

MSB

LSB

Analog Input Select

0 : P1 input

1 : ADC Input

Figure 13-2 A/D convertor Registers

PORT select

R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0

ADS2

ADS1

ADS0

Function

AN0

R10

AN0

AN1

AN2

AN3

AN4

R14

AN4

R13

AN3

R13

R12

AN2

R12

R11

AN1

R11

0

1

0

1

Figure 13-3 A/D Conversion Data Register

56

November 2001 Ver 1.1

HMS81C4x60

14. Pulse Width Modulation (PWM)

The PWM circuit is shown in Figure 14-1, .

The PWM circuit consists of the counter, comparator, Data

register.

Example

The PWM control registers are PWMR4~0, PWMCR2~1,

PWM5H, PWM5L.

14bit PWM

8bit PWM

(f_ex=4MHz)

Resolution

Input Clock

Frame cycle

14 bits

2MHz

8 bits

The more details about registers are shown Figure 14-2 .

250KHz

1,024uS

8,192uS

PWMCR2 [EB_H]

PWMCR1 [EA_H]

2 1 0

3

CNTB

PWM5

PWM4

PWMR5 [E5_H]

PWMR4 [E4_H]

PWMR3 [E3_H]

EN5

EN4

EN3

EN2

EN1

PWM3

PWM2

PWMR2 [E2_H]

PWMR1 [E1_H]

PWM1

PWMR0 [E0_H]

8bit comparator

EN0

PWM0

CNTB

PS5

IF1Frame

8bit counter

Figure 14-1 8bit register (PWM7~0) circuit

PWMCR2 [EB_H]

CNTB

PWMCR1 [EA_H]

CNT

PWMR5H 8bit [E8_H]

PWMR5L 6bit [E9_H]

PWM8

14bit comparator

MSB

LSB

PS2

14bit counter

Figure 14-2 14bit register (PWM8) circuit

November 2001 Ver 1.1

57

HMS81C4x60

8bit PWM Control

Sub PWM Frame Cycle = Main Frame Cycle / 64.

The HMS81C4x60 contains a one 14bit PWM and five

8bit PWM module.

4. Table 14-1, “PWM5L and Sub frame matching table,”

on page 58 show PWM5L function.

1. 8bit PWM0~5 is wholy same internal circuit, but

PWM0~5 output port is CMOS bidirectional I/O pin.

Sub frame number which is

added 1 clock

Pulse

count

Bit value

2. Al l PWM polarity has the same by POL2’s value.

if Bit0=1 32

1

2

4

8

3. Calulate Frame cycle and Pulse width is as following.

PWM Frame Cycle = 2¹³/ f_ex(Sec)

PWM Width = (PWMRn+1) × 2⁵/ f_ex(n=0~5)

Pulse Duty (%) = (PWMRn +1) / 256 × 100(%) (n=0~5)

if Bit1=1 16, 48

if Bit2=1 8, 24, 40, 56

if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60

2, 6, 10, 14, 18, 22, 26, 30, 34,

if Bit4=1

16

38, 42, 46, 50, 54

Positive Polarity (POL2=0)

Negative Polarity (POL2=1)

1, 3, 5, 7, 9, 11, 13, 15, 17, 19,

21, 23, 25, 27, 29, 31, 33, 35, 37,

39, 41, 43, 45, 47, 49, 51, 53, 55,

if Bit5=1

32

1

2

1

2

57, 59, 61, 63

Table 14-1 PWM5L and Sub frame matching table

1. Frame cycle

2. Pulse Width

Main PWM Frame

0

1

2

61 62 63

Figure 14-3 Wave form example for 8bit PWM

.....

4. PWM output is enabled during ENn(n=0~5) bit (See

PWMCR1~2) contains 1.

Sub PWM Frame

which is added

1 clock

ADDRESS: 00E0_H~E4_H

PWMR4~0

INITIAL VALUE: Undefined

1 clock width : PS2

R/W R/W

R/W R/W R/W R/W R/W R/W

PW M0D7 PW M0D6 PW M0D5 PW M0D4 PW M0D3 PW M0D2 PW M0D1 PW M0D0

MSB

LSB

Each PWM Data Store

Figure 14-5 Wave form example for 14bit PWM

Figure 14-4 8bit PWM Registers

ADDRESS: 00E8_H

5. CNTB controls all PWM counter enable.

If CNTB=0, than Counter is disabled.

PWM5H

INITIAL VALUE: Undefined

R/W R/W

R/W R/W R/W R/W R/W R/W

PWM 5H7 PW M5H6 PW M5H5 PW M5H4 PW M5H3 PW M5H2 PW M5H1 PW M5H0

14bit PWM Control

MSB

LSB

1. 14bit PWM’s operation concept is not the same as 8bit

PWM.

ADDRESS: 00E9_H

INITIAL VALUE: Undefined

PWM5L

1 PWM frame contains 64 sub PWMs.

PWM5H : Set sub PWM’s basic Pulse Width.

PWM5L : Number of sub PWM which is added 1 clock.

R/W R/W

R/W R/W R/W R/W R/W R/W

-

PW M5L5 PW M5L4 PW M5L3 PW M5L2 PW M5L1 PW M5L0

MSB

LSB

2. PWM polarity is selected by POL1’s value.

If POL1=0, Positive Polarity.

Figure 14-6 PWM5H, PWM5L Register

3. Calulate Frame cycle and Pulse width is as following.

Main PWM Frame Cycle = 2¹⁶/ f_ex(Sec).

58

November 2001 Ver 1.1

HMS81C4x60

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00EA_H

INITIAL VALUE: 0000 0000_b

TM R1

BUZ

EN5

EN4

EN3

EN2

EN1

EN0

PWMCR1

MSB

LSB

R30/PWM0 Select

0 : R30

1 : PWM0

R31/PWM1 Select

0 : R31

1 : PWM1

R32/PWM2 Select

0 : R32

1 : PWM2

R33/PWM3 Select

0 : R33

1 : PWM3

R34/PWM4 Select

0 : R34

1 : PWM4

R35/PWM5 Select

0 : R35

1 : PWM5

R3 /Buzzer Select

0 : R36

1 : Buzzer output

R37/TMR1 Select

0 : R37

1 : TMR1

Figure 14-7 PWM Control Register 1

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00EB_H

INITIAL VALUE: 0000 0000_b

-

POL8 PO L14 CNTB

PWMCR2

MSB

LSB

14Bit/8Bit PWM Count stop/start

0 : Count start

1 : Count stop

14Bit PWM Output Polarity

0 : Positive Polarity

1 : Negitive Polarity

8Bit PWM Output Polarity

0 : Positive Polarity

1 : Negative Polarity

Figure 14-8 PWM Control Register 2

November 2001 Ver 1.1

59

HMS81C4x60

15. Interrupt Interval Measurement Circuit

The Interrupt interval measurement circuit is shown in Fig-

ure 15-1.

tor, 8bit counter, measured result storing register, FIFO (9

bit, 6 level) interrupt, Control register, etc.

The Interrupt interval measurement circuit consists of the

input multiplexer, sampling clock multiplexer, Edge detec-

The more details about registers are shown Figure 15-2 .

Data Bus

7

4

FCLR IMS I34H I34L

ISEL IDCK IDST

DPOL

FOE FFUL FEMP

IDCR [F9_H]

PS8

IDFS [FA_H]

8bit counter

1

MUX

0

PS9

Clear

Overflow

8

4

INT34

1

MUX

Edge detector

0

FCLR

INT3

MUX

0

FIFO

(9bit, 6level)

1

D7

D6

D5

D4

D3

D2

D1

D0

IDR [FB_H]

Figure 15-1 Block Diagram of Interrupt interval measurement circuit

Control

5. You can select interrupt occuring point by set Interrupt

Mode Select bit (IMS), every edge what you selected or

FIFO 4 level is filled.

The HMS81C4x60 contains a Interrupt interval measure-

ment module.

6. If input signal’s interval is larger than maximum counter

value (0FF_H), counter occurring an interrupt and count

again from 00_H.

1. Select interrupt input pin what you want to measure by

set the FUNC [00CE_H].

2. Set IDCR [00F9_H] : FIFO clear, interrupt mode select,

interrupt edge select, external interrupt INT3 select, sam-

pling clock select, COUNT start/stop select.

7. See Figure 15-7 FIFO operating mechanism.

[Example]

;Set INT3 for remote control pulse

reception

3. Set IDCR [00F9_H] : set IDST to start measuring.

LDM

:

FUNC,#0000_1001b;INT3 SET

IDCR,#1001_0001b ;64uSec PCS

4. Counter value is stored to IDR [00FB_H] when selected

edge is detected. After data was written, timer is cleard au-

tomatically and it counts continue.

:

60

November 2001 Ver 1.1

HMS81C4x60

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00F9_H

INITIAL VALUE: 0001 -000_b

FCLR

IM S

I34H

I34L

-

ISEL

IDCK

IDST

IDCR

MSB

LSB

Counter control

0 : Stop

1 : Clear & Count

Sample Clock Select

0 : PS9(128uSec)

1 : PS8(64uSec)

External Interrupt Select

0 : INT3 fixed

External Interrupt Edge Select

00 : No Select

01 : Falling Edge

10 : Rising Edge

11 : Both Edge

Interrupt Mode

0 : Every Selected Edge by I34H/L

1 : Every FIFO 4Level is Filled

FIFO Clear

0 : Ignored

1 : Clear & Return to 0

Figure 15-2 Int. interval determination control register

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 00FA_H

INITIAL VALUE: 0--- -001_b

DPO L

FO E

FFUL FEM P

IDFS

MSB

LSB

FIFO Empty Flag

0 : Data Filled

1 : Empty

FIFO Full flag

0 : Not Full

1 : Full

FIFO Overrun Error Flag

0 : No Error

1 : Error Detected

Data Polarity

0 : Data is stored every falling edge

1 : Data is stored every rising edge

Figure 15-3 Port function select register

W

ADDRESS: 00CE_H

INITIAL VALUE: --00 000-_b

-

EC3S

EC2S INT3S INT2S INT1S

-

FUNC

MSB

LSB

R24/INT3 Select

0 : R23

1 : INT3

Figure 15-4 Port function select register

November 2001 Ver 1.1

61

HMS81C4x60

ADDRESS: 00FB_H

INITIAL VALUE: Undefined

IDR

c

e

R

Interrupt input

d

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

f

Figure 15-6 INT. interval determination FIFO data

register

Detecting

edge

Item

Symbol I34H

I34L

1

0

1

Rising edge

Frame Cycle

Falling

edge

1

Both edge

Pulse width

Figure 15-5 Setting for measurement

1) FIFO storing mechanism

FEMP=1, FFUL=0

FEMP=0, FFUL=0

Data 1

FEMP=0, FFUL=1

Data 1

FEMP=0, FFUL=1

Data 1

Data 2

Data 3

Data 2

Data 3

Data 4

Data 5

Data 4

Data 5

Data 6

Data 7

Data in

Data 6 will be erased.

FOE=1 (Over run error)

2) FIFO reading mechanism

Read out

FEMP=0

FEMP=1

FEMP=0

Data 1

Data 2

Figure 15-7 Example for FIFO operating mechanism

62

November 2001 Ver 1.1

HMS81C4x60

16. Buzzer driver

The Buzzer driver circuit is shown in Figure 16-1.

register controls source clock and output frequency.

The Buzzer driver circuit consists of the 6bit counter, 6bit

comparator, Buzzer data register BUR(00EE_H). The BUR

The more details about registers are shown Figure 16-2 .

Data Bus

8

BUR write

BUCK BUCK

BU5 BU4 BU3 BU2

BU1 BU0

BUR [EE_H]

1

0

6

BUZZ

6bit Comparator

Output

Generator

clear

PS7

6

00

01

10

11

PS8

PS9

6bit counter

clear

PS10

MUX

PWMCR1

TM R1 BUZ

EN5

EN4

EN3

EN2

EN1

EN0

Figure 16-1 Block Diagram of Buzzer driver circuit

Control

3. Set BUZ bit for output enable.

The HMS81C4x60 contains a Buzzer driver module.

4. Output waveform is rectagle clock which has 50% duty.

5. You can use this clock for the other purposes.

1. Select an input clock among PS7~PS10 by set the

BUCK1~0 of BUR.

ADDRESS : 0EE_H

RESET VALUE : ???? ????_b

BUCK1

BUCK0

Clock source

PS7

Buzzer data Register

W

0

1

0

1

0

1

BUR

BUCK1 BUCK0 BU5 BU4 BU3 BU2

BU0

BU1

PS8

Input select

Buzzer count data

PS9

ADDRESS : 0EA_H

RESET VALUE : 0000 0000_b

PWM control Register 1

PS10

RW

PWMCR1

TM R1 BUZ

EN5

EN4

EN3

EN2

EN1

EN0

2. Select output frequency by change the BU5~0.

Output frequency = 1 / (PSx × BUy × 2) Hz.

x=7~10, y=5~0

R36/Buzz select

0: R36

1: Buzz output

See example Table 16-1.

Figure 16-2 Buzzer driver Registers

Note: Do not select 00_Hto BU5~0. It means counter stop.

November 2001 Ver 1.1

63

HMS81C4x60

BUR5~0

Output frequency (KHz)

PS8 PS9

PS7

PS10

Dec Hex

(32 S)

(64 S)

(128 S)

(256 S)

µ

1

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

31.25

62.50

125.0

62.5

41.744

31.252

25.0

20.832

17.858

17.628

13.884

12.5

250.0

125.0

83.488

62.504

50.0

41.664

35.716

35.256

27.768

25.0

2

15.625

10.436

7.813

6.25

31.25

20.872

15.626

12.50

10.416

8.928

8.814

6.942

6.25

3

4

5

6

5.208

4.464

3.907

3.472

3.125

2.841

2.604

2.404

2.242

2.083

1.953

1.838

1.736

1.644

1.562

1.438

1.420

1.359

1.302

1.25

1.202

1.158

1.116

1.078

1.042

1.008

0.976

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

0.548

0.539

0.530

0.521

0.512

0.504

0.496

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

5.682

5.208

4.808

4.484

4.166

3.906

3.676

3.472

3.288

3.124

2.876

2.840

2.718

2.604

2.50

2.404

2.316

2.232

2.156

2.084

2.016

1.952

1.894

1.838

1.786

1.736

1.690

1.644

1.602

1.562

1.524

1.488

1.454

1.420

1.388

1.358

1.33

1.302

1.276

1.25

1.226

1.202

1.18

1.158

1.136

1.116

1.096

1.078

1.06

1.042

1.024

1.008

0.992

12.364

10.416

9.616

8.968

8.332

7.812

7.342

6.944

6.576

6.248

5.752

5.680

5.436

5.208

5.0

4.808

4.632

4.464

4.302

4.168

4.032

3.904

3.788

3.676

3.552

3.472

3.380

3.288

3.204

3.124

3.048

2.978

2.908

2.840

2.776

2.706

2.66

2.604

2.542

2.5

2.452

2.404

2.36

2.316

2.272

2.232

2.192

2.156

2.12

2.084

2.048

2.016

1.984

24.728

20.832

19.232

17.936

16.664

15.624

14.684

13.888

13.152

12.496

11.504

11.360

10.872

10.416

10.0

9.616

9.262

8.928

8.604

8.336

8.064

7.808

7.576

7.352

7.104

6.944

6.760

6.576

6.408

6.248

6.096

5.956

5.816

5.680

5.552

5.412

5.320

5.208

5.184

5.0

4.904

4.808

4.720

4.632

4.544

4.464

4.384

4.312

4.24

4.168

4.096

4.032

3.968

Table 16-1 . Example for f_ex=4MHz

64

November 2001 Ver 1.1

HMS81C4x60

17. On Screen Display (OSD)

The HMS81C4x60 can support 512 OSD chacters and font

size is used 12×10, 12×12, 12×14, 12×16, 16×18. It can

support 48 character columns and 2 line buffers respective-

ly and also support full screen OSD when use interrupt.

Each characters have bit plane of 24bit and support at-

tribute with OSD line and full screen OSD respectively.

OSD circuit consists of the Position attribute register, Line

register, Full screen screen control register, I/O polarity

register, font ROM, VRAM, etc. On Screen Display block

diagram is shown in Figure 17-1 and the more details about

display characters are shown in Figure 17-2.

Line 1,2 Attribute,

Position register

Full screen control

register

Display On/Off Control

register

Line register

I/O Porarity Rigister

OSDCON3 [AE2_H]

OSDLN [AE5_H]

OSDCON1 [AE0_H]

OSDCON2 [AE1_H]

L1ATTR [AF0_H]

L1VPOS [AF1_H]

L2ATTR [AF3_H]

L2VPOS [AF4_H]

Horizontal position register

LHPOS [AE6_H]

Field detection register

FDWSET [AE3_H]

Edge color register

EDGECOL [AE4_H]

OSD Control

Circuit

R

G

B

Color Pallet

DAC

VRAM

Font ROM

Output

Control

Circuit

YS

OSD Generation Circuit

YM

dot clock

HSYNC

VSYNC

Synchronization

Circuit

PLL

Xin

Figure 17-1 Block Diagram of On Screen Display circuit

November 2001 Ver 1.1

65

HMS81C4x60

[12 10 Character Font]

×

[12 12 Character Font]

×

- italic (only 12 12 mode can be supported)

×

[12 14 Character Font]

×

Foreground Character

- 512 color (8 pallet)

- color selecting : VRAM n-character bit 19~16

Background

- 512 color (8 pallet)

- color selecting : VRAM n-character bit 23~20

Foreground Character outline

- setting by LnATTR register

- color selecting : EDGECOL register

[12 16 Character Font]

×

Character shadow

- setting by LnATTR register and VRAM n-character bit 9

- color selecting : EDGECOL register

Background shadow color

- setting by VRAM n-character bit 15~12

- color selecting : EDGECOL register

- 512 color (8 pallet)

[16 18 Character Font]

×

OSD background shadow

- Character flash

- background underline

Figure 17-2 OSD Character Font Example

66

November 2001 Ver 1.1

HMS81C4x60

17.1 Feature of OSD

The Feature of OSD shown in below.

- Font pixel matrix

- Character size

: 3 fonts(2 times, 1.5 times, 1 times)

: 12×10, 12×12, 12×14, 12×16, 16×18 dots

- The number of font pattern

- Progressive scan line switch

- Attribute

: 512 fonts

: Outline, Shadow, Rounding

- RGB DAC

- Display ability

: 48Character × n lines (multilined by OSD interrupt)

- 8 foreground pallet of 512 colors for each character

- 8 background pallet of 512 colors for each character

- Full screen 8 background color

: 8 level each color

- Display clock frequency

: 12MHz ~ 64MHz

17.2 OSD Registers

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0AE0_H

INITIAL VALUE: 0000 0000_b

FSBC3 FSBC2 FSBC1 FSBC0 PRSCN DLINE DDCLK STO CK

OSDCON1

MSB

LSB

Stop OSD clock

0 :Release OSD clock

1 : Stop OSD clock

Double dot clock mode

0 : Normal

1 : Double

Double scan line mode

0 : Normal

1 : Double

Progressive scan line mode

0 : Interace mode

1 : Progressive mode

Full screen background color register

0000 : Transparency

0001 : Half blank

0010 : white

0011 : Black

0111 ~ 0100 : Reserved

1000 : color 0

1001 : color 1

1010 : color 2

1011 : color 3

1100 : color 4

1101 : color 5

1110 : color 6

1111 : color 7

Figure 17-3 OSD Control Registers - 1

OSDCON1

If you set this bit to 1, OSD input clock is divided by two ,

than it makes OSD horisontal image size as doubled.

bit 0: STOCK

bit 2: DLINE

It stop or start OSD clock. If oscillation is stoped, IC’s

power consumption is decreased.

If you set this bit to 1, OSD vertical scan counter input

clock is doubled from normal state. It makes OSD vertical

bit 1: DDCLK

November 2001 Ver 1.1

67

HMS81C4x60

image size as doubled.

bit 3: PRSCN

bit 7~4: FSBC3 ~ FSBC0

It controls full screen background color as figure shows.

NOTE:

It control progressive scan line mode.

Data slicer operate when OSDCON1.PRSCN(0AE0.3) bit of OSD register is

cleared. Namely, it operate interace scan display mode.

bit clear than interace mode and bit set than processive

mode.

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0AE1_H

INITIAL VALUE: 0000 0000_b

FLART O BGW

FS3

FS2

FS1

FS0

O LN O SDON

OSDCON2

MSB

LSB

On/off of all OSD

0 :Off

1 : On

On OSD line1 and line2

0 : Off OSD line

1 : On OSD line

Font size

0000 : 12 16

×

0001 : 12 14

×

0010 : 12 12

×

0011 : 12 10

×

0111 ~ 0100 : Reseved

1000 : 16 18

×

1111 ~ 1001 : Reserved

12/14 dot background width of 1 OSD character

0 : 12 dot

1 : 14 dot

Flash rate when closed caption decoder is used

0 : 32 Vsync is one period

1 : 64 Vsync is one period

Figure 17-4 OSD Control Register - 2

It controls OSD font size.

OSDCON2

bit 0: OSDON

bit 6: OBGW

It controls OSD, Full screen background at once. It does

not affect anything to Vsync interrupt and OSD interrupt,

etc.

It controls dot background width. Default width is 12dots.

If its value is set, 2 dots (background color) are added both

left and right side of character.

bit 1: ONL

bit 7: FLRAT

It controls OSD line1 and line2 on/off. If its value is 1,

OSD line is on.

It controls OSD flash rate when closed caption decoder is

used. Bit clear than 32 Vsync is one period and bit set than

64 Vsync is one period.

bit 2 ~ 5: FS0 ~ FS3

68

November 2001 Ver 1.1

HMS81C4x60

W

ADDRESS: 0AE2_H

INITIAL VALUE: 0000 0000_b

SELCK1

SELCK2 ONDAC POLRG POLYM

POLYS

POLHS

POLVS

OSDCON3

MSB

LSB

Vsync polarity

0 : Active low

1 : Active high

Hsync polarity

0 : Active low

1 : Active high

YS polarity

0 : Active low

1 : Active high

YM polarity

0 : Active low

1 : Active high

RGB pin polarity

0 : Active low

1 : Active high

On/Off of RGB DAC

0 : Off

1 : On

Select dot clock

00 : Clock from DLL

01 : Clock from LC OSC for EVA only

10 : Clock 1 for test

11 : Reserved

Figure 17-5 I/O Polarity(Initial) Register

OSDCON3

It controls Hsync/Vsync polarity, YS/YM polarity, RGB

polarity, RGB DAC on/off and select dot clock.

bit7~0 : SELCK1, SELCK0, ONDAC, POLRG, POLYM,

POLYS, POLHS, POLVS

W

ADDRESS: 0AE3_H

INITIAL VALUE: 0111 1010_b

FM AX3 FM AX2 FM AX1 FM AX0 DBFLG FM IN2 FM IN1 FM IN0

FDWSET

MSB

LSB

Field Detection Min. Pointer

Field Detection Polarity

0 : Masking between Min. and Max.

1 : Detect between Min. and Max.

Field Detection Max. Pointer

Field Detection Window:

( {1’b0, (FMIN2 ~ FMIN0)} < hptr[10:7] < (FMAX3 ~ FMAX0))

FDWSET

window.

FDWSET (Field Detection Window Setting) register de-

tects the begin of Vsync(Vertical Sync.) signal and distin-

guishs its current field is Even field or Odd field.

FMAX[3:0] can divide the region between Hsync(Hori-

zontal Sync.) by 16 windows. You can assume there is 4

bit horizontal counter, for example HCOUNT[3:0](hptr[10

:7]) which count 0~15.

The region of FMIN[2:0] ~ FMAX[3:0] is field detection

November 2001 Ver 1.1

69

HMS81C4x60

If the start of Vsync is detected at the window, next field is

even. Else if Vsync is detected another region of the win-

dow, next field is odd.

Ex1: VSync(Odd)

It means start of Vsync is detected during FMIN[2:0] <

HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 0, it

distinguish odd field.

Ex2: VSync(Even)

HSync

And, start of Vsync is detected during FMIN[2:0] <

HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 1, it

distinguish even field.

FMIN

FMIN[2:0], FMAX[3:0] are compared with the horizontal

counter in OSD block.

FMAX

Figure 17-6 FDWSET detection region

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0AE4_H

INITIAL VALUE: 1000 0111_b

EDG2C3 EDG2C2 EDG2C1 EDG2C0 EDG1C3 EDG1C2 EDG1C1 EDG1C0

EDGECOL

MSB

LSB

Edge 1 color of shadow, outline, edge

0000 : Transparency

0001 : Reserved

0010 : white

0011 : Black

0100 : Same as foreground character color

0111 ~ 0101 : Reserved

1000 : color 0

1001 : color 1

1010 : color 2

1011 : color 3

1100 : color 4

1101 : color 5

1110 : color 6

1111 : color 7

Edge 2 color of shadow, outline, edge

0000 : Transparency

0001 : Reserved

0010 : white

0011 : Black

0100 : Same as foreground character color

0111 ~ 0101 : Reserved

1000 : color 0

1001 : color 1

1010 : color 2

1011 : color 3

1100 : color 4

1101 : color 5

1110 : color 6

1111 : color 7

Figure 17-7 Character, Window color Register

EDGECOL

It control shadow color, outline color and edge color.

bit 7 ~ bit 0 : EDG1C0,EDG1C1,EDG1C2,EDG1C3

EDG2C0,EDG2C1,EDG2C2,EDG2C3

Low 4 bits controls edge 1 shadow, outline color and high

4 bits controls edge 2 shadow, outline color.

70

November 2001 Ver 1.1

HMS81C4x60

W

ADDRESS: 0AE5_H

INITIAL VALUE: Undefined

W INC3 W INC2 W INC1 W INC0 SHEC3 SHEC2 SHEC1 SHEC0

CHEDCL

MSB

LSB

Foreground shadow, outline edge color

0000 : Transparency

0001 : Reserved

0010 : white

0011 : Black

0100 : Same as foreground character color

0111 ~ 0101 : Reserved

1000 : color 0

1001 : color 1

1010 : color 2

1011 : color 3

1100 : color 4

1101 : color 5

1110 : color 6

1111 : color 7

Scroll window background color

0000 : Transparency

0001 : Reserved

0010 : White

0011 : Black

0111 ~ 0100 : Reserved

1000 : Color 0

1001 : Color 1

1010 : Color 2

1011 : Color 3

1100 : Color 4

1101 : Color 5

1110 : Color 6

1111 : Color 7

Figure 17-8 Scroll window color Register

CHEDCL

scroll window background color.

bit 7 ~ bit 0 : SHEC0,SHEC1,SHEC2,SHEC3

WINC0,WINC1,WINC2,WINC3

Low 4 bits controls scroll window background color and

high 4 bits controls foreground shadow outline edge color.

It controls foreground shadow and outline edge color and

R

ADDRESS: 0AE6_H

INITIAL VALUE: ---0 0000_H

-

VLR4

VLR3

VLR2

VLR1

VLR0

OSDLN

MSB

LSB

OSD line being displayed

00000 : Not displayed any OSD line yet after Vsync

00001 : 1st line OSD being displayed

.......

11111 : 31st line OSD being displayed

Figure 17-9 OSD Line Register

OSDLN

bit 4 ~ bit 0 : VLR4 ~ VLR0

ADDRESS: 0AE7_H

INITIAL VALUE: Undefined

LHPOS

It shows current display OSD line from 1 to 31.

W

LH7

LH6

LH5

LH4

LH3

LH2

LH1

LH0

MSB

LSB

OSD Line Horizontal Position 00_H~ FF_H

November 2001 Ver 1.1

71

HMS81C4x60

Figure 17-10 OSD Line Horizontal Position Register

It control OSD line horizontal position. Position value

from 00h to FFh.

LHPOS

bit 7 ~ bit 0 : LH7 ~ LH0

W

ADDRESS: 0AE8_H

INITIAL VALUE: 0000 0000_H

DCKF4 DCKF3 DCKF2 DCKF1 DCKF0

-

DLLMOD

MSB

LSB

1 : OSD test mode

1 : Dll test mode

1 : Reset clock count test mode

Dot clock frequency

R

ADDRESS: 0AE9_H

INITIAL VALUE: --00 0000_H

-

DLLTST

MSB

LSB

Figure 17-11 DLL mode Register

DLLMOD

Value

Frequency

bit 2 ~ 0 : If you set this bit to 1, the status is changed test

mode.

DCKF4 DCKF4 DCKF4 DCKF4 DCKF4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

21.33MHz

19.69MHz

18.29MHz

17.07MHz

16.00MHz

15.05MHz

14.22MHz

13.47MHz

12.80MHz

12.19MHz

11.63MHz

11.13MHz

10.67MHz

reserved

bit 7 ~ bit 3 : DCKF4 ~ DCKF0

It control dot clock frequency.

Dot clock frequency is as below.

Value

Frequency

DCKF4 DCKF4 DCKF4 DCKF4 DCKF4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

stop dll clock

reserved

64.00MHz

51.20MHz

42.67MHz

36.57MHz

32.00MHz

28.44MHz

25.60MHz

23.27MHz

Table 17-1 Dot Clock Frequency (f_ex=4Mhz)

72

November 2001 Ver 1.1

HMS81C4x60

W

ADDRESS: 0AEA_H

INITIAL VALUE: 0000 0000_H

O BG H1 W DSL1 ENOL1 ENSH1 CSZ11 CSZ10 FSC1

L1V8

L1ATTR

MSB

LSB

OSD line 1 vertical position (bit 8)

Foreground shadow or outline color select

0 : Edge 1 color

1 : Edge 2 color

Size of character

00 : Normal

01 : 1.5 times

10 : 2 times

11 : Reserved

Enable/disable of shadow

0 : Disable

1 : Enable

Enable/disable of outline

0 : Disable

1 : Enable

Width of shadow, outline

0 : 1 dot

1 : Proportional to character size

OSD chraracter background height

0 : font height

1 : font height + 2

Figure 17-12 OSD line 1 attribute register

L1ATTR

bit 4: ENSH1

bit 0 : L1V8

It enables line 1’s character(foreground) shadow.

bit 5: ENOL1

It is equivalent to L1VPOS’s most significant bit(bit 8).

See more details in L1VPOS.

It enables line 1’s character(foreground) outline.

bit 6: WDSL1

bit 1: FSC1

It selects character outline and shadow color. If it is 1, it se-

lect EDGE2 color of EDGECOL register. Or not, it select

EDGE1 color. According to EDGECOL register and this

bit character and shadow colors are selected simulteneous-

ly

It shows thickness of line 1’s shadow and outline.This bit

is set than one dot and bit clear is proportional to character

size. If only character size is 2 times, 2 times per vertically

and horizontally. In case 1 dot width would be enable.

bit 7: OBGH1

bit 3~2: CSZ11~CSZ10

It controls character’s background height. Default height is

16dots. If its value is set, 2 dots (background color) are

added both top and bottom side of character.

It controls OSD character’s size ( normal, 1.5 times, 2

times). You can use this register and DDCLK, DLINE bit,

horizontal / vertical size can be controlled (x1, x1.5, x2).

November 2001 Ver 1.1

73

HMS81C4x60

W

ADDRESS: 0AEB_H

INITIAL VALUE: Undefined

-

SEL1ULSEL1O WSEL1FL SEL1IT SEL1SH

L1EATR

MSB

LSB

Select shadow/round of line 1 each character when

VRAM.ENRND is set.

0 : round character

1 : shadow character

Select italic/upper edge of line 1 each character.

Italic character can be displayed only when character

size is 1, 1.5 times, and VRAM.BSU is set.

0 : Upper edge character

1 : Italic character

Select flash/left edge of line 1 character when

VRAM.BSL is set.

0 : Left edge character

1 : Flash

Select OSD/window when display. If this bit is 0,

background window would be displayed.

0 : Background window selected

1 : OSD line selected

Select underline /lower edge of line 1 each character

0 : Underline

1 : Lower edge line

L1EATR

L1ATTR.

It shows OSD line 1 extend attribute register.

ADDRESS: 0AEE_H

INITIAL VALUE: Undefined

L2EATR

ADDRESS: 0AEC_H

INITIAL VALUE: Undefined

W

L1VPOS

-

SEL2ULSEL2O WSEL2FL SEL2IT SEL2SH

W

MSB

LSB

LIV7

LIV6

LIV5

LIV4

LIV3

LIV2

LIV1

LIV0

MSB

LSB

OSD line 1 vertical position 000_H~ 1FF_H

L2EATR

It shows OSD line 2’s extened attribute register.

L1VPOS

It shows OSD line 1’s vertical position in 9bit format

(LIV8 + L1VPOS, 000 ~ 1FF_H).

ADDRESS: 0AEF_H

INITIAL VALUE: Undefined

L2VPOS

W

L2V7

L2V6

L2V5

L2V4

L2V3

L2V2

L2V1

L2V0

ADDRESS: 0AED_H

L2ATTR

MSB

LSB

INITIAL VALUE: Undefined

W

OBG H2 W DSL2 ENO L2 ENSH2 CSZ22 CSZ21 FSC2

L2V2

L2VPOS

MSB

LSB

It shows OSD line 2’s vertical position. Its function is the

same as L1VPOS.

L2ATTR

It shows OSD line 2’s attributes. Its function is the same as

74

November 2001 Ver 1.1

HMS81C4x60

ADDRESS: 0AF0_H

INITIAL VALUE: Undefined

ADDRESS: 0AF4_H

INITIAL VALUE: Undefined

WINSH

VCNT

W

R

W

R

W INSH7 W INSH6 W INSH5 W INSH4 W INSH3 W INSH2 W INSH1 W INSH0

VCNT6 VCNT6 VCNT6 VCNT6 VCNT6 VCNT6 VCNT6 FLDID

MSB

LSB

MSB

LSB

Current scan line line vertical position [6:0]

OSD scroll window start horizontal position

Current display field

0 : Odd field

1 : Even field

WINSH

It shows OSD scroll window start horizontal position.

VCNT

It shows Vsync count register and counted by pixel clock.

VCNT counter clock start at Vsync start edge.

ADDRESS: 0AF1_H

INITIAL VALUE: Undefined

WINSY

W

WINSY7 WINSY6 WINSY5 WINSY4 WINSY3 WINSY2 WINSY1 WINSY0

MSB

LSB

ADDRESS: 0AF5_H

INITIAL VALUE: Undefined

HCNT

OSD scroll window start vertical position

R

HCNT7 HCNT6 HCNT5 HCNT4 HCNT3 HCNT2 HCNT1 HCNT0

MSB

LSB

WINSY

Horizontal counter hptr[10:3]

It shows OSD scroll window start vertical position.

HCNT

ADDRESS: 0AF2_H

INITIAL VALUE: Undefined

WINEH

It shows Hsync count register and counted by pixel clock.

HCNT counter clock start at Hsync start edge.

W

W INEH7 W INEH6 W INEH5 W INEH4 W INEH3 W INEH2 W INEH1 W INEH0

MSB

LSB

OSD scroll window end horizontal position

ADDRESS: 0AF9_H

CULTAD

INITIAL VALUE: Undefined

W

WINEH

-

FIL15

-

MSB

LSB

It shows OSD scroll window end horizontal position.

Normal/Test mode select

00 : Normal mode

01 ~ 11 : Test mode

ADDRESS: 0AF3_H

INITIAL VALUE: Undefined

1.5 times character mode

0 : line double mode 1.5 times

WINEY

1 : field interleaving mode 1.5 times

W

WINEY7 WINEY6 WINEY5 WINEY4 WINEY3 WINEY2 WINEY1 WINEY0

MSB

LSB

CULTAD

It shows normal and test mode and 1.5 times mode.

OSD scroll window end vertical position

WINEY

It shows OSD scroll window end vertical position.

November 2001 Ver 1.1

75

HMS81C4x60

17.3 VRAM

VRAM contains a OSD line buffer, 48 character’s at-

tributes.

Bit

No.

Name

Function

Each character’s attribute is constructed with 3 bytes, it

contains color data for background, shadow, outline, char-

acter and character number ( 000_H~ 1FF_H, 512 characters

), etc.

Edge color of lower and right

background shadow edge

0 : edge 1 color

0B

BSCDR

1 : edge 2 color

Background shadow upper eddge

control/italic depend on

LxEATR.SELxIT

Line Character

Address (bit 47~0)

Hexa decimal

No.

add. No.

0 : disable

0C

BSU

1 : enable

1

2

A80

A40

A41

A42

:

A00

if(LxEATR.SELxIT == 0) background

shadow upper edge enable

else(LxEATR.SELxIT == 1) italic

enable

A81

A82

:

A01

A02

:

3

1

:

Background shadow lower edge

control/underline depend on

LxEATR.SELxUL

0 : disable

1 : enable

if(LxEATR.SELxUL == 0)

background shadow lower edge

enable

46

47

48

1

AAD

AAE

AAF

B80

B81

B82

:

A6D

A6E

A6F

B40

B41

B42

:

A2D

A2E

A2F

B00

B01

B02

:

0D

BSD

2

else(LxEATR.SELxUL ==

1)underline enable

3

Background shadoww left edge

control/flash(blInking) depend on

LxEATR.SELxFL

0 : disable

1 : enable

if(LxEATR.SELxFL == 0) background

shadow left edge enable

else(LxEATR.SELxFL == 1)

flash(flicking) enable

2

:

46

47

48

BAD

BAE

BAF

B6D

B6E

B6F

B2D

B2E

B2F

0E

0F

BSL

BSR

Table 17-2 VRAM memory map

Background shadow right edge

control

0 : disable

1 : enable

Bit

No.

Name

Function

FC3

~FC0

Foreground color for character (11

colors)

10~13

14~17

CG8

~CG0

Character font code

1FFh ~ 000h

00~08

09

BC3

~BC0

Background color for character (12

colors)

Round enable/disable

0 : disable

ENRND

BSCUL

Table 17-3 VRAM attribute

1 : enable

Edge color of upper and left

background shadow edge

0 : edge 1 color

0A

1 : edge 2 color

76

November 2001 Ver 1.1

HMS81C4x60

RESET VALUE: Undefined

Composition of VRAM

0A80 0A40 0A00 Character 1 Attr.

0A81 0A41 0A01 Character 2 Attr.

LINE 1

(page A)

0A82 0A42 0A02

Character 3 Attr.

:

Character 48 Attr.

0AAF 0A6F 0A2F

0B80 0B40 0B00 Character 1 Attr.

0B81 0B41 0B01 Character 2 Attr.

LINE 2

(page B)

0B82 0B42 0B02

Character 3 Attr.

:

Character 48 Attr.

0BAF 0B6F 0B2F

CG 8

CG 7

CG 6

CG 5

CG 4

CG 3

CG 2

CG 1

CG 0

Character font address (512 fonts)

BSR

BC3

BSL

BC2

BSD

BC1

BSU BSCDR BSCUL ENRND CG 8

see table 17-3 VRAM attribute

BC0

FC3

FC2

FC1

FC0

Character color select (11 characters)

0000 : Transparency

0001 : Reserved

0010 : White

0011 : Black

0111 ~ 0100 : Reserved

1000 : Color 0

1001 : Color 1

1010 : Color 2

1011 : Color 3

1100 : Color 4

1101 : Color 5

1110 : Color 6

1111 : Color 7

Background color select (12 characters)

0000 : Transparency

0001 : Reserved

0010 : White

0011 : Black

0111 ~ 0100 : Reserved

1000 : Color 0

1001 : Color 1

1010 : Color 2

1011 : Color 3

1100 : Color 4

1101 : Color 5

1110 : Color 6

1111 : Color 7

November 2001 Ver 1.1

77

HMS81C4x60

17.4 Character ROM

The HMS81C4x60 Character ROM are used 512 types of

Font Dot Pattern data. As displayed one character, need 12

× 10 ~ 16 × 18bits Dot Pattern data.

5. A character’s address and dot position in font ROM is

described in Figure 17-13.

1. Each horizontal data (12dots) needs 2bytes ROM.

16 × 18

12 × 14

2. One character is constructed with 16 horizontal data to

vertically. As a result, one character needs 32bytes (2 × 16

bytes).

Left

address

Right

address

14060

14061

14062

14063

14064

14065

14066

14067

14068

14069

1406A

1406B

1406C

1406D

1406E

1406F

14070

14071

14072

14073

14074

14075

14076

14077

14078

14079

1407A

1407B

1407C

1407D

1407E

1407F

10060

10061

10062

10063

10064

10065

10066

10067

10068

10069

1006A

1006B

1006C

1006D

1006E

1006F

10070

10071

10072

10073

10074

10075

10076

10077

10078

10079

1007A

1007B

1007C

1007D

1007E

1007F

3. HMS81C4x60 contains 512 characters. Total Font

ROM memory size is calculated as 16,384bytes ( 32bytes

/ character × 512 characters )

4. Font ROM memory is located from 10000_H~ 17FFF_H,

this memory can not be accessed by user program.

Address range

Charact

er code

Upper 8bit

14000_H~ 14011_H

14020_H~ 14031_H

14040_H~ 14051_H

:

Lower 8bit

10000_H~ 10011_H

10020_H~ 10031_H

10040_H~ 10051_H

:

000_H

001_H

002_H

:

(14000H + xyz0H) ~ (10000H + xyz0H) ~

(14000H + 2*xyzFH) (10000H + 2*xyzFH)

xyz_H

:

1FD_H

1FE_H

1FF_H

17FA0_H~ 17FB1_H

17FC0_H~ 17FD1_H

17FE0_H~ 17FF1_H

13FA0_H~ 13FD1_H

13FC0_H~ 13FD1_H

13FE0_H~ 13FF1_H

Figure 17-13 Character Dot Pattern

Table 17-4 Font ROM memory map

78

November 2001 Ver 1.1

HMS81C4x60

17.5 Color Look Up Table

[Example] Color data table

Color_example_table:

db 0000_0000b ;color 0 = Gray

db 0000_0011b ;color 1 = Red

db 0010_1011b ;color 2 = Green

;

RESET VALUE : Undefined

W

7

W

6

W

5

W

4

W

3

W

2

W

1

W

0

RED0

<0AD0_H>

R07 R60

R71 R62

R72 R62

G70 G60

G71 G61

G72 G62

R50

R51

R52

G50

G51

G52

B50

B51

B52

R40

R41

R42

G40

G41

G42

B40

B41

B42

R30

R20

R10

R11

R12

G10

G11

G12

B10

B11

B12

R00

R01

R02

G00

G01

G02

B00

B01

B02

db 0000_0000b ;color 3 = Yellow

db 0000_0101b ;color 4 = Blue

db 0100_1101b ;color 5 = Magenta

;

db 0000_0000b ;color 6 = Cyan

db 1001_0001b ;color 7 = half blue

db 1111_0001b

RED1

<0AD1_H>

R31

R21

RED2

<0AD2_H>

R32 R22

GREEN0

<0AD3_H>

G30

G31

G32

B30

B31

B32

G20

G21

G22

B20

B21

B22

GREEN1

<0AD4_H>

GREEN2

<0AD5_H>

BLUE0

<0AD6_H>

B70

B71

B72

B60

B61

B62

BLUE1

<0AD7_H>

BLUE2

<0AD8_H>

Composition of color 7

Composition of color 6

Composition of color 0

Composition of color 1

Composition of color 2

Composition of color 5

Composition of color 4

Composition of color 3

Red : {R02,R01,R00}

Green : {G02,G01,G00}

Blue : {B02,B01,B00}

Figure 17-14 Color look up table

November 2001 Ver 1.1

79

HMS81C4x60

18. DATA SLICER

HMS81C4x60 supports Closed Caption decoding standard

with 0.5MHz data rate. Also it can capture 4 horizontal

lines information per frame, because it has 4 horozontal

lines capture memory. It is able to select even or odd field

at one field interval. Data Slicer captures caption informa-

tion from line 21 in vertical blanking interval of CVBS,

and stores these data to buffer memory.

18.1 Data Slicer Circuit

Figure 18-1 shown the data slicer circuit.

CVBS signal is entered to CVBS pin via 0.47uF capacitor.

The black level of signal is about 2V. SCAP pin is connect-

ed to external 560pF capacitor which adjust the referance

voltage of comparator. Its slicer level is adapted to input

signal.

SCAP

560pF

CVBS

0.47uF

HMS81C4x60

Figure 18-1 Data Slicer Circuit

18.2 Configuration of Data Slicer

Figure 18-2 shows the block diagram of the Data Slicer.

Run-in key timing

Sync-tip timing

CPU control

Timing

Controller

Data capture

timing

CVBS

Memory

Interface

Controller

Data

Filter

Slicer

Memory

Reference

Voltage

Figure 18-2 Data Slicer Block Diagram

This data slicer block separates caption information from

CVBS signal. Data slicer composes high speed comparator

and on-chip low pass filter. The output data of comparator

is stored in memory through the filter and memory inter-

face controller, which should be decoded to caption data

by software. Slicer memory addressed 600h ~ 6FFh.

80

November 2001 Ver 1.1

HMS81C4x60

18.3 Slicer Registers

Slicer Control Register

which select operating frequency of the slicer, slicer de-

coding method and switch slicer on/off.

Slicer Control Register is the specific control register,

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0BE0_H

INITIAL VALUE: 0000 0000_b

-

RIKTST SELCK

-

DEM E1 DEM E0 SLO N

SLCON

MSB

LSB

Slicer On/Off

0 : Slicer Off

1 : Slicer On

Decoding Method

00 : Normal

01 : Reserved

10 : Reserved

11 : Reversed

Slicer Clock

0 : Normal clock

1 : Test clock

RIK slicer test mode

00 : Normal clock

01 : Reserved

10 : Reserved

11 : Reserved

Figure 18-3 Slicer Control Register

buffer of line 0 and slicer line 0 position. Also it is used to

Slicer Information Register 0

select line number in Vertical blanking interval.

Slicer Information Register 0 selects even or odd field

W

ADDRESS: 0BE1_H

INITIAL VALUE: 0000 0000_b

LFC0

SLINF0

SLPOS0

MSB

LSB

Line0 enable

00 : disable all line 0

01 : reserved

10 : reserved

11 : enable all line 0 (even and odd field)

Slicer line 0 position

Figure 18-4 Slicer Information Register 0

buffer of line 1 and slicer line 1 position. Also it is used to

Slicer Information Register 1

select line number in Vertical blanking interval.

Slicer Information Register 1 selects even or odd field

W

ADDRESS: 0BE2_H

INITIAL VALUE: 0000 0000_b

LFC1

SLINF1

SLPOS1

MSB

LSB

Line 1 Field

00 : disable all line 1

01 : reserved

10 : reserved

11 : enable all line 1 (even and odd field)

Slicer line 1 position

Figure 18-5 Slicer Information Register 1

November 2001 Ver 1.1

81

HMS81C4x60

Run-in key Start/End position Register

Both timmings are counted up by 8MHz clock. The refer-

ance voltage of comparator is charged by external signal

during this time interval. Figure 18-6 and Figure 18-7

shows the RIK register’s configure.

RIKST points the start postion of run-in key, it is delayed

from start edge of Hsync. RIKED points the end position

of run-in key, it is also delayed from start edge of Hsync.

W

ADDRESS: 0BE3_H

INITIAL VALUE: XXXX XXXX_b

RIKST7 RIKST6 RIKST5 RIKST4 RIKST3 RIKST2 RIKST1 RIKST0

RIKST

MSB

LSB

Run-in key window start position

Figure 18-6 Run-in key Start Position Register

W

ADDRESS: 0BE4_H

INITIAL VALUE: XXXX XXXX_b

RIKED7 RIKED6 RIKED5 RIKED4 RIKED3 RIKED2 RIKED1 RIKED0

RIKED

MSB

LSB

Run-in key window end position

Figure 18-7 Run-in key End Position Register

16MHz clock. Figure 18-8 and Figure 18-9 shows the

Sync Start/End Position Register

Sync-tip register’s configure.

Sync Start and End position Register are used to make

Sync tip window. Both timmings are counted up by

W

ADDRESS: 0BE7_H

INITIAL VALUE: XXXX XXXX_b

SNCST7 SNCST6 SNCST5 SNCST4 SNCST3 SNCST2 SNCST1 SNCST0

SNCST

MSB

LSB

Sync-tip window start position

Figure 18-8 Sync-tip start position register

W

ADDRESS: 0BE8_H

INITIAL VALUE: XXXX XXXX_b

SNCED7 SNCED6 SNCED5 SNCED4 SNCED3 SNCED2 SNCED1 SNCED0

SNCED

MSB

LSB

Sync-tip window end position

Figure 18-9 Sync-tip end position register

82

November 2001 Ver 1.1

HMS81C4x60

18.4 Data Sampling

Line 21 Closed Caption signal

Interrupt occurrence

Figure 18-10 shows the closed caption signal. The signal

composes color burst, clock run-in, start bit(001), 16bit

ASCII data with 2 parity bit. Sliced raw datas are sampled

by 4MHz frequency.

The slicer interrupt is occured after writing the sliced two

lines data to memory buffer.

Signal timing

Figure 18-11 shows an example of variable signals, which

includes Vsync(vertical Sync.), Hsync(horizontal Sync.),

CVBS(composit video in), SCAP(slicer capacitor), Run-in

key and Sync tip. Line 21 closed caption signal run after

Vsync interrupt. The signal’s black(base) level voltage is

charged on Sync-tip switch-on period, and the referance

voltage of comparator is charged on RIK switch-on perid.

Because RIK time is related to SCAP voltage(comparator

referance voltage or slicer level) which is charged by clock

run-in signal, user can adjust the slicer level by RIK time.

The sliced data is stored to RAM buffer. (0600h~ 06FFh)

[ CAPTION DATA ]

CLOCK RUN IN

TWO (7 BIT + PARITY )

CHARACTERS

( DATA )

program

color

burst

START BIT(001)

12.91us

33.76us

3.972us

51.26us

61.342us

Figure 18-10 Closed caption signal

Address assign

Table 18-1 shows the map of assigned buffer memory.

Setting

Even Field

Address

0600h ~ 063Fh

0640h ~ 067Fh

0680h ~ 06BFh

06C0h ~ 06FFh

First Line

Odd Field

Even Field

Odd Field

Secont Line

Table 18-1 Address assign

November 2001 Ver 1.1

83

HMS81C4x60

5V

1

Vsync

Hsync

CVBS

SCAP

RIK

5V

2

1 Hsync cycle

5V

2.5V

2V

line 21 signal

2.2V

0.5V

Slicer capacitor charging level

Run-in key start/stop timming

5V

3

0V

5V

Sync-tip start/stop timming

4

Sync_tip

0V

Figure 18-11 Signal timing

[Example]

Initializing slicer register.

CCD_INIT: LDM

SLINF0,#0011_0011b

SLINF1,#0000_0000b

RIKST,#01

; slicer line 21

; no field

LDM

; run-in key start : 1 -> 0.125uS(8MHz)

RIKED,#8Ch

; run-in key end : 8ch -> 17.5uS(8MHz)

; sync tip start : 1 -> 0.0625uS(16MHz)

; sync tip end : 58h -> 5.5uS(16MHz)

; normal clock, 16MHz, slicer start

SNCST,#01

SNCED,#58h

SLCON,#01h

84

November 2001 Ver 1.1

HMS81C4x60

2

19. I C Bus Interface

The I²C Bus interface circuit is shown in Figure 19-1.

This multi-master I²C Bus interface circuit consists of the

I²C address register, the I²C data shift register, the I²C

clock control register, the I²C control register, the I²C sta-

tus register and other control circuits.

The multi-master I²C Bus interface is a serial communica-

tions circuit, conforming to the Phlips I²C Bus data trans-

fer format. This interface, offering both arbitration lost

detection and a synchronous functions, is useful for the

multi-master serial communications.

The more details about registers are shown Figure 19-2~

Figure 19-5.

SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb

ICAR [D8_H]

Address

comparator

Interrupt

IFI2CR

Generation

Circuit

D7

D6

D5

D4

D3

D2

D1

D0

ICDR [D9_H]

SDA

Data

Control

Circuit

Noise

Elimination

Circuit

MST TRX

BB

AL

AD0 ADRb LRB

ICSR [00DA_H]

BB

Circuit

AL

Circuit

BSEL1 BSEL1 ACKb ESO CCR3 CCR2 CCR1 CCR0

ICCR [00DB_H]

SCL

Clock

Control

Circuit

Noise

Elimination

Circuit

Clock Source

Clock division

Figure 19-1 Block Diagram of multi-master I²C circuit

I²C address register

Control

The HMS81C4x60 contains two I²C Bus interface mod-

ules. It supports multi-master function, so it contains arbi-

tration lost detection, synchronization function,etc.

It contains slave address (7bit) which is used during slave

mode and Read/Write bit.

Bit 7 ~ 1 : Slave address 6~0

ITEM

Function

Philips I²C standard

Note: Bit 7~1 (SAD6~0) store slave address. The address

data transmitted from the master is compared with the con-

tents of these bits.

Format

7bit addressing format

Master transmitter

Communication Master receiver

mode

Slave transmitter

Slave receiver

November 2001 Ver 1.1

85

HMS81C4x60

The more details about its bits are shown Table 19-1.

ADDRESS : 00D8_H

Bit

No.

RESET VALUE : 0000 0000_b

Name

Function

RW

R

SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb

ICAR

00: Slave / Receiver mode

01: Slave / Transmitter mode

10: Master / Receiver mode

11: Master / Transmitter mode

MST is cleared when

Slave address

Read/Write Bit

Figure 19-2 I²C address Register

- After reset.

- After the arbitration lost is occured and

1 byte data transmission is finished.

I²C data shift register [ICDR]

7

6

MST - After stop condition is detected.

TRX

- When start condition is disabled by

start condition duplication preventation

function.

The I²C data shift register is an 8bit shift register to store

received data and write transmit data.

TRX is cleared when

- After reset.

- When arbitration lost or stop condition

is occured .

- When MST is ‘0’, and start condition

or ACK non-return mode is detected.

When transmit data is written into this register, it is trans-

fered to the outside from bit7 in synchronization with the

SCL clock, and each time one-bit data is output, the data of

this register are shifted one bit to the left. When data is re-

ceived, it is input to this register from bit0 in synchroniza-

tion with the SCL clock, and each time one-bit data is

input, the data of this register are shifted one bit to the left.

BB(Bus busy)bit is 1 during bus is busy.

This bit can be written by S/W. its value

is ‘1’ by start condition, and cleared by

stop condition.

5

BB

The I²C data shift register is in a write enable status only

when the ESO bit of the I²C control register (address

00DC_H) is “1”. The bit counter is reset by a write instruc-

tion to the I²C data shift register. Reading data from the

I²C data shift register is always enabled regardless of the

ESO bit value.

PIN(Pending Interrupt Not)bit is inter-

rupt request bit.

If I²C interrupt request is issued, its

value is 0.

PIN is cleared when

- After 1 byte trasmission / receive is fin-

ished.

PIN is set when

- After reset.

ADDRESS : 00D9_H

RESET VALUE : 0000 0000_b

RW

D7

RW

D6

RW

D5

RW

D4

RW

D3

RW

4

D2

D1

D0

ICDR

Shift left 1-bit each SCL

- After write instruction is excuted into

I²C data shift register ICDR.

- When PIN bit low, the output of SCL is

pulled down, So if you want to release

SCL, you must perform write instruction

CDR.

Figure 19-3 Data shift register

I²C status register

The I²C status register controls the I²C Bus interface sta-

tus. The low-order 4bits are read only bits and the high-or-

der 4bits can be read out and written to.

Arbitration lost detection flag.

If arbitration lost is detected, AL=1, or 0.

3

2

AL

General call detection flag.

If general call is detected, AD0=1, or

not 0.

AD0

* General call : If received address is all

‘0’ . it is called general call.

Address represent flag

1

ADRb

0 : current contents is address

1 : current contents is data

86

November 2001 Ver 1.1

HMS81C4x60

Bit

No.

Name

Function

Last received bit.

Bit

No.

Name

Function

0

LRB

it is used for receive confirmation. If

ACK is returned, LRB=0, or not 1.

I²C connection control.

00: No connection

01: SCL0, SDA0

7

6

BSEL1

BSEL0

Table 19-1 Bit function

10: SCL1, SDA1

11: SCL0, SDA0, SCL1, SDA1

If acknowlege clock is returned, this bit

is 0, or not 1.

ADDRESS : 00DA_H

5

4

ACK

ESO

RESET VALUE : 0001 0000_b

RW

BB

RW

R

I²C Bus interface use enable flag

0: Disabled

MST TRX

AL

AD0 ADRb LRB

ICSR

1: Enabled

Figure 19-4 I²C status Register

SCL Frequency selection

SCL frequency = f_ex/ (12 * CCR)

I²C control register

f_ex= 4MHz

Value

It controls communication data format.

It controls SCL mode, SCL frequency, etc.

0000 Not allowed

0001 Not allowed

0010 333.3KHz

0011 222.2KHz

0100 166.6KHz

0101 133.3KHz

0110 111.1KHz

0111 95.2KHz

1000 83.3KHz

1001 74.1KHz

1010 66.6KHz

1011 60.6KHz

1100 55.5KHz

1101 51.3KHz

1110 47.6KHz

1111 44.4KHz

It contains 8bit data to transmit to external device when tr-

asmitter mode, or received 8bit data from external device

when receive mode.

3

2

1

0

CCR3

CCR2

CCR1

CCR0

ADDRESS : 00DB_H

RESET VALUE : 0000 0000_b

RW

ICCR

BSEL1 BSEL0 ACKb ESO CCR3 CCR2 CCR1 CCR0

Figure 19-5 I²C control Register

Table 19-2 Bit function

SCL

I²C Request

Figure 19-6 Interrupt request signal generation timing

November 2001 Ver 1.1

87

HMS81C4x60

START condition generation

STOP condition generation

When the ESO bit of the I²C control register (00DB_H) is

“1”, writing to the I²C status register will generate START

condition. Refer to Figure 19-7 for the START condition

generation timing diagram.

Writing ‘C0h’ to ICSR will generate a stop condition,

w h e n E S O ( I C C R b i t 3 ) i s ‘ 1 ’

ICSR write signal

(I²C status reg.)

SCL

t_SETUP

t_HOLD

ICSR write signal

(I²C status reg.)

SDA

t_BB

SCL

t_SETUP

t_HOLD

BB (Bus busy) flag

SDA

t_BB

t_SETUP: Setup time

t_HOLD: Hold time

BB (Bus busy) flag

t_BB

: Set time for BB

t_SETUP: Setup time

t_HOLD: Hold time

Figure 19-8 STOP condition generating timing diagram

t_BB

: Set time for BB

START / STOP condition generation time is shown Table

19-3.

Figure 19-7 START condition generation timing

ITEM

Timing SPEC.

Setup time

3.3uS (n=20cycles)

RESTART condition generation

( t_SETUP

)

RESTART condition’s setting sequence is as followings.

1. Write 020_Hto I²C status register (ICSR, 00DA_H)

Hold time

3.3uS (n=20cycles)

3.0uS (n=18cycles)

( t_HOLD

)

Set/Reset time for

BB flag ( t_BB

2. Write slave address to I²C data shift register (ICDR,

00D9_H)

)

Table 19-3 Example time ( f_ex=4MHz )

3. Write 0F0_Hto I²C status register (ICSR, 00DA_H)

88

November 2001 Ver 1.1

HMS81C4x60

Figure 19-9 START / STOP condition detection timing

START / STOP condition detect

START / STOP condition is detected when Table 19-3 is

satisfied.

START / STOP detection time is showed Table 19-4.

ITEM

SCL release time

Setup time

Timing SPEC.

> 2.0uS (n=12cycles)

> 1.0uS (n=6cycles)

SCL release time

SCL

Hold time

t_SETUP

t_HOLD

Table 19-4 Example time ( f_ex=4MHz )

SDA (START)

SDA (STOP)

Address data communication

The first transmitted data from master is compared with

I²C address register (ICAR, 00D8_H). At this time R/W is

not compared but it determines next data operation. i.e,

transmitting or receiving data

t_SETUP: Setup time

t_HOLD: Hold time

Master -> Slave (with 7bit address)

ACK

/ACK

ACK

START Slave addr.

7bit

ACK Data

Data

STOP

R/W

(“0”)

Slave -> Master (with 7bit address)

Data block from master to slave

Data block from slave to master

ACK

START Slave addr.

7bit

ACK Data

Data

STOP

ACK

R/W

(“1”)

Figure 19-10 Address data communication format

November 2001 Ver 1.1

89

HMS81C4x60

20. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction

such as endless looping caused by noise or the like, and re-

sumes the CPU to the normal state.

When the watchdog timer is not being used for malfunc-

tion detection, it can be used as a timer to generate an in-

terrupt at fixed intervals.

The watchdog timer signal for detecting malfunction can

be selected either a reset CPU or a interrupt request.

6-bit up-counter

Clock source

WDT

(BIT overflow : IFBIT)

clear

comparator

IFWDT

Watchdog Timer interrupt

6-bit compare data

6

to reset CPU

enable

WDTCL[bit6]

WDTR[bit5~0]

WDTON[bit5]

CKCTLR

WDTR

Watchdog Timer Register

Clock control Register

[00D7_H]

[00D6_H]

Figure 20-1 Block Diagram of Watchdog Timer

Watchdog Timer Control

ADDRESS : 00D6_H

Figure 20-2 shows the watchdog timer control register.

The watchdog timer is automatically disabled after reset.

RESET VALUE : 0000 0000_b

W

R

WDT ENP

BTCL BTS2 BTS1 BTS0

CKCTLR

ON

CK

The CPU malfunction is detected as setting the detection

time, selecting output, and clearing the binary counter. Re-

peatedly clearing the binary counter within the setting de-

tection time.

Watchdog timer On/Off control

0: Normal 6bit timer, Watchdog off

1: Watchdog timer

ADDRESS : 00D7_H

RESET VALUE : -011 1111_b

If the malfunction occurs for any cause, the watchdog tim-

er output will become active at the rising overflow from

the binary counters unless the binary counter are cleared.

At this time, when WDTON=1 a reset is generated, which

drives the RESET pin low to reset the internal hardware.

When WDTON=0, a watchdog timer interrupt (IFWDT) is

generated.

W

WDT

CL

WDTR

Slave address

Watchdog timer Clear

0: Watchdog timer free run

1: Watchdog timer clear and free run

Automatically cleared this bit after 1cycle

Figure 20-2 Watchdog timer register

90

November 2001 Ver 1.1

HMS81C4x60

Example: Sets the watchdog timer detection time

LDM WDTR,#01??????b

;Clear Counter and set value(??????b)

;You have to set WDTR first, for prevent unpredictable interrupt

;when you set WDTON bit.

LDM CKCTLR,#00111???b

;Select clock source(???b) and WDTON=1

LDM WDTR,#01??????b

;Clear counter

Within WDT

detection time

:

LDM WDTR,#01??????b

Within WDT

detection time

:

LDM WDTR,#01??????b

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 5 in

CKTCLR) to "1". WDTON is initialized to "0" during re-

set, WDTON should be set to "1" to operate after reset is

released.

Example: 6-bit timer interrupt setting up.

LDX

TXSP

LDM

:

#03FH

;SP← 3F

CKTCLR,#000?????b ;WDTON←0

WDTR,#01??????b ;WDTCL←0

Example: Enables watchdog timer reset

:

LDM

:

CKTCLR,#001?????b ;WDTON←1

Refer table and see BIT timer ().

:

Watchdog

timer input IFWDT cycle

CKCTLR

BTS2~0

BIT input

clock

The watchdog timer is disabled by clearing bit 5 (WD-

TON) of CKTCLR.

clock

000_b

001_b

010_b

011_b

100_b

101_b

110_b

111_b

PS4 (4uS)

PS5 (8uS)

1,024uS

2,028uS

4,096uS

8,192uS

16,384uS

32,768uS

32,256uS

64,512uS

Watchdog Timer Interrupt

PS6 (16uS)

PS7 (32uS)

PS8 (64uS)

PS9 (128uS)

129,024uS

258,048uS

516,096uS

1,032,192uS

2,064,384uS

The watchdog timer can also be used as a simple 6-bit tim-

er by clearing bit 5 (WDTON) of CKTCLR. The interval

of watchdog timer interrupt is decided by Basic Interval

Timer.

Interval equation is shown as below.

PS10 (256uS) 65,536uS

T = WDTR × Interval of BIT

PS11 (512uS) 131,072uS 4,128,768uS

Table 20-1 Watchdog timer MAX. cycle (Ex:f_ex=4MHz)

The stack pointer (SP) should be initialized before using

the watchdog timer output as an interrupt source.

November 2001 Ver 1.1

91

HMS81C4x60

Source clock

BIT overflow

3

0

2

0

1

2

1

Binary-counter

Counter

Clear

n

3

WDTR

Match

Detect

IFWDT interrupt

WDTR ← "0100_0011b"

WDT reset

reset

Figure 20-3 Watchdog timer Timing

Minimizing Current Consumption

that if unspecified voltage, i.e. if unfirmed voltage level is

applied to input pin, there can be little current (max. 1mA

at around 2V) flow.

It should be set properly that current flow through port

doesn't exist.

If it is not appropriate to set as an input mode, then set to

output mode considering there is no current flow. Setting

to High or Low is decided considering its relationship with

external circuit. For example, if there is external pull-up re-

sistor then it is set to output mode, i.e. to High, and if there

is external pull-down register, it is set to low. See Figure

20-4.

First conseider the setting to input mode. Be sure that there

is no current flow after considering its relationship with

external circuit. In input mode, the pin impedance viewing

from external MCU is very high that the current doesn’t

flow.

But input voltage level should be V_SSor V_DD. Be careful

92

November 2001 Ver 1.1

HMS81C4x60

OUTPUT PIN

ON

INPUT PIN

V_DD

ON

internal

pull-up

OPEN

O

OFF

O

i

V_DD

GND

V_DD

GND

ON

X

OFF

OPEN

Weak pull-up current flows

O

In the left case, much current flows from port to GND.

V_DD

INPUT PIN

OUTPUT PIN

V_DD

L

i=0

L

ON

OFF

ON

OPEN

O

i

i=0

OFF

i

GND

Very weak current flows

i=0

X

GND

X

O

In the left case, Tr. base current flows from port to GND.

To avoid power consumption, low output to the port .

O

When port is configured as an input, input level should

be closed to 0V or 5V to avoid power consumption.

Figure 20-4 Application example of Port under Power Consumption

November 2001 Ver 1.1

93

HMS81C4x60

21. OSCILLATOR CIRCUIT

The HMS81C4x60 has two oscillation circuits internally.

display) frequency, respectively, of a inverting amplifier

which can be configured for use as an on-chip oscillator, as

shown in Figure 21-1 .

X

_INand X_OUTare input and output for main frequency and

OSC1 and OSC2 are input and output for OSD(On Screen

Recommend

fc (MHz) C1 & C2 (pF)

C1

X_OUT

4

15

C2

fc (MHz)

X_IN

V_SS

Crystal Oscillator

Open

X_OUT

X_IN

External Clock

External Oscillator

Figure 21-1 Oscillation Circuit

Oscillation components have their own characteristics, so

user should consult the component manufacturers for ap-

propriate values of external components.

In addition, see Figure 21-2 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow wiring to in-

tersect with other signal conductors. Do not allow wiring to

come near changing high current. Set the potential of the

X_OUT

X_IN

SS

grounding position of the oscillator capacitor to that of V .

Do not ground to any ground pattern where high current is

present. Do not fetch signals from the oscillator.

Figure 21-2 Layout example of Oscillator PCB circuit

94

November 2001 Ver 1.1

HMS81C4x60

22. RESET

The HMS81C4x60 have two types of reset generation pro-

cedures; one is an external reset input, other is a watch-dog

timer reset. Table 22-1 shows on-chip hardware initializa-

tion by reset action.

On-chip Hardware

Initial Value

On-chip Hardware

Peripheral clock

Initial Value

(FFFF_H) - (FFFE_H)

Program counter

PC

DPGR

G

Off

Disable

00_H

0

RAM page register

G-flag of PSW

Watchdog timer

Control registers

Refer to Table 8-1 on page 22

Table 22-1 Initializing Internal Status by Reset Action

22.1 External Reset Input

The reset input is the RESET pin, which is the input to a

Schmitt Trigger. A reset in accomplished by holding the

RESET pin low for at least 8 oscillator periods, within the

operating voltage range and oscillation stable, a reset is ap-

plied and the internal state is initialized. After reset, 64ms

(at 4 MHz) add with 7 oscillator periods are required to

start execution as shown in Figure 22-2 .

A connecting for simple power-on-reset is shown in Figure

22-1 .

V_DD

RESET

Internal RAM is not affected by reset. When V_DDis turned

on, the RAM content is indeterminate. Therefore, this

RAM should be initialized before reading or testing it.

+

−

MCU

GND

When the RESET pin input goes high, the reset operation

is released and the program execution starts at the vector

address stored at addresses FFFE_H- FFFF_H.

Figure 22-1 Simple Power-on-Reset Circuit

1

2

3

4

5

6

7

Oscillator

(X pin)

IN

RESET

Fetch

ADDRESS

BUS

FFFE FFFF Start

?

DATA

BUS

OP

ADH

FE

ADL

?

MAIN PROGRAM

RESET Process Step

1

Stabilization Time

_ST= 62.5mS at 4.19MHz

t

t_ST

=

x 256

f_MAIN1024

÷

Figure 22-2 Timing Diagram after RESET

November 2001 Ver 1.1

95

HMS81C4x60

22.2 Watchdog Timer Reset

Refer to “20. WATCHDOG TIMER” on page 90.

96

November 2001 Ver 1.1

HMS81C4x60

23. OTP Programming

23.1 HMS87C4x60 OTP Programming

User can burn out HMS87C4x60 OTP through the general

Gang programmer using special ROM writer. In Devleop-

ment tool package auxiliary, HMS87C4x60 has ROM

writer socket. HMS87C4x60 have two ROM memory ar-

eas. One is Program ROM memory and the other is Font

ROM memory. Program ROM area is from 1000h to

FFFFh Font ROM area is from 10000h to 17FFFh.

Program Writing

There are two kind of OTP file. One is program OTP

file(***.OTP) and the other is font OTP file(***.FNT).

You can make each file through ASMLINKER.exe and

OSDFONT.exe respectively. All OTP file is Motolora S-

format. You can burn the program file and font file respec-

tively or together. To burn program file and font file re-

spectively, refer following procedure

Blank Check

1. Make program OTP file and font OTP file repec-

tively.

1000H

2. Burn program OTP file(Set chip target address

1000h ~ FFFFh)

3. Burn font OTP file(Set chip target address 10000h

~17FFFh)

Program

Memory

To burn program file and font file together, refer following

procedure

FFFFH

1. Add program OTP file and font OTP file

OSD Font

Memory

2. Burn OTP file(Set chip target address 1000h ~

17FFFh)

17FFFH

About other details, refer ROM wirter manual.

Figure 23-1 HMS87C4x60 OTP Memory Map

November 2001 Ver 1.1

97

HMS81C4x60

23.2 .Device Configuration Data

OM1

1

2

3

4

5

6

7

8

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

OM2

OM3

PGMB

DIO<6>

DIO<5>

9

VPP

A16

DIO<4>

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

DIO<0>

DIO<1>

DIO<2>

DIO<3>

OEB

CEB

AHB

DIO<7>

ALB

32SDIP

Figure 23-2 Figure Pin Configuration in OTP Programming Mode

HMS87C4x60

Mode

Program

VPP

11.25

5

CEB

Low

OEB

High

Low

High

Low

PGMB

Low

High

X

Verify

Optional Verify

Gang Write

Gang Verify

11.25

11.25, 5

Low

X

Figure 23-3 Figure Mode Table

98

November 2001 Ver 1.1

HMS81C4x60

24. Assemble mnemonics

24.1 Instruction Map

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

SET1 BBS

BBS

dp.bit,rel

ADC

#imm

ADC

dp

ADC

dp+X

ADC

!abs

ASL

A

ASL TCALL

BIT

dp

POP PUSH

SETA1

.bit

NOP

BRK

000

001

010

dp.bit

A.bit,rel

dp

0

A

SBC

#imm

SBC

dp

SBC

!abs

ROL

A

ROL TCALL CLRA1 COM

POP

BRA

rel

SBC

dp+X

PUSH

//

CLRC

CLRG

X

dp

2

.bit

dp

X

CMP

#imm

CMP

dp

CMP

dp+X

CMP

!abs

LSR

A

LSR TCALL NOT1 TST

POP PUSH PCALL

//

dp

4

M.bit

dp

Y

Upage

OR1

OR

#imm

OR

dp

OR

dp+X

OR

!abs

ROR

A

ROR TCALL

POP PUSH

CMPX

dp

//

DI

RET

011

100

101

dp

6

PSW

OR1B

AND1

AND

#imm

AND

dp

AND

dp+X

AND

!abs

INC

A

INC TCALL

CMPY CBNE

dp

INC

X

//

CLRV

SETC

TXSP

dp

8

dp+X

AND1B

EOR1

EOR

#imm

EOR

dp

EOR

dp+X

EOR

!abs

DEC

A

DEC TCALL

DBNE XMA

dp

DEC

X

TSPX

dp

10

dp+X

EOR1B

LDC

LDA

#imm

LDA

dp

LDA

dp+X

LDA

!abs

LDY TCALL

LDX

dp

LDX

dp+Y

//

SETG

EI

TXA

TAX

XCN

XAS

DAS

110

111

dp

12

LDCB

LDM

dp,#imm

STA

dp

STA

dp+X

STA

!abs

STY TCALL STC

STX

dp

STX

dp+Y

dp

14

M.bit

10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

BPL

rel

CLR1 BBC

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL

!abs

ASL TCALL

BIT ADDW LDX

JMP

[!abs]

JMP

!abs

000

001

010

011

100

101

110

111

dp.bit

A.bit,rel

dp+X

1

!abs

dp

#imm

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp]+Y

ROL

!abs

ROL TCALL CALL TEST SUBW

JMP

[dp]

SBC

[dp+X]

LDY

//

#imm

dp+X

3

!abs

dp

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR

!abs

LSR TCALL

TCLR1 CMPW CMPX CALL

//

MUL

dp+X

5

!abs

dp

#imm

[dp]

BNE

rel

OR

{X}

OR

!abs+Y

OR

[dp+X]

OR

[dp]+Y

ROR

!abs

ROR TCALL DBNE

LDYA CMPY

CMPX

RETI

!abs

dp+X

7

Y

dp

#imm

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC TCALL

CMPY INCW

INC

DIV

TAY

TYA

DAA

NOP

dp+X

9

!abs

dp

Y

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC TCALL XMA

XMA DECW DEC

dp+X

11

{X}

dp

Y

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY

!abs

LDY TCALL LDA

LDX STYA

XAY

dp+X

13

{X}+

!abs

dp

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY

!abs

STY TCALL STA

STX CBNE

XYX

dp+X

15

{X}+

!abs

dp

November 2001 Ver 1.1

99

HMS81C4x60

24.2 Alphabetic order table of instruction

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

ADC #imm

OPERATION

CODE

NVGBHIZC

1

04

05

06

07

15

16

17

14

1D

84

85

86

87

95

96

97

94

8B

08

09

19

18

y2

y3

x2

x3

2

3

2

1

2

3

2

1

3

1

2

3

2

3

2

3

2

3

Add with carry.

A + (M) + C

2

ADC dp

A ←

3

ADC dp + X

ADC !abs

4

NV - - H - ZC

N - - - - - Z -

5

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

5

6

7

6

8

3

9

ADDW dp

AND #imm

AND dp

5

16-bits add without carry : YA

Logical AND

YA + (dp+1)(dp)

←

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

2

3

A ^ (M)

A ←

AND dp + X

AND !abs

4

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

5

6

3

AND1 M.bit

AND1B M.bit

4

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

←

4

Bit AND C-flag and NOT : C

Arithmetic shift left

C ^ ~(M.bit)

←

ASL

A

2

ASL dp

4

C

7 6 5 4 3 2 1 0

← ← ← ← ← ← ← ← ← ← "0"

N - - - - - ZC

- - - - - - - -

ASL dp + X

ASL !abs

5

BBC A.bit,rel

BBC dp.bit,rel

BBS A.bit,rel

BBS dp.bit,rel

4/6

5/7

4/6

5/7

Branch if bit clear :

if(bit) = 0, then PC

Branch if bit clear :

if(bit) = 1, then PC

PC + rel

←

- - - - - - - -

Branch if carry bit clear :

if(C) = 0, then PC PC + rel

28

BCC rel

50

2

2/4

MM - - - - Z -

←

29

30

31

32

33

34

35

36

37

BCS rel

BEQ rel

BIT dp

BIT !abs

BMI rel

BNE rel

BPL rel

BRA rel

BRK

D0

F0

0C

1C

90

70

10

2F

0F

2

3

2

1

2/4

4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

←

Branch if equal : if (Z) = 1, then PC

Bit test A with memory :

PC + rel

←

MM - - - - Z -

Z

A ^ M, N

(M ), V ← (M )

←

7 6

←

5

2/4

4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

←

Branch if not equal : if (Z) = 0, then PC

PC + rel

←

Branch if not minus : if (N) = 0, then PC

PC + rel

←

Branch always : PC

Software interrupt:

PC + rel

←

8

B

“1”, M(SP)

(PC ), SP

SP - 1,

←

H

- - - 1 - 0 - -

M(s)

(PC ), SP

S - 1, M(SP)

PSW,

←

L

SP

SP - 1, PC

(0FFDE ), PC

(0FFDF )

←

H

←

L

H

38

39

BVC rel

BVS rel

30

B0

2

2/4

Branch if overflow bit clear :

If (V) = 0, then PC PC + rel

- - - - - - - -

←

Branch if overflow bit set :

If (V) = 1, then PC

Subroutine call

PC + rel

←

40

41

CALL !abs

CALL [dp]

3B

5F

3

2

8

M(SP)

(PC ), SP

SP-1, M(SP)

(PC ), SP SP-1

← ←

L

←

- - - - - - - -

H

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

←

L

H

42

43

44

45

46

47

CBNE dp,rel

CBNE dp + X, rel

CLR1 dp.bit

CLR1A A.bit

CLRC

FD

8D

y1

3

2

1

5/7

6/8

4

Compare and branch if not equal ;

If A (M), then PC

PC + rel.

≠

←

Clear bit : (M.bit)

“0”

- - - - - - - -

- - - - - - - 0

- - 0 - - - - -

←

2B

20

40

2

Clear A.bit : (A.bit)

“0”

←

2

Clear C-flag : C

Clear G-flag : G

“0”

←

CLRG

2

100

November 2001 Ver 1.1

HMS81C4x60

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

CLRV

OPERATION

CODE

NVGBHIZC

48

49

50

51

52

53

54

55

56

57

80

44

45

46

47

55

56

57

54

5D

1

2

3

2

1

2

3

4

5

6

3

4

Clear V-flag : V

“0”

- 0 - - 0 - - -

←

CMP #imm

CMP dp

Compare accumulator contents with memory contents

A - (M)

CMP dp + X

CMP !abs

N - - - - - ZC

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPW dp

Compare YA contents with memory pair contents :

YA - (dp+1)(dp)

N - - - - - ZC

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

CMPX #imm

CMPX dp

CMPX !abs

CMPY #imm

CMPY dp

CMPY !abs

COM dp

5E

6C

7C

7E

8C

9C

2C

DF

CF

AC

7B

A8

A9

B9

B8

AF

BE

BD

60

9B

E0

A4

A5

A6

A7

B5

96

97

94

AB

88

89

99

98

8F

9E

9D

1B

1F

3F

2

3

2

3

2

1

3

2

1

2

3

1

2

1

2

3

2

1

3

1

2

3

1

2

3

2

3

Compare X contents with memory contents

X - (M)

4

2

Compare Y contents with memory contents

Y - (M)

3

4

1’s complement : (dp)

~(dp)

N - - - - - Z -

N - - - - - ZC

←

DAA

3

Decimal adjust for addition

DAS

3

Decimal adjust for substraction

Decrement and branch if not equal :

DBNE dp,rel

DBNE Y,rel

5/7

4/6

2

- - - - - - - -

if (M) 0, then PC

PC + rel.

←

≠

DEC

A

Decrement

DEC dp

4

M

M - 1

←

DEC dp + X

DEC !abs

5

N - - - - - Z -

5

DEC

X

Y

2

DECW dp

DI

6

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

- - - - - 0 - -

NV - - H - Z -

- - - - - 1 - -

←

3

Disable interrupts : I

“0”

←

DIV

12

3

Divide : YA / X

Q:A, R:Y

←

EI

Enable interrupts

Exclusive OR

:

I

“1”

←

EOR #imm

EOR dp

2

3

A

(M)

←

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

EOR1 M.bit

EOR1B M.bit

4

N - - - - - Z -

5

6

3

5

Bit exclusive-OR C-flag : C

C

(M.bit)

- - - - - - - C

N - - - - - ZC

←

5

Bit exclusive-OR C-flag and NOT : C

Increment

C

(M.bit)

←

INC

A

2

INC dp

4

(M)

(M) + 1

←

INC dp + X

INC !abs

5

N - - - - - Z -

INC

X

Y

2

INCW dp

JMP !abs

JMP [!abs]

JMP [dp]

6

Increment memory pair : (dp+1)(dp)

Unconditional jump

{(dp+1)(dp)} + 1

N - - - - - Z -

- - - - - - - -

←

3

5

PC

jump address

←

4

November 2001 Ver 1.1

101

HMS81C4x60

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

99

LDA #imm

LDA dp

C4

C5

C6

C7

D5

D6

D7

D4

DB

CB

E4

1E

CC

CD

DC

3E

C9

D9

D8

7D

48

2

3

2

1

3

2

3

2

3

2

1

2

3

1

3

2

3

2

1

3

2

3

4

5

6

3

4

5

2

3

4

2

3

4

5

2

4

5

9

2

5

2

3

4

5

6

3

5

6

Load accumulator

(M)

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

A

←

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [dp + X]

LDA [dp]+Y

LDA {X}

N - - - - - Z -

LDA {X}+

LDC M.bit

LDCB M.bit

LDM dp,#imm

LDX #imm

LDX dp

X-register auto-increment : A

(M), X

X + 1

←

Load C-flag : C

(M.bit)

- - - - - - - C

- - - - - - - -

←

Load C-flag with NOT : C

~(M.bit)

←

Load memory with immediate data : (M)

Load X-register

imm

←

X

(M)

←

N - - - - - Z -

LDX dp + Y

LDX !abs

LDY #imm

LDY dp

Load X-register

(M)

Y

←

N - - - - - Z -

N - - - - - ZC

LDY dp + Y

LDY !abs

LDYA dp

Load YA

:

YA

(dp+1)(dp)

←

LSR

A

Logical shift right

LSR dp

49

7 6 5 4 3 2 1 0

"0"→ → → → → → → → → →

C

LSR dp + X

LSR !abs

MUL

59

58

5B

00,FF

4B

64

Multiply

:

YA

Y x A

N - - - - - Z -

- - - - - - - -

←

NOP

No operation

NOT1 M.bit

OR #imm

OR dp

Bit complement : (M.bit)

Logical OR

~(M.bit)

←

65

A

A V (M)

←

OR dp + X

OR !abs

OR !abs + Y

OR [dp +X}

OR [dp] + Y

OR {X}

66

67

N - - - - - Z -

75

76

77

74

OR1 M.bit

OR1B M.bit

PCALL

6B

4F

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

←

Bit OR C-flag and NOT : C

C V ~(M.bit)

←

U-page call : M(SP)

(PC ), SP ← SP -1,

←

H

M(SP)

(PC ), SP

SP -1,

←

- - - - - - - -

L

PC_L

(upage), PC

"OFF "

←

H

←

H

138

139

140

141

142

143

144

145

146

POP

A

X

Y

0D

2D

4D

6D

0E

2E

4E

6E

6F

1

4

5

Pop from stack

SP SP + 1, Reg.

M(SP)

SP - 1

- - - - - - - -

(restored)

←

POP PSW

PUSH

A

X

Y

Push to stack

M(SP) Reg. SP

←

- - - - - - - -

PUSH PSW

RET

Return from subroutine :

SP SP+1, PC M(SP), SP

- - - - - - - -

(restored)

SP+1, PC

M(SP)

M(SP),

←

L

H

147

RETI

7F

1

6

Return from interrupt :

SP

SP+1, PSW

M(SP), SP

SP+1,PC

←

L

←

SP+1, PC

H

M(SP)

←

102

November 2001 Ver 1.1

HMS81C4x60

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

OPERATION

Rotate left through carry

CODE

NVGBHIZC

148

149

150

151

152

153

154

ROL

A

28

29

39

38

68

69

79

1

2

3

1

2

4

5

2

4

5

ROL dp

N - - - - - ZC

C

7 6 5 4 3 2 1 0

← ← ← ← ← ← ← ← ←

ROL dp + X

ROL !abs

ROR

A

Rotate right through carry

ROR dp

N - - - - - ZC

7 6 5 4 3 2 1 0

→ → → → → → → → →

C

ROR dp + X

155

ROR !abs

78

3

5

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

SBC #imm

SBC dp

24

25

26

27

35

36

37

34

x1

2

3

2

1

2

1

2

3

2

1

3

2

3

2

3

2

1

2

3

4

5

6

3

4

2

3

4

5

6

3

4

6

4

5

4

5

2

8

Substract with carry

A - (M) - ~(C)

A

←

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [dp + X]

SBC [dp] + Y

SBC {X}

NV - - HZC

SET1 dp.bit

SETA1 A.bit

SETC

Set bit : (M.bit)

“1”

- - - - - - - -

- - - - - - - 1

- - 1 - - - - -

←

0B

A0

C0

E5

E6

E7

F5

F6

F7

F4

FB

EB

EC

ED

FC

E9

F9

F8

DD

3D

E8

9F

nA

Set A.bit : (A.bit)

“1”

←

Set C-flag : C

Set G-flag : G

“1”

←

SETG

“1”

STA dp

Store accumulator contents in memory

(M)

STA dp + X

STA !abs

STA !abs + Y

STA [dp + X]

STA [dp] + Y

STA {X}

A

←

- - - - - - - -

STA {X}+

STC M.bit

STX dp

X-register auto-increment : (M)

A, X

X + 1

←

Store C-flag : (M.bit)

C

- - - - - - - -

←

Store X-register contents in memory

(M)

STX dp + Y

STX !abs

STY dp

X

←

Store Y-register contents in memory

(M)

STY dp + X

STY !abs

STYA dp

SUBW dp

TAX

Y

- - - - - - - -

←

Store YA : (dp+1)(dp)

YA

- - - - - - - -

NV - - H - ZC

N - - - - - Z -

←

16-bits substract without carry : YA

YA - (dp+1)(dp)

←

Transfer accumulator contents to X-register : X

Transfer accumulator contents to Y-register : Y

Table call :

A

←

TAY

A

←

TCALL

n

M(SP)

(PC ), SP

H

SP -1,

SP -1

←

- - - - - - - -

(PC ), SP

L

PC_L

(Table vector L), PC

(Table vector H)

←

H

188

189

TCLR1 !abs

TSET1 !abs

5C

3C

3

6

Test and clear bits with A :

A - (M), (M) (M) ^ ~(A)

N - - - - - Z -

←

Test and set bits with A :

A - (M), (M) (M) V (A)

←

190

191

192

193

194

195

196

TSPX

TST dp

TXA

AE

4C

C8

8E

BF

EE

DE

1

2

1

2

3

2

4

SP

N - - - - - Z -

- - - - - - - -

Transfer stack-pointer contents to X-register : X ←

Test memory contents for negative or zero : (dp) - 00_H

Transfer X-register contents to accumulator : A

X

←

TXSP

TYA

Transfer X-register contents to stack-pointer : SP

X

←

Transfer Y-register contents to accumulator : A

Y

←

XAX

Exchange X-register contents with accumulator : X A

f

XAY

Exchange Y-register contents with accumulator : Y A

- - - - - - - -

f

November 2001 Ver 1.1

103

HMS81C4x60

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

197

XCN

CE

1

5

Exchange nibbles within the accumulator:

N - - - - - Z -

A₇~ A₄

A₃~ A₀

f

198

199

200

201

XMA dp

XMA dp + X

XMA {X}

XYX

BC

AD

BB

FE

2

1

5

6

5

4

Exchange memory contents with accumulator

(M)

A

N - - - - - Z -

- - - - - - - -

f

Exchange X-register contents with Y-register : X

Y

f

24.3 Instruction Table by Function

1. Arithmetic/Logic Operation

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

ADC #imm

OPERATION

1

04

05

06

07

15

16

17

14

84

85

86

87

95

96

97

94

08

09

19

18

44

45

46

47

55

56

57

54

5E

6C

7C

7E

8C

9C

2C

DF

CF

A8

A9

B9

B8

AF

BE

2

3

2

1

2

3

2

1

2

3

2

3

2

1

2

3

2

3

2

1

2

3

1

2

3

4

5

6

3

2

3

4

5

6

3

2

4

5

2

3

4

5

6

3

2

3

4

2

3

4

3

2

4

5

2

Add with carry.

2

ADC dp

A + (M) + C

A ←

3

ADC dp + X

ADC !abs

4

NV - - H - ZC

5

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

6

7

8

9

AND #imm

AND dp

Logical AND

A ^ (M)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

A ←

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

N - - - - - Z -

N - - - - - ZC

ASL

A

Arithmetic shift left

ASL dp

C

7 6 5 4 3 2 1 0

← ← ← ← ← ← ← ← ← ← "0"

ASL dp + X

ASL !abs

CMP #imm

CMP dp

Compare accumulator contents with memory contents

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPX #imm

CMPX dp

CMPX !abs

CMPY #imm

CMPY dp

CMPY !abs

COM dp

Compare X contents with memory contents

X - (M)

N - - - - - ZC

Compare Y contents with memory contents

Y - (M)

1’s complement : (dp)

~(dp)

N - - - - - Z -

N - - - - - ZC

←

DAA

Decimal adjust for addition

Decimal adjust for substraction

Decrement

DAS

DEC

A

DEC dp

M

M - 1

←

DEC dp + X

DEC !abs

N - - - - - Z -

DEC

X

Y

104

November 2001 Ver 1.1

HMS81C4x60

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

DIV

9B

A4

A5

A6

A7

B5

96

97

94

88

89

99

98

8F

9E

48

49

59

58

5B

64

65

66

67

75

76

77

74

28

29

39

38

68

69

79

1

2

3

2

1

2

3

1

2

3

1

2

3

2

1

2

3

1

2

12

2

3

4

5

6

3

2

4

5

2

4

5

9

2

3

4

5

6

3

2

4

5

2

4

5

Divide : YA /

Exclusive OR

Q:A, R:Y

NV - - H - Z -

X ←

EOR #imm

EOR dp

A

(M)

←

EOR dp + X

EOR !abs

N - - - - - Z -

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

INC

A

Increment

(M) (M) + 1

N - - - - - ZC

N - - - - - Z -

INC dp

←

INC dp + X

INC !abs

INC

LSR

X

Y

A

Logical shift right

LSR dp

N - - - - - ZC

N - - - - - Z -

7 6 5 4 3 2 1 0

"0"→ → → → → → → → → →

C

LSR dp + X

LSR !abs

MUL

Multiply

Logical OR

A V (M)

:

YA

Y x A

←

OR #imm

OR dp

A

←

OR dp + X

OR !abs

OR !abs + Y

OR [dp +X}

OR [dp] + Y

OR {X}

N - - - - - Z -

ROL

A

Rotate left through carry

ROL dp

N - - - - - ZC

C

7 6 5 4 3 2 1 0

← ← ← ← ← ← ← ← ←

ROL dp + X

ROL !abs

ROR

A

Rotate right through carry

ROR dp

7 6 5 4 3 2 1 0

→ → → → → → → → →

C

ROR dp + X

79

ROR !abs

78

3

5

80

81

82

83

84

85

86

87

88

89

SBC #imm

SBC dp

24

25

26

27

35

36

37

34

4C

CE

2

3

2

1

2

1

2

3

4

5

6

3

5

Substract with carry

A - (M) - ~(C)

A

←

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [dp + X]

SBC [dp] + Y

SBC {X}

NV - - HZC

Test memory contents for negative or zero : (dp) - 00_H

Exchange nibbles within the accumulator:

TST dp

N - - - - - Z -

XCN

A₇~ A₄

A₃~ A₀

f

November 2001 Ver 1.1

105

HMS81C4x60

2. Register / Memory Operation

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

LDA #imm

OPERATION

CODE

NVGBHIZC

1

C4

C5

C6

C7

D5

D6

D7

D4

DB

E4

1E

CC

CD

DC

3E

C9

D9

D8

E5

E6

E7

F5

2

3

2

1

3

2

3

2

3

2

3

2

1

2

3

2

3

1

2

1

2

3

4

5

6

3

4

5

2

3

4

2

3

4

3

4

5

6

3

4

5

4

5

2

4

5

6

5

4

Load accumulator

A (M)

←

2

LDA dp

3

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [dp + X]

LDA [dp]+Y

LDA {X}

LDA {X}+

LDM dp,#imm

LDX #imm

LDX dp

4

5

N - - - - - Z -

6

7

8

9

X-register auto-increment : A

(M), X

X + 1

←

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Load memory with immediate data : (M)

Load X-register

imm

- - - - - - - -

←

X

(M)

←

N - - - - - Z -

LDX dp + Y

LDX !abs

LDY #imm

LDY dp

Load X-register

(M)

Y

←

N - - - - - Z -

LDY dp + Y

LDY !abs

STA dp

Store accumulator contents in memory

(M)

STA dp + X

STA !abs

STA !abs + Y

STA [dp + X]

STA [dp] + Y

STA {X}

STA {X}+

STX dp

A

←

- - - - - - - -

F6

F7

F4

FB

EC

ED

FC

E9

F9

X-register auto-increment : (M)

A, X

X + 1

←

Store X-register contents in memory

(M)

STX dp + Y

STX !abs

STY dp

X

- - - - - - - -

←

Store Y-register contents in memory

(M)

STY dp + X

STY !abs

TAX

Y

←

F8

E8

9F

Transfer accumulator contents to X-register : X

Transfer accumulator contents to Y-register : Y

Transfer stack-pointer contents to X-register : X ←

Transfer X-register contents to accumulator : A

A

N - - - - - Z -

- - - - - - - -

←

TAY

A

←

TSPX

AE

C8

8E

BF

EE

DE

BC

AD

BB

FE

SP

TXA

X

←

TXSP

Transfer X-register contents to stack-pointer : SP

X

←

TYA

Transfer Y-register contents to accumulator : A

Y

←

XAX

Exchange X-register contents with accumulator : X A

f

XAY

Exchange Y-register contents with accumulator : Y A

- - - - - - - -

f

XMA dp

XMA dp + X

XMA {X}

XYX

Exchange memory contents with accumulator

(M)

A

N - - - - - Z -

- - - - - - - -

f

Exchange X-register contents with Y-register : X

Y

f

3. 16-Bit Operation

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

ADDW dp

OPERATION

CODE

NVGBHIZC

1

2

1D

5D

2

5

4

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

N - - - - - ZC

←

CMPW dp

Compare YA contents with memory pair contents :

YA - (dp+1)(dp)

3

4

DECW dp

INCW dp

BD

9D

2

6

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

{(dp+1)(dp)} + 1

N - - - - - Z -

←

Increment memory pair : (dp+1)(dp)

←

106

November 2001 Ver 1.1

HMS81C4x60

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

LDYA dp

OPERATION

CODE

NVGBHIZC

N - - - - - Z -

- - - - - - - -

5

6

7

7D

DD

3D

2

5

Load YA

:

YA

(dp+1)(dp)

←

STYA dp

SUBW dp

Store YA : (dp+1)(dp)

YA

←

16-bits substract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

←

4. Bit Manipulation

OP

BYTE

NO.

CYCLE

NO

FLAG

NO.

MNENONIC

AND1 M.bit

OPERATION

CODE

NVGBHIZC

1

2

8B

0C

1C

y1

3

2

3

2

1

3

2

1

3

4

5

4

2

5

4

5

4

2

6

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

←

AND1B M.bit

BIT dp

Bit AND C-flag and NOT : C

Bit test A with memory :

C ^ ~(M.bit)

←

3

MM - - - - Z -

Z

A ^ M, N

(M ), V

(M )

6

←

4

BIT !abs

7

5

CLR1 dp.bit

CLR1A A.bit

CLRC

Clear bit : (M.bit)

“0”

- - - - - - - -

- - - - - - - 0

- - 0 - - - - -

- 0 - - 0 - - -

- - - - - - - C

- - - - - - - -

- - - - - - - C

- - - - - - - -

- - - - - - - 1

- - 1 - - - - -

- - - - - - - -

←

6

2B

20

Clear A.bit : (A.bit)

“0”

←

7

Clear C-flag : C

Clear G-flag : G

Clear V-flag : V

“0”

←

8

CLRG

40

9

CLRV

80

10

11

12

13

14

15

16

17

18

19

20

21

22

EOR1 M.bit

EOR1B M.bit

LDC M.bit

LDCB M.bit

NOT1 M.bit

OR1 M.bit

OR1B M.bit

SET1 dp.bit

SETA1 A.bit

SETC

AB

CB

4B

6B

x1

Bit exclusive-OR C-flag : C

C

(M.bit)

←

Bit exclusive-OR C-flag and NOT : C

C

(M.bit)

←

Load C-flag : C

(M.bit)

←

Load C-flag with NOT : C

~(M.bit)

←

Bit complement : (M.bit)

←

Bit OR C-flag : C

C V (M.bit)

←

Bit OR C-flag and NOT : C

C V ~(M.bit)

←

Set bit : (M.bit)

“1”

←

0B

A0

C0

EB

5C

Set A.bit : (A.bit)

“1”

←

Set C-flag : C

Set G-flag : G

“1”

←

SETG

“1”

STC M.bit

TCLR1 !abs

Store C-flag : (M.bit)

C

←

Test and clear bits with A :

A - (M), (M) (M) ^ ~(A)

N - - - - - Z -

←

23

TSET1 !abs

3C

3

6

Test and set bits with A :

A - (M), (M) (M) V (A)

←

5. Branch / Jump Operation

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

1

2

3

4

BBC A.bit,rel

BBC dp.bit,rel

BBS A.bit,rel

BBS dp.bit,rel

y2

y3

x2

x3

2

4/6

5/7

4/6

5/7

Branch if bit clear :

if(bit) = 0, then PC

Branch if bit clear :

if(bit) = 1, then PC

- - - - - - - -

3

PC + rel

←

2

- - - - - - - -

3

Branch if carry bit clear :

if(C) = 0, then PC PC + rel

5

BCC rel

50

2

2/4

MM - - - - Z -

←

6

7

BCS rel

BEQ rel

BMI rel

BNE rel

BPL rel

BRA rel

BVC rel

D0

F0

90

70

10

2F

30

2

2/4

4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

←

Branch if equal : if (Z) = 1, then PC

PC + rel

←

8

Branch if munus : if (N) = 1, then PC

PC + rel

←

9

Branch if not equal : if (Z) = 0, then PC

PC + rel

←

10

11

12

Branch if not minus : if (N) = 0, then PC

PC + rel

←

Branch always : PC

PC + rel

←

2/4

Branch if overflow bit clear :

If (V) = 0, then PC PC + rel

- - - - - - - -

←

13

BVS rel

B0

2

2/4

Branch if overflow bit set :

If (V) = 1, then PC PC + rel

←

November 2001 Ver 1.1

107

HMS81C4x60

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

14

15

CALL !abs

CALL [dp]

3B

5F

3

2

8

Subroutine call

M(SP) (PC ), SP

SP-1, M(SP)

(PC ), SP SP-1

←

L

←

- - - - - - - -

H

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

←

L

H

16

17

18

19

20

21

22

23

CBNE dp,rel

CBNE dp + X, rel

DBNE dp,rel

DBNE Y,rel

JMP !abs

FD

8D

AC

7B

1B

1F

3F

4F

3

2

3

2

5/7

6/8

5/7

4/6

3

Compare and branch if not equal ;

If A (M), then PC PC + rel.

- - - - - - - -

≠

←

Decrement and branch if not equal :

if (M) 0, then PC

PC + rel.

←

≠

Unconditional jump

JMP [!abs]

JMP [dp]

5

PC

jump address

- - - - - - - -

←

4

U-page call : M(SP)

(PC ), SP

H

SP -1,

←

PCALL

6

←

M(SP)

(PC ), SP

SP -1,

←

L

PC_L

(upage), PC

"OFF "

←

H

←

H

24

TCALL

n

nA

1

8

Table call :

M(SP)

(PC ), SP

H

SP -1,

SP -1

←

- - - - - - - -

(PC ), SP

L

PC_L

(Table vector L), PC

(Table vector H)

←

H

6. Control Operation & etc.

OP

CODE

BYTE

NO.

CYCLE

NO

FLAG

NVGBHIZC

NO.

MNENONIC

OPERATION

1

BRK

0F

1

8

Software interrupt:

“1”, M(SP)

B

(PC ), SP

SP - 1,

←

H

- - - 1 - 0 - -

M(s)

(PC ), SP

S - 1, M(SP)

PSW,

←

L

SP

SP - 1, PC

(0FFDE ), PC

(0FFDF )

←

H

←

L

H

2

3

DI

EI

60

E0

FF

0D

2D

4D

6D

0E

2E

4E

6E

6F

1

3

2

4

5

Disable interrupts : I

“0”

- - - - - 0 - -

- - - - - 1 - -

- - - - - - - -

←

Enable interrupts

No operation

:

I

“1”

←

4

NOP

POP

5

A

X

Y

Pop from stack

6

SP

SP + 1, Reg.

M(SP)

SP - 1

- - - - - - - -

(restored)

←

7

8

POP PSW

9

PUSH

A

X

Y

Push to stack

M(SP) Reg. SP

10

11

12

13

←

- - - - - - - -

PUSH PSW

RET

Return from subroutine :

SP SP+1, PC M(SP), SP

- - - - - - - -

(restored)

SP+1, PC

M(SP)

←

L

H

14

RETI

7F

1

6

Return from interrupt :

SP

SP+1, PSW

M(SP), SP SP+1,PC

←

M(SP),

←

L

SP+1, PC

H

M(SP)

←

108

November 2001 Ver 1.1


型号：	HMS81C4260
厂家：	HYNIX SEMICONDUCTOR
描述：	HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS HYNIX SEMICONDUCTOR INC 。 8位单芯片微控制器微控制器
文件：	总110页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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