HMT112S6TFR8C [HYNIX]
204pin DDR3 SDRAM SODIMM;
| 型号： | HMT112S6TFR8C |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 204pin DDR3 SDRAM SODIMM 动态存储器 双倍数据速率 |
| 文件： | 总48页 (文件大小：544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
204pin DDR3 SDRAM SODIMM
DDR3 SDRAM
Unbuffered SODIMMs
Based on 1Gb T-die
HMT112S6TFR8C
HMT125S6TFR8C
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.0 / Nov. 2009
1
Revision History
Revision No.
History
Draft Date
Sep.2009
Remark
Preliminary
Web posting
0.1
1.0
Initial Release
JEDEC Update
Nov. 2009
Rev. 1.0 / Nov. 2009
2
Description
Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM
devices. These Unbuffered DDR3 SDRAM DIMMs are intended for use as main memory when installed in
systems such as mobile personal computers.
Features
• VDD=1.5V +/- 0.075V
• VDDQ=1.5V +/- 0.075V
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the
DDR3 SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC
(Burst Chop) 4
• On Die Termination (ODT) supported
• RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
# of
ranks
Part Number
Density
Organization
Component Composition
HMT112S6TFR8C-G7/H9
HMT125S6TFR8C-G7/H9
1GB
2GB
128Mx64
256Mx64
128Mx8(H5TQ1G83TFR)*8
128Mx8(H5TQ1G83TFR)*16
1
2
Rev. 1.0 / Nov. 2009
3
Key Parameters
CAS
Latency
(tCK)
tCK
(ns)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
MT/s
Grade
CL-tRCD-tRP
DDR3-1066
DDR3-1333
-G7
-H9
1.875
1.5
7
9
13.125
13.5
13.125
13.5
37.5
36
50.625
49.5
7-7-7
9-9-9
Speed Grade
Frequency [MHz]
CL8
Grade
Remark
CL6
CL7
CL9
CL10
-G7
-H9
800
800
1066
1066
1066
1066
1333
1333
Address Table
1GB(1Rx8)
2GB(2Rx8)
Refresh Method
Row Address
Column Address
Bank Address
Page Size
8K/64ms
A0-A13
A0-A9
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
BA0-BA2
1KB
Rev. 1.0 / Nov. 2009
4
Pin Descriptions
Num
ber
Num
ber
Pin Name
Description
Pin Name
Description
Data Input/Output
CK[1:0]
CK[1:0]
CKE[1:0]
RAS
Clock Input, positive line
Clock Input, negative line
Clock Enables
2
2
2
1
1
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
EVENT
64
8
Data Masks
Data strobes
8
Row Address Strobe
Column Address Strobe
Data strobes, negative line
Temperature event pin
8
CAS
1
Logic Analyzer specific test pin (No
connect on SODIMM)
WE
Write Enable
Chip Selects
Address Inputs
1
2
TEST
RESET
VDD
1
1
S[1:0]
Reset Pin
A[9:0],A11,
A[15:13]
14
Core and I/O Power
Ground
18
52
VSS
A10/AP
A12/BC
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
1
1
3
2
VREFDQ
VREFCA
BA[2:0]
ODT[1:0]
1
1
Input/Output Reference
On Die Termination Inputs
Serial Presence Detect (SPD)
Clock Input
VTT
SCL
1
Termination Voltage
SPD Power
2
VDDSPD
NC
SDA
SPD Data Input/Output
SPD Address Inputs
1
2
1
2
SA[1:0]
Reserved for future use
Total:
204
Rev. 1.0 / Nov. 2009
5
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.
CK0/CK0
CK1/CK1
IN
Cross Point
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Active
High
CKE[1:0]
S[1:0]
IN
IN
Enables the associated DDR3 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1.
Active
Low
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3
SDRAM mode register.
ODT[1:0]
IN
IN
Active
Low
When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE
define the operation to be executed by the SDRAM.
RAS, CAS, WE
VREFDQ
VREFCA
Supply
IN
Reference voltage for SSTL15 inputs.
BA[2:0]
—
—
—
Selects which SDRAM internal bank of eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read of Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high
autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction
with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge. A12(BC) is samples during READ and WRITE com-
mands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop:
LOW, burst chopped).
A[9:0],
A10/AP,
A11,
A12/BC
A[15:13]
IN
DQ[63:0]
DM[7:0]
I/O
IN
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
Active
High
V
DD, VDDSPD
Supply
I/O
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
VSS
The data strobes, associated with one data byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
Cross Point In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead-
ing edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS.
DQS[7:0],
DQS[7:0]
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
SA[1:0]
IN
—
Rev. 1.0 / Nov. 2009
6
Symbol
Type
Polarity
Function
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
SDA
I/O
—
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SCL
IN
—
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
OUT
(open
drain)
EVENT
VDDSPD
Active Low
No pull-up resister is provided on DIMM.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Supply
IN
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
RESET
TEST
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 1.0 / Nov. 2009
7
Pin Assignments
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
#
Side
#
Side
#
Side
53 DQ19 54
VSS
57 DQ24 58 DQ29 109 BA0
#
Side
#
Side
#
Side
#
Side
#
Side
VREFDQ
VSS
VSS
VDD
VDD
1
2
105
106
157 DQ42 158 DQ46
159 DQ43 160 DQ47
VSS
3
4
DQ4
DQ5
VSS
55
56
DQ28 107 A10/AP 108
BA1
VSS
VSS
5
DQ0
DQ1
VSS
6
110
112
114
RAS 161
162
VSS
VDD
WE
VDD
S0
7
8
59 DQ25 60
111
163 DQ48 164 DQ52
165 DQ49 166 DQ53
VSS
9
10
DQS0
61
62
DQS3 113
VSS
VSS
11
13
15
17
19
21
23
25
DM0
VSS
12 DQS0 63
DM3
VSS
64 DQS3 115 CAS
116 ODT0 167
VDD
120 ODT1 171 DQS6 172
168
VSS
VSS
VDD
14
16
18
20
22
24
26
28
65
66
117
118
169 DQS6 170 DM6
A132
S1
VSS
DQ2
DQ3
VSS
DQ6
DQ7
VSS
67 DQ26 68 DQ30 119
VSS
69
71
DQ27
VSS
70
72
74
76
78
80
82
DQ31 121
VSS
122
124
NC
173
174 DQ54
VDD
VDD
REFCA
VSS
123
175 DQ50 176 DQ55
V
VSS
DQ8
DQ9
VSS
DQ12 73 CKE0
CKE1 125 TEST 126
177 DQ51 178
VDD
VDD
VSS
VSS
DQ13
VSS
75
77
79
127
128
179
180 DQ60
A152
NC
BA2
VDD
129 DQ32 130 DQ36 181 DQ56 182 DQ61
A142
VDD
VSS
27
29
31
33
35
37
39
41
43
45
47
49
51
DQS1
DQS1
VSS
DM1
131 DQ33 132 DQ37 183 DQ57 184
VSS
VSS
VSS
30 RESET 81
133
134
185
186 DQS7
VSS
DQ14 85
32
34
36
38
40
42
44
46
48
50
52
83 A12/BC 84
A11 135 DQS4 136 DM4 187 DM7 188 DQS7
VSS
140 DQ38 191 DQ58 192 DQ62
141 DQ34 142 DQ39 193 DQ59 194 DQ63
VSS
VSS
DQ10
DQ11
VSS
A9
86
88
A7
137 DQS4 138
189
190
VDD
VDD
VSS
DQ15
VSS
87
89
139
A8
A5
90
A6
A4
VSS
VSS
VSS
198 EVENT
DQ16
DQ17
VSS
DQ20 91
92
143 DQ35 144
VSS
147 DQ40 148 DQ45 199
195
196
VDD
VDD
DQ21
VSS
93
95
97
99
94
145
146 DQ44 197
SA0
VDDSPD
A3
A1
96
A2
A0
200
202
204
SDA
SCL
VTT
VSS
DQS2
DQS2
VSS
DM2
VSS
98
149 DQ41 150
201 SA1
VDD
VDD
VSS
VTT
100
102
104
151
152 DQS5 203
DQ22 101 CK0
DQ23 103 CK0
CK1 153 DM5 154 DQS5
VSS VSS
DQ18
CK1 155
156
NC = No Connect; RFU = Reserved Future Use
1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be con-
nected to the termination resistor.
Rev. 1.0 / Nov. 2009
8
Functional Block Diagram
1GB, 128Mx64 Module(1Rank of x8)
SCL
A0
A1
SCL
SA0
SA1
Temp Sensor
(with SPD)
240ohm
+/-1%
240ohm
+/-1%
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
SDA
ZQ
ZQ
A2
EVENT
EVENT
DQ[0:7]
DQ[8:15]
The SPD may be
integrated with the Temp
Sensor or may be
D0
D1
D2
D3
D4
a separate component
SCL
A0
A1
SCL
SA0
SA1
(SPD)
WP
SDA
A2
V
Vtt
tt
SPD/TS
D0–D7
D0–D7
D0–D7
V
V
DDSPD
240ohm
+/-1%
240ohm
+/-1%
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
V
REFCA
ZQ
ZQ
ZQ
ZQ
REFDQ
VDD
Q[16:23]
DQ[24:31]
VSS
D0–D7, SPD, Temp sensor
D5
CK0
CK0
CK1
CK1
S1
D0–D7
D0–D7
Terminated near
card edge
NC
NC
NC
ODT1
CKE1
Temp Sensor
D0-D7
EVENT
RESET
240ohm
+/-1%
240ohm
+/-1%
DQS4
DQS4
DM4
DQS5
DQS5
DM5
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
DQ [0:7]
ZQ
Q[32:39]
DQ[40:47]
D6
V1
V2
V3
D5
V4
D4
D6
D7
V1
V2
V3
D1
V4
D0
D2
D3
240ohm
+/-1%
240ohm
+/-1%
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
ZQ
Q[48:55]
DQ[56:63]
DQ [0:7]
D7
Address and Control Lines
NOTES
1. DQ wiring may differ from that
shown however, DQ, DM, DQS, and
DQS relationships are maintained as
shown
Rank 0
Rev. 1.0 / Nov. 2009
9
2GB, 256Mx64 Module(2Rank of x8)
VDD
VDD
Cterm
Vtt
Cterm
Vtt
Vtt
240ohm
+/-1%
240ohm
+/-1%
240ohm
+/-1%
240ohm
+/-1%
DQS3
DQS3
DM3
DQ[24:31]
DQS4
DQS4
DM4
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
DQ [0:7]
DQS
DQS
DM
DQS
DQS
DM
ZQ
ZQ
ZQ
ZQ
DQ[32:39]
DQ [0:7]
DQ [0:7]
D11
D12
D3
D4
240ohm
+/-1%
240ohm
+/-1%
240ohm
+/-1%
240ohm
+/-1%
DQS1
DQS1
DM1
DQ[8:15]
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
DQS6
DQS6
DM6
ZQ
ZQ
ZQ
ZQ
DQ [0:7]
DQ[48:55]
D9
D6
D1
D14
240ohm
+/-1%
240ohm
+/-1%
240ohm
+/-1%
ZQ
240ohm
+/-1%
ZQ
DQS0
DQS0
DM0
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
DQS7
DQS7
DM7
ZQ
ZQ
DQ[0:7]
DQ [0:7]
DQ[56:43]
D0
D8
D7
D15
240ohm
+/-1%
ZQ
240ohm
+/-1%
ZQ
240ohm
+/-1%
240ohm
+/-1%
DQS2
DQS2
DM2
DQ[6:23]
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
ZQ
ZQ
DQS5
DQS5
DM5
DQ [0:7]
D5
D2
D13
D10
DQ[40:47]
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
Vtt
Vtt
SPD/TS
D0–D15
D0–D15
D0–D15
V
DDSPD
V1
V9
V5
V2
V8
D6
D7
D3
D12
D5
V
REFCA
D9
D8
SCL
A0
A1
SCL
SA0
SA1
V
REFDQ
(SPD)
VDD
SDA
SDA
V3
V7
VSS
D0–D15, SPD, Temp sensor
A2
WP
V4
V6
CK0
CK1
D0–D7
D10
D8–D15
D0–D7
CK0
SCL
A0
A1
SCL
SA0
SA1
Temp Sensor
(with SPD)
CK1
D8–D15
D0-D7
CKE0
V4
V2
V5
V6
V8
A2
D8-D15
D0–D7
CKE1
S0
EVENT
EVENT
D15
D14
D2
D13
D4
D0
D1
S1
ODT0
ODT1
D8–D15
D0–D7
V7
V3
Vtt
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS rela-
tionships are maintained as shown
V1
V9
D8–D15
Temp Sensor
D0-D15
Rank 0
Rank 1
D11
EVENT
RESET
Rev. 1.0 / Nov. 2009
10
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
Notes
VDD
- 0.4 V ~ 1.975 V
V
1,
VDDQ
VIN, VOUT
TSTG
- 0.4 V ~ 1.975 V
- 0.4 V ~ 1.975 V
-55 to +100
V
1,
1
V
oC
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
oC
Notes
0 to 85
1,2
TOPER
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs sup-
port Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet
and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range.
Rev. 1.0 / Nov. 2009
11
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol
Parameter
Units Notes
Min.
Typ.
Max.
VDD
1.425
1.500
1.575
V
V
1,2
1,2
Supply Voltage
Supply Voltage for Output
VDDQ
1.425
1.500
1.575
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Signal-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and ADDress
DDR3-800/1066/1333
Symbol
Parameter
Unit Notes
Min
Max
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VIL.CA(AC175)
VIH.CA(AC150)
VIL.CA(AC150)
DC input logic high
DC input logic low
Vref + 0.100
VSS
VDD
V
V
V
V
V
V
V
1
Vref - 0.100
Note2
1
AC input logic high
Vref + 0.175
Note2
1, 2
1, 2
1, 2
1, 2
3, 4
AC input logic low
Vref - 0.175
Note2
AC Input logic high
Vref + 0.150
Note2
AC input logic low
Vref - 0.150
0.51 * VDD
VRefCA(DC
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 25.
)
Reference Voltage for ADD, CMD inputs
0.49 * VDD
3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for
RefCA(DC)
Ref
Ref
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Rev. 1.0 / Nov. 2009
12
AC and DC Input Levels for Signal-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Single Ended AC and DC Input Levels for DQ and DM
DDR3-800/1066
DDR3-1333
Symbol
Parameter
Unit Notes
Min
Max
Min
Max
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VIL.CA(AC175)
VIH.CA(AC150)
VIL.CA(AC150)
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC Input logic high
AC input logic low
Vref + 0.100
VSS
VDD
Vref + 0.100
VDD
V
V
V
V
V
V
1
Vref - 0.100
Note2
VSS
Vref - 0.100
1
Vref + 0.175
Note2
-
-
-
-
1, 2
1, 2
1, 2
1, 2
Vref - 0.175
Note2
Vref + 0.150
Note2
Vref + 0.150
Note2
Note2
Vref - 0.150
Vref - 0.150
Reference Voltage for DQ,
DM inputs
VRefDQ(DC
)
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3, 4
Notes:
1. Vref = VrefDQ (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 25.
3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for
RefDQ(DC)
Ref
Ref
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Rev. 1.0 / Nov. 2009
13
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages
and V
are illustrated in
RefDQ
VRefCA
figure below. It shows a valid reference voltage V (t) as a function of time. (V stands for V and
RefCA
Ref
Ref
V
likewise).
RefDQ
V
(DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to
Ref
Ref
meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page 20. Further-
more V (t) may temporarily deviate from V
by no more than +/- 1% VDD.
Ref
Ref (DC)
voltage
VDD
V
(t)
Ref
V
ac-noise
Ref
V
Ref(DC)max
V
Ref(DC)
VDD/2
V
Ref(DC)min
VSS
time
Illustration of V
tolerance and V
ac-noise limits
Ref
Ref(DC)
The voltage levels for setup and hold time measurements V
, V
, V
, and V
are depen-
IL(DC)
IH(AC)
IH(DC)
IL(AC)
dent on V
.
Ref
“V ” shall be understood as V
, as defined in figure above.
Ref
Ref(DC)
This clarifies that dc-variations of V affect the absolute voltage a signal has to reach to achieve a valid
Ref
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for V
deviations from the optimum position within the data-eye of the input
Ref(DC)
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with V ac-noise. Timing and voltage effects due to ac-noise on V up to the speci-
Ref
Ref
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
Rev. 1.0 / Nov. 2009
14
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
t
DVAC
VIL.DIFF.AC.MIN
VIL.DIFF.MIN
0
half cycle
V
IL.DIFF.MAX
VIL.DIFF.AC.MAX
t
DVAC
time
Definition of differential ac-swing and “time above ac-level” t
DVAC
Rev. 1.0 / Nov. 2009
15
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3-800, 1066, 1333
Symbol
Parameter
Unit Notes
Min
Max
VIHdiff
VILdiff
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
+ 0.200
Note 3
Note 3
- 0.200
V
V
V
V
1
1
2
2
VIHdiff (ac)
VILdiff (ac)
2 x (VIH (ac) - Vref)
Note 3
Note 3
2 x (VIL (ac) - Vref)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 25.
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 350mV
@ |VIH/Ldiff (ac)| = 300mV
Slew Rate [V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
-
-
-
-
-
-
1.6
1.4
1.2
1.0
< 1.0
0
Rev. 1.0 / Nov. 2009
16
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-
ended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
Rev. 1.0 / Nov. 2009
17
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-800, 1066, 1333
Symbol
Parameter
Unit Notes
Min
Max
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
V
V
V
V
1,2
1,2
1,2
1,2
VSEH
VSEL
Note 3
(VDD / 2) = 0.175
(VDD / 2) = 0.175
Note 3
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 25.
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in the table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
VDD
CK, DQS
V
IX
VDD/2
V
IX
V
IX
CK, DQS
VSS
Vix Definition
Rev. 1.0 / Nov. 2009
18
Cross point voltage for differential input signals (CK, DQS)
DDR3-800, 1066, 1333
Parameter
Symbol
Unit Notes
Min
Max
-150
-175
150
175
mV
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
VIX
VIX
mV
1
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
mV
Notes:
1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are
IX
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential
slew rate of CK - CK is larger than 3 V/ns.
2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 18
for VSEL and VSEH standard values.
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-
ended slew rate definition for data signals.
Rev. 1.0 / Nov. 2009
19
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Differential Input Slew Rate Definition
Measured
Description
Defined by
Max
Min
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Delta
TRdiff
vIHdiffmin
0
vILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.0 / Nov. 2009
20
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
DDR3-800, 1066,
Symbol
Parameter
Unit
Notes
1333
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
0.8 x VDDQ
V
V
V
V
V
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
VTT + 0.1 x VDDQ
1
1
V
TT - 0.1 x VDDQ
Notes:
1. The swing of ± 0.1 x V
is based on approximately 50% of the static single ended output high or low
DDQ
swing with a driver impedance of 40Ω and an effective test load of 25Ω to V = V
/ 2.
DDQ
TT
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
DDR3-800, 1066,
Symbol
Parameter
Unit
Notes
1333
VOHdiff (AC)
VOLdiff (AC)
Notes:
1. The swing of ± 0.2 x V
+ 0.2 x VDDQ
V
V
1
1
AC differential output high measurement level (for output SR)
- 0.2 x VDDQ
AC differential output low measurement level (for output SR)
is based on approximately 50% of the static differential output high or low
DDQ
swing with a driver impedance of 40Ω and an effective test load of 25Ω to V = V
/2 at each of the
DDQ
TT
differential outputs.
Rev. 1.0 / Nov. 2009
21
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between V
and V
for single ended signals are shown in table and figure below.
OL(AC)
OH(AC)
Single-ended Output slew Rate Definition
Measured
Description
Defined by
From
VOL(AC)
VOH(AC)
To
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
[VOH(AC)-VOL(AC)] / DeltaTFse
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
vOH(AC)
V∏
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800
DDR3-1066
Min Max
2.5
DDR3-1333
Min Max
2.5
Units
Parameter
Symbol
Min
2.5
Max
Single-ended Output Slew Rate
SRQse
5
5
5
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Rev. 1.0 / Nov. 2009
22
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
VOLdiff (AC)
VOHdiff (AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta
TRdiff
vOHdiff(AC)
O
vOLdiff(AC)
Delta
TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3-800
DDR3-1066
Min Max
10
DDR3-1333
Min Max
10
Units
Parameter
Symbol
Min
Max
Differential Output Slew Rate
Description: SR; Slew Rate
SRQdiff
5
10
5
5
V/ns
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Rev. 1.0 / Nov. 2009
23
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
25 Ohm
CK, CK
DQ
DQS
DQS
VTT = VDDQ/2
DUT
Reference Load for AC Timing and Output Slew Rate
Rev. 1.0 / Nov. 2009
24
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter
DDR3-800 DDR3-1066DDR3-1333 Units
Maximum peak amplitude allowed for overshoot area. (See figure below)
Maximum peak amplitude allowed for undershoot area. (See figure below)
Maximum overshoot area above VDD (See figure below)
0.4
0.4
0.4
0.4
0.5
0.5
0.4
0.4
0.4
0.4
V
V
0.67
0.67
V-ns
V-ns
Maximum undershoot area below VSS (See figure below)
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDD
VSS
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Address and Control Overshoot and Undershoot Definition
Rev. 1.0 / Nov. 2009
25
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter
DDR3-800 DDR3-1066DDR3-1333 Units
Maximum peak amplitude allowed for overshoot area (See figure below)
Maximum peak amplitude allowed for undershoot area (See figure below)
Maximum overshoot area above VDD (See figure below)
Maximum undershoot area below VSS (See figure below)
(CK, CK, DQ, DQS, DQS, DM)
0.4
0.4
0.4
0.4
0.4
0.4
V
V
0.25
0.25
0.19
0.19
0.15
0.15
V-ns
V-ns
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Clock, Data Strobe and Mask Overshoot and Undershoot Definition
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.0 / Nov. 2009
26
Refresh parameters by device density
Refresh parameters by device density
Parameter
RTT_Nom Setting
512Mb
1Gb
2Gb
4Gb
8Gb
Units
REF command ACT or
REF command time
tRFC
90
110
160
300
350
ns
0 °C ≤ T
85 °C < T
≤ 85 °C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
us
us
Average periodic
refresh interval
CASE
tREFI
≤ 95 °C
CASE
Rev. 1.0 / Nov. 2009
27
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 31.
Speed Bin
DDR3-800E
6-6-6
Unit
Notes
CL - nRCD - nRP
Parameter
Symbol
min
max
tAA
15
20
ns
ns
ns
ns
ns
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tRCD
15
15
—
—
—
tRP
tRC
52.5
37.5
ACT to ACT or REF command period
ACT to PRE command period
tRAS
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
CL = 5
CL = 6
CWL = 5
CWL = 5
1, 2, 3, 4
1, 2, 3
2.5
nCK
nCK
6
5
Supported CL Settings
Supported CWL Settings
Rev. 1.0 / Nov. 2009
28
DDR3-1066 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 31.
Speed Bin
DDR3-1066F
7-7-7
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ns
ns
ns
ns
ACT to internal read or
write delay time
tRCD
13.125
13.125
50.625
37.5
—
—
tRP
PRE command period
ACT to ACT or REF
command period
tRC
—
ACT to PRE command
period
tRAS
9 * tREFI
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
Reserved
Reserved
ns
ns
1, 2, 3, 4, 5
CWL = 6
4
CWL = 5
CL = 6
2.5
3.3
ns
1, 2, 3, 5
1, 2, 3, 4
4
CWL = 6
Reserved
Reserved
ns
CWL = 5
CL = 7
ns
CWL = 6
1.875
1.875
< 2.5
< 2.5
ns
1, 2, 3, 4
4
CWL = 5
CL = 8
Reserved
ns
CWL = 6
ns
1, 2, 3
nCK
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8
5, 6
Rev. 1.0 / Nov. 2009
29
DDR3-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 31.
Speed Bin
DDR3-1333H
9-9-9
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.5
max
Internal read command
to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)8
13.5
(13.125)8
ACT to internal read or
write delay time
—
—
—
13.5
(13.125)8
PRE command period
49.5
(49.125)8
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
36
9 * tREFI
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
Reserved
Reserved
ns
ns
ns
ns
ns
ns
1,2, 3,4, 6
CWL = 6, 7
4
CWL = 5
2.5
3.3
1, 2, 3, 6
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1, 2, 3, 4, 6
4
4
1.875
1.875
< 2.5
< 2.5
tCK(AVG)
CWL = 6
ns
1, 2, 3, 4, 6
Reserved
Reserved
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 5
ns
ns
ns
ns
ns
ns
ns
1, 2, 3, 4
4
CWL = 6
1, 2, 3, 6
1, 2, 3, 4
4
CWL = 7
Reserved
Reserved
CWL = 5, 6
CWL = 7
CL = 9
1.5
1.5
<1.875
<1.875
1, 2, 3, 4
CWL = 5, 6
Reserved
Reserved
4
CL = 10
ns
ns
1, 2, 3
tCK(AVG)
CWL = 7
nCK
Supported CL Settings
Supported CWL Settings
6, 8, (7), 9, (10)
5, 6, 7
nCK
Rev. 1.0 / Nov. 2009
30
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making
a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements
from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the
next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] =
tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX
corresponding to CLSE LECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
8. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini-
mum value of 13.125 ns. SPD settings are also programmed to match. For example, DDR3 1333H devices
supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16),
tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H
or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRP-
min (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be pro-
grammed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H
and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
Rev. 1.0 / Nov. 2009
31
Environmental Parameters
Symbol
Parameter
Operating temperature
Rating
Units
Notes
o
T
0 to 65
C
1, 3
OPR
H
Operating humidity (relative)
10 to 90
-50 to +100
5 to 95
%
1
1
OPR
o
T
Storage temperature
C
STG
H
Storage humidity (without condensation)
Barometric Pressure (operating & storage)
%
1
STG
P
105 to 69
K Pascal
1, 2
BAR
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only,
and device functional operation at or above the conditions indicated is not implied. Expousure to absolute
maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 1.0 / Nov. 2009
32
Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112S6TFR8C
Symbol
CCK
Min
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
Unit
pF
Pin
CK0, CK0
pF
CCTRL
CI
CKE, ODT, CS
pF
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
pF
CIO
2GB: HMT125S6TFR8C
Pin
CK0, CK0
Symbol
CCK
Min
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
Unit
pF
pF
CCTRL
CI
CKE, ODT, CS
pF
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
pF
CIO
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 1.0 / Nov. 2009
33
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
•
”0” and “LOW” is defined as VIN <= V
ILAC(max).
”1” and “HIGH” is defined as VIN >= V
IHAC(max).
•
•
•
•
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0 (Output Buffer enabled in MR1);
B
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.0 / Nov. 2009
34
IDDQ (optional)
IDD
VDD
RESET
CK/CK
VDDQ
DDR3
SDRAM
RTT = 25 Ohm
CKE
CS
DQS, DQS
DQ, DM,
VDDQ/2
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 1.0 / Nov. 2009
35
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1066
DDR3-1333
Symbol
Unit
7-7-7
1.875
7
9-9-9
1.5
9
tCK
ns
CL
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nRCD
nRC
nRAS
nRP
7
9
27
20
7
33
24
9
1KB page size
2KB page size
1KB page size
2KB page size
20
27
4
20
30
4
nFAW
nRRD
6
5
nRFC -512Mb
nRFC-1 Gb
nRFC- 2 Gb
nRFC- 4 Gb
nRFC- 8 Gb
48
59
86
160
187
60
74
107
200
234
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output
IDD0
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
IDD1
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.0 / Nov. 2009
36
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2N
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2NT
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
IDDQ2NT Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
(optional)
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
IDD2P0
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
IDD2P1
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
IDD2Q
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD3N
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Rev. 1.0 / Nov. 2009
37
Symbol
IDD3P
Description
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDDQ4R Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Read Current
(optional)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
IDD4R
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
IDD4W
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
IDD5B
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 1.0 / Nov. 2009
38
Symbol
Description
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Auto Self-Refresh Current
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6TC
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a,f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
IDD7
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature
range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Nov. 2009
39
a)
Table 3 - IDD0 Measurement-Loop Pattern
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
-
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
40
a)
Table 4 - IDD1 Measurement-Loop Pattern
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD 00
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRCD
...
0
1
0
1
0
0
0
0
0
0
0
0
00000000
-
nRAS
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD 00
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRCD
...
0
1
0
1
0
0
0
0
F
0
00110011
-
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
Rev. 1.0 / Nov. 2009
41
a)
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
a)
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
0
1
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
42
a)
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Pattern
Datab)
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
-
2,3
D,D
RD
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
a)
Table 8 - IDD4W Measurement-Loop Pattern
Datab)
0
WR
D
D,D
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
2,3
4
5
6,7
-
-
00110011
-
-
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
43
a)
Table 9 - IDD5B Measurement-Loop Pattern
Datab)
0
1
REF
D, D
D, D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
0
1.2
00
00
3,4
5...8
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC-1
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
44
a)
Table 10 - IDD7 Measurement-Loop Pattern
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
1
0
1
2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
repeat above D Command until nRRD - 1
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
D
1
0
0
0
0
3
00
0
0
F
0
0
-
-
4
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
0
F
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
2*nFAW+nRRD+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
11
2&nFAW+nRRD+2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
12 2*nFAW+2*nRRD
13 2*nFAW+3*nRRD
D
1
0
0
0
0
3
00
0
0
0
0
-
14 2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
15 3*nFAW
16 3*nFAW+nRRD
17 3*nFAW+2*nRRD
18 3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
-
19 3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
45
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
1GB, 128M x 64 SO-DIMM: HMT112S6TFR8C
Symbol
IDD0
DDR3 1066
360
DDR3 1333
400
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
480
520
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
240
280
280
320
80
80
200
280
240
280
280
320
160
200
720
840
720
840
1080
80
1120
80
IDD6ET
IDD6TC
IDD7
96
96
96
96
1040
1280
2GB, 256M x 64 SO-DIMM: HMT125S6TFR8C
Symbol
IDD0
DDR3 1066
600
DDR3 1333
680
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
720
800
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
480
560
560
640
160
160
400
560
480
560
560
640
320
400
960
1120
1120
1400
160
960
1320
160
IDD6ET
IDD6TC
IDD7
192
192
192
192
1280
1560
Rev. 1.0 / Nov. 2009
46
Module Dimensions
128Mx64 - HMT112S6TFR8C
Front
Side
3.80mm max
67.60mm
2.0
4.00±0.10
SPD
Detail-A
1.00±0.08 mm
pin 1
pin 203
21.00
39.00
2.15
2Xφ1.80±0.10
1.65±0.10
3.00
Back
Detail of Contacts A
0.3~1.0
±0.03
0.45
0.60
1.00
±0.05
Note:
1. ±0.13tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.0 / Nov. 2009
47
256Mx64 - HMT125S6TFR8C
Front
67.60mm
Side
3.80mm max
2.0
4.00±0.10
Detail-
A
Detail-B
1.00±0.08 mm
pin 1
pin 203
21.00
1.65±0.10
39.00
2.15
2Xφ1.80±0.10
3.00
Back
SPD
Detail of Contacts A
0.3~1.0
±0.03
0.45
0.60
1.00
±0.05
Note:
1. ±0.13tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.0 / Nov. 2009
48
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