HMT125V7AFP4C-H9 [HYNIX]
240pin DDR3 SDRAM VLP Registered DIMM; 240PIN DDR3 SDRAM VLP DIMM注册
| 型号： | HMT125V7AFP4C-H9 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 240pin DDR3 SDRAM VLP Registered DIMM |
| 文件： | 总25页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin DDR3 SDRAM VLP Registered DIMM
DDR3 SDRAM VLP
Registered DIMM
Based on 1Gb A version
HMT112V7AFP8C
HMT125V7AFP8C
HMT125V7AFP4C
HMT351V7AMP4C
** Contents may be changed at any time without any notice.
Rev. 0.2 / December 2008
1
Revision History
Revision No.
History
Draft Date
2008-8
Remark
0.1
Initial Release
0.2
Added IDD, corrected typos
2008-12
Rev. 0.2 / December 2008
2
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
3.2 2GB, 256Mx72 Module(2Rank of x8)
3.3 2GB, 256Mx72 Module(1Rank of x4)
3.4 4GB, 512Mx72 Module(2Rank of x4)
4. Input/Output Capacitance & AC Parametrics
5. IDD Specifications
6. DIMM Outline Diagram
6.1 1GB, 128Mx72 Module(1Rank of x8)
6.2 2GB, 256Mx72 Module(2Rank of x8)
6.3 2GB, 256Mx72 Module(1Rank of x4)
6.4 4GB, 512Mx72 Module(2Rank of x4)
Rev. 0.2 / December 2008
3
1. Description
This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A gen-
eration. These are intended for use as main memory in server and workstation systems, providing a high performance
8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• BL switch on the fly
• 8banks
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 78ball
FBGA(x4/x8), 96ball FBGA(x16) with support balls
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Auto Self Refresh supported
• P r o g ra m m a b l e a d d i t i ve l a t e n c y 0 , C L- 1 , a n d C L- 2 s u p
ported
• 8 bit pre-fetch
• Heat Spreader installed for 4GB
• SPD with Integrated TS of Class B
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
1.1.2 Ordering Information
# of
DRAMs
# of
ranks
Part Name
Density Organization
Materials
FDHS
HMT112V7AFP8C-G7/H9
HMT125V7AFP8C-G7/H9
HMT125V7AFP4C-G7/H9
HMT351V7AMP4C-G7/H9
1GB
2GB
2GB
4GB
128Mx72
256Mx72
256Mx72
512Mx72
9
1
2
1
2
Lead free
Lead free
Lead free
Lead free
X
X
X
O
18
18
36
*Please Contact local sales administrator for more details of part number
Rev. 0.2 / December 2008
4
1.2 Speed Grade & Key Parameters
MT/S
DDR3-1066
-G7
DDR3-1333
-H9
Unit
Grade
tCK (min)
CAS Latency
tRCD (min)
tRP (min)
1.875
7
1.5
9
ns
tCK
ns
13.125
13.125
37.5
13.5
13.5
36
ns
tRAS (min)
tRC (min)
ns
50.625
7-7-7
49.5
9-9-9
ns
CL-tRCD-tRP
tCK
1.3 Address Table
1GB(1Rx8)
2GB(2Rx8)
2GB(1Rx4)
4GB(2Rx4)
Organization
Refresh Method
Row Address
Column Address
Bank Address
Page Size
128M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
256M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
256M x 72
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
512M x 72
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
# of Rank
1
2
1
2
# of Device
9
18
18
36
Rev. 0.2 / December 2008
5
2. Pin Architecture
2.1 Pin Definition
Num
-ber
Pin
Name
Num
-ber
Pin Name
Description
Description
A0–A9,A11
A13-A15
Address Inputs
14
A10/AP Address Input/Autoprecharge
A12/BC Address Input/Autoprecharge
1
BA0–BA2
RAS
SDRAM Bank Addresses
Row Address Strobe
Column Address Strobe
Write Enable
3
1
1
1
1
1
1
3
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
CAS
SDA
WE
SA0–SA2 SPD Address Inputs
Parity Bit For The Address and Control
S0–S3
Chip Selects
4
2
Par_in
ERR_OUT
EVENT
TEST
1
1
1
1
Bus
Parity Error Found on the Address and
Control Bus
CKE0–CKE1
ODT0–ODT1
DQ0–DQ63
Clock Enables
Reserved for Optional Hardware
temperature Sensing
On-die termination Inputs
Data Input/Output
2
Memory Bus Test Tool (Not Connected
and Not Usable on DIMMs)
64
CB0–CB7
Data Check Bits Input/Output
Data Strobes
8
9
9
RESET
VDD
Register and SDRAM control pin
Power Supply
1
22
59
1
DQS0–DQS8
DQS0–DQS8
Data Strobes, Negative Line
VSS
Ground
VREFDQ Reference Voltage for DQ
VREFCA Reference Voltage for CA
Data Masks
DM0–DM8
DQS9-DQS17 Data Strobes
9
1
TDQS9-TDQS17
Termination Data Strobes
VTT
Termination Voltage
SPD Power
4
VDDSPD
CK1
1
Data Strobes, Negative Line
Termination Data Strobes
DQS9–DQS17
TDQS9–TDQS17
9
Clock Input, positive line
Clock Input, negative line
1
CK0
CK0
Clock Input, positive line
Clock Input, positive Line
1
1
CK1
1
Rev. 0.2 / December 2008
6
2.2 Input/Output Functional Description
Symbol
Type
Polarity
Function
Positive line of the differential pair of system clock inputs that drives input
to the on-DIMM Clock Driver.
CK0
IN
Positive Line
Negative line of the differential pair of system clock inputs that drives the
input to the on-DIMM Clock Driver.
CK0
IN
Negative Line
CK1
CK1
IN
IN
Positive Line Terminated but not used on RDIMMs
Negative Line Terminated but not used on RDIMMs
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers of the SDRAMs. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
CKE0–CKE1
IN
Active High
Enables the command decoders for the associated rank of SDRAM when
low and disables decoders.When decoders are disabled, new commands
are ignored and previous operations continue.Other combinations of these
input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal
control words in the register device(s).For modules with two regis-
ters,S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
S0–S3
IN
IN
Active Low
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
RAS, CAS, WE
ODT0–ODT1
VREFDQ
IN
Active High On-Die Termination control signals
Reference voltage for DQ0-DQ63 and CB0-CB7
Supply
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0,
CKE1, Par_In, ODT0 and ODT1.
VREFCA
Supply
Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
VDDQ
Supply
Selects which SDRAM bank of eight is activated.
BA0-BA2 define to which bank an Active, Read, Write or Precharge com-
mand is being applied.Bank address also determines mode register is to be
accessed during an MRS cycle.
BA0–BA2
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank.A10 is sampled during a
Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be pre-
charged, the bank is selected by BA.A12 is also utilized for BL 4/8 identifi-
cation for “BL on the fly” during CAS command. The address inputs also
provide the op-code during Mode Register Set commands.
A0-A9
A10/AP
A11
A12/BC
A13-A15
IN
—
—
DQ0–DQ63,
CB0–CB7
I/O
Data and Check Bit Input/Output pins.
Rev. 0.2 / December 2008
7
Symbol
DM0–DM8
VDD, VSS
Type
IN
Polarity
Function
Active High Masks write data when high, issued concurrently with input data.
Power and ground for the DDR3 SDRAM input buffers, and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Supply
Supply
I/O
VTT
DQS0-DQS17
DQS0–DQS17
Positive Edge Positive line of the differential data strobe for input and output data.
Negative Edge Negative line of the differential data strobe for input and output data.
I/O
TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Reg-
ister A11=1 in MR1, DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via
mode register A11=0 in MR1, DM/TDQS will provide the data mask func-
tion and TDQS is not used.x4/x16 DRAMs must disable the TDQS function
via mode register A11=0 in MR1.
TDQS9-TDQS17
TDQS9-TDQS17
OUT
These signals are tied at the system planar to either VSS or VDDSPD to con-
figure the serial SPD EEPROM address range.
SA0–SA2
SDA
—
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
VDDSPD to act as a pullup on the system board.
I/O
IN
—
—
This signal is used to clock data into and out of the SPD EEPROM. An
external resistor may be connected from the SCL bus time to VDDSPD to act
as a pull up.
SCL
Serial EEPROM positive power supply wired to a separate power pin at the
connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) opera-
tion.
VDDSPD
EVENT
Supply
OUT
(open
drain)
This signal indicates that a thermal event has been detected in the thermal
Active Low sensing device. The system should guarantee the electrical level require-
ment is met for the EVENT pin on TS/SPD part.
The RESET pin is connected to the RESET pin on the register and to the
RESET pin on the DRAM. When low, all register outputs will be driven low
and the Clock Driver clocks to the DRAMs and register(s) will be set to low
level (the Clock Driver will remain synchronized with the input clock)
RESET
IN
Par_In
Err_Out
TEST
IN
Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even)
OUT
(open
drain)
Parity error detected on the Address and Control bus.A resistor may be
connected from Err_Out bus line to VDD on the system planar to act as a
pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 0.2 / December 2008
8
2.3 Pin Assignment
Front Side
(left 1–60)
Back Side
(right 121–180)
Front Side
(left 61–120)
Back Side
(right 181–240)
Pin #
Pin #
Pin #
Pin #
1
VREFDQ
121
122
123
124
125
126
127
128
129
130
131
132
133
V
SS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
A2
VDD
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
A1
VDD
2
VSS
DQ4
DQ5
3
DQ0
DQ1
NC, CK1
NC, CK1
VDD
VDD
4
VSS
CK0
5
VSS
DM0,DQS9,TDQS9
NC, DQS9,TDQS9
CK0
6
DQS0
DQS0
VDD
VDD
7
VSS
VREFCA
Par_in, NC
VDD
EVENT, NC
A0
8
VSS
DQ6
DQ7
9
DQ2
DQ3
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VSS
A10 / AP
BA1
VSS
DQ12
DQ13
VDD
BA0
VDD
DQ8
DQ9
RAS
VSS
WE
S0
VSS
134 DM1,DQS10,TDQS10
CAS
VDD
DQS1
DQS1
135
136
137
138
139
140
141
142
NC,DQS10,TDQS10
VDD
ODT0
A13
VSS
S1, NC
ODT1, NC
VDD
VSS
DQ14
DQ15
VDD
DQ10
DQ11
S3, NC
VSS
S2, NC
VSS
VSS
DQ20
DQ21
VSS
DQ36
DQ37
DQ16
DQ17
DQ32
DQ33
VSS
VSS
VSS
143 DM2,DQS11,TDQS11
VSS
203 DM4,DQS13,TDQS13
DQS2
DQS2
144
145
146
147
148
149
150
151
NC,DQS11,TDQS11
DQS4
DQS4
204
205
206
207
208
209
210
211
NC, DQS13,TDQS13
VSS
VSS
VSS
DQ22
DQ23
VSS
DQ38
DQ39
DQ18
DQ19
DQ34
DQ35
VSS
VSS
VSS
DQ28
DQ29
VSS
DQ44
DQ45
DQ24
DQ25
DQ40
DQ41
VSS
VSS
VSS
152 DM3,DQS12,TDQS12
153 NC, DQS12,TDQS12
NC = No Connect; RFU = Reserved Future Use
VSS
212 DM5,DQS14,TDQS14
213 NC, DQS14,TDQS14
DQS3
DQS5
Rev. 0.2 / December 2008
9
Front Side
(left 1–60)
Back Side
(right 121–180)
Front Side
(left 61–120)
Back Side
(right 181–240)
Pin #
Pin #
Pin #
Pin #
34
35
36
37
38
39
40
DQS3
154
155
156
157
158
159
160
V
SS
94
95
DQS5
214
215
216
217
218
219
220
VSS
VSS
DQ30
DQ31
VSS
DQ46
DQ47
DQ26
DQ27
96
DQ42
DQ43
VSS
97
VSS
VSS
CB4, NC
CB5, NC
98
VSS
DQ52
DQ53
CB0, NC
CB1, NC
99
DQ48
DQ49
VSS
100
VSS
DM8,DQS17,TDQS17
NC
41
VSS
161
101
VSS
221 DM6,DQS15,TDQS15
42
43
44
45
46
47
48
DQS8
DQS8
162
163
164
165
166
167
168
NC,DQS17,TDQS17
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
DQS6
DQS6
222
223
224
225
226
227
228
229
NC, DQS15,TDQS15
VSS
VSS
VSS
CB6, NC
CB7, NC
VSS
DQ54
DQ55
CB2, NC
CB3, NC
DQ50
DQ51
VSS
VSS
VSS
NC(TEST)
RESET
VSS
DQ60
DQ61
VTT, NC
KEY
DQ56
DQ57
KEY
VSS
49
50
51
52
53
54
55
56
VTT, NC
CKE0
169
170
171
172
173
174
175
176
CKE1, NC
VDD
VSS
230 DM7,DQS16,TDQS16
DQS7
DQS7
231
232
233
234
235
236
237
NC, DQS16,TDQS16
VDD
A15
VSS
BA2
A14
VSS
DQ62
DQ63
Err_Out, NC
VDD
VDD
DQ58
DQ59
A12 / BC
A9
VSS
A11
VSS
VDDSPD
SA1
VDD
SA0
SCL
SA2
VTT
A7
57
58
59
60
VDD
177
178
179
180
118
119
120
238
239
240
SDA
A8
A6
VSS
A5
A4
VDD
VTT
VDD
A3
NC = No Connect; RFU = Reserved Future Use
Rev. 0.2 / December 2008
10
3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
DQS8_t
DQS8_c
DM8/DQS17_t
DQS17_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS4_t
DQS4_c
DM4/DQS13_t
DQS13_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D8
D3
D2
D1
D4
D5
D6
D7
CB[7:0]
DQ[39:32]
DQS5_t
DQS5_c
DM5/DQS14_t
DQS14_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS3_t
DQS3_c
DM3/DQS12_t
DQS12_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQ[47:40]
DQ[31:24]
DQS6_t
DQS6_c
DM6/DQS15-t
DQS15_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS2_t
DQS2_c
DM2/DQS11_t
DQS11_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQ[55:48]
DQ[23:16]
ZQ
DQS1_t
DQS1_c
DM1/DQS10_t
DQS10_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS7_t
DQS7_c
DM7/DQS16_t
DQS16_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
VDDSPD
SPD
VDD
D0–D8
DQ[15:8]
DQ[63:56]
VTT
VREFCA
VREFDQ
D0–D8
D0–D8
Vtt
ZQ
DQS0_t
DQS0_c
DQS_t
DQS_c
VSS
D0–D8
DM0/DQS9_t
DQS9_c
TDQS_t
TDQS_c
DQ [7:0]
D0
DQ[7:0]
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240Ω ±1%.For all other resistor values refer to the
appropriate wiring diagram.
Vtt
S0_n
S1_n
BA[N:0]
RS0A_n →CS0_n: SDRAMs D[3:0], D8
RS0BCK_n
RBA[N:0]A
RBA[N:0]B
RA[N:0]A
RA[N:0]B
→CS0_n: SDRAMs D[7:4]
1:
2
R
E
G
I
S
T
E
R
/
→
BA[N:0]: SDRAMs D[3:0], D8
BA[N:0]: SDRAMs D[7:4]
A[N:0]: SDRAMs D[3:0], D8
A[N:0]: SDRAMs D[7:4]
→
→
→
A[N:0]
RAS_n
RRASA_n
RRASB_n
RCASA_n
RCASB_n
RWEA_n
RWEB_n
→
RAS_n: SDRAMs D[3:0], D8
RAS_n: SDRAMs D[7:4]
CAS_n: SDRAMs D[3:0], D8
CAS_n: SDRAMs D[7:4]
WE_n: SDRAMs D[3:0], D8
WE_n: SDRAMs D[7:4]
VDDSPD
EVENT
SCL
VDDSPD
SA0
SA0
SA1
SA2
VSS
→
→
→
→
→
CAS_n
EVENT SPD with SA1
Integrated
WE_n
CKE0
SCL
SA2
VSS
TS
SDA
RCKE0A
RCKE0B
RODT0A
RODT0B
PCK0A_t
PCK0B_t
PCK0A_c
PCK0B_c
→
→
→
→
→
→
→
→
CKE0: SDRAMs D[3:0], D8
CKE0: SDRAMs D[7:4]
ODT0: SDRAMs D[3:0], D8
ODT0: SDRAMs D[7:4]
CK_t: SDRAMs D[3:0], D8
CK_t: SDRAMs D[7:4]
CK_c: SDRAMs D[3:0], D8
CK_c: SDRAMs D[7:4]
SDA
ODT0
CK0_t
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
P
L
L
120
Ω
±
1%
CK0_c
CK1_t
120
Ω
1%
±
CK1_c
OERR_n
RST_n
PAR_IN
Err_Out_n
RST_n: SDRAMs D[8:0]
RESET_n
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330
Ω resistor to ground
Rev. 0.2 / December 2008
11
3.2 2GB, 256Mx72 Module(2Rank of x8)
DQS8_t
DQS8_c
DM8/DQS17_t
DQS17_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS4_t
DQS4_c
DM4/DQS13-t
DQS13_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
D8
D3
D2
D1
D0
D4
D5
D6
D7
D17
D12
D11
D10
D9
D13
D14
D15
D16
CB[7:0]
DQ[39:32]
DQS3_t
DQS3_c
DM3/DQS12_t
DQS12_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS5_t
DQS5_c
DM5/DQS14_t
DQS14_
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQ[31:24]
DQ[47:40]
ZQ
ZQ
ZQ
ZQ
DQS2_t
DQS2_c
DM2/DQS11_t
DQS11_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS6_t
DQS6_c
DM6/DQS15_t
DQS15_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQ[23:16]
DQ55:48]
DQS1_t
DQS1_c
DM1/DQS10_t
DQS10_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS7_t
DQS7_c
DM7/DQS16_t
DQS16_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
DQ[15:8]
DQ[63:56]
ZQ
ZQ
ZQ
ZQ
DQS0_t
DQS0_c
DM0/DQS9_t
DQS9_c
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
ZQ
Vtt
DQ[7:0]
VDDSPD
EVENT_n
SCL
VDDSPD
SA0
SA0
SA1
SA2
VSS
EVENT SPD with SA1
Integrated
SCL
SA2
VSS
Vtt
TS
SDA
SDA
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15Ω ±5%.
3. ZQ resistors are 240Ω ±1%. For all other resistor values
refer to the appropriate wiring diagram.
VDDSPD
Serial PD
V
DD
4. See the wiring diagrams for all resistors associated with the
command, address and control bus.
D0–D17
D0–D17
D0–D17
D0–D17
VTT
VREFCA
VREFDQ
VSS
D0–D17
Rev. 0.2 / December 2008
12
S0_n
RS0A_n
RS0B_n
→
→
CS0_n: SDRAMs D[3:0], D8
CS0_n: SDRAMs D[7:4]
1:2
S1_n
R
E
G
I
S
T
E
R
/
S[3:2] NC
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
RBA[N:0]A
RBA[N:0]B
RA[N:0]A
RA[N:0]B
→
→
BA[N:0]: SDRAMs D[3:0], D[12:8], D17
BA[N:0]: SDRAMs D[7:4], D[16:13]
→
→
A[N:0]: SDRAMs D[3:0], D[12:8], D17
A[N:0]: SDRAMs D[7:4], D[16:13]
RRASA_n
RRASB_n
→
→
RAS_n: SDRAMs D[3:0], D[12:8], D17
RAS_n: SDRAMs D[7:4], D[16:13]
RCASA_n
RCASB_n
→
→
CAS_n: SDRAMs D[3:0], D[12:8], D17
CAS_n: SDRAMs D[7:4], D[16:13]
WE_n: SDRAMs D[3:0], D[12:8], D17
WE_n: SDRAMs D[7:4], D[16:13]
CKE0: SDRAMs D[3:0], D8
CKE0: SDRAMs D[7:4]
RWEA_n
RWEB_n
→
→
P
L
L
RCKE0A
RCKE0B
→
→
RODT0A
RODT0B
→
→
ODT0: SDRAMs D[3:0], D8
ODT0: SDRAMs D[7:4]
ODT0
PCK0A_t
PCK0B_t
→
→
CK-t: SDRAMs D[3:0], D8
CK_t: SDRAMs D[7:4]
CK0_t
CK0_c
120Ω
PCK0A_c
PCK0B_c
→
→
CK_c: SDRAMs D[3:0], D8
CK_c: SDRAMs D[7:4]
CK1_t
CK1_c
120
Ω
PAR_IN
Err_Out_n
RESET_n
RST_n
RST_n: SDRAMs D[17:0]
Rev. 0.2 / December 2008
13
3.3 2GB, 256Mx72 Module(1Rank of x4)
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS8_t
DQS8_c
VSS
DQS17_t
DQS17_c
VSS
DQS4_t
DQS4_c
VSS
DQS13_t
DQS13_c
VSS
D8
D3
D2
D1
D0
D17
D12
D11
D10
D9
D4
D5
D6
D7
D13
D14
D15
D16
CB[3:0]
DQ [3:0]
CB[7:4]
DQ [3:0]
DQ[35:32]
DQ [3:0]
DQ[39:36]
DQ [3:0]
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS3_t
DQS3_c
VSS
DQS12_t
DQS12_c
VSS
DQ[31:28]
DQS5_t
DQS5_c
VSS
DQS14_t
DQS14_c
VSS
DQ[47:44]
DQ[27:24]
DQ [3:0]
DQ [3:0]
DQ[43:40]
DQ [3:0]
DQ [3:0]
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS2_t
DQS2_c
VSS
DQS11_t
DQS11_c
VSS
DQS6_t
DQS6_c
VSS
DQS15_t
DQS15_c
VSS
DQ[19:16]
DQ [3:0]
DQ23:20]
DQ [3:0]
DQ[51:48]
DQ [3:0]
DQ[55;52]
DQ [3:0]
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS1_t
DQS1_c
VSS
DQS10_t
DQS10_c
VSS
DQS7_t
DQS7_c
VSS
DQS16_t
DQS16_c
VSS
DQ[11;8]
DQ [3:0]
DQ[15:12]
DQ [3:0]
DQ[59:56]
DQ [3:0]
DQ[63:60]
DQ [3:0]
DQS_t
DQS_c
DM
DQS_t
DQS_c
DM
DQS0_t
DQS0_c
VSS
DQS9_t
DQS9_c
VSS
DQ[7:4]
Vtt
DQ[3:0]
DQ [3:0]
DQ [3:0]
Vtt
VDDSPD
EVENT
SCL
VDDSPD
SA0
SA0
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
EVENT SPD with SA1
SA1
SA2
VSS
Integrated
SCL
SA2
VSS
TS
SDA
SDA
VDDSPD
SPD
Note:
VDD
D0–D17
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15 %.
Ω ±5
VTT
VREFCA
VREFDQ
3. See the wiring diagrams for all resistors associated with the com-
mand, address and control bus.
D0–D17
D0–D17
4. ZQ resistors are 240Ω ±1%. For all other resistor values refer to the
appropriate wiring diagram.
VSS
D0–D17
Rev. 0.2 / December 2008
14
S0_n
S1_n
RS0A_n
RS1A_n
RS0B_n
RS1B_n
→
→
→
→
CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17
CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35
CS0B_n: SDRAMs D[7:4], D[16:13]
1:2
CS1B_n: SDRAMs D[25:22], D[34:31]
R
E
G
I
S
T
E
R
/
BA[2:0]
A[15:0]
RAS_n
RBA[2:0]A
RBA[2:0]B
RA[15:0]A
RA[15:0]B
RRASA_n
RRASB_n
RCASA_n
RCASB_n
RWEA_n
RWEB_n
RCKE0A
RCKE0B
RODT[1:0]A
RODT[1:0]B
→
→
BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
CAS_n
→
WE_n
→WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
P
L
L
CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17
CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35
CKE[1:0]
ODT[1:0]
→
→
ODT0: SDRAMs D[3:0], D8. D[12:9], D17
ODT0: SDRAMs D[21:18], D26, D[30:27], D35
CK0A_t_R0
CK0B_t_R0
CK0A_t_R1
CK0B_t_R1
CK0A_c_R0
CK0B_c_R0
CK0A_c_R1
CK0B_c_R1
→
CK-t: SDRAMs D[3:0], D8, D[21:18], D26
CK_t: SDRAMs D[7:4], D[25:22]
CK-t: SDRAMs D[12:9], D17, D[30:27], D35
CK_t: SDRAMs D[16:13], D[34:31]
CK_c: SDRAMs D[3:0], D8, D[21:18], D26
CK_c: SDRAMs D[7:4], D[25:22]
CK_c: SDRAMs D[12:9], D17, D[30:27], D35
CK_c: SDRAMs D[16:13], D[34:31]
CK0_t
CK0_c
→
→
→
→
→
→
→
120
Ω
CK1_t
CK1_c
120
Ω
PAR_IN
Err_Out_n
RESET_n
RST_n
RST_n: All SDRAMs
* S[3:2]_n are NC
(Note: Otherwise stated differently all resistors values on this base are 22 +-5%)
Ω
Rev. 0.2 / December 2008
15
3.4 4GB, 512Mx72 Module(2Rank of x4)
VSS
RS0_n
RS1_n
DM CS_n ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS_n ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS_n ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS_n ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS0_t
DQS0_c
DQ[3:0]
DQS9_t
DQS9_c
DQ[7:4]
D0
D18
D9
D27
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS1_t
DQS1_c
DQ[11:8]
DQS10_t
DQS10_c
DQ[12:15]
D1
D19
D10
D28
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS2_t
DQS2_c
DQ[16:19]
DQS11_t
DQS11_c
DQ[20:23]
D2
D20
D11
D29
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS3_t
DQS3_c
DQ[24:27]
DQS12_t
DQS12_c
DQ[28:31]
D3
D21
D12
D30
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS4_t
DQS4_c
DQ[32:35]
DQS13_t
DQS13_c
DQ[36:39]
D4
D22
D13
D31
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS5_t
DQS5_c
DQ[40:43]
DQS14_t
DQS14_c
DQ[44:47]
D5
D23
D14
D32
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS6_t
DQS6_c
DQ[48:51]
DQS15_t
DQS15_c
DQ[52:55]
D6
D24
D15
D33
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS7_t
DQS7_c
DQ[56:59]
DQS16_t
DQS16_c
DQ[60:63]
D7
D25
D16
D34
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DM CS_n ZQ
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS_t
DQS_c
DQ [3:0]
DQS8_t
DQS8_c
CB[3:0]
DQS17_t
DQS17_c
CB[7:4]
D8
D26
D17
D35
VDDSPD
SPD
VDDSPD
EVENT
VDDSPD
SA0
SA0
SA1
SA2
VSS
V
DD
D0–D17
EVENT SPD with SA1
VTT
VREFCA
VREFDQ
Integrated
SCL
SA2
VSS
SCL
D0–D17
D0–D17
TS
SDA
SDA
VSS
D0–D17
Plan to use SPD with Integrated TS of Class B and might be
changed on customer’s requests. For more details of SPD and
Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.2 / December 2008
16
S0_n
S1_n
RS0A_n
RS1A_n
RS0B_n
RS1B_n
→
→
→
→
CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17
CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35
CS0B_n: SDRAMs D[7:4], D[16:13]
1:2
CS1B_n: SDRAMs D[25:22], D[34:31]
R
E
G
I
S
T
E
R
/
BA[2:0]
A[15:0]
RAS_n
RBA[2:0]A
RBA[2:0]B
RA[15:0]A
RA[15:0]B
RRASA_n
RRASB_n
RCASA_n
RCASB_n
RWEA_n
RWEB_n
RCKE0A
RCKE0B
RODT[1:0]A
RODT[1:0]B
→
→
BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
CAS_n
→
WE_n
→WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
→
→
P
L
L
CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17
CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35
CKE[1:0]
ODT[1:0]
→
→
ODT0: SDRAMs D[3:0], D8. D[12:9], D17
ODT0: SDRAMs D[21:18], D26, D[30:27], D35
CK0A_t_R0
CK0B_t_R0
CK0A_t_R1
CK0B_t_R1
→
CK_t: SDRAMs D[3:0], D8, D[21:18], D26
CK_t: SDRAMs D[7:4], D[25:22]
CK_t: SDRAMs D[12:9], D17, D[30:27], D35
CK_t: SDRAMs D[16:13], D[34:31]
CK0_t
CK0_c
→
→
→
120
Ω
CK0A_c_R0
CK0B_c_R0
CK0A_c_R1
CK0B_c_R1
→
→
→
→
CK_c: SDRAMs D[3:0], D8, D[21:18], D26
CK_c: SDRAMs D[7:4], D[25:22]
CK_c: SDRAMs D[12:9], D17, D[30:27], D35
CK_c: SDRAMs D[16:13], D[34:31]
CK1_t
CK1_c
120
Ω
PAR_IN
Err_Out_n
RESET_n
RST_n
RST_n: All SDRAMs
* S[3:2]_n are NC
(Note: Otherwise stated differently all resistors values on this base are 22 +-5%)
Ω
Rev. 0.2 / December 2008
17
4. Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112V7AFP8C
Symbol
Min
Max
Unit
Pin
pF
pF
pF
pF
pF
CK0, CK0
CKE, ODT
CS
CCK
CI1
CI2
CI3
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB: HMT125V7AFP8C
Symbol
Min
Max
Unit
Pin
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CI3
CIO
2GB: HMT125V7AFP4C
Symbol
Min
Max
Unit
Pin
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
CI3
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
4GB: HMT351V7AMP4C
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
CI3
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.2 / December 2008
18
o
5. IDD Specifications (Tcase: 0 to 95 C)
1GB, 128M x 72 R-DIMM: HMT112V7AFP8C
Symbol
IDD0
DDR3 800
1484
1664
1259
1304
1502
318
DDR3 1066
1592
1799
1349
1394
1502
318
DDR3 1333
1664
1889
1439
1484
1502
318
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
462
480
498
1259
1349
498
1349
1439
588
1439
1529
633
2024
1304
2204
2474
318
2294
1304
2564
2564
318
2654
1304
2834
2654
318
IDD6ET
IDD6TC
IDD7
336
336
336
336
336
336
2654
3014
3464
2GB, 256M x 72 R-DIMM: HMT125V7AFP8C
Symbol
IDD0
DDR3 800
1979
2159
1754
1844
2240
408
DDR3 1066
2177
2384
1934
2024
2240
408
DDR3 1333
2399
2564
2114
2204
2240
408
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
696
732
768
1754
1934
798
1934
2114
948
2114
2294
1038
3329
1979
3509
3329
408
2519
1799
2699
2969
408
2879
1889
3149
3149
408
IDD6ET
IDD6TC
IDD7
444
444
444
444
444
444
3149
3599
4139
Rev. 0.2 / December 2008
19
2GB, 256M x 72 R-DIMM: HMT125V7AFP4C
Symbol
IDD0
DDR3 800
2204
2564
1754
1844
2240
408
DDR3 1066
2420
2834
1934
2024
2240
408
DDR3 1333
2564
3014
2114
2204
2240
408
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
696
732
768
1754
1934
768
1934
2114
948
2114
2294
1038
4544
1844
4904
4544
408
3284
1844
3644
4184
408
3824
1844
4364
4364
408
IDDET
IDD6TC
IDD7
444
444
444
444
444
444
4544
5264
6164
4GB, 512M x 72 R-DIMM: HMT351V7AMP4C
Symbol
IDD0
DDR3 800
3194
3554
2744
2924
3716
588
DDR3 1066
3590
4004
3104
3284
3716
588
DDR3 1333
3914
4364
3464
3644
3716
588
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
1164
2744
3104
1308
4274
2834
4634
5174
588
1236
3104
3464
1668
4994
3014
5534
5534
588
1308
3464
3824
1848
5894
3194
6254
5894
588
IDDET
IDD6TC
IDD7
660
660
660
660
660
660
5534
6434
7514
Rev. 0.2 / December 2008
20
6. Dimm Outline Diagram
6.1 128Mx72 - HMT112V7AFP8C
Front
14.90
13.60
2.10
± 0.15
Detail C
18.75
15.80
±
±
0.15
0.1
3
3
±
±
0.1
0.1
1
120
8.00 ± 0.1
2X3.0
± 0.10
71.00
47.00
Detail A
5.175
Detail B
128.95
133.35
Back
240
121
Side
3.65mm max
Detail of Contacts B
Detail of Contacts C
Detail of Contacts A
0.80
± 0.05
2.50
14.90
0.4
13.60
0.3~0.1
1.00
1.50
±0.10
5.00
1.27 ± 010mm
max
Rev. 0.2 / December 2008
21
6.2 256Mx72 - HMT125V7AFP8C
Front
14.90
13.60
2.10
± 0.15
Detail C
18.75
15.80
±
±
0.15
0.1
3
3
±
±
0.1
0.1
1
120
8.00 ± 0.1
2X3.0
± 0.10
71.00
47.00
Detail A
5.175
Detail B
128.95
133.35
Back
240
121
Side
3.65mm max
Detail of Contacts B
Detail of Contacts C
Detail of Contacts A
0.80
± 0.05
2.50
14.90
0.4
13.60
0.3~0.1
1.00
1.50
±0.10
5.00
1.27 ± 010mm
max
Rev. 0.2 / December 2008
22
6.3 256Mx72 - HMT125V7AFP4C
Front
14.90
13.60
2.10
± 0.15
Detail C
18.75
15.80
±
±
0.15
0.1
3
3
±
±
0.1
0.1
1
120
8.00 ± 0.1
2X3.0
± 0.10
71.00
47.00
Detail A
5.175
Detail B
128.95
133.35
Back
240
121
Side
3.65mm max
Detail of Contacts B
Detail of Contacts C
Detail of Contacts A
0.80
± 0.05
2.50
14.90
0.4
13.60
0.3~0.1
1.00
1.50
±0.10
5.00
1.27 ± 010mm
max
Rev. 0.2 / December 2008
23
6.4 512Mx72 - HMT351V7AMP4C
Front
14.90
13.60
2.10
± 0.15
Detail C
18.75
15.80
±
±
0.15
0.1
3
3
±
±
0.1
0.1
1
120
8.00 ± 0.1
2X3.0
± 0.10
71.00
47.00
Detail A
5.175
Detail B
128.95
133.35
Back
240
121
Side
3.95mm max
Detail of Contacts B
Detail of Contacts C
Detail of Contacts A
0.80
± 0.05
2.50
14.90
13.60
0.4
0.3~0.1
1.00
1.50
±0.10
1.27 ± 010mm
max
5.00
Rev. 0.2 / December 2008
24
6.4 512Mx72 - HMT351V7AMP4C
Front
36.58
36.58
18.75
± 0.15
12.3 13.3
1
120
126.8
Back
240
121
Detail of Contacts B
Detail of Contacts C
Detail of Contacts A
Side
9.35mm max
0.80
±
0.05
2.50
14.90
0.4
13.60
0.3~0.1
1.00
1.50
±0.10
2.15mm
1.27 ±010mm
max
5.00
Rev. 0.2 / December 2008
25
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明