HMT151R7AFP4C-G7_技术文档

240pin DDR3 SDRAM Registered DIMM

DDR3 SDRAM Registered DIMM

Based on 1Gb A version

HMT112R7AFP8C

HMT125R7AFP8C

HMT125R7AFP4C

HMT151R7AFP4C

HMT151R7AFP8C

HMT31GR7AMP4C

** Contents may be changed at any time without any notice.

Rev. 0.4 /Jul. 2009

1

Revision History

Revision No.

History

Draft Date

2008-8

Remark

0.1

Initial Release

0.2

0.3

Added IDD Specification

2008-11

2009-02

Reflected the actual measurement, non-

physical change (max thickness)

0.4

Added Environment Parameter

2009-07

Rev. 0.4 / Jul. 2009

2

Table of Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Features

1.1.2 Ordering Information

1.2 Key Parameters

1.3 Speed Grade

1.4 Address Table

2. Pin Architecture

2.1 Pin Definition

2.2 Input/Output Functional Description

2.3 Pin Assignment

3. Functional Block Diagram

3.1 1GB, 128Mx72 Module(1Rank of x8)

3.2 2GB, 256Mx72 Module(2Rank of x8)

3.3 2GB, 256Mx72 Module(1Rank of x4)

3.4 4GB, 512Mx72 Module(2Rank of x4)

3.5 4GB, 512Mx72 Module(4Rank of x8)

3.6 8GB,

1Gx72 Module(4Rank of x4)

4. Environment Parameter

5. Input/Output Capacitance & AC Parametrics

6. IDD Specifications

7. DIMM Outline Diagram

7.1 1GB, 128Mx72 Module(1Rank of x8)

7.2 2GB, 256Mx72 Module(2Rank of x8)

7.3 2GB, 256Mx72 Module(1Rank of x4)

7.4 4GB, 512Mx72 Module(2Rank of x4)

7.5 4GB, 512Mx72 Module(4Rank of x8)

7.6 8GB,

1Gx72 Module(4Rank of x4)

Rev. 0.4 / Jul. 2009

3

1. Description

This Hynix DDR3 SDRAM Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These

are intended for use as main memory in server and workstation systems, providing a high performance 8 byte inter-

face in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.

1.1 Product Features & Ordering Information

1.1.1 Features

• VDD=VDDQ=1.5V

• BL switch on the fly

• 8 banks

• VDDSPD=3.3V to 3.6V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• 8K refresh cycles /64ms

• DDR3 SDRAM Package: JEDEC standard 78ball

FBGA(x4/x8), 96ball FBGA(x16) with support balls

• On chip DLL align DQ, DQS and /DQS transition with

CK transition

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

the clock

• TDQS (Termination Data Strobe) supported (x8 device

based only)

• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)

supported

• Write Levelization supported

• Auto Self Refresh supported

• 8 bit pre-fetch

• P r o g ra m m a b l e a d d i t i v e l a t e n c y 0 , C L- 1 , a n d C L- 2 s u p

ported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

• Heat Spreader installed for 4GB/8GB

• SPD with Integrated TS of Class B

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

* This product in compliance with the directive petaining of RoHS.

1.1.2 Ordering Information

# of

DRAMs

# of

ranks

Part Number

Density

Organization

Materials

FDHS

HMT112R7AFP8C-G7/H9

HMT125R7AFP8C-G7/H9

HMT125R7AFP4C-G7/H9

HMT151R7AFP4C-G7/H9

HMT151R7AFP8C-G7/H9

HMT31GR7AMP4C-G7/H9

1GB

2GB

4GB

8GB

128Mx72

256Mx72

512Mx72

1Gx72

9

1

2

1

2

4

Lead free

X

18

36

72

X

O

* Please Contact local sales administrator for more details of part number

Rev. 0.4 / Jul. 2009

4

1.2 Key Parameters

MT/s

DDR3-1066

-G7

DDR3-1333

-H9

Unit

Grade

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

1.875

7

1.5

9

ns

tCK

ns

13.125

37.5

13.5

36

ns

tRAS(min)

tRC(min)

ns

50.625

7-7-7

49.5

9-9-9

ns

CL-tRCD-tRP

tCK

1.3 Speed Grade

Frequency [MHz]

Grade

CL5

Remark

CL6

CL7

CL8

CL9

CL10

-G7

-H9

800

1066

1333

1.4 Address Table

1GB(1Rx8)

128M x 72

2GB(2Rx8)

2GB(1Rx4)

4GB(2Rx4)

4GB(4Rx8)

8GB(4Rx4)

Organization

256M x 72

512M x 72

1G x 72

Refresh

Method

8K/64ms

A0-A13

A0-A9

8K/64ms

A0-A13

A0-A9

8K/64ms

A0-A13

8K/64ms

A0-A13

8K/64ms

A0-A13

A0-A9

8K/64ms

A0-A13

Row Address

Column

Address

A0-A9,A11

Bank Address

Page Size

BA0-BA2

1KB

1

1KB

2

1KB

1

1KB

2

1KB

4

1KB

4

# of Rank

# of Device

9

18

36

72

Rev. 0.4 / Jul. 2009

5

2. Pin Architecture

2.1 Pin Definition

Num

-ber

Name

Num

-ber

Pin Name

Description

A0–A9,A11

A13-A15

Address Inputs

14

A10/AP Address Input/Autoprecharge

A12/BC Address Input/Autoprecharge

1

BA0–BA2

RAS

SDRAM Bank Addresses

Row Address Strobe

Column Address Strobe

Write Enable

3

1

3

SCL

Serial Presence Detect (SPD) Clock Input

SPD Data Input/Output

CAS

SDA

WE

SA0–SA2 SPD Address Inputs

Parity Bit For The Address and Control

S0–S3

Chip Selects

4

2

Par_in

ERR_OUT

EVENT

TEST

1

Bus

Parity Error Found on the Address and

Control Bus

CKE0–CKE1

ODT0–ODT1

DQ0–DQ63

Clock Enables

Reserved for Optional Hardware

temperature Sensing

On-die termination Inputs

Data Input/Output

2

Memory Bus Test Tool (Not Connected

and Not Usable on DIMMs)

64

CB0–CB7

Data Check Bits Input/Output

Data Strobes

8

9

RESET

VDD

Register and SDRAM control pin

Power Supply

1

22

59

1

DQS0–DQS8

Data Strobes, Negative Line

VSS

Ground

VREFDQ Reference Voltage for DQ

VREFCA Reference Voltage for CA

Data Masks

DM0–DM8

DQS9-DQS17 Data Strobes

9

1

TDQS9-TDQS17

Termination Data Strobes

VTT

Termination Voltage

SPD Power

4

VDDSPD

CK1

1

Data Strobes, Negative Line

Termination Data Strobes

DQS9–DQS17

TDQS9–TDQS17

9

Clock Input, positive line

Clock Input, negative line

1

CK0

Clock Input, positive line

Clock Input, positive Line

1

CK1

1

Rev. 0.4 / Jul. 2009

6

2.2 Input/Output Functional Description

Symbol

Type

Polarity

Function

Positive line of the differential pair of system clock inputs that drives input

to the on-DIMM Clock Driver.

CK0

IN

Positive Line

Negative line of the differential pair of system clock inputs that drives the

input to the on-DIMM Clock Driver.

CK0

IN

Negative Line

CK1

IN

Positive Line Terminated but not used on RDIMMs

Negative Line Terminated but not used on RDIMMs

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers of the SDRAMs. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all

banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

CKE0–CKE1

IN

Active High

Enables the command decoders for the associated rank of SDRAM when

low and disables decoders.When decoders are disabled, new commands

are ignored and previous operations continue.Other combinations of these

input signals perform unique functions, including disabling all outputs

(except CKE and ODT) of the register(s) on the DIMM or accessing internal

control words in the register device(s).For modules with two regis-

ters,S[3:2] operate similarly to S[1:0] for the second set of register out-

puts or register control words.

S0–S3

IN

Active Low

When sampled at the positive rising edge of the clock, CAS, RAS, and WE

define the operation to be executed by the SDRAM.

RAS, CAS, WE

ODT0–ODT1

VREFDQ

IN

Active High On-Die Termination control signals

Reference voltage for DQ0-DQ63 and CB0-CB7

Supply

Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0,

CKE1, Par_In, ODT0 and ODT1.

VREFCA

Supply

Power supply for the DDR3 SDRAM output buffers to provide improved

noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ

shares the same power plane as VDD pins.

VDDQ

Supply

Selects which SDRAM bank of eight is activated.

BA0-BA2 define to which bank an Active, Read, Write or Precharge com-

mand is being applied.Bank address also determines mode register is to be

accessed during an MRS cycle.

BA0–BA2

IN

—

Provided the row address for Active commands and the column address

and Auto Precharge bit for Read/Write commands to select one location

out of the memory array in the respective bank.A10 is sampled during a

Precharge command to determine whether the Precharge applies to one

bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be pre-

charged, the bank is selected by BA.A12 is also utilized for BL 4/8 identifi-

cation for “BL on the fly” during CAS command. The address inputs also

provide the op-code during Mode Register Set commands.

A0-A9

A10/AP

A11

A12/BC

A13-A15

IN

—

DQ0–DQ63,

CB0–CB7

I/O

Data and Check Bit Input/Output pins.

Rev. 0.4 / Jul. 2009

7

Symbol

DM0–DM8

VDD, VSS

Type

IN

Polarity

Function

Active High Masks write data when high, issued concurrently with input data.

Power and ground for the DDR3 SDRAM input buffers, and core logic.

Termination Voltage for Address/Command/Control/Clock nets.

Supply

I/O

VTT

DQS0-DQS17

DQS0–DQS17

Positive Edge Positive line of the differential data strobe for input and output data.

Negative Edge Negative line of the differential data strobe for input and output data.

I/O

TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Reg-

ister A11=1 in MR1, DRAM will enable the same termination resistance

function on TDQS/TDQS that is applied to DQS/DQS. When disabled via

mode register A11=0 in MR1, DM/TDQS will provide the data mask func-

tion and TDQS is not used.x4/x16 DRAMs must disable the TDQS function

via mode register A11=0 in MR1.

TDQS9-TDQS17

OUT

These signals are tied at the system planar to either VSS or VDDSPD to con-

figure the serial SPD EEPROM address range.

SA0–SA2

SDA

—

This bidirectional pin is used to transfer data into or out of the SPD

EEPROM. An external resistor may be connected from the SDA bus line to

VDDSPD to act as a pullup on the system board.

I/O

IN

—

This signal is used to clock data into and out of the SPD EEPROM. An

external resistor may be connected from the SCL bus time to VDDSPD to act

as a pull up.

SCL

Serial EEPROM positive power supply wired to a separate power pin at the

connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) opera-

tion.

VDDSPD

EVENT

Supply

OUT

(open

drain)

This signal indicates that a thermal event has been detected in the thermal

Active Low sensing device. The system should guarantee the electrical level require-

ment is met for the EVENT pin on TS/SPD part.

The RESET pin is connected to the RESET pin on the register and to the

RESET pin on the DRAM. When low, all register outputs will be driven low

and the Clock Driver clocks to the DRAMs and register(s) will be set to low

level (the Clock Driver will remain synchronized with the input clock)

RESET

IN

Par_In

Err_Out

TEST

IN

Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even)

OUT

(open

drain)

Parity error detected on the Address and Control bus.A resistor may be

connected from Err_Out bus line to VDD on the system planar to act as a

pull up.

Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Rev. 0.4 / Jul. 2009

8

2.3 Pin Assignment

Front Side

(left 1–60)

Back Side

(right 121–180)

Front Side

(left 61–120)

Back Side

(right 181–240)

Pin #

1

VREFDQ

121

122

123

124

125

126

127

128

129

130

131

132

133

V

SS

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

A2

VDD

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

A1

VDD

2

VSS

DQ4

DQ5

3

DQ0

DQ1

NC, CK1

VDD

4

VSS

CK0

5

VSS

DM0,DQS9,TDQS9

NC, DQS9,TDQS9

CK0

6

DQS0

VDD

7

VSS

VREFCA

Par_in, NC

VDD

EVENT, NC

A0

8

VSS

DQ6

DQ7

9

DQ2

DQ3

VDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

VSS

A10 / AP

BA1

VSS

DQ12

DQ13

VDD

BA0

VDD

DQ8

DQ9

RAS

VSS

WE

S0

VSS

134 DM1,DQS10,TDQS10

CAS

VDD

DQS1

135

136

137

138

139

140

141

142

NC,DQS10,TDQS10

VDD

ODT0

A13

VSS

S1, NC

ODT1, NC

VDD

VSS

DQ14

DQ15

VDD

DQ10

DQ11

S3, NC

VSS

S2, NC

VSS

DQ20

DQ21

VSS

DQ36

DQ37

DQ16

DQ17

DQ32

DQ33

VSS

143 DM2,DQS11,TDQS11

VSS

203 DM4,DQS13,TDQS13

DQS2

144

145

146

147

148

149

150

151

NC,DQS11,TDQS11

DQS4

204

205

206

207

208

209

210

211

NC, DQS13,TDQS13

VSS

DQ22

DQ23

VSS

DQ38

DQ39

DQ18

DQ19

DQ34

DQ35

VSS

DQ28

DQ29

VSS

DQ44

DQ45

DQ24

DQ25

DQ40

DQ41

VSS

152 DM3,DQS12,TDQS12

153 NC, DQS12,TDQS12

NC = No Connect; RFU = Reserved Future Use

VSS

212 DM5,DQS14,TDQS14

213 NC, DQS14,TDQS14

DQS3

DQS5

Rev. 0.4 / Jul. 2009

9

Front Side

(left 1–60)

Back Side

(right 121–180)

Front Side

(left 61–120)

Back Side

(right 181–240)

Pin #

34

35

36

37

38

39

40

DQS3

154

155

156

157

158

159

160

V

SS

94

95

DQS5

214

215

216

217

218

219

220

VSS

DQ30

DQ31

VSS

DQ46

DQ47

DQ26

DQ27

96

DQ42

DQ43

VSS

97

VSS

CB4, NC

CB5, NC

98

VSS

DQ52

DQ53

CB0, NC

CB1, NC

99

DQ48

DQ49

VSS

100

VSS

DM8,DQS17,TDQS17

NC

41

VSS

161

101

VSS

221 DM6,DQS15,TDQS15

42

43

44

45

46

47

48

DQS8

162

163

164

165

166

167

168

NC,DQS17,TDQS17

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

DQS6

222

223

224

225

226

227

228

229

NC, DQS15,TDQS15

VSS

CB6, NC

CB7, NC

VSS

DQ54

DQ55

CB2, NC

CB3, NC

DQ50

DQ51

VSS

NC(TEST)

RESET

VSS

DQ60

DQ61

VTT, NC

KEY

DQ56

DQ57

KEY

VSS

49

50

51

52

53

54

55

56

VTT, NC

CKE0

169

170

171

172

173

174

175

176

CKE1, NC

VDD

VSS

230 DM7,DQS16,TDQS16

DQS7

231

232

233

234

235

236

237

NC, DQS16,TDQS16

VDD

A15

VSS

BA2

A14

VSS

DQ62

DQ63

Err_Out, NC

VDD

DQ58

DQ59

A12 / BC

A9

VSS

A11

VSS

VDDSPD

SA1

VDD

SA0

SCL

SA2

VTT

A7

57

58

59

60

VDD

177

178

179

180

118

119

120

238

239

240

SDA

A8

A6

VSS

A5

A4

VDD

VTT

VDD

A3

NC = No Connect; RFU = Reserved Future Use

Rev. 0.4 / Jul. 2009

10

3. Functional Block Diagram

3.1 1GB, 128Mx72 Module(1Rank of x8)

ZQ

DQS8

DM8/DQS17

DQS17

CB[7:0]

DQS

TDQS

DQ [7:0]

DQS4

DM4/DQS13

DQS13

DQ[39:32]

DQS

TDQS

DQ [7:0]

D8

D3

D2

D4

D5

D6

D7

DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS

TDQS

DQ [7:0]

DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS

TDQS

DQ [7:0]

DQS6

DM6/DQS15

DQS15

DQ[55:48]

DQS

TDQS

DQ [7:0]

DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS

TDQS

DQ [7:0]

ZQ

DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS

TDQS

DQ [7:0]

DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS

TDQS

DQ [7:0]

V_DDSPD

SPD

D1

D0

VDD

D0–D8

V_TT

VREFCA

VREFDQ

D0–D8

Vtt

ZQ

DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS

TDQS

DQ [7:0]

VSS

D0–D8

Note:

1.DQ-to-I/O wiring may be changed within byte.

2.ZQ resistors are 240Ω ±1%.For all other resistor values refer to the

appropriate wiring diagram.

Vtt

S0

S1

BA[N:0]

RS0A

RS0B

RBA[N:0]A

RA[N:0]A

→

CS0: SDRAMs D[3:0], D8

CS0: SDRAMs D[7:4]

1:

2

R

E

G

I

S

T

E

R

/

→

BA[N:0]: SDRAMs D[3:0], D8

BA[N:0]: SDRAMs D[7:4]

A[N:0]

RAS

→

A[N:0]: SDRAMs D[3:0], D8

A[N:0]: SDRAMs D[7:4]

RRASA

→

RAS: SDRAMs D[3:0], D8

RAS: SDRAMs D[7:4]

VDDSPD

EVENT

SCL

VDDSPD

SA0

SA1

SA2

VSS

CAS

RCASA

RWEA

RCKE0A

RCKE0B

RODT0A

RODT0B

PCK0A

PCK0B

PCK0A

PCK0B

→

CAS: SDRAMs D[3:0], D8

CAS: SDRAMs D[7:4]

EVENT SPD with SA1

Integrated

WE

SCL

SA2

VSS

→

WE: SDRAMs D[3:0], D8

WE: SDRAMs D[7:4]

CKE0: SDRAMs D[3:0], D8

CKE0: SDRAMs D[7:4]

TS

CKE0

SDA

ODT0

CK0

→

ODT0: SDRAMs D[3:0], D8

ODT0: SDRAMs D[7:4]

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

P

L

→

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

120

Ω

±

1%

CK0

→

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

120

Ω

1%

±

CK0

OERR

RST

PAR_IN

Err_Out

RST: SDRAMs D[8:0]

RESET

S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330

Ω resistor to ground

Rev. 0.4 / Jul. 2009

11

3.2 2GB, 256Mx72 Module(2Rank of x8) - page1

DQS8

DM8/DQS17

DQS17

CB[7:0]

DQS

TDQS

DQ [7:0]

DQS4

DM4/DQS13

DQS13

DQ[39:32]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

D8

D3

D2

D1

D0

D4

D5

D6

D7

D17

D12

D11

D10

D9

D13

D14

D15

D16

ZQ

DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS

TDQS

DQ [7:0]

DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

ZQ

DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS

TDQS

DQ [7:0]

DQS6

DM6/DQS15

DQS15

DQ55:48]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

ZQ

DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS

TDQS

DQ [7:0]

DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

ZQ

Vtt

DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS

TDQS

DQ [7:0]

DQS

TDQS

DQ [7:0]

ZQ

VDDSPD

EVENT

SCL

VDDSPD

SA0

SA1

SA2

VSS

EVENT SPD with SA1

Vtt

Integrated

SCL

SA2

VSS

TS

SDA

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

Note:

1. DQ-to-I/O wiring may be changed within a byte.

2. Unless otherwise noted, resistor values are 15Ω ±5%.

3. ZQ resistors are 240Ω ±1%. For all other resistor values

refer to the appropriate wiring diagram.

V_DDSPD

Serial PD

V

DD

4. See the wiring diagrams for all resistors associated with the

command, address and control bus.

D0–D17

V_TT

VREFCA

VREFDQ

VSS

D0–D17

Rev. 0.4 / Jul. 2009

12

3.2.2 2GB, 256Mx72 Module(2Rank of x8)-page2

S0

RS0A

RS0B

RS1A

RS1B

→

CS0: SDRAMs D[3:0], D8

CS0: SDRAMs D[7:4]

1:2

S1

→

CS1: SDRAMs D[12:9], D17

CS1: SDRAMs D[16:13]

R

E

G

I

S

T

E

R

/

S[3:2] NC

BA[N:0]

RBA[N:0]A

→

BA[N:0]: SDRAMs D[3:0], D[12:8], D17

BA[N:0]: SDRAMs D[7:4], D[16:13]

RBA[N:0]B

→

A[N:0]

RAS

RA[N:0]A

RA[N:0]B

→

A[N:0]: SDRAMs D[3:0], D[12:8], D17

→

A[N:0]: SDRAMs D[7:4], D[16:13]

RRASA

RRASB

→

RAS: SDRAMs D[3:0], D[12:8], D17

RAS: SDRAMs D[7:4], D[16:13]

CAS

RCASA

RCASB

RWEA

RWEB

RCKE0A

RCKE0B

RCKE1A

RCKE1B

→

CAS: SDRAMs D[3:0], D[12:8], D17

CAS: SDRAMs D[7:4], D[16:13]

WE

→

WE: SDRAMs D[3:0], D[12:8], D17

WE: SDRAMs D[7:4], D[16:13]

CKE0

CKE1

→

CKE0: SDRAMs D[3:0], D8

CKE0: SDRAMs D[7:4]

P

L

→

CKE1: SDRAMs D[12:9], D17

CKE1: SDRAMs D[16:13]

ODT0

RODT0A

RODT0B

→

ODT0: SDRAMs D[3:0], D8

ODT0: SDRAMs D[7:4]

ODT1

CK0

RODT1A

→

ODT1: SDRAMs D[12:9], D17

ODT1: SDRAMs D[16:13]

PCK0A

PCK0B

PCK1A

PCK1B

PCK0A

PCK0B

PCK1A

PCK1B

→

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

→

120

±5%

Ω

CK: SDRAMs D[12:9], D17

CK: SDRAMs D[16:13]

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

CK: SDRAMs D[12:9], D17

CK: SDRAMs D[16:13

CK0

]

CK1

120

Ω

±5%

PAR_IN

OERR

Err_Out

RESET

RST

RST: SDRAMs D[17:0]

* S[3:2], CK1 and CK1 are NC

Rev. 0.4 / Jul. 2009

13

3.3 2GB, 256Mx72 Module(1Rank of x4)-page1

ZQ

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS8

VSS

DQS17

VSS

DQS4

VSS

DQS13

VSS

CB[3:0]

D8

D3

D2

D1

D0

CB[7:4]

D17

D12

D11

D10

D9

DQ[35:32]

D4

D5

D6

D7

DQ[39:36]

D13

D14

D15

D16

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS3

VSS

DQS12

VSS

DQ[31:28]

DQS5

VSS

DQS14

VSS

DQ[47:44]

DQ[27:24]

DQ[43:40]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS2

VSS

DQS11

VSS

DQS6

VSS

DQS15

VSS

DQ[19:16]

DQ23:20]

DQ[51:48]

DQ[55;52]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS1

VSS

DQS10

VSS

DQS7

VSS

DQS16

VSS

DQ[11;8]

DQ[15:12]

DQ[59:56]

DQ[63:60]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS0

VSS

DQS9

VSS

DQ[7:4]

Vtt

DQ[3:0]

Vtt

VDDSPD

EVENT

SCL

VDDSPD

SA0

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

EVENT SPD with SA1

SA1

SA2

VSS

Integrated

SCL

SA2

VSS

TS

SDA

V_DDSPD

SPD

Note:

VDD

D0–D17

1. DQ-to-I/O wiring may be changed within a nibble.

2. Unless otherwise noted, resistor values are 15%.

3. See the wiring diagrams for all resistors associated with the com-

mand, address and control bus.

4. ZQ resistors are 240 %.±F1or all other resistor values refer to the

appropriate wiring diagram.

Ω ±5

V_TT

VREFCA

VREFDQ

Ω

VSS

D0–D17

Rev. 0.4 / Jul. 2009

14

3.3 2GB, 256Mx72 Module(1Rank of x4)-page2

S0

RS0A

RS0B

RS1A

RS1B

→

CS0: SDRAMs D[3:0], D[12:8], D17

CS0: SDRAMs D[7:4], D[16:13]

CS1: SDRAMs D[12:9], D17

S1

→

RBA[N:0]A

1:2

CS1: SDRAMs D[16:13]

BA[N:0]

A[N:0]

RAS

R

E

G

I

S

T

E

R

/

→

BA[N:0]: SDRAMs D[3:0], D[12:8], D17

BA[N:0]: SDRAMs D[7:4], D[16:13]

RBA[N:0]B

RA[N:0]A

RA[N:0]B

→

A[N:0]: SDRAMs D[3:0], D[12:8], D17

→

A[N:0]: SDRAMs D[7:4], D[16:13]

RRASA

RRASB

→

RAS: SDRAMs D[3:0], D[12:8], D17

RAS: SDRAMs D[7:4], D[16:13]

CAS

RCASA

RCASB

RWEA

RWEB

RCKE0A

RCKE0B

→

CAS: SDRAMs D[3:0], D[12:8], D17

CAS: SDRAMs D[7:4], D[16:13]

WE

→

WE: SDRAMs D[3:0], D[12:8], D17

WE: SDRAMs D[7:4], D[16:13]

CKE0: SDRAMs D[3:0], D[12:8], D17

CKE0: SDRAMs D[7:4], D[16:13]

CKE0

ODT0

P

L

RODT0A

RODT0B

→

ODT0: SDRAMs D[3:0], D[12:8]. D17

ODT0: SDRAMs D[7:4], D[16:13]

L

CK0

PCK0A

PCK0B

→

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

PCK0A

PCK0B

→

CK: SDRAMs D[3:0], D8

CK: SDRAMs D[7:4]

PAR_IN

OERR

Err_Out

RESET

RST

RST: SDRAMs D[17:0]

* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330

resistor to ground.)

Ω

Rev. 0.4 / Jul. 2009

15

3.4 4GB, 512Mx72 Module(2Rank of x4)-page1

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQS17

VSS

DQS8

VSS

CB[7:4]

DQ [3:0]

D17

D12

D11

D10

D0

DQ [3:0]

D35

D30

D29

D28

D18

CB[3:0]

DQ [3:0]

D8

D3

D2

D1

D9

DQ [3:0]

D26

D21

D20

D19

D27

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS12

VSS

DQS3

VSS

DQ[31:28]

DQ[27:24]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS11

VSS

DQS2

VSS

DQ[23:20]

DQ[19:16]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS10

VSS

DQS1

VSS

DQ[15:12]

DQ[11:8]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS0

VSS

DQS9

VSS

DQ[3:0]

DQ[7:4]

Vtt

Rev. 0.4 / Jul. 2009

16

3.4 4GB, 512Mx72 Module(2Rank of x4)-page2

DQS

DQS14

DQS13

DQS14

VSS

DQS

DM

DQS

DM

DQS13

VSS

DQS

DM

DQS

DM

DQ[47:44]

DQ [3:0]

D14

DQ [3:0]

D32

D22

D34

D25

DQ[39:36]

DQ [3:0]

D13

DQ [3:0]

D31

D23

D33

D24

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS4

VSS

DQS5

VSS

D4

D5

DQ[35:32]

DQ[43:40]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS16

VSS

DQS15

VSS

DQ[63:60]

D16

DQ[55:52]

D15

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS

DM

DQ [3:0]

DQS7

VSS

DQS6

VSS

DQ[59:56]

D7

DQ[51:48]

D6

Vtt

V

SPD

DDSPD

VDDSPD

EVENT

SCL

VDDSPD

SA0

SA1

SA2

VSS

VDD

D0–D35

EVENT SPD with SA1

V

TT

Integrated

SCL

SA2

VSS

VREFCA

VREFDQ

TS

SDA

VSS

D0–D35

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

Note:

1. DQ-to-I/O wiring may be changed within a nibble.

2. See wiring diagrams for all resistors values.

3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.

Rev. 0.4 / Jul. 2009

17

3.4 4GB, 512Mx72 Module(2Rank of x4)-page3

S0

S1

RS0A

RS0B

RS1A

RS1B

→

CS0: SDRAMs D[3:0], D[12:8], D17

CS0: SDRAMs D[7:4], D[16:13]

1:2

→

CS1: SDRAMs D[21:18], D[30:26], D35

CS1: SDRAMs D[25:22], D[34:31]

R

E

G

I

S

T

E

R

/

BA[N:0]

A[N:0]

RBA[N:0]A

→

BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RBA[N:0]B

→

RA[N:0]A

RA[N:0]B

→

A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

→

A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RAS

CAS

RRASA

RRASB

→

RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RCASA

RCASB

RWEA

RWEB

RCKE0A

RCKE0B

RCKE1A

RCKE1B

→

CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

WE

→

WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

CKE0

CKE1

→

CKE0: SDRAMs D[3:0], D[12:8], D17

CKE0: SDRAMs D[7:4], D[16:13]

P

L

→

CKE1: SDRAMs D[21:18], D[30:26], D35

CKE1: SDRAMs D[25:22], D[34:31]

ODT0

RODT0A

RODT0B

→

ODT0: SDRAMs D[3:0], D[12:8], D17

ODT0: SDRAMs D[7:4], D[16:13]

ODT1

CK0

RODT1A

→

ODT1: SDRAMs D[21:18], D[30:26], D35

ODT1: SDRAMs D[25:22], D[34:31]

PCK0A

PCK0B

PCK1A

PCK1B

PCK0A

PCK0B

PCK1A

PCK1B

→

CK: SDRAMs D[3:0], D[12:8], D17

CK: SDRAMs D[7:4], D[16:13]

→

CK: SDRAMs D[21:18], D[30:26], D35

CK: SDRAMs D[25:22], D[34:31]

CK: SDRAMs D[3:0], D[12:8], D17

CK: SDRAMs D[7:4], D[16:13]

CK: SDRAMs D[21:18], D[30:26], D35

CK: SDRAMs D[25:22], D[34:31]

CK0

CK1

120

Ω

±5%

CK1

PAR_IN

Err_Out

RESET

RST

RST: SDRAMs D[35:0]

* S[3:2], CK1 and CK1 are NC

Rev. 0.4 / Jul. 2009

18

3.5 4GB, 512Mx72 Module(4Rank of x8)-page1

DQS

DQS0

DM0/TDQS9

TDQS9

DQ[7:0]

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

U2

U3

U4

U5

U6

U11

U12

U13

U14

U15

U20

U21

U22

U23

U24

U29

U30

U31

U32

U33

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS1

DM1/TDQS10

TDQS10

DQ[15:8]

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS2

DM2/TDQS11

TDQS11

DQ[32:16]

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS3

DM3/TDQS12

TDQS12

DQ[31:24]

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS8

DM8/TDQS17

TDQS17

CB[7:0]

Vtt

Rev. 0.4 / Jul. 2009

19

3.5 4GB, 512Mx72 Module(4Rank of x8)-page2

DQS

DQS4

DM4/TDQS13

TDQS13

DQ[39:32]

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

TDQS

DQ [7:0]

ZQ

U7

U16

U17

U18

U19

U25

U26

U27

U28

U34

U35

U36

U37

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS5

DM5/TDQS14

TDQS14

DQ[47:40]

U8

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS6

DM6/TDQS15

TDQS15

DQ[55:48]

U9

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS

TDQS

DQ [7:0]

ZQ

DQS3

DM3/TDQS12

TDQS12

DQ[31:24]

U10

Vtt

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

VDDSPD

SA0

EVENT SPD with SA1

SA1

SA2

VSS

EVENT

SCL

Integrated

SCL

SA2

VSS

TS

SDA

V_DDSPD

Serial PD

U1–U37

VDD

Notes:

V_TT

1. DQ-to-I/O wiring may be changed within a byte.

2. See wiring diagrams for resistor values.

3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.

U1-U37

V

REFCA

V

REFDQ

VSS

U1-U37

Rev. 0.4 / Jul. 2009

20

3.5 4GB, 512Mx72 Module(4Rank of x8)-page3

S0

S1

S2

S3

CS0

CS1

CS2

CS3

WBA[N:0]

EBA[N:0]

WA[N:0]

→

CS0: SDRAMs U[10:2]

CS1: SDRAMs U[19:11]

CS2: SDRAMs U[28:20]

CS3: SDRAMs U[37:29]

1:2

R

E

G

I

S

T

E

R

/

BA[N:0]

→BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]

→

BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]

A[N:0]

RAS

→A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]

EA[N:0]

→

A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]

RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]

RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]

WRAS

ERAS

WCAS

ECAS

WWE

EWE

WCKE0 →

ECKE0

WCKE1

ECKE1

WODT0

EODT0

WODT0

EODT0

PCK0

PCK1

PCK2

PCK3

PCK0

PCK1

PCK2

PCK3

→

CAS

CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]

CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]

WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]

WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]

CKE0: SDRAMs U[6:2], U[24:20]

→CKE0: SDRAMs U[10:7], U[28:25]

WE

CKE0

CKE1

ODT0

ODT1

CK0

P

L

→

CKE1: SDRAMs U[15:11], U[33:29]

→CKE1: SDRAMs U[19:16], U[37:34]

→

ODT0: SDRAMs U[6:2]

→

ODT0: SDRAMs U[10:7]

→

ODT1: SDRAMs U[24:20]

→

ODT1: SDRAMs U[28:25]

→

CK: SDRAMs U[6:2], U[15:11]

CK: SDRAMs U[10:7], U[28:25]

CK: SDRAMs U[24:20], U[33:29]

CK: SDRAMs U[19:16], U[37:34]

CK: SDRAMs U[6:2], U[15:11]

CK: SDRAMs U[10:7], U[28:25]

CK: SDRAMs U[24:20], U[33:29]

CK: SDRAMs U[19:16], U[37:34]

CK0

CK1

120

Ω

±5%

CK1

PAR_IN

Err_Out

RESET

RST

RST: SDRAMs U[37:2]

Rev. 0.4 / Jul. 2009

21

3.6 8GB, 1Gx72 Module(4Rank of x4)-page1

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS8

VSS

DQS

DM

D9

D7

D5

D3

D1

D8

D6

D4

D2

D0

D45

D47

D49

D51

D53

D44

D46

D48

D50

D52

CB[3:0]

DQ [3:0]

VSS

DQS3

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[27:24]

DQ [3:0]

VSS

DQS2

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[19:16]

DQ [3:0]

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS1

VSS

DQS

DM

DQ[11:8]

DQ [3:0]

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS0

VSS

DQS

DM

DQ[3:0]

DQ [3:0]

Vtt

Rev. 0.4 / Jul. 2009

22

3.6 8GB, 1Gx72 Module(4Rank of x4)-page2

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS17

VSS

DQS

DM

D27

D25

D23

D21

D19

D26

D24

D22

D20

D18

D63

D65

D67

D69

D71

D62

D64

D66

D68

D70

CB[7:4]

DQ [3:0]

VSS

DQS12

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[31:28]

DQ [3:0]

VSS

DQS11

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[23:20]

DQ [3:0]

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS10

VSS

DQS

DM

DQ[11:8]

DQ [3:0]

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS9

VSS

DQS

DM

DQ[7:4]

DQ [3:0]

Vtt

Rev. 0.4 / Jul. 2009

23

3.6 8GB, 1Gx72 Module(4Rank of x4)-page3

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS4

VSS

DQS

DM

D11

D13

D15

D17

D10

D12

D14

D16

D13

D41

D39

D37

D42

D40

D38

D36

DQ[35:32]

DQ [3:0]

VSS

DQS5

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[43:40]

DQ [3:0]

VSS

DQS6

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[51:48]

DQ [3:0]

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS7

VSS

DQS

DM

DQ[59:56

DQ [3:0]

Vtt

Rev. 0.4 / Jul. 2009

24

3.6 8GB, 1Gx72 Module(4Rank of x4)-page4

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS13

VSS

DQS

DM

D29

D31

D33

D35

D28

D30

D32

D34

D61

D59

D57

D55

D60

D58

D56

D54

DQ[39:36]

DQ [3:0]

VSS

DQS14

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[47:44]

DQ [3:0]

VSS

DQS15

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[55:52]

DQ [3:0]

VSS

ZQ

VSS

ZQ

VSS

ZQ

VSS

ZQ

DQS

DM

DQS

DM

DQS

DM

DQS16

VSS

DQS

DM

DQ[63:60]

DQ [3:0]

Vtt

V

SPD

DDSPD

VDDSPD

EVENT

SCL

VDDSPD

SA0

SA1

SA2

VSS

V

DD

D0–D71

EVENT SPD with SA1

V

TT

Integrated

SCL

SA2

VSS

D0–D71

VREFCA

VREFDQ

TS

SDA

VSS

D0–D71

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

Note:

1. DQ-to-I/O wiring may be changed within a nibble.

2. Unless otherwise noted, resistor values are 15 Ohms ± 5%.

3. See the wiring diagrams for all resistors associated with the command, address and

control bus.

4. ZQ resistors are 240 Ohms ±1%. For all other resistor values refer to the appropriate

wiring diagram.

Rev. 0.4 / Jul. 2009

25

3.6 8GB, 1Gx72 Module(4Rank of x4)-page5

S0

ARS0A

ARS0B

→

CS1: SDRAMs D1,D3,D5,D7 D9,

D19, D21, D23, D25, D27

CS1: SDRAMs D11, D13, D15, D17,

D29, D31, D33, D35

S2

BRS2A

BRS2B

→

CS1: SDRAMs D45,D47,D49,D51,D53

D63,D65,D67,D69,D71

CS1: SDRAMs D37,D39,D41,D43,

D55,D57,D59,D61

1:2

R

E

G

I

S

T

E

R

/

R

E

G

I

S

T

E

R

/

S1

S3

ARS1A

ARS1B

→

CS0: SDRAMs D0, D2, D4, D6, D8,

D18, D20, D22, D24, D26

CS0: SDRAMs D10, D12, D14, D16,

BRS3A

BRS3B

→

CS0: SDRAMs D44.D46,D48,D50,D52,

D62,D64,D66,D68,D70

CS0: SDRAMs D36,D38,D40,D42,

D28, D30, D32, D34

D54,D56,D58,D60

BA[N:0]

A[N:0]

ARBA[N:0]A

ARBA[N:0]B

→

BA[N:0]: SDRAMs D[9:0],D[27:18] BA[N:0]

BA[N:0]: SDRAMs D[17:10],D[35:28]

BRBA[N:0]A

BRBA[N:0]B

→

BA[N:0]: SDRAMs D[53:44],D[71:62]

→

→BA[N:0]: SDRAMs D[43:36],D[61:54]

ARA[N:0]A

→

A[N:0]: SDRAMs D[9:0],D[27:18]

BRA[N:0]A

→

A[N:0]: SDRAMs D[55:44],D[71:62]

A[N:0]

ARA[N:0]B

→

A[N:0]: SDRAMs D[17:10],D[35:28]

BRA[N:0]B

→A[N:0]: SDRAMs D[43:36],D[61:54]

RAS

CAS

RAS

ARRASA

ARRASB

→

RAS: SDRAMs D[9:0],D[27:18]

RAS: SDRAMs D[17:10],D[35:28]

BRRASA

BRRASB

→

RAS: SDRAMs D[53:44],D[71:62]

RAS: SDRAMs D[43:36],D[61:54]

P

L

P

L

ARCASA

ARCASB

ARWEA

ARWEB

→

CAS: SDRAMs D[9:0],D[27:18]

CAS: SDRAMs D[17:10],D[35:28]

BRCASA

BRCASB

BRWEA

→

CAS: SDRAMs D[53:44],D[71:62]

CAS: SDRAMs D[43:36],D[61:54]

CAS

→

WE: SDRAMs D[9:0],D[27:18]

WE: SDRAMs D[17:10],D[35:28]

→

WE: SDRAMs D[53:44],D[71:62]

WE

BRWEB →WE: SDRAMs D[43:36],D[61:54]

ARCKE0A

ARCKE0B

ARCKE1A

ARCKE1B

→

CKE1: SDRAMs D1,D3,D5,D7,D9,

D19, D21, D23, D25, D27

CKE1: SDRAMs D11,D13,D15,D17,

D29, D31, D33, D35

CKE0: SDRAMs D0,D2,D4,D6,D8,

D18, D20, D22, D24, D26

CKE0: SDRAMs D10,D12,D14,D16,

D28, D30, D32, D34

ODT1: SDRAMs D1,D3,D5,D7,D9,

D19, D21, D23, D25, D27

ODT0: SDRAMs D11,D13,D15,D17,

BRCKE0A

BRCKE0B

BRCKE1A

BRCKE1B

→

CKE1: SDRAMs D45,D47,D49,D51,D53,

D63,D65,D67,D69,D71

CKE1: SDRAMs D37,D39,D41,D43,

D55,D57,D59,D61

CKE0: SDRAMs D44.D46,D48,D50,D52,

D62,D64,D66,D68,D70

CKE0: SDRAMs D36,D38,D40,D42,

D54,D56,D58,D60

ODT1: SDRAMs D45,D47,D49,D51,D53

D63,D65,D67,D69,D71

ODT0: SDRAMs D37,D39,D41,D43

CKE0

A

B

→

CKE1

ODT0

CKE1

ODT1

ARODT0A

ARODT0B

→

BRODT1A

BRODT1B

→

D29, D31, D33, D35

D55,D57,D59,D61

APCK0A

APCK0B

APCK1A

APCK1B

APCK0A

APCK0B

APCK1A

APCK1B

→

CK: SDRAMs D[9:0]

CK: SDRAMs D[17:10]

CK: SDRAMs D[27:18]

CK: SDRAMs D[35:28]

CK: SDRAMs D[9:0]

CK: SDRAMs D[17:10]

CK: SDRAMs D[27:18]

CK: SDRAMs D[35:28]

BPCK0A

BPCK0B

BPCK1A

BPCK1B

BPCK0A

BPCK0B

BPCK1A

BPCK1B

→

CK: SDRAMs D[53:44]

CK: SDRAMs D[43:36]

CK: SDRAMs D[71:62]

CK: SDRAMs D[61:54]

CK: SDRAMs D[53:44]

CK: SDRAMs D[43:36]

CK: SDRAMs D[71:62]

CK: SDRAMs D[61:54]

CK0

→

120

Ω

120

Ω

±5%

PAR_IN

Err_Out

RESET

RST

RESET

RST

RST: SDRAMs D[35:0]

* S[3:2], CK1 and CK1 are NC

CK1

120Ω

±5%

CK1

Rev. 0.4 / Jul. 2009

26

4. Environmental Parameter

Environmental Parameters

Symbol

Parameter

Operating temperature

Rating

Units

Notes

T

See Note

3

OPR

H

Operating humidity (relative)

10 to 90

-50 to +100

5 to 95

%

1

OPR

o

T

Storage temperature

C

STG

H

Storage humidity (without condensation)

Barometric Pressure (operating & storage)

%

1

STG

P

105 to 69

K Pascal

1, 2

BAR

Note:

1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional

operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended

periods may affect reliablility.

2. Up to 9850 ft.

3. The designer must meet the case temperature specifications for individual module components.

Rev. 0.4 / Jul. 2009

27

5. Pin Capacitance (VDD=1.5V, VDDQ=1.5V)

1GB: HMT112R7AFP8C

Symbol

Min

Max

Unit

pF

CK0, CK0

CKE, ODT

CS

CCK

CI1

CI2

CI3

CIO

TBD

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

2GB: HMT125R7AFP8C

Symbol

Min

Max

Unit

pF

CK0, CK0

CCK

CI1

CI2

TBD

CKE, ODT

CS

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

CI3

CIO

2GB: HMT125R7AFP4C

Symbol

Min

Max

Unit

pF

CK0, CK0

CCK

CI1

CI2

CI3

CIO

TBD

CKE, ODT

CS

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

4GB: HMT151R7AFP4C

Symbol

Min

Max

Unit

pF

CK0, CK0

CCK

CI1

CI2

CI3

CIO

TBD

CKE, ODT

CS

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

Rev. 0.4 / Jul. 2009

28

4GB: HMT151R7AFP8C

Symbol

Min

Max

Unit

pF

CK0, CK0

CCK

CI1

CI2

CI3

CIO

TBD

CKE, ODT

CS

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

8GB: HMT31GR7AMP4C

Symbol

Min

Max

Unit

pF

CK0, CK0

CCK

CI1

CI2

CI3

CIO

TBD

CKE, ODT

CS

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

Note:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Rev. 0.4 / Jul. 2009

29

o

6. IDD Specifications (Tcase: 0 to 95 C)

1GB, 128M x 72 R-DIMM: HMT112R7AFP8C

Symbol

IDD0

DDR3 800

1484

1664

1259

1304

1502

318

DDR3 1066

1592

1799

1349

1394

1502

318

DDR3 1333

1664

1889

1439

1484

1502

318

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

462

480

498

1259

1349

498

1349

1439

588

1439

1529

633

2024

1304

2204

2474

318

2294

1304

2564

318

2654

1304

2834

2654

318

IDD6ET

IDD6TC

IDD7

336

2654

3014

3464

2GB, 256M x 72 R-DIMM: HMT125R7AFP8C

Symbol

IDD0

DDR3 800

1979

2159

1754

1844

2240

408

DDR3 1066

2177

2384

1934

2024

2240

408

DDR3 1333

2399

2564

2114

2204

2240

408

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

696

732

768

1754

1934

798

1934

2114

948

2114

2294

1038

3329

1979

3509

3329

408

2519

1799

2699

2969

408

2879

1889

3149

408

IDD6ET

IDD6TC

IDD7

444

3149

3599

4139

Rev. 0.4 / Jul. 2009

30

2GB, 256M x 72 R-DIMM: HMT125R7AFP4C

Symbol

IDD0

DDR3 800

2204

2564

1754

1844

2240

408

DDR3 1066

2420

2834

1934

2024

2240

408

DDR3 1333

2564

3014

2114

2204

2240

408

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

696

732

768

1754

1934

768

1934

2114

948

2114

2294

1038

4544

1844

4904

4544

408

3284

1844

3644

4184

408

3824

1844

4364

408

IDDET

IDD6TC

IDD7

444

4544

5264

6164

4GB, 512M x 72 R-DIMM: HMT151R7AFP4C

Symbol

IDD0

DDR3 800

3194

3554

2744

2924

3716

588

DDR3 1066

3590

4004

3104

3284

3716

588

DDR3 1333

3914

4364

3464

3644

3716

588

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

1164

2744

3104

1308

4274

2834

4634

5174

588

1236

3104

3464

1668

4994

3014

5534

588

1308

3464

3824

1848

5894

3194

6254

5894

588

IDDET

IDD6TC

IDD7

660

5534

6434

7514

Rev. 0.4 / Jul. 2009

31

4GB, 512M x 72 R-DIMM: HMT151R7AFP8C

Symbol

IDD0

DDR3 800

2969

3149

2744

2924

3716

588

DDR3 1066

3347

3554

3104

3284

3716

588

DDR3 1333

3689

3914

3464

3644

3716

588

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

1164

2744

3104

1308

3509

2789

3689

3959

588

1236

3104

3464

1668

4049

3059

4319

588

1308

3464

3824

1848

4679

3329

4859

4679

588

IDDET

IDD6TC

IDD7

660

4139

4769

5489

8GB, 1G x 72 R-DIMM: HMT31GR7AMP4C

Symbol

IDD0

DDR3 800

5174

5534

4724

5084

6668

948

DDR3 1066

5930

6344

5444

5804

6668

948

DDR3 1333

6614

7064

6164

6524

6668

948

Unit

mA

note

IDD1

IDD2N

IDD2NT

IDDQ2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

2100

4724

5444

2388

6254

4814

6614

7154

948

2244

5444

6164

3108

7334

5354

7874

948

2388

6164

6884

3468

8594

5894

8954

8594

948

IDDET

IDD6TC

IDD7

1092

7514

1092

8774

1092

10214

Rev. 0.4 / Jul. 2009

32

7.1 128Mx72 - HMT112R7AFP8C

Front

133.35

128.95

SPD/TS

2.10

± 0.15

4X3.00

± 0.10

Detail A

Detail B

Detail C

1

120

1

2X3.00

±

0.10

5.175

71.00

47.00

5.0

Back

121

240

1

Side

3.43mm max

Detail of Contacts C

Detail of Contacts A

Detail of Contacts B

1.20

± 0.15

0.80

± 0.05

2.50

3

± 0.1

0.3~0.1

1.00

1.50

±0.10

5.00

1.27 ± 010mm

max

Rev. 0.4 / Jul. 2009

33

7.2 256Mx72 - HMT125R7AFP8C

Front

133.35

128.95

SPD/TS

2.10

± 0.15

4X3.00

± 0.10

Detail A

Detail C

Detail B

47.00

1

120

1

2X3.00

±

0.10

5.175

71.00

5.0

Back

121

240

1

Side

3.43mm max

Detail of Contacts C

Detail of Contacts A

Detail of Contacts B

1.20

± 0.15

0.80

± 0.05

2.50

3

± 0.1

0.3+0.1

1.00

1.50

±0.10

5.00

1.27 ± 010mm

max

6.3 256Mx72 - HMT125R7AFP4C

Rev. 0.4 / Jul. 2009

34

7.3 256Mx72 - HMT125R7AFP4C

Front

133.35

128.95

SPD/TS

2.10

± 0.15

4X3.00

± 0.10

Detail A

2X3.00

Detail C

Detail B

47.00

1

120

1

±

0.10

5.175

71.00

5.0

Back

121

240

1

Side

3.43mm max

Detail of Contacts C

Detail of Contacts A

Detail of Contacts B

1.20

± 0.15

0.80

± 0.05

2.50

3

± 0.1

0.3~0.1

1.00

1.50

±0.10

5.00

1.27 ± 010mm

max

Rev. 0.4 / Jul. 2009

35

7.4 512Mx72 - HMT151R7AFP4C

Front

133.35

Detail B

128.95

SPD/TS

2.10

± 0.15

4X3.00

± 0.10

Detail A

1

120

1

2X3.00

± 0.10

71.00

47.00

Detail C

5.175

Detail D

5.0

Back

121

240

1

Side

3.46mm max

Detail of Contacts D

Detail of Contacts A

Detail of Contacts B

Detail of Contacts C

1.20

± 0.15

0.80

± 0.05

2.50

14.90

13.60

0.4

3

± 0.1

0.3~0.1

1.00

1.50

±0.10

5.00

1.27 ±010mm

max

Rev. 0.4 / Jul. 2009

36

7.4 512Mx72 - HMT151R7AFP4C - Heat Spreader

Front

133.75

133.35

127

42.7

2.786

20.9

6.35

8

3.69

5.39

7.74

6.3

2.15

36.7

120

1

7.36

33.4

46.46

80.54

119.64

Back

57.2

2.7

121

240

Side

7.19mm max

1.27 ±010mm

max

Rev. 0.4 / Jul. 2009

37

7.5 512Mx72 - HMT151R7AFP8C

Front

14.90

13.60

Detail B

2.10

± 0.15

SPD/TS

3

±

0.1

Min 1.45

Detail A

1

120

2X3.0

± 0.10

71.00

47.00

Detail C

5.175

Detail D

5.0

128.95

133.35

Back

121

240

1

Side

3.46mm max

Detail of Contacts D

Detail of Contacts A

Detail of Contacts B

Detail of Contacts C

1.20

± 0.15

0.80

± 0.05

2.50

14.90

0.4

13.60

3

± 0.1

0.3~0.1

1.00

1.50

±0.10

5.00

1.27 ± 010mm

max

Rev. 0.4 / Jul. 2009

38

7.5 512Mx72 - HMT151R7AFP8C - Heat Spreader

Front

133.75

133.35

127

42.7

2.786

20.9

6.35

8

3.69

5.39

7.74

6.3

2.15

36.7

120

1

7.36

33.4

46.46

80.54

119.64

Back

57.2

2.7

121

240

Side

7.19mm max

1.27 ±010mm

max

Rev. 0.4 / Jul. 2009

39

7.6 1Gx72 - HMT31GR7AMP4C

Front

133.35

128.95

Detail B

SPD/TS

2.10

± 0.15

DDP

4X3.00

± 0.10

Detail A

DDP

1

120

1

2X3.00

±

0.10

5.175

71.00

47.00

Detail C

Detail D

5.0

Back

DDP

240

DDP

121

1

Side

3.69mm max

Detail of Contacts D

Detail of Contacts A

Detail of Contacts B

Detail of Contacts C

1.20

± 0.15

0.80

± 0.05

2.50

14.90

0.4

13.60

3

± 0.1

0.3~0.1

1.00

1.50

±0.10

5.00

1.27 ± 010mm

max

Rev. 0.4 / Jul. 2009

40

7.6 1Gx72 - HMT31GR7AMP4C - Heat Spreader

Front

133.75

133.35

127

42.7

2.786

20.9

6.35

5.16

4.06

8.2

7.74

1.1

10.1

2.15

36.7

6.8

120

1

7.36

33.4

46.46

80.54

119.64

Back

57.2

2.7

121

240

Side

7.35mm max

1.27 ±010mm

max

Rev. 0.4 / Jul. 2009

41


型号：	HMT151R7AFP4C-G7
厂家：	HYNIX SEMICONDUCTOR
描述：	DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, RDIMM-240 时钟动态存储器双倍数据速率内存集成电路
文件：	总41页 (文件大小：1649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HMT151R7AFP4C-G7 [HYNIX]

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