HMT325U6BFR8C_技术文档

240pin DDR3 SDRAM Registered DIMM

DDR3 SDRAM

Unbuffered DIMMs

Based on 2Gb B-Die

HMT325U6BFR8C

HMT325U7BFR8C

HMT351U6BFR8C

HMT351U7BFR8C

* Hynix Semiconductor reserves the right to change products or specifications without notice.

Rev. 0.2 / Feb. 2010

1

Revision History

Revision No.

History

Draft Date

Dec. 2009

Feb. 2010

Remark

0.1

Initial Release

0.2

Added IDD Specification

Rev. 0.2 / Feb. 2010

2

Description

Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line

Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM

devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems

such as PCs and workstations.

Features

• VDD=1.5V +/- 0.075V

• VDDQ=1.5V +/- 0.075V

• VDDSPD=3.0V to 3.6V

• Functionality and operations comply with the

DDR3 SDRAM datasheet

• 8 internal banks

• Data transfer rates: PC3-10600, PC3-8500, or

PC3-6400

• Bi-directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly: BL 8 or BC

(Burst Chop) 4

• Supports ECC error correction and detection

• On Die Termination (ODT) supported

• Temperature sensor with integrated SPD (Serial

Presence Detect) EEPROM

• RoHS compliant

* This product is in compliance with the RoHS directive.

Ordering Information

# of

ranks

Part Number

Density Organization

Component Composition

FDHS

HMT325U6BFR8C-G7/H9/PB

HMT325U7BFR8C-G7/H9/PB

HMT351U6BFR8C-G7/H9/PB

HMT351U7BFR8C-G7/H9/PB

2GB

4GB

256Mx64

256Mx72

512Mx64

512Mx72

256Mx8(H5TQ2G83BFR)*8

256Mx8(H5TQ2G83BFR)*9

256Mx8(H5TQ2G83BFR)*16

256Mx8(H5TQ2G83BFR)*18

1

2

X

Rev. 0.2 / Feb. 2010

3

Key Parameters

CAS

Latency

(tCK)

tCK

(ns)

tRCD

(ns)

tRP

(ns)

tRAS

(ns)

tRC

(ns)

MT/s

Grade

CL-tRCD-tRP

DDR3-1066

DDR3-1333

DDR3-1600

-G7

-H9

-PB

1.875

1.5

7

9

13.125

13.5

13.125

13.5

37.5

36

50.625

49.5

7-7-7

9-9-9

1.25

11

13.75

35

48.75

11-11-11

Speed Grade

Frequency [MHz]

Grade

CL6

Remark

CL7

CL8

CL9

CL10

CL11

-G7

-H9

-PB

800

1066

1333

1600

Address Table

2GB(1Rx8)

4GB(2Rx8)

Refresh Method

Row Address

Column Address

Bank Address

Page Size

8K/64ms

A0-A14

A0-A9

8K/64ms

A0-A14

A0-A9

8K/64ms

A0-A14

A0-A9

8K/64ms

A0-A14

A0-A9

BA0-BA2

1KB

BA0-BA2

1KB

BA0-BA2

1KB

BA0-BA2

1KB

Rev. 0.2 / Feb. 2010

4

Pin Descriptions

Pin Name

Description

SDRAM address bus

SDRAM bank select

Pin Name

SCL

Description

I²C serial bus clock for EEPROM

A0–A15

I²C serial bus data line for EEPROM

BA0–BA2

SDA

I²C slave address select for EEPROM

SDRAM core power supply

RAS

CAS

SDRAM row address strobe

SDRAM column address strobe

SDRAM write enable

SA0–SA2

VDD

*

VDDQ_*

WE

SDRAM I/O Driver power supply

SDRAM I/O reference supply

S0–S1

DIMM Rank Select Lines

VREFDQ

SDRAM command/address reference

supply

CKE0–CKE1

SDRAM clock enable lines

VREFCA

ODT0–ODT1

DQ0–DQ63

CB0–CB7

On-die termination control lines

DIMM memory data bus

DIMM ECC check bits

VSS

VDDSPD

NC

Power supply return (ground)

Serial EEPROM positive power supply

Spare pins (no connect)

SDRAM data strobes

(positive line of differential pair)

Memory bus analysis tools

(unused on memory DIMMS)

DQS0–DQS8

DM0–DM8

CK0–CK1

TEST

SDRAM data strobes

(negative line of differential pair)

RESET

Set DRAMs to Known State

SDRAM I/O termination supply

Reserved for future use

-

SDRAM data masks/high data strobes

(x8-based x72 DIMMs)

VTT

SDRAM clocks

(positive line of differential pair)

RSVD

-

SDRAM clocks

(negative line of differential pair)

CK0–CK1

*The VDD and VDDQ pins are tied common to a single power-plane on these designs

Rev. 0.2 / Feb. 2010

5

Input/Output Functional Descriptions

Symbol

Type

Polarity

Function

CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl

CK0–CK1

Differential inputs are sampled on the crossing of positive edge of CK and negative

SSTL

crossing

edge of CK. Output (read) data is reference to the crossing of CK and CK

(Both directions of crossing).

Activates the SDRAM CK signal when high and deactivates the CK signal

CKE0–CKE1

S0–S1

SSTL

Active High when low. By deactivating the clocks, CKE low initiates the Power Down

mode, or the Self Refresh mode.

Enables the associated SDRAM command decoder when low and disables

the command decoder when high. When the command decoder is dis-

abled, new commands are ignored but previous operations continue. This

Active Low

signal provides for external rank selection on systems with multiple ranks.

RAS, CAS, WE

ODT0–ODT1

SSTL

Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.

When high, termination resistance is enabled for all DQ, DQS, DQS and DM

Active High

pins, assuming this function is enabled in the Mode Register 1 (MR1).

VREFDQ

VREFCA

Supply

Reference voltage for SSTL15 I/O inputs.

Reference voltage for SSTL 15 command/address inputs.

Power supply for the DDR3 SDRAM output buffers to provide improved

noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ

shares the same power plane as VDD pins.

VDDQ

Supply

SSTL

BA0–BA2

—

Selects which SDRAM bank of eight is activated.

During a Bank Activate command cycle, Address input defines the row

address (RA0–RA15).

During a Read or Write command cycle, Address input defines the column

address. In addition to the column address, AP is used to invoke autopre-

charge operation at the end of the burst read or write cycle. If AP is high,

autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-

charged. If AP is low, autoprecharge is disabled. During a Precharge com-

mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which

bank(s) to precharge. If AP is high, all banks will be precharged regardless

of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to

define which bank to precharge. A12(BC) is sampled during READ and

WRITE commands to determine if burst chop (on-the-fly) will be per-

formed (HIGH, no burst chop; LOW, burst chopped).

A0–A15

SSTL

DQ0–DQ63,

CB0–CB7

SSTL

—

Data and Check Bit Input/Output pins.

DM is an input mask signal for write data. Input data is masked when DM

is sampled High coincident with that input data during a write access. DM

is sampled on both edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading.

DM0–DM8

VDD, VSS

Active High

Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD

and VDDQ pins are tied to VDD/VDDQ planes on these modules.

Supply

Rev. 0.2 / Feb. 2010

6

Symbol

Type

Polarity

Function

Data strobe for input and output data.

DQS0–DQS8

Differential

crossing

SSTL

These signals are tied at the system planar to either VSS or VDDSPD to con-

figure the serial SPD EEPROM address range.

SA0–SA2

—

This bidirectional pin is used to transfer data into or out of the SPD

EEPROM. An external resistor may be connected from the SDA bus line to

VDDSPD to act as a pullup on the system board.

SDA

—

This signal is used to clock data into and out of the SPD EEPROM. An

external resistor may be connected from the SCL bus time to VDDSPD to act

as a pullup on the system board.

SCL

—

Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ

power plane. EEPROM supply is operable from 3.0V to 3.6V.

VDDSPD

Supply

Pin Assignments

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

1

2

VREFDQ

VSS

VREFDQ 121

V

SS

V

SS

61

62

63

64

65

66

67

68

69

70

A2

VDD

A2

181

182

183

184

185

186

A1

VDD

CK0

VDD

NC

A1

VDD

CK0

VDD

NC

V

SS

122

123

124

125

DQ4

DQ5

DQ4

DQ5

VDD

CK1

VDD

3

DQ0

DQ1

CK1

VDD

4

DQ1

VSS

5

VSS

DM0

NC

DM0

NC

6

DQS0

DQS0 126

DQS0 127

VDD

7

VSS

VREFCA

NC

VREFCA 187

8

VSS

V

SS

128

129

130

DQ6

DQ7

DQ6

DQ7

NC

VDD

A10

188

189

190

A0

9

DQ2

DQ3

DQ2

DQ3

VDD

BA1²

VDD

RAS

S0

10

VSS

A10

BA0²

VDD

WE

BA0²

VDD

WE

11

12

13

14

15

16

VSS

V

SS

131

132

133

134

DQ12

DQ13

DQ12

DQ13

71

72

73

74

75

76

191

192

193

194

195

196

VDD

RAS

S0

DQ8

DQ9

DQ8

DQ9

VSS

DM1

NC

DM1

NC

CAS

VDD

S1

CAS

VDD

S1

VDD

ODT0

A13

VDD

ODT0

A13

DQS1

DQS1 135

DQS1 136

VSS

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.

Rev. 0.2 / Feb. 2010

7

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

V

SS

V

SS

137

DQ14

DQ15

DQ14

DQ15

77

78

ODT1

VDD

NC

ODT1

VDD

NC

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

VDD

NC

VDD

NC

DQ10

DQ11

DQ10 138

DQ11 139

VSS

79

VSS

140

141

DQ20

DQ21

DQ20

DQ21

80

VSS

DQ36

DQ37

DQ36

DQ37

DQ16

DQ17

DQ16

81

DQ32

DQ33

DQ32

DQ33

DQ17 142

143

VSS

82

VSS

DM2

NC

DM2

NC

83

VSS

DM4

NC

DM4

NC

DQS2

DQS2 144

DQS2 145

84

DQS4

VSS

85

VSS

146

DQ22

DQ23

DQ22

DQ23

86

VSS

DQ38

DQ39

DQ38

DQ39

DQ18

DQ19

DQ18 147

DQ19 148

87

DQ34

DQ35

DQ34

DQ35

VSS

88

VSS

149

DQ28

DQ29

DQ28

DQ29

89

VSS

DQ44

DQ45

DQ44

DQ45

DQ24

DQ25

DQ24 150

DQ25 151

90

DQ40

DQ41

DQ40

DQ41

VSS

91

VSS

152

DM3

NC

DM3

NC

92

VSS

DM5

NC

DM5

NC

DQS3

DQS3 153

DQS3 154

93

DQS5

VSS

94

VSS

155

DQ30

DQ31

DQ30

DQ31

95

VSS

DQ46

DQ47

DQ46

DQ47

DQ26

DQ27

DQ26 156

DQ27 157

96

DQ42

DQ43

DQ42

DQ43

VSS

97

VSS

158

159

160

161

NC

CB4

CB5

98

VSS

DQ52

DQ53

DQ52

DQ53

NC

CB0

CB1

99

DQ48

DQ49

DQ48

DQ49

VSS

100

101

102

103

104

105

106

107

VSS

DM8

NC

DM8

NC

VSS

DM6

NC

DM6

NC

DQS8 162

DQS8 163

DQS6

VSS

164

165

166

167

NC

CB6

CB7

VSS

DQ54

DQ55

DQ54

DQ55

NC

CB2

CB3

DQ50

DQ51

DQ50

DQ51

VSS

NC

VSS

DQ60

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.

Rev. 0.2 / Feb. 2010

8

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

#

x64

Non-ECC

x72

ECC

48

NC

KEY

NC

168

Reset

108

109

110

111

112

113

114

115

116

117

DQ56

DQ57

DQ56

DQ57

228

229

230

231

232

233

234

235

236

237

DQ61

KEY

VSS

49

50

51

52

53

54

55

56

NC

CKE0

VDD

BA2

NC

169 CKE1/NC

CKE1/NC

VDD

NC

VSS

DM7

NC

DM7

NC

CKE0

VDD

BA2

NC

170

171

172

173

174

175

176

VDD

NC

DQS7

VSS

NC

VSS

DQ62

DQ63

DQ62

DQ63

VDD

A12

A9

VDD

A12

A9

DQ58

DQ59

DQ58

DQ59

VDD

All

VDD

All

VSS

VDDSPD

SA1

VDDSPD

SA1

A7²

VDD

A7²

VDD

SA0

SCL

SA2

VTT

SA0

SCL

SA2

VTT

A8²

A6²

VDD

A8²

A6²

VDD

57

58

59

60

177

178

179

180

118

119

120

238

239

240

SDA

A5²

A4²

VDD

A5²

A4²

VDD

VSS

VTT

A3²

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.

Rev. 0.2 / Feb. 2010

9

On DIMM Thermal Sensor

The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal

sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.

Connection of Thermal Sensor

EVENT

SCL

SDA

SA0

SA1

SA2

EVENT

SCL

SPD with

Integrated

TS

SA0

SA1

SA2

SDA

Temperature-to-Digital Conversion Performance

Parameter

Temperature Sensor Accuracy (Grade B)

Resolution

Condition

Min

Typ

Max

Unit

Active Range,

75°C < T_A< 95°C

-

± 0.5

± 1.0

°C

Monitor Range,

40°C < T_A< 125°C

-

± 2.0

± 3.0

°C

-20°C < T_A< 125°C

± 2.0

°C

0.25

Rev. 0.2 / Feb. 2010

10

Functional Block Diagram

2GB, 256Mx64 Module(1Rank of x8)

S0

DQS0

DQS4

DM4

DQS0

DM0

DM CS

DQS DQS

DM CS DQS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4

D0

ZQ

DQS5

DM5

DQS1

DM1

DQS

DM CS

DM CS DQS DQS

I/O 0

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ8

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D5

D1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

ZQ

DQS6

DM6

DQS2

DM2

DQS DQS

DM CS

DM CS DQS DQS

I/O 0

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D6

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

ZQ

DQS7

DM7

DQS3

DM3

CS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

D7

DM CS DQS DQS

I/O 0

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

ZQ

Serial PD

Notes:

SCL

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS/DQS resistors;Refer to

associated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring details

section of this document.

5. Refer to Section 3.1 of this document for

details on address mirroring.

SDA

WP

A0

A1

A2

BA0–BA2

BA0–BA2: SDRAMs D0–D7

SA0 SA1 SA2

A0–A15

RAS

A0–A15: SDRAMs D0–D7

RAS: SDRAMs D0–D7

CAS: SDRAMs D0–D7

CAS

V

DDSPD

SPD

CKE: SDRAMs D0–D7

CKE0

V

DD/VDD

Q

D0–D7

WE: SDRAMs D0–D7

ODT: SDRAMs D0–D7

CK: SDRAMs D0–D7

WE

ODT0

CK0

VREFDQ

6. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

D0–D7

V

SS

CK0

D0–D7

V

REFCA

7. One SPD exists per module.

RESET

RESET: SDRAMs D0-D7

Rev. 0.2 / Feb. 2010

11

2GB, 256Mx72 Module(1Rank of x8)

S0

DQS0

DM0

DQS4

DM4

DM CS

I/O 0

DQS DQS

DQS

CS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4

D0

ZQ

DQS5

DM5

DQS1

DM1

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS

CS DQS DQS

D1

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

ZQ

DQS6

DM6

DQS2

DM2

DQS DQS

DM CS

I/O 0

DQS

CS DQS

D2

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D6

ZQ

DQS7

DM7

DQS3

DM3

CS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS

DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D7

D3

ZQ

DQS8

DM8

SPD(TS integrated)

EVENT

DQS

CS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Notes:

SCL

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S rela-

tionships must be maintained as

shown.

D8

SDA

EVENT

A0

A1

A2

SA0 SA1

SA2

ZQ

3. DQ,CB,DM,DQS/DQS resistors;Refer

to associated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring

details section of this document.

5. For each DRAM, a unique ZQ resistor

is connected to ground.The ZQ resis-

tor is 240ohm+-1%

BA0–BA2

BA0–BA2: SDRAMs D0–D8

A0–A15: SDRAMs D0–D8

RAS: SDRAMs D0–D8

A0–A15

RAS

VDDSPD

SPD

VDD/VDDQ

D0–D8

CAS

CKE0

WE

ODT0

CK0

CAS: SDRAMs D0–D8

CKE: SDRAMs D0–D8

WE: SDRAMs D0–D8

ODT: SDRAMs D0–D8

CK: SDRAMs D0–D8

VREFDQ

VSS

D0–D8

6. One SPD exists per module.

VREFCA

D0–D8

RESET

RESET: SDRAMs D0-D8

Rev. 0.2 / Feb. 2010

12

4GB, 512Mx64 Module(2Rank of x8)

S1

S0

DQS0

DM0

DQS4

DM4

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D12

D4

D8

D0

ZQ

DQS1

DM1

DQS5

DM5

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ10

DQ11

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D13

D5

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D9

D1

DQ12

DQ13

DQ14

DQ15

ZQ

DQS6

DM6

DQS2

DM2

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D14

D6

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D10

D2

ZQ

DQS3

DM3

DQS7

DM7

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D15

D7

D11

D3

ZQ

Serial PD

ZQ

Notes:

BA0–BA2

A0–A15

CKE1

CKE0

RAS

BA0–BA2: SDRAMs D0–D15

A0-A15: SDRAMs D0–D15

CKE: SDRAMs D8–D15

CKE: SDRAMs D0–D7

RAS: SDRAMs D0–D15

CAS: SDRAMs D0–D15

WE: SDRAMs D0–D15

SCL

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS,DQS resistors;Refer to

associated topology diagram.

SDA

WP

A0

A1

A2

SA0 SA1 SA2

CAS

VDDSPD

SPD

WE

4. Refer to Section 3.1 of this document for

details on address mirroring.

VDD/VDDQ

D0–D15

ODT0

ODT1

CK0

ODT: SDRAMs D0–D7

ODT: SDRAMs D8–D15

CK: SDRAMs D0–D7

CK: SDRAMs D8–D15

VREFDQ

VSS

5. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

D0–D15

CK0

VREFCA

6. One SPD exists per module.

CK1

D0–D15

CK1

RESET

RESET: SDRAMs D0-D3

Rev. 0.2 / Feb. 2010

13

4GB, 512Mx72 Module(2Rank of x8)

S1

S0

DQS0

DM0

DQS4

DM4

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

D4

D13

D9

D0

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

ZQ

DQS1

DM1

DQS5

DM5

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D14

D5

I/O 1

D1

D10

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

ZQ

DQS6

DM6

DQS2

DM2

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D15

D11

D6

D2

ZQ

DQS3

DM3

DQS7

DM7

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D16

D7

D12

D3

ZQ

VDDSPD

SPD

DQS8

DM8

SPD(TS integrated)

VDD/VDDQ

D0–D17

SCL

V

REFDQ

DM CS DQS DQS

I/O 0

DM CS DQS DQS

I/O 0

SDA

EVENT

Vss

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

D0–D17

A0

A1

A2

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D17

D8

VREFCA

SA0 SA1

SA2

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,CB,DM/DQS/DQS resistors;Refer to

associated topology diagram.

ZQ

BA0–BA2

A0–A15

CKE0

CKE1

RAS

BA0-BA2: SDRAMs D0–D17

A0-A15: SDRAMs D0–D17

CKE: SDRAMs D0–D8

CKE: SDRAMs D9–D17

RAS: SDRAMs D0–D17

CAS: SDRAMs D0–D17

4. Refer to Section 3.1 of this document for

details on address mirroring.

ODT0

ODT: SDRAMs D0–D8

ODT: SDRAMs D9–D17

CK: SDRAMs D0–D8

CK: SDRAMs D9–D17

RESET: SDRAMs D0-D17

ODT1

CK0

CK1

5. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

6. One SPD exists per module.

CAS

WE

WE: SDRAMs D0–D17

RESET

Rev. 0.2 / Feb. 2010

14

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Units

Notes

VDD

- 0.4 V ~ 1.975 V

V

1,

VDDQ

V_IN, V_OUT

T_STG

- 0.4 V ~ 1.975 V

-55 to +100

V

1,

1

V

^oC

1, 2

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement

conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

DRAM Component Operating Temperature Range

Temperature Range

Symbol

Parameter

Normal Operating Temperature Range

Extended Temperature Range

Rating

Units

^oC

Notes

0 to 85

1,2

T_OPER

85 to 95

^oC

1,3

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-

surement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-

ing operation, the DRAM case temperature must be maintained between 0 - 85^oC under all operating conditions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85^oC and 95^oC

case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It

is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.

Please refer to the DIMM SPD for option availability

b. Hynix DDR3 SDRAMs support Auto Self-Refresh and Extended Temperature Range and please refer to Hynix

component datasheet and/or the DIMM SPD for tREFI requirement in the Extended Temperature Range.

Rev. 0.2 / Feb. 2010

15

AC & DC Operating Conditions

Recommended DC Operating Conditions

Rating

Symbol

Parameter

Units Notes

Min.

Typ.

Max.

VDD

1.425

1.500

1.575

V

1,2

Supply Voltage

Supply Voltage for Output

VDDQ

1.425

1.500

1.575

Notes:

1. Under all conditions, VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

AC & DC Input Measurement Levels

AC and DC Logic Input Levels for Single-Ended Signals

AC and DC Input Levels for Single-Ended Command and Address Signals

Single Ended AC and DC Input Levels for Command and Address

DDR3-800/1066/1333/1600

Symbol

Parameter

Unit Notes

Min

Max

VIH.CA(DC100)

VIL.CA(DC100)

VIH.CA(AC175)

VIL.CA(AC175)

VIH.CA(AC150)

VIL.CA(AC150)

DC input logic high

DC input logic low

Vref + 0.100

VSS

VDD

V

1

Vref - 0.100

Note2

1

AC input logic high

Vref + 0.175

Note2

1, 2

3, 4

AC input logic low

Vref - 0.175

Note2

AC Input logic high

Vref + 0.150

Note2

AC input logic low

Vref - 0.150

0.51 * VDD

V_RefCA(DC

Notes:

1. For input only pins except RESET, Vref = VrefCA (DC).

2. Refer to “Overshoot and Undershoot Specifications” on page 29.

)

Reference Voltage for ADD, CMD inputs

0.49 * VDD

3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for

RefCA(DC)

Ref

reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

Rev. 0.2 / Feb. 2010

16

AC and DC Input Levels for Single-Ended Signals

DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table

below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “DDR3 Device

Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-

els.

Single Ended AC and DC Input Levels for DQ and DM

DDR3-800/1066

DDR3-1333/1600

Symbol

Parameter

Unit Notes

Min

Max

Min

Max

VIH.CA(DC100)

VIL.CA(DC100)

VIH.CA(AC175)

VIL.CA(AC175)

VIH.CA(AC150)

VIL.CA(AC150)

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC Input logic high

AC input logic low

Vref + 0.100

VSS

VDD

Vref + 0.100

VDD

V

1

Vref - 0.100

Note2

VSS

Vref - 0.100

1

Vref + 0.175

Note2

-

1, 2

Vref - 0.175

Note2

Vref + 0.150

Note2

Vref + 0.150

Note2

Vref - 0.150

Reference Voltage for DQ,

DM inputs

V_RefDQ(DC

)

0.49 * VDD

0.51 * VDD

0.49 * VDD

0.51 * VDD

V

3, 4

Notes:

1. Vref = VrefDQ (DC).

2. Refer to “Overshoot and Undershoot Specifications” on page 29.

3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for

RefDQ(DC)

Ref

reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

Rev. 0.2 / Feb. 2010

17

Vref Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages

and V

are illustrated in

RefDQ

VRefCA

figure below. It shows a valid reference voltage V (t) as a function of time. (V stands for V and

RefCA

Ref

V

likewise).

RefDQ

V

(DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to

Ref

meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page 24. Further-

more V (t) may temporarily deviate from V

by no more than +/- 1% VDD.

Ref

Ref (DC)

voltage

VDD

V

(t)

Ref

V

ac-noise

Ref

V

Ref(DC)max

V

Ref(DC)

VDD/2

V

Ref(DC)min

VSS

time

Illustration of V

tolerance and V

ac-noise limits

Ref(DC)

Ref

The voltage levels for setup and hold time measurements V

, V

, and V

are depen-

IH(AC)

IH(DC)

IL(AC)

IL(DC)

dent on V

.

Ref

“V ” shall be understood as V

, as defined in figure above.

Ref

Ref(DC)

This clarifies that dc-variations of V affect the absolute voltage a signal has to reach to achieve a valid

Ref

high or low level and therefore the time to which setup and hold is measured. System timing and voltage

budgets need to account for V

deviations from the optimum position within the data-eye of the input

Ref(DC)

signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and

voltage associated with V ac-noise. Timing and voltage effects due to ac-noise on V up to the speci-

Ref

fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.

Rev. 0.2 / Feb. 2010

18

AC and DC Logic Input Levels for Differential Signals

Differential signal definition

t

DVAC

V_{IL.DIFF.AC.MIN}

V_IL.DIFF.MIN

0

half cycle

V

IL.DIFF.MAX

V_{IL.DIFF.AC.MAX}

t

DVAC

time

Definition of differential ac-swing and “time above ac-level” t

DVAC

Rev. 0.2 / Feb. 2010

19

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)

Differential AC and DC Input Levels

DDR3-800, 1066, 1333, & 1600

Symbol

Parameter

Unit Notes

Min

Max

VIHdiff

VILdiff

Differential input high

Differential input logic low

Differential input high ac

Differential input low ac

+ 0.200

Note 3

- 0.200

V

1

2

VIHdiff (ac)

VILdiff (ac)

2 x (VIH (ac) - Vref)

Note 3

2 x (VIL (ac) - Vref)

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL

(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level

applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-

tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 29.

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 350mV

@ |VIH/Ldiff (ac)| = 300mV

Slew Rate [V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

> 4.0

4.0

-

3.0

2.0

1.8

-

1.6

1.4

1.2

1.0

< 1.0

0

Rev. 0.2 / Feb. 2010

20

Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has

also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH

(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)

/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if

VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-

ended signals CK and CK.

VDD or VDDQ

VSEHmin

VSEH

VDD/2 or VDDQ/2

CK or DQS

VSELmax

VSEL

VSS or VSSQ

time

Single-ended requirements for differential signals.

Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-

nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the

transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended

components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,

but adds a restriction on the common mode characteristics of these signals.

Rev. 0.2 / Feb. 2010

21

Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU

DDR3-800, 1066, 1333, & 1600

Symbol

Parameter

Unit Notes

Min

Max

Single-ended high level for strobes

Single-ended high level for Ck, CK

Single-ended low level for strobes

Single-ended low level for CK, CK

(VDD / 2) + 0.175

(VDD /2) + 0.175

Note 3

V

1,2

VSEH

VSEL

Note 3

(VDD / 2) = 0.175

Note 3

Notes:

1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)

of DQs.

2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced

ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-

tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 29.

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and

strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the

requirements in table below. The differential input cross point voltage VIX is measured from the actual

cross point of true and complement signals to the midlevel between of VDD and VSS

VDD

CK, DQS

V

IX

VDD/2

V

IX

V

IX

CK, DQS

VSS

Vix Definition

Rev. 0.2 / Feb. 2010

22

Cross point voltage for differential input signals (CK, DQS)

DDR3-800, 1066, 1333, & 1600

Parameter

Symbol

Unit Notes

Min

Max

-150

-175

150

175

mV

Differential Input Cross Point Voltage

relative to VDD/2 for CK, CK

V_IX

mV

1

Differential Input Cross Point Voltage

relative to VDD/2 for DQS, DQS

-150

150

mV

Notes:

1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are

IX

monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential

slew rate of CK - CK is larger than 3 V/ns.

2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 22

for VSEL and VSEH standard values.

Slew Rate Definitions for Single-Ended Input Signals

See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-

gle-ended slew rate definitions for address and command signals.

See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-

ended slew rate definition for data signals.

Rev. 0.2 / Feb. 2010

23

Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table

and Figure below.

Differential Input Slew Rate Definition

Measured

Description

Defined by

Max

Min

Differential input slew rate for rising edge

(CK-CK and DQS-DQS)

VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff

VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff

Differential input slew rate for falling edge

(CK-CK and DQS-DQS)

Notes:

The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.

Delta

TRdiff

vIHdiffmin

0

vILdiffmax

Delta

TFdiff

Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#

Differential Input Slew Rate Definition for DQS, DQS and CK, CK

Rev. 0.2 / Feb. 2010

24

AC & DC Output Measurement Levels

Single Ended AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Single-ended AC and DC Output Levels

DDR3-800, 1066,

Symbol

Parameter

Unit

Notes

1333 and 1600

V_OH(DC)

V_OM(DC)

V_OL(DC)

V_OH(AC)

V_OL(AC)

0.8 x V_DDQ

V

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

0.5 x V_DDQ

0.2 x V_DDQ

V_TT+ 0.1 x V_DDQ

1

V

_TT- 0.1 x V_DDQ

Notes:

1. The swing of ±0.1 x V

is based on approximately 50% of the static single ended output high or low

DDQ

swing with a driver impedance of 40Ω and an effective test load of 25Ω to V = V

/ 2.

DDQ

TT

Differential AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Differential AC and DC Output Levels

DDR3-800, 1066,

Symbol

Parameter

Unit

Notes

1333 and 1600

V_{OHdiff (AC)}

V_{OLdiff (AC)}

Notes:

1. The swing of ±0.2 x V

+ 0.2 x V_DDQ

V

1

AC differential output high measurement level (for output SR)

- 0.2 x V_DDQ

AC differential output low measurement level (for output SR)

is based on approximately 50% of the static differential output high or low

DDQ

swing with a driver impedance of 40Ω and an effective test load of 25Ω to V = V

/2 at each of the

DDQ

TT

differential outputs.

Rev. 0.2 / Feb. 2010

25

Single Ended Output Slew Rate

When the Reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between V

and V

for single ended signals are shown in table and Figure below.

OL(AC)

OH(AC)

Single-ended Output slew Rate Definition

Measured

Description

Defined by

From

V_OL(AC)

V_OH(AC)

To

V_OH(AC)

V_OL(AC)

[V_OH(AC)-V_OL(AC)] / DeltaTRse

[V_OH(AC)-V_OL(AC)] / DeltaTFse

Single-ended output slew rate for rising edge

Single-ended output slew rate for falling edge

Notes:

1. Output slew rate is verified by design and characterisation, and may not be subject to production test.

Delta TRse

vOH(AC)

V∏

vOl(AC)

Delta TFse

Single Ended Output Slew Rate Definition

Single Ended Output slew Rate Definition

Output Slew Rate (single-ended)

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Single-ended Output Slew Rate

SRQse

2.5

5

2.5

5

2.5

5

TBD

5

V/ns

Description: SR; Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

Rev. 0.2 / Feb. 2010

26

Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and Figure

below.

Differential Output Slew Rate Definition

Measured

Description

Defined by

From

To

V_{OHdiff (AC)}[V_{OHdiff (AC)}-V_{OLdiff (AC)}] / DeltaTRdiff

V_{OLdiff (AC)}[V_{OHdiff (AC)}-V_{OLdiff (AC)}] / DeltaTFdiff

V_{OLdiff (AC)}

V_{OHdiff (AC)}

Differential output slew rate for rising edge

Differential output slew rate for falling edge

Notes:

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Delta

TRdiff

vOHdiff(AC)

O

vOLdiff(AC)

Delta

TFdiff

Differential Output Slew Rate Definition

Differential Output slew Rate Definition

Differential Output Slew Rate

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Differential Output Slew Rate

Description: SR; Slew Rate

SRQdiff

5

10

5

10

5

10

TBD

10

V/ns

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

Rev. 0.2 / Feb. 2010

27

Reference Load for AC Timing and Output Slew Rate

Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing

parameters of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the

actual load presented by a production tester. System designers should use IBIS or other simulation tools to

correlate the timing reference load to a system environment. Manufacturers correlate to their production

test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

VDDQ

25 Ohm

CK, CK

DQ

DQS

VTT = VDDQ/2

DUT

Reference Load for AC Timing and Output Slew Rate

Rev. 0.2 / Feb. 2010

28

Overshoot and Undershoot Specifications

Address and Control Overshoot and Undershoot Specifications

AC Overshoot/Undershoot Specification for Address and Control Pins

DDR3- DDR3- DDR3- DDR3-

Parameter

Units

800

1066

1333

1600

Maximum peak amplitude allowed for overshoot area. (See Figure below)

Maximum peak amplitude allowed for undershoot area. (See Figure below)

Maximum overshoot area above VDD (See Figure below)

0.4

0.5

0.4

V

0.67

0.33

V-ns

Maximum undershoot area below VSS (See Figure below)

(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)

See figure below for each parameter definition

Maximum Amplitude

Overshoot Area

VDD

VSS

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Address and Control Overshoot and Undershoot Definition

Rev. 0.2 / Feb. 2010

29

Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask

DDR3- DDR3- DDR3- DDR3-

Parameter

Units

800

1066

1333

1600

Maximum peak amplitude allowed for overshoot area. (See Figure below)

Maximum peak amplitude allowed for undershoot area. (See Figure below)

Maximum overshoot area above VDD (See Figure below)

Maximum undershoot area below VSS (See Figure below)

(CK, CK, DQ, DQS, DQS, DM)

0.4

V

0.25

0.19

0.15

0.13

V-ns

See figure below for each parameter definition

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Clock, Data Strobe and Mask Overshoot and Undershoot Definition

Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

Rev. 0.2 / Feb. 2010

30

Refresh parameters by device density

Parameter

RTT_Nom Setting

512Mb

90

1Gb

2Gb

4Gb

8Gb

Units Notes

REF command ACT or

REF command time

tRFC

110

160

300

350

ns

0 °C ≤ T

85 °C < T

≤ 85 °C

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

us

Average periodic

refresh interval

CASE

tREFI

≤ 95 °C 3.9

CASE

Rev. 0.2 / Feb. 2010

31

Standard Speed Bins

DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

DDR3-800 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 36.

Speed Bin

DDR3-800E

6-6-6

Unit

Notes

CL - nRCD - nRP

Parameter

Symbol

min

max

t_AA

15

20

ns

Internal read command to first data

ACT to internal read or write delay time

PRE command period

t_RCD

15

—

t_RP

t_RC

52.5

37.5

ACT to ACT or REF command period

ACT to PRE command period

t_RAS

9 * tREFI

3.3

t_CK(AVG)

Reserved

ns

CL = 5

CL = 6

CWL = 5

1, 2, 3, 4

1, 2, 3

2.5

n_CK

6

5

Supported CL Settings

Supported CWL Settings

Rev. 0.2 / Feb. 2010

32

DDR3-1066 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 36.

Speed Bin

DDR3-1066F

7-7-7

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

max

Internal read command to

first data

t_AA

13.125

20

ns

ACT to internal read or

write delay time

t_RCD

13.125

50.625

37.5

—

t_RP

PRE command period

ACT to ACT or REF

command period

t_RC

—

ACT to PRE command

period

t_RAS

9 * tREFI

t_CK(AVG)

CWL = 5

CL = 5

Reserved

ns

1, 2, 3, 4, 5

CWL = 6

4

CWL = 5

CL = 6

2.5

3.3

ns

1, 2, 3, 5

1, 2, 3, 4

4

CWL = 6

Reserved

ns

CWL = 5

CL = 7

ns

CWL = 6

1.875

< 2.5

ns

1, 2, 3, 4

4

CWL = 5

CL = 8

Reserved

ns

CWL = 6

ns

1, 2, 3

n_CK

Supported CL Settings

Supported CWL Settings

6, 7, 8

5, 6

Rev. 0.2 / Feb. 2010

33

DDR3-1333 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 36.

Speed Bin

DDR3-1333H

9-9-9

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

13.5

max

Internal read command

to first data

t_AA

t_RCD

t_RP

20

ns

(13.125)⁸

13.5

(13.125)⁸

ACT to internal read or

write delay time

—

13.5

(13.125)⁸

PRE command period

49.5

(49.125)⁸

ACT to ACT or REF

command period

t_RC

ACT to PRE command

period

t_RAS

36

9 * tREFI

t_CK(AVG)

CWL = 5

CL = 5

Reserved

ns

1,2, 3,4, 6

CWL = 6, 7

4

CWL = 5

2.5

3.3

1, 2, 3, 6

CL = 6

CL = 7

CL = 8

CWL = 6

CWL = 7

CWL = 5

Reserved

1, 2, 3, 4, 6

4

1.875

< 2.5

t_CK(AVG)

CWL = 6

ns

1, 2, 3, 4, 6

Reserved

t_CK(AVG)

CWL = 7

CWL = 5

ns

1, 2, 3, 4

4

CWL = 6

1, 2, 3, 6

1, 2, 3, 4

4

CWL = 7

Reserved

CWL = 5, 6

CWL = 7

CL = 9

1.5

<1.875

1, 2, 3, 4

CWL = 5, 6

Reserved

4

CL = 10

ns

1, 2, 3

t_CK(AVG)

CWL = 7

n_CK

Supported CL Settings

Supported CWL Settings

6, 8, (7), 9, (10)

5, 6, 7

n_CK

Rev. 0.2 / Feb. 2010

34

DDR3-1600 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 36.

Speed Bin

DDR3-1600K

11-11-11

Unit

Note

CL - nRCD - nRP

Parameter

Symbol

min

13.75

max

Internal read command

to first data

t_AA

t_RCD

t_RP

20

ns

(13.125)⁸

13.75

(13.125)⁸

ACT to internal read or

write delay time

—

13.75

(13.125)⁸

PRE command period

48.75

(48.125)⁸

ACT to ACT or REF

command period

t_RC

ACT to PRE command

period

t_RAS

35

9 * tREFI

t_CK(AVG)

CWL = 5

CL = 5

Reserved

ns

1, 2, 3, 4, 7

CWL = 6, 7

4

CWL = 5

2.5

3.3

1, 2, 3, 7

CL = 6

CL = 7

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5, 6

CWL = 7

CWL = 8

CWL = 5, 6

Reserved

1, 2, 3, 4, 7

4

1.875

1.5

< 2.5

1, 2, 3, 4, 7

4

Reserved

4

1, 2, 3, 7

1, 2, 3, 4, 7

1, 2, 3, 4

4

CL = 8

CL = 9

Reserved

<1.875

1, 2, 3, 4, 7

1, 2, 3, 4

4

Reserved

CL = 10

CL = 11

t_CK(AVG)

CWL = 7

CWL = 8

1.5

<1.875

<1.5

ns

1, 2, 3, 7

1,2,3,4

Reserved

CWL = 5, 6,7

CWL = 8

ns

4

t_CK(AVG)

1.25

1, 2, 3

n_CK

Supported CL Settings

Supported CWL Settings

6, (7), 8, (9), 10, 11

5, 6, 7, 8

n_CK

Rev. 0.2 / Feb. 2010

35

Speed Bin Table Notes

Absolute Specification (T_OPER; V_DDQ= V_DD= 1.5V +/- 0.075 V);

Notes:

1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making

a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements

from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized

by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the

next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] =

tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’.

3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG)

down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX

corresponding to CLSE LECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table

which are not subject to Production Tests but verified by Design/Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table

which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table

which are not subject to Production Tests but verified by Design/Characterization.

8. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini-

mum value of 13.125ns. SPD settings are also programmed to match. For example, DDR3 1333H devices

supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16),

tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H

or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRP-

min (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be pro-

grammed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H

and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.

Rev. 0.2 / Feb. 2010

36

Environmental Parameters

Symbol

Parameter

Rating

Units

Notes

o

T

0 to +55

C

3

OPR

Operating temperature (ambient)

Operating humidity (relative)

H

10 to 90

-50 to +100

5 to 95

%

OPR

o

T

Storage temperature

1

C

STG

H

Storage humidity (without condensation)

Barometric Pressure (operating & storage)

%

STG

P

105 to 69

K Pascal

1, 2

BAR

Note:

1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating

only, and device functional operation at or above the conditions indicated is not implied. Expousure to

absolute maximum rating conditions for extended periods may affect reliablility.

2. Up to 9850 ft.

3. The component maximum case Temperature (T_CASE) shall not exceed the value specified in the DDR3

DRAM component specification.

Rev. 0.2 / Feb. 2010

37

Pin Capacitance (VDD=1.5V, VDDQ=1.5V)

2GB: HMT325U6BFR8C

Symbol

C_CK

Min

TBD

Max

TBD

Unit

pF

CK0, CK0

pF

C_CTRL

C_I

CKE, ODT, CS

pF

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

pF

C_IO

2GB: HMT325U7BFR8C

CK0, CK0

Symbol

C_CK

Min

TBD

Max

TBD

Unit

pF

C_CTRL

C_I

CKE, ODT, CS

pF

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

pF

C_IO

4GB: HMT351U6BFR8C

Symbol

C_CK

Min

TBD

Max

TBD

Unit

pF

CK0, CK0

pF

C_CTRL

C_I

CKE, ODT, CS

pF

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

pF

C_IO

4GB: HMT351U7BFR8C

Symbol

C_CK

Min

TBD

Max

TBD

Unit

pF

CK0, CK0

pF

C_CTRL

C_I

CKE, ODT, CS

pF

Address, RAS, CAS, WE

DQ, DM, DQS, DQS

pF

C_IO

Note:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Rev. 0.2 / Feb. 2010

38

IDD and IDDQ Specification Parameters and Test Conditions

IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure

below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup

and test load for IDD and IDDQ measurements.

•

IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,

IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all

VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-

rents.

•

IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all

VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-

rents.

Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can

be used to support correlation of simulated IO power to actual IO power as outlined in the Figure

below (Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ

Measurement). In DRAM module application, IDDQ cannot be measured separately since VDD and

VDDQ are using on merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply:

•

”0” and “LOW” is defined as VIN <= V

ILAC(max).

”1” and “HIGH” is defined as VIN >= V

IHAC(max).

•

“MID_LEVEL” is defined as inputs are VREF = VDD/2.

Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.

Basic IDD and IDDQ Measurement Conditions are described in Table 2.

Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.

IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-

ited to setting

RON = RZQ/7 (34 Ohm in MR1);

Qoff = 0 (Output Buffer enabled in MR1);

B

RTT_Nom = RZQ/6 (40 Ohm in MR1);

RTT_Wr = RZQ/2 (120 Ohm in MR2);

TDQS Feature disabled in MR1

•

Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time

before actual IDD or IDDQ measurement is started.

Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

Rev. 0.2 / Feb. 2010

39

IDDQ (optional)

IDD

VDD

RESET

CK/CK

VDDQ

DDR3

SDRAM

RTT = 25 Ohm

CKE

CS

DQS, DQS

DQ, DM,

VDDQ/2

RAS, CAS, WE

TDQS, TDQS

A, BA

ODT

ZQ

VSS

VSSQ

Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements

[Note: DIMM level Output test load condition may be different from above

Application specific

memory channel

environment

IDDQ

Test Load

Channel

IO Power

Simulation

IDDQ

Simulation

IDDQ

Simulation

Correction

Channel IO Power

Number

Correlation from simulated Channel IO Power to actual Channel IO Power supported

by IDDQ Measurement

Rev. 0.2 / Feb. 2010

40

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns

DDR3-1066

DDR3-1333

DDR3-1600

Symbol

Unit

7-7-7

1.875

7

9-9-9

1.5

9

11-11-11

t_CK

1.25

11

39

28

11

24

32

5

ns

CL

nCK

n_RCD

n_RC

n_RAS

n_RP

7

9

27

20

7

33

24

9

1KB page size

2KB page size

1KB page size

2KB page size

20

27

4

20

30

4

n_FAW

n_RRD

6

5

6

n_RFC-512Mb

n_RFC-1 Gb

n_RFC- 2 Gb

n_RFC- 4 Gb

n_RFC- 8 Gb

48

59

86

160

187

60

74

107

200

234

72

88

128

240

280

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8^a); AL: 0; CS: High between ACT and

PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;

DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output

I_DD0

Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 3.

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8^a); AL: 0; CS: High between ACT,

RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:

stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and

I_DD1

RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 4.

Rev. 0.2 / Feb. 2010

41

Symbol

Description

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

I_DD2N

banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details:

see Table 5.

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

I_DD2NT

banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: toggling according to Table 6;

Pattern Details: see Table 6.

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output

I_DD2P0

Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Slow

Exit^c)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output

I_DD2P1

Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit^c)

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output

I_DD2Q

Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

I_DD3N

banks open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see

Table 5.

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer

I_DD3P

and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0

Rev. 0.2 / Feb. 2010

42

Symbol

Description

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between RD; Command, Address,

Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different

data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,

RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode

I_DD4R

Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 7.

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between WR; Command, Address,

Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different

data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,

WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode

I_DD4W

Registers^b); ODT Signal: stable at HIGH; Pattern Details: see Table 8.

Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8^a); AL: 0; CS: High between REF; Command,

Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;

I_DD5B

Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers^b);

ODT Signal: stable at 0; Pattern Details: see Table 9.

Self-Refresh Current: Normal Temperature Range

T_CASE: 0 - 85 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Normal^e); CKE:

I_DD6

Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer

and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL

Self-Refresh Current: Extended Temperature Range

T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Extended^e);

I_DD6ET

CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh

operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL

Auto Self-Refresh Current

T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Enabled^d);Self-Refresh Temperature Range (SRT): Normal^e); CKE:

I_DD6TC

Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output

Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL

Rev. 0.2 / Feb. 2010

43

Symbol

Description

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8^a),f); AL: CL-1; CS:

High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table

10; Data IO: read data burst with different data between one burst and the next one according to Table 10;

DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-

I_DD7

ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern

Details: see Table 10.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]

= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit

d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature

range

f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Rev. 0.2 / Feb. 2010

44

a)

Table 3 - IDD0 Measurement-Loop Pattern

Data^b)

0

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

0

1,2

3,4

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS

PRE

0

1

0

00

0

-

...

repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC+0

1*nRC+1, 2

1*nRC+3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC+nRAS

...

0

1

0

F

0

-

repeat pattern 1...4 until 2*nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 0.2 / Feb. 2010

45

a)

Table 4 - IDD1 Measurement-Loop Pattern

Data^b)

0

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

0

1,2

3,4

...

repeat pattern 1...4 until nRCD - 1, truncate if necessary

RD 00

repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRCD

...

0

1

0

1

0

00000000

-

nRAS

PRE

0

1

0

00

0

...

repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC+0

1*nRC+1,2

1*nRC+3,4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary

RD 00

repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC+nRCD

...

0

1

0

1

0

F

0

00110011

-

1*nRC+nRAS

...

0

1

0

F

0

repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-

LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are

MID_LEVEL.

Rev. 0.2 / Feb. 2010

46

a)

Table 5 - IDD2N and IDD3N Measurement-Loop Pattern

Data^b)

0

D

1

0

1

0

1

0

1

0

F

0

-

0

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

8-11

12-15

16-19

20-23

24-17

28-31

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

a)

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern

Data^b)

0

D

1

0

1

0

1

0

1

0

-

0

1

0

F

0

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

8-11

12-15

16-19

20-23

24-17

28-31

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 0.2 / Feb. 2010

47

a)

Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern

Data^b)

0

RD

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

0

1

-

2,3

D,D

RD

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

a)

Table 8 - IDD4W Measurement-Loop Pattern

Data^b)

0

WR

D

D,D

WR

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

0

1

2,3

4

5

6,7

-

00110011

-

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 0.2 / Feb. 2010

48

a)

Table 9 - IDD5B Measurement-Loop Pattern

Data^b)

0

1

REF

D, D

0

1

0

1

0

1

0

1

0

F

0

-

0

1.2

00

3,4

5...8

repeat cycles 1...4, but BA[2:0] = 1

repeat cycles 1...4, but BA[2:0] = 2

repeat cycles 1...4, but BA[2:0] = 3

repeat cycles 1...4, but BA[2:0] = 4

repeat cycles 1...4, but BA[2:0] = 5

repeat cycles 1...4, but BA[2:0] = 6

repeat cycles 1...4, but BA[2:0] = 7

9...12

13...16

17...20

21...24

25...28

29...32

33...nRFC-1

2

repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Rev. 0.2 / Feb. 2010

49

a)

Table 10 - IDD7 Measurement-Loop Pattern

ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9

Data^b)

0

1

0

1

2

...

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

-

00000000

-

repeat above D Command until nRRD - 1

nRRD

nRRD+1

nRRD+2

...

2*nRRD

3*nRRD

4*nRRD

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

F

0

-

00110011

-

repeat above D Command until 2* nRRD - 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 1, but BA[2:0] = 3

2

3

D

1

0

3

00

0

F

0

-

4

Assert and repeat above D Command until nFAW - 1, if necessary

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 1, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 1, but BA[2:0] = 7

5

6

7

8

nFAW

nFAW+nRRD

nFAW+2*nRRD

nFAW+3*nRRD

nFAW+4*nRRD

D

1

0

7

00

0

F

9

Assert and repeat above D Command until 2* nFAW - 1, if necessary

2*nFAW+0

2*nFAW+1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

F

0

-

00110011

-

10

2&nFAW+2

Repeat above D Command until 2* nFAW + nRRD - 1

2*nFAW+nRRD

2*nFAW+nRRD+1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

-

00000000

-

11

2&nFAW+nRRD+2

Repeat above D Command until 2* nFAW + 2* nRRD - 1

repeat Sub-Loop 10, but BA[2:0] = 2

repeat Sub-Loop 11, but BA[2:0] = 3

12 2*nFAW+2*nRRD

13 2*nFAW+3*nRRD

D

1

0

3

00

0

-

14 2*nFAW+4*nRRD

Assert and repeat above D Command until 3* nFAW - 1, if necessary

repeat Sub-Loop 10, but BA[2:0] = 4

15 3*nFAW

16 3*nFAW+nRRD

17 3*nFAW+2*nRRD

18 3*nFAW+3*nRRD

repeat Sub-Loop 11, but BA[2:0] = 5

repeat Sub-Loop 10, but BA[2:0] = 6

repeat Sub-Loop 11, but BA[2:0] = 7

D

1

0

7

00

0

-

19 3*nFAW+4*nRRD

Assert and repeat above D Command until 4* nFAW - 1, if necessary

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 0.2 / Feb. 2010

50

IDD Specifications (Tcase: 0 to 95^oC)

* Module IDD values in the datasheet are only a calculation based on the component IDD spec.

The actual measurements may vary according to DQ loading cap.

2GB, 256M x 64 U-DIMM: HMT325U6BFR8C

Symbol

IDD0

DDR3 1066

360

DDR3 1333

400

DDR3 1600

440

Unit

mA

note

IDD1

440

480

520

IDD2N

IDD2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

200

240

256

280

320

96

120

200

240

280

320

120

640

760

840

640

760

880

1200

96

1240

96

1280

96

IDD6ET

IDD6TC

IDD7

120

880

1080

1160

2GB, 256M x 72 U-DIMM: HMT325U7BFR8C

Symbol

IDD0

DDR3 1066

405

DDR3 1333

450

DDR3 1600

495

Unit

mA

note

IDD1

495

540

585

IDD2N

IDD2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

225

270

288

315

360

108

135

225

270

315

360

135

720

855

945

720

855

990

1350

108

1395

108

1440

108

IDD6ET

IDD6TC

IDD7

135

990

1215

1305

Rev. 0.2 / Feb. 2010

51

4GB, 512M x 64 U-DIMM: HMT351U6BFR8C

Symbol

IDD0

DDR3 1066

560

DDR3 1333

640

DDR3 1600

760

Unit

mA

note

IDD1

640

720

840

IDD2N

IDD2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

400

480

512

560

640

192

240

400

480

560

640

240

840

1000

1480

192

1160

1200

1600

192

840

1400

192

IDDET

IDD6TC

IDD7

240

1080

1320

1480

4GB, 512M x 72 U-DIMM: HMT351U7BFR8C

Symbol

IDD0

DDR3 1066

630

DDR3 1333

720

DDR3 1600

855

Unit

mA

note

IDD1

720

810

945

IDD2N

IDD2NT

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

450

540

576

630

720

216

270

450

540

630

720

270

945

1125

1665

216

1305

1350

1800

216

945

1575

216

IDDET

IDD6TC

IDD7

270

1215

1485

1665

Rev. 0.2 / Feb. 2010

52

Module Dimensions

256Mx64 - HMT325U6BFR8C

Front

2.10±0.15

Min 1.45

Max R0.70

30.00

SPD

4x3.00±0.10

17.30

DETAIL-B

DETAIL-A

2xφ2.50±0.10

9.50

2x2.30±0.10

47.00

71.00

5.175

128.95

133.35

Back

Side

Detail - A

Detail - B

3.18

FULL R

2.50

0.80±0.05

2.50±0.20

1.00

1.27

± 0.10

0.3~1.0

1.50±0.10

5.00

Note:

1. ±0.13tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 0.2 / Feb. 2010

53

256Mx72 - HMT325U7BFR8C

Front

2.10±0.15

Min 1.45

SPD

Max R0.70

30.00

4x3.00±0.10

17.30

DETAIL-B

DETAIL-A

2xφ2.50±0.10

9.50

2x2.30±0.10

47.00

5.175

71.00

128.95

133.35

Back

Side

3.18

Detail - A

Detail - B

FULL R

2.50

0.80±0.05

2.50±0.20

1.00

1.27

± 0.10

0.3~1.0

1.50±0.10

5.00

Note:

1. ±0.13tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 0.2 / Feb. 2010

54

512Mx64 - HMT351U6BFR8C

Front

2.10±0.15

Min 1.45

Max R0.70

30.00

SPD

4x3.00±0.10

17.30

DETAIL-B

DETAIL-A

2xφ2.50±0.10

9.50

2x2.30±0.10

47.00

71.00

5.175

128.95

133.35

Back

Side

Detail - A

Detail - B

4.00

FULL R

2.50

0.80±0.05

2.50±0.20

1.00

1.27

± 0.10

0.3~1.0

1.50±0.10

5.00

Note:

1. ±0.13tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 0.2 / Feb. 2010

55

512Mx72 - HMT351U7BFR8C

Front

2.10±0.15

Min 1.45

Max R0.70

SPD

30.00

4x3.00±0.10

17.30

DETAIL-B

DETAIL-A

2xφ2.50±0.10

9.50

2x2.30±0.10

47.00

5.175

71.00

128.95

133.35

Back

Side

Detail - A

Detail - B

4.00

FULL R

2.50

0.80±0.05

2.50±0.20

1.00

1.27

± 0.10

0.3~1.0

1.50±0.10

5.00

Note:

1. ±0.13tolerance on all dimensions unless otherwise stated.

Units: millimeters

Rev. 0.2 / Feb. 2010

56


型号：	HMT325U6BFR8C
厂家：	HYNIX SEMICONDUCTOR
描述：	240pin DDR3 SDRAM Registered DIMM 动态存储器双倍数据速率
文件：	总56页 (文件大小：464K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HMT325U6BFR8C [HYNIX]

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