HY27SF082G2B [HYNIX]
2Gbit (256Mx8bit/128Mx16bit) NAND Flash; 2Gb的( 256Mx8bit / 128Mx16bit )NAND闪存型号: | HY27SF082G2B |
厂家: | HYNIX SEMICONDUCTOR |
描述: | 2Gbit (256Mx8bit/128Mx16bit) NAND Flash |
文件: | 总51页 (文件大小:381K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
2Gb NAND FLASH
HY27SF(08/16)2G2B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.3 / Feb. 2008
1
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit/128Mx16bit) NAND Flash Memory
Revision History
Revision No.
History
Draft Date
Remark
0.0
0.1
0.2
Sep. 11. 2007 Preliminary
Dec. 12. 2007 Preliminary
Jan. 17. 2008
Initial Draft.
1) Add Block Protection.
1) Delete Preliminary
1) Change AC Characteristic
tCHZ
30
0.3
Feb. 12. 2008
Before
After
50
Rev 0.3 / Feb. 2008
2
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
STATUS REGISTER
- Cost effective solutions for mass storage applications
- Normal Status Register (Read/Program/Erase)
- Extended Status Register (EDC)
MULTIPLANE ARCHITECTURE
- Array is split into two independent planes. Parallel
Operations on both planes are available, halving
Program and erase time.
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare
size
NAND INTERFACE
- x8/x16 bus width.
- Address/ Data Multiplexing
- Pinout compatiblity for all densities
- 5th cycle : Multiplane information
SUPPLY VOLTAGE
CHIP ENABLE DON’T CARE
- 1.8V device : Vcc = 1.7 V ~1.95 V
- Simple interface with microcontroller
MEMORY CELL ARRAY
BLOCK PROTECTION
- x8 : (2K + 64) bytes x 64 pages x 2048 blocks
- x16 : (1K + 32) words x 64 pages x 2048 blocks
- To Protect Block against Write/Erase
HARDWARE DATA PROTECTION
PAGE SIZE
- Program/Erase locked during Power transitions.
- (2K + 64 spare) Bytes
- (1K + 32 spare) Words
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
BLOCK SIZE
- (128K + 4Kspare) Bytes
- (64K + 2Kspare) Words
PACKAGE
- HY27SF(08/16)2G2B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27SF(08/16)2G2B-T (Lead)
- HY27SF(08/16)2G2B-TP (Lead Free)
PAGE READ / PROGRAM
- Random access : 25us (max.)
- Sequential access : 45ns (min.)
- Page program time : 250us (typ.)
- Multi-page program time (2 pages) : 250us (typ.)
COPY BACK PROGRAM
- Automatic block download without latency time
FAST BLOCK ERASE
- Block erase time: 2.0ms (typ.)
- Multi-block erase time (2 blocks) : 2.0ms (typ.)
CACHE READ
- Internal (2048 + 64) Byte buffer to improve the read
throughtput.
Rev 0.3 / Feb. 2008
3
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1.SUMMARY DESCRIPTION
Hynix NAND HY27SF(08/16)2G2B Series have 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 1.8V Vcc
Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi-
cal 250us and an erase operation can be performed in typical 2.0ms on a 128K-byte block.
Data in the page can be read out at 45ns cycle time per byte(x8). The I/O pins serve as the ports for address and data
input/output as well as command input.
This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The
on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where
required, and internal verification and margining of data. The modify operations can be locked using the WP input. The
output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple mem-
ories the R/B pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management. When a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error
every 528byte (x8) or 1bit error out of every 264-word (x16) can be detected. Due to this feature, it is no more nor neces-
sary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read
(both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the HY27SF(08/16)2G2B Series extended reliability of 100K pro-
gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE
don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro-
controller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension, and Block Protection.
Especially Block Protection allows protection on Block 0 or OTP area of the device against Write/Erase operations on that
block.
The HY27SF(08/16)2G2B Series are available in 48-TSOP1 12 x 20 mm.
1.1 Product List
PART NUMBER
ORGANIZATION
Vcc RANGE
PACKAGE
HY27SF(08/16)2G2B
x8 / x16
1.7V ~ 1.95V
48-TSOP1
Rev 0.3 / Feb. 2008
4
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
9&&
,2ꢀa,2ꢁ
&(
,2ꢂa,2ꢃꢄꢅꢆ[ꢃꢇꢅ2QO\ꢈ
:(
5ꢉ%
5(
$/(
&/(
:3
966
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
ALE
CE
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready / Busy
Vcc
Power Supply
Vss
Ground
NC
No Connection
Table 1: Signal Names
Rev 0.3 / Feb. 2008
5
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
ꢁ
ꢄꢊ
ꢁ
ꢄꢊ
1&
1&
1&
1&
1&
1&
5ꢀ%
5(
9VV
1&
1&
1&
1&
1&
1&
5ꢀ%
5(
1&
1&
1&
1&
,ꢀ2ꢃ
,ꢀ2ꢅ
,ꢀ2ꢂ
,ꢀ2ꢄ
1&
1&
1&
9FF
9VV
1&
1&
1&
,ꢀ2ꢆ
,ꢀ2ꢇ
,ꢀ2ꢁ
,ꢀ2ꢈ
1&
1&
1&
1&
,ꢀ2ꢁꢂ
,ꢀ2ꢃ
,ꢀ2ꢁꢄ
,ꢀ2ꢅ
,ꢀ2ꢁꢆ
,ꢀ2ꢂ
,ꢀ2ꢁꢇ
,ꢀ2ꢄ
1&
1&
9FF
1&
1&
&(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1$1'ꢅ)ODVK
7623ꢃ
1$1'ꢅ)ODVK
7623ꢃ
ꢁꢇ
ꢁꢆ
ꢆꢃ
ꢆꢅ
ꢁꢇ
ꢁꢆ
ꢆꢃ
ꢆꢅ
1&
ꢆ[ꢃꢇꢈ
ꢆ[ꢂꢈ
,ꢀ2ꢁꢁ
,ꢀ2ꢆ
,ꢀ2ꢁꢈ
,ꢀ2ꢇ
,ꢀ2ꢉ
,ꢀ2ꢁ
,ꢀ2ꢊ
,ꢀ2ꢈ
9VV
ꢇꢄ
ꢇꢂ
ꢇꢄ
ꢇꢂ
Figure 2: 48TSOP1 Contact, x8 and x16 Device
Rev 0.3 / Feb. 2008
6
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name
Description
DATA INPUTS/OUTPUTS
IO0-IO7
IO8-IO15(1)
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
ALE
CE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
This input controls the selection of the device.
WRITE ENABLE
WE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
RE
WRITE PROTECT
WP
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
R/B
Vcc
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The Vcc supplies the power for all the operations (Read, Write, Erase).
Vss
NC
GROUND
NO CONNECTION
Table 2: Pin Description
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
3. An internal voltage detector disables all functions whenever VCC is below 1.1V (1.8V version) to protect the device
from any involuntary program/erase during power transitions.
Rev 0.3 / Feb. 2008
7
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
IO0
A0
IO1
A1
IO2
A2
IO3
A3
IO4
IO5
IO6
IO7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A4
A5
A6
A7
L(1)
A16
A24
L(1)
A17
A25
L(1)
A18
A26
L(1)
A19
A27
A8
A9
A10
A14
A22
A11
A15
A23
A12
A20
A28
A13
A21
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
I/O8-
IO15
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
L(1)
L(1)
L(1)
L(1)
L(1)
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A0
A8
A1
A9
A2
A3
A4
A5
A6
A7
L(1)
A14
A22
L(1)
A15
A23
L(1)
A16
A24
L(1)
A17
A25
L(1)
A18
A26
A10
A13
A21
L(1)
A11
A19
A27
A12
A20
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
Acceptable command
during busy
FUNCTION
1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE
READ1
00h
00h
90h
FFh
80h
85h
80h
30h
35h
-
-
-
READ FOR COPY-BACK
READ ID
-
-
-
-
RESET
-
-
-
-
-
Yes
PAGE PROGRAM
COPY BACK PGM
MULTI PLANE PROGRAM
MULTI PLANE COPYBACK
PROGRAM
BLOCK ERASE
10h
10h
11h
-
-
81h
10h
85h
60h
60h
11h
D0h
60h
81h
-
10h
-
-
MULTI PLANE
BLOCK ERASE
D0h
READ STATUS REGISTER
RANDOM DATA INPUT
RANDOM DATA OUTPUT
READ CACHE (RANDOM)
READ CACHE (SEQUENTIAL)
READ CACHE END
70h
85h
05h
00h
31h
3Fh
7Bh
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Yes
-
E0h
31h
-
-
READ EDC STATUS REGISTER
-
Table 5: Command Set
Note:
1. READ EDC STATUS REGISTER is only available on Copy Back operation.
Rev 0.3 / Feb. 2008
8
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
CLE
H
L
ALE
L
CE
L
WE
Rising
Rising
Rising
Rising
Rising
H
RE
WP
MODE
H
X
Command Input
Address Input(5 cycles)
Command Input
Address Input(5 cycles)
Read Mode
H
L
L
H
X
H
L
L
H
H
Write Mode
Data Input
H
L
L
H
H
L
L
H
H
L(1)
L
L
L
Falling
X
Sequential Read and Data Output
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
L
L
H
H
X
X
X
X
X
X
X
X
X
H
X
X
X
X
H
L
X
X
X
X
X
X
H
X
0V/Vcc
Stand By
Table 6: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
Rev 0.3 / Feb. 2008
9
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be
high. See Figure 4 and Table 13 for details of the timings requirements. Command codes are always applied on IO7:0
regardless of the bus configuration. (x8 or x16)
2.2 Address Input
Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses
for the 4Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable
low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify-
ing operation (write/erase) the Write Protect pin must be high. See Figure 5 and Table 13 for details of the timings
requirements. Addresses are always applied on IO7:0 regardless of the bus configuration (x8 or x16).
2.3 Data Input
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serial and timed
by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch
Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 6 and
Table 13 for details of the timings requirements.
2.4 Data Output
Data Output bus operation allows to read data from the memory array and to check the status register content, the EDC
register content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low,
Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 7,8,10,11,12 and Table 13
for details of the timings requirements.
2.5 Write Protect
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modifying operation does not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protec-
tion even during the power up.
2.6 Standby
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.3 / Feb. 2008
10
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read
This operation is operated by writing 00h and 30h to the command register along with five address cycles.
Two types of operations are available: random read, serial page read. The random read mode is enabled when the
page address is changed. The 2112 bytes (x8) or 1056 words (x16) of data within the selected page are transferred to
the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by
analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in
45ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device out-
put the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command. Random data output can be operated multiple times regardless of how many times it is done in a
page.
3.2 Page Program
The device is programmed by page. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 8 times. The addressing should be done on each pages
in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-
lowed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do not need
to be loaded. The device supports random data input in a page.
The column address of next data, which will be entered, may be changed to the address which follows random data
input command (85h). Random data input may be operated multiple times regardless of how many times it is done in
a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without pre-
viously entering the serial data will not initiate the programming process. The internal write state controller automati-
cally executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for
other tasks. Once the program process starts, the Read Status Register command may be entered to read the status
register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Sta-
tus bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write
verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the com-
mand register. Figure 14 details the sequence.
Rev 0.3 / Feb. 2008
11
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3.3 Multi Plane Program
Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-
lowed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st
plane (A<18>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device
supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h)
stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h
command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page
must be within 2nd plane (A<18>=1). The data of 2nd page other than those to be programmed do not need to be
loaded. Program Confirm command (10h) makes parallel programming of both pages start. User can check operation
status by R/B pin or read status register command, as if it were a normal page program; status register command is
also available during Dummy Busy time (tDBSY). In case of fail in 1st or 2nd page program, fail bit of status register
will be set: Device supports pass/fail status of each plane. Figure 19 details the sequence.
3.4 Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in there cycles initiated by an
Erase Setup command (60h). Only address A18 to A28 is valid while A12 to A17 is ignored (x8). The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two step sequence of
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase
and erase verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When
the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 18 details the sequence.
3.5 Multi Plane Erase
Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multiplane erase
does not need any Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for
multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for mul-
tiple plane program. Figure 20 details the sequence
Rev 0.3 / Feb. 2008
12
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3.6 Copy-back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page
without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated
and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequen-
tial execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation
with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer.
A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not
need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command
(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status
register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Sta-
tus bit(I/O 6) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 16 & Figure 17). The
command register remains in Read Status command mode until another valid command is written to the command
register. During copy-back program, data modification is possible using random data input command (85h) as shown
in Figure17.
Copy-back program operation is allowed only within same plane.
3.7 Multi-Plane Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system
performance is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and
the rest of the block also need to be copied to the newly assigned free block.
The operation for performing a copy-back program is a sequential execution of page-read without serial access and
copying-program with the address of destination page. A read operation with "35h" command and the address of the
source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready
state, optional data read-out is allowed by toggling RE (See Figure 21), or Copy Back command (85h) with the
address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin
the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 21.
Most NAND devices require 2 bit external ECC only due to copy back operation while 1 bit ECC can be enough for all
other operation. Reason is that during read for copy back + copy back program sequence a bit error due to charge
loss is not checked by external error detection/correction scheme. On the contrary, 2Gbit NAND includes automatic
Error Detection Code during copy back operation: thanks to this, 2 bit external ECC is no more required, with signifi-
cant advantage for customers that can always use single bit ECC. More details on EDC operation are available in sec-
tion 3.8.
Rev 0.3 / Feb. 2008
13
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3.8 EDC Operation
Error Detection Code check automatically starts immediately after device becomes busy for a copy back program oper-
ation (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 bytes,
where each 528byte group is composed by 512 bytes of main array and 16 bytes of spare area (see Table 20,21).
So described 528byte area is called “EDC unit”. In the x16 version EDC allows detection of 1 single bit error every 264
words, where each 264 word group is composed by 256 words of main array and 8 words of spare area (see Table
20,21). So described 264 word area is called “ EDC unit”.
To Properly use EDC, some limitations apply:
- Random data input can be used only once in copy back program or page program or multiple page program, unless
user inputs data for a whole EDC unit (or more whole EDC units).
- Any page program operation must be done on whole page basis, or on whole EDC unit.
EDC result can be checked only during copy back program through 7Bh (specific Read EDC register command, Table 22)
3.9 Read Status Register
The device contains a Status Register which may be read to find out whether, program or erase operation is completed,
and whether the program or erase operation is completed successfully. After writing 70h command to the command
register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, which-
ever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connec-
tions even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table
14 for specific Status Register definitions. The command register remains in Status Read mode until further commands
are issued to it. Therefore, if the status register is read during a random data output, the read command (00h) should
be given before starting read cycles.
3.10 Read EDC Status Register
The operation is available only in copy back program and it allows the detection of errors occurred during read for copy
back. In case of multiple plane copy back, it is not possible to know which of the two read operation caused the error.
After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Register to the I/O
pins on the falling edge of CE or RE, whichever occurs last.
Operation is same read status register command. Refer to below Table 22 for specific EDC Register definitions.
3.11 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd,
4th, 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to
it. Figure 22 shows the operation sequence, while tables 15 explain the byte meaning.
3.12 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table
14 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure
25.
Rev 0.3 / Feb. 2008
14
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3.13 Cache Read
Cache read can be used to increase the read operation speed when accessing sequential pages within a block.
First, issue a normal page read (00-30h). See figure 13.
The R/B signal goes low for tR during the time it takes to transfer the first page of data from the memory to the data
register. After R/B returns to high (31h) command is latched into the command register. R/B goes low while data is
being transferred from the data register to the cache register. After the data register contents are transferred to the
cache register, another page read is automatically started as part of the 31h command. Data is transferred from the
next sequential page of the memory array to the data register during the same time data is being read serially from
the cache register. If the total time to output data exceeds tR, then the page read is hidden.
The second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands.
R/B will stay low. This time can vary, depending on whether the previous memory-to-data-register transfer was com-
pleted prior to issuing the next 31h command.
If the data transfer from memory to the data register is not completed before the 31h command is issued, R/B stays
low until the transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command. R/B will stay low until the
previous page read is complete and the data has been transferred to the cache register.
To read out the last page of data (3Fh) command is issued. This command transfers data from the data register to the
cache register without issuing another page read.
Rev 0.3 / Feb. 2008
15
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power On/Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device). WP pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a
reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.
Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be
obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance.
Rev 0.3 / Feb. 2008
16
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Parameter
Symbol
Min
Typ
Max
Unit
Valid Block
Number
NVB
2008
-
2048
Blocks
Table 7 : Valid Blocks Numbers
NOTE:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
Symbol
Parameter
Value
0 to 70
Unit
℃
Ambient Operating Temperature (Commercial Temperature Range)
Ambient Operating Temperature (Industrial Temperature Range)
Temperature Under Bias
TA
-40 to 85
-50 to 125
℃
TBIAS
TSTG
℃
Storage Temperature
Input or Output Voltage
Supply Voltage
-65 to 150
-0.6 to 2.7
-0.6 to 2.7
V
VIO(2)
Vcc
V
V
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 0.3 / Feb. 2008
17
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
$ꢇꢊꢋaꢋ$ꢈ
$''5(66
5(*,67(5ꢀ
&2817(5
352*5$0
(5$6(
;
&21752//(5
+9ꢋ*(1(5$7,21
ꢊꢀꢋꢂꢅ0ELWꢅꢌꢅꢇꢋꢅ0ELW
'
(
1$1'ꢅ)ODVK
0(025<ꢅ$55$<
&
2
'
(
5
$/(
&/(
:(
&(
:3
&200$1'
,17(5)$&(
/2*,&
5(
3$*(ꢋ%8))(5
<ꢋ'(&2'(5
&200$1'
5(*,67(5
'$7$
5(*,67(5
%8))(56
,2
Figure 3: Block Diagram
Rev 0.3 / Feb. 2008
18
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1.8Volt
Parameter
Sequential
Symbol
Test Conditions
Unit
Min
Typ
Max
tRC=45ns
CE=VIL, IOUT=0mA
ICC1
-
10
20
mA
Read
Operating
Current
Program
Erase
ICC2
ICC3
-
-
-
-
10
10
20
20
mA
mA
CE=VIH,
WP=0V/Vcc
Stand-by Current (TTL)
Stand-by Current (CMOS)
ICC4
-
-
1
mA
uA
CE=Vcc-0.2,
WP=0V/Vcc
ICC5
ILI
10
50
Input Leakage Current
Output Leakage Current
Input High Voltage
VIN=0 to Vcc (max)
-
-
-
-
-
-
-
uA
uA
V
± 10
± 10
Vcc+0.3
0.2xVcc
-
ILO
VIH
VIL
VOUT =0 to Vcc (max)
-
-
0.8xVcc
-0.3
Input Low Voltage
-
V
Output High Voltage Level
Output Low Voltage Level
VOH
VOL
IOH=-100uA
IOL=100uA
Vcc-0.1
-
V
1
V
IOL
(R/B)
Output Low Current (R/B)
VOL=0.2V
3
4
-
mA
Table 9: DC and Operating Characteristics
Value
1.8Volt
0V to VCC
5ns
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (1.7V - 1.95V)
VCC/2
1 TTL GATE and CL=30pF
Table 10: AC Conditions
Rev 0.3 / Feb. 2008
19
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Item
Input / Output Capacitance
Input Capacitance
Symbol
CI/O
Test Condition
VIL=0V
Min
Max
10
Unit
pF
-
-
CIN
VIN=0V
10
pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter
Symbol
tPROG
tDBSY
NOP
Min
Typ
Max
700
1
Unit
Program Time / Multi-Plane Program Time
Dummy Busy Time for Two Plane Program
Number of partial Program Cycles in the same page
Block Erase Time / Multi-Plane Block Erase Time
Read Cache Busy Time
-
-
-
-
-
250
0.5
-
us
us
8
Cycles
ms
tBERS
2
2.5
tR
tRBSY
3
us
Table 12: Program / Erase Characteristics
Rev 0.3 / Feb. 2008
20
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1.8V
Parameter
Symbol
Unit
Min
25
10
35
10
25
25
10
20
10
45
15
Max
CLE Setup time
CLE Hold time
CE setup time
CE hold time
tCLS
tCLH
tCS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
tCH
WE pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE High hold time
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tR
Data Transfer from Cell to register
ALE to RE Delay
25
tAR
10
10
25
25
CLE to RE Delay
tCLR
tRR
Ready to RE Low
RE Pulse Width
tRP
WE High to Busy
tWB
tRC
100
Read Cycle Time
45
RE Access Time
tREA
tRHZ
tCHZ
tCOH
tRHOH
tRLOH
tREH
tIR
30
100
50
RE High to Output High Z
CE High to Output High Z
CE High to Output hold
RE High to Output Hold
RE Low to Output Hold
RE High Hold Time
15
15
5
10
0
Output High Z to RE low
CE Low to RE Low
tCR
10
100
60
100
tADL
tWHR
tRHW
Address to data loading time
WE High to RE low
RE High to WE low
5/10/500(1)
Device Resetting Time (Read / Program / Erase)
tRST
(2)
Write Protection time
tWW
100
ns
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Rev 0.3 / Feb. 2008
21
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
IO
0
Page Program
Block Erase
Read
NA
Cache Read
CODING
Pass / Fail
Pass / Fail
NA
NA
NA
NA
NA
Pass: ‘0’ Fail: ‘1’
1
NA
NA
NA
NA
NA
NA
NA
NA
NA
-
-
-
-
2
NA
3
NA
4
NA
Ready /
Busy
P/E/R
Controller Bit
5
6
7
Ready / Busy
Ready / Busy
Write Protect
Ready / Busy
Ready / Busy
Write Protect
Active: ‘0’ Idle:’1’
Busy: ‘0’ Ready:’1’
Ready /
Busy
Ready/Busy
NA
Protected: ‘0’
Write
Protect
Not Protected: ‘1’
Table 14 : Status Register Coding
DEVICE IDENTIFIER CYCLE
DESCRIPTION
1st
2nd
3rd
4th
5th
Manufacturer Code
Device Identifier
Internal chip number, cell Type, etc.
Page Size, Block Size, Spare Size, Organization
Multiplane information
Table 15: Device Identifier Coding
Bus
1st cycle
2nd cycle
3rd
cycle
4th
cycle
5th
cycle
Part Number
Voltage
Width (Manufacture Code) (Device Code)
HY27SF082G2B
HY27SF162G2B
1.8V
1.8V
x8
ADh
ADh
DAh
CAh
10h
10h
15h
55h
44h
44h
x16
Table 16: Read ID Data Table
Rev 0.3 / Feb. 2008
22
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Description
IO7
IO6
IO5 IO4
IO3 IO2
IO1 IO0
1
2
4
8
0 0
0 1
1 0
1 1
Die / Package
Cell Type
2 Level Cell
4 Level Cell
0 0
0 1
1 0
1 1
8 Level Cell
16 Level Cell
1
2
4
8
0 0
0 1
1 0
1 1
Number of
Simultaneously
Programmed Pages
Interleave program
Between multiple chips
Not
Supported
0
1
Not
Supported
0
1
Write Cache
Table 17: 3rd Byte of Device Idendifier Description
Description
1KB
2KB
4KB
8KB
IO7
IO6
IO5-4
IO3
IO2
IO1-0
0 0
0 1
1 0
1 1
Page Size
(Without Spare Area)
Spare Area Size
(Byte / 512Byte)
8
16
0
1
50ns
30ns
25ns
Reserved
0
0
1
1
0
1
0
1
Serial Access Time
64K
0 0
0 1
1 0
1 1
Block Size
(Without Spare Area)
128K
256K
512KB
X8
X16
0
1
Organization
Table 18: 4th Byte of Device Identifier Description
Rev 0.3 / Feb. 2008
23
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Description
IO7
IO6 IO5 IO4
IO3 IO2
IO1
IO0
1
2
4
8
0
0
1
1
0
1
0
1
Plane Number
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64Mb
128Mb
256Mb
512Mb
1Gb
Plane Size
(w/o redundant Area)
2Gb
4Gb
8Gb
Reserved
0
0
0
Table 19: 5rd Byte of Device Idendifier Description
Rev 0.3 / Feb. 2008
24
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Table 20: Page organization in EDC units (x8)
Table 21: Page organization in EDC units (x16)
IO
0
Copy back Program
Pass/Fail
CODING
Pass: ‘0’ Fail: ‘1’
NO error: ‘0’
1
EDC status
EDC Validity
NA
2
Invalid: ‘0’ Valid: ‘1’
-
3
4
NA
-
5
Ready/Busy
Ready/Busy
Write Protect
Busy: ‘0’ Ready: ‘1’
Busy: ‘0’ Ready: ‘1’
Protected: ‘0’ Not Protected: ‘1’
6
7
Table 22: EDC Register Coding
Rev 0.3 / Feb. 2008
25
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
W&/
6
W&/+
W&+
&/(
W&6
&(
W:3
:(
W$/6
W$/+
$/(
W'6
W'+
,ꢀ2ꢋ[
&RPPDQG
Figure 4: Command Latch Cycle
W&/6
W&6
&/(
W:&
W:&
W:&
W:&
&(
W:3
W:3
W:3
W:3
:(
W:+
W$/+
W:+
W$/+
W:+
W$/+
W:+
W$/+
W$/6
W$/6
W$/6
W$/6
W$/6
W$/+
W'+
$/(
W'+
W'+
W'+
W'+
W'6
W'6
W'6
W'6
W'6
&ROꢌ$GGꢁ
&ROꢌ$GGꢇ
5RZꢋ$GGꢁ
5RZꢋ$GGꢇ
5RZꢋ$GGꢆ
,ꢉ2[
Figure 5: Address Latch Cycle
Rev 0.3 / Feb. 2008
26
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
W&/+
W&+
&/(
&(
W:&
W$/6
$/(
W:3
W:3
W:3
:(
W:+
W'+
W:+
W'+
W'+
W'6
',1ꢁꢄ
W'6
',1ꢁILQDO
W'6
,ꢀ2[
1RWHVꢀꢁ',1ꢁILQDOꢁPHDQVꢁꢂꢃꢄꢄꢂ%\WHVꢁꢅ[ꢆꢇ
Figure 6: Input Data Latch Cycle
Rev 0.3 / Feb. 2008
27
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
W5&
&(
5(
W&+=
W5(+
W5($
W5($
W5($
W&2+
W5+=
W5+=
W5+2+
,ꢀ2[
5ꢀ%
'RXW
'RXW
'RXW
W55
1RWHVꢍꢋ7UDQVLWLRQꢋLVꢋPHDVXUHGꢋDWꢋꢎꢀꢏꢇꢈꢈP9ꢋIURPꢋVWHDG\ꢋVWDWHꢋYROWDJHꢋZLWKꢋORDGꢌ
ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ7KLVꢋSDUDPHWHUꢋLVꢋVDPSOHGꢋDQGꢋQRWꢋꢁꢈꢈꢐꢋWHVWHGꢌꢋꢑW&+=ꢒꢋW5+=ꢓ
ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋW5+2+ꢋVWDUWVꢋWRꢋEHꢋYDOLGꢋZKHQꢋIUHTXHQF\ꢋLVꢋORZHUꢋWKDQꢋꢆꢆ0+]ꢌ
Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
W&5
&(
W5&
W&+=
W&2+
W53
W5(+
5(
W5+=
W5($
W5($
W5/2+
W5+2+
,ꢀ2[
5ꢀ%
'RXW
'RXW
W55
1RWHVꢍꢋ7UDQVLWLRQꢋLVꢋPHDVXUHGꢋꢋDWꢋꢎꢀꢏꢇꢈꢈP9ꢋIURPꢋVWHDG\ꢋVWDWHꢋYROWDJHꢋZLWKꢋORDGꢌ
ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ7KLVꢋSDUDPHWHUꢋLVꢋVDPSOHGꢋDQGꢋQRWꢋꢁꢈꢈꢐꢋWHVWHGꢌꢋꢑW&+=ꢒꢋW5+=ꢓ
ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋW5/2+ꢋLVꢋYDOLGꢋZKHQꢋIUHTXHQF\ꢋLVꢋKLJKHUꢋWKDQꢋꢆꢆ0+]ꢌ
ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋW5+2+ꢋVWDUWVꢋWRꢋEHꢋYDOLGꢋZKHQꢋIUHTXHQF\ꢋLVꢋORZHUꢋWKDQꢋꢆꢆ0+]ꢌ
Figure 8: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)
Rev 0.3 / Feb. 2008
28
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
W&/5
&/(
&(
W&/6
W&6
W&/+
W&+
W:3
:(
W&+=
W&2+
W&5
W:+5
5(
W5+=
W5+2+
W'+
W5($
W'6
ꢈꢉK
W,5
,ꢀ2[
6WDWXVꢁ2XWSXW
Figure 9: Status Read Cycle
W
&/5
&/(
&(
W
:&
:(
$/(
W
:%
W
$5
W
5+=
W
5
W
5&
5(
W
55
ꢉꢉK
&ROꢋ$GGꢄ
5RZꢁ$GGꢄ
ꢊꢉK
'RXWꢁ1
'RXWꢁ1ꢌ
'RXWꢁ0
&ROꢋ$GGꢂ
5RZꢁ$GGꢂ 5RZꢁ$GGꢊ
,ꢀ2[
&ROXPQꢀ$GGUHVV
5RZꢀ$GGUHVV
%XV\
5ꢀ'
Figure 10: Read1 Operation (Read One Page)
Rev 0.3 / Feb. 2008
29
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
&/(
&(
:(
W:%
W&+=
W&2+
W$5
$/(
5(
W5
W5&
W55
'RXW
1
'RXW
1ꢎꢁ
'RXW
1ꢎꢇ
&ROꢌ
&ROꢌ
5RZ
5RZ
5RZ
ꢈꢈK
ꢆꢈK
,ꢀ2[
5ꢀ%
$GGꢁ
$GGꢇ
$GGꢁ
$GGꢇ
$GGꢆ
&ROXPQꢋ$GGUHVV
5RZꢋ$GGUHVV
%XV\
Figure 11: Read1 Operation intercepted by CE
Rev 0.3 / Feb. 2008
30
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 12 : Random Data output
Rev 0.3 / Feb. 2008
31
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
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Figure 13: Read Operation with Read Cache
Rev 0.3 / Feb. 2008
32
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
&/(
&(
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Figure 14: Page Program Operation
Rev 0.3 / Feb. 2008
33
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 15 : Random Data In
Rev 0.3 / Feb. 2008
34
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 16: Copy Back Program Operation
Rev 0.3 / Feb. 2008
35
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 17: Copy Back Program Operation with Random Data Input
Rev 0.3 / Feb. 2008
36
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
&/(
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5(
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&RPPDQG ,ꢀ2ꢈ ꢁꢋ(UURUꢋLQꢋ(UDVH
(UDVHꢋ&RPPDQG
Figure 18: Block Erase Operation (Erase One Block)
Rev 0.3 / Feb. 2008
37
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 19: Multiple plane page program
Rev 0.3 / Feb. 2008
38
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
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$ꢅꢆꢀaꢀ$ꢅꢋꢀꢎꢀ)L[HGꢀµ/RZ¶
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$ꢅꢍꢀaꢀ$ꢆꢌꢀꢎꢀ9DOLG
Figure 20 : Multiple plane erase operation
Rev 0.3 / Feb. 2008
39
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure 21: Multi plane copyback program Operation
Rev 0.3 / Feb. 2008
40
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
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&(
:(
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Figure 22: Read ID Operation
Rev 0.3 / Feb. 2008
41
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE signal is ignored during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
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Figure 23: Program Operation with CE don’t-care.
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Figure 24: Read Operation with CE don’t-care.
Rev 0.3 / Feb. 2008
42
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
:(
$/(
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5(
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567
Figure 25: Reset Operation
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Figure 26: Power On and Data Protection Timing
VTH = 1.5 Volt for 1.8 Volt Supply devices
Rev 0.3 / Feb. 2008
43
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
5S
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Figure 27: Ready/Busy Pin electrical specifications
Rev 0.3 / Feb. 2008
44
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
wG]Z
wGZX
wG]Z
wGZX
O][P
O][P
a
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a
a
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a
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kG
kG
lUPGyGGGOwP
kh{hGpuGaGkGOXP kGO][P
kh{hGpuGaGkGOXP
kGO][P
Figure 28: page programming within a block
Rev 0.3 / Feb. 2008
45
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte(1st word) in the spare area of the
1st or 2nd th page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read
before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the
Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart
shown in Figure 29. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
67$57
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,QFUHPHQW
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1R
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/DVW
EORFN"
<HV
(1'
Figure 29: Bad Block Management Flowchart
Rev 0.3 / Feb. 2008
46
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Bad Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give
errors in the Status Register.
Unlike the case of odd page which carries a possibility of affecting previous page, the failure of a page program oper-
ation does not affect the data in other pages in the same block, the block can be replaced by re-programming the cur-
rent data and copying the rest of the replaced block to an available valid block.
Refer to Table 23 and Figure 30 for the recommended procedure to follow if an error occurs during an operation.
Operation
Erase
Recommended Procedure
Block Replacement
Program
Read
Block Replacement
ECC (with 1bit/528byte)
Table 23: Block Failure
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QꢀꢀꢀꢀSDJH
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Figure 30: Bad Block Replacement
NOTE :
1. An error occurs on nth page of the Block A during program or erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth data of block A which is in controller buffer memory is copied into nth page of Block B
4. Bad block table should be updated to prevent from eraseing or programming Block A
Rev 0.3 / Feb. 2008
47
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 31~34)
:(
W
::
ꢌꢁK
,ꢂ2[
ꢅꢁK
5ꢂ%
Figure 31: Enable Programming
:(
W
::
ꢌꢁK
ꢅꢁK
,ꢂ2[
5ꢂ%
Figure 32: Disable Programming
Rev 0.3 / Feb. 2008
48
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
:(
W
::
ꢊꢁK
'ꢁK
,ꢂ2[
5ꢂ%
Figure 33: Enable Erasing
:(
W
::
ꢊꢁK
,ꢂ2[
'ꢁK
5ꢂ%
Figure 34: Disable Erasing
Rev 0.3 / Feb. 2008
49
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
ꢈꢌ
H
$ꢆ
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'
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(ꢅ
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Figure 35: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
millimeters
Symbol
Min
Typ
Max
1.200
0.150
1.030
0.250
0.200
0.100
12.120
20.100
18.500
A
A1
A2
B
0.050
0.980
0.170
0.100
C
CP
D
11.910
19.900
18.300
12.000
20.000
18.400
0.500
E
E1
e
L
0.500
0
0.680
5
alpha
Table 24: 48-TSOP1 - 48-lead Plastic Thin Small Outline,
12 x 20mm, Package Mechanical Data
Rev 0.3 / Feb. 2008
50
HY27SF(08/16)2G2B Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
MARKING INFORMATION - TSOP1
Packag
Marking Exam ple
K
G
O
2
R
B
H
x
Y
x
2
x
7
x
S
F
x
x
2
TSOP1
Y
W
W
x
x
- hynix
- KOR
: Hynix Symbol
: Origin Country
: Part Number
- HY27SFxx2G2B xxxx
HY: Hynix
27: NAND Flash
S: Power Supply
F: Classification
xx : Bit Organization
2G: Density
: S(1.8V)
: Single Level Cell+Single Die+Large Block
: 08(x8), 16(x16)
: 2Gbit
: 2(1nCE & 1R/nB; Sequential Row Read Disable)
: 3rd Generation
2: Mode
B: Version
: T(48-TSOP1)
x: Package Type
x: Package Material
: Blank(Normal), P(Lead Free)
: C(0℃ ~70℃ ), I(-40℃ ~85℃ )
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
x: Operating Temperature
x: Bad Block
- Y: Year (ex: 5=year 2005, 6= year 2006)
- ww: Work Week (ex: 12= work week 12)
- xx: Process Code
Note
- Capital Letter
- Sm all Letter
: Fixed Item
: Non-fixed Item
Rev 0.3 / Feb. 2008
51
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