HY29DL162BT-70I_技术文档

HY29DL162/HY29DL163

16 Megabit (2M x 8/1M x16) Low Voltage,

Dual Bank, Simultaneous Read/Write Flash Memory

KEY FEATURES

n Data# Polling and Toggle Bits

n Single Power Supply Operation

− Read, program, and erase operations

from 2.7 to 3.6 V

− Provide software confirmation of completion

of program or erase operations

n Ready/Busy# Pin

− Ideal for battery-powered applications

n Simultaneous Read/Write Operations

− Host system can program or erase in one

bank while simultaneously reading from any

sector in the other bank with zero latency

between read and write operations

n High Performance

− Provides hardware confirmation of

completion of program or erase operations

n Erase Suspend

− Suspends an erase operation to allow

programming data to or reading data from

a sector in the same bank

− Erase Resume can then be invoked to

complete the suspended erasure

n Hardware Reset Pin (RESET#) Resets the

Device to Reading Array Data

− 70 and 80 ns access time versions with

30pF load

− 90 and 120 ns access time versions with

100pF load

n WP#/ACC Input Pin

n Ultra Low Power Consumption (Typical

Values)

− Write protect (WP#) function allows

hardware protection of two outermost boot

sectors, regardless of sector protect status

− Acceleration (ACC) function provides

accelerated program times

− Automatic sleep mode current: 200 nA

− Standby mode current: 200 nA

− Read current: 10 mA (at 5 MHz)

− Program/erase current: 15 mA

n Boot-Block Sector Architecture with 39

Sectors in Two Banks for Fast In-System

Code Changes

n Fast Program and Erase Times

− Sector erase time: 0.5 sec typical

− Byte/Word program time utilizing

Acceleration function: 10 µs typical

n Space Efficient Packaging

n Secured Sector: An Extra 64 Kbyte Sector

that Can Be:

− 48-pin TSOP and 48-ball FBGA packages

− Factory locked and identifiable: 16 bytes

available for a secure, random factory-

programmed Electronic Serial Number

− Customer lockable: Can be read, program-

med, or erased just like other sectors

n Flexible Sector Architecture

− Sector Protection allows locking of a

sector or sectors to prevent program or

erase operations within that sector

− Temporary Sector Unprotect allows

changes in locked sectors (requires high

voltage on RESET# pin)

n Automatic Erase Algorithm Erases Any

Combination of Sectors or the Entire Chip

n Automatic Program Algorithm Writes and

Verifies Data at Specified Addresses

n Compliant with Common Flash Memory

Interface (CFI) Specification

LOGIC DIAGRAM

20

8

7

A[19:0]

CE#

DQ[7:0]

DQ[14:8]

DQ[15]/A[-1]

WP#/ACC

RY/BY#

OE#

W E#

RESET#

BYTE#

n Minimum 100,000 Write Cycles per Sector

(1,000,000 cycles Typical)

n Compatible with JEDEC Standards

− Pinout and software compatible with

single-power supply Flash devices

− Superior inadvertent write protection

Preliminary

Revision 1.3, June 2001

HY29DL162/HY29DL163

GENERAL DESCRIPTION

The HY29DL162/HY29DL163 (HY29DL16x) is a

16 Mbit, 3 volt-only CMOS Flash memory orga-

nized as 2,097,152 (2M) bytes or 1,048,576 (1M)

words. The device is available in 48-pin TSOP

and 48-ball FBGA packages. Word-wide data

(x16) appears on DQ[15:0] and byte-wide (x8) data

appears on DQ[7:0].

Device programming is performed a byte/word at

a time by executing the four-cycle Program Com-

mand write sequence. This initiates an internal

algorithm that automatically times the program

pulse widths and verifies proper cell margin. Faster

programming times can be achieved by placing

the HY29DL16x in the Unlock Bypass mode, which

requires only two write cycles to program data in-

stead of four.

The HY29DL16x Flash memory array is organized

into 39 sectors in two banks. Bank 1 contains

eight 8 Kbyte boot/parameter sectors and 3 or 7

larger sectors of 64 Kbytes each, depending on

the version of the device. Bank 2 contains the

rest of the memory array, organized as 28 or 24

sectors of 64 Kbytes:

The HY29DL16x’s sector erase architecture allows

any number of array sectors, in one or both banks,

to be erased and reprogrammed without affecting

the data contents of other sectors. Device erasure

is initiated by executing the Erase Command se-

quence. This initiates an internal algorithm that

automatically preprograms the sector before ex-

ecuting the erase operation. As during program-

ming cycles, the device automatically times the

erase pulse widths and verifies proper cell mar-

gin. Hardware Sector Group Protection option-

ally disables both program and erase operations

in any combination of the sector groups, while

Temporary Sector Group Unprotect, which re-

quires a high voltage on one pin, allows in-system

erasure and code changes in previously protected

sector groups. Erase Suspend enables the user

to put erase on hold in a bank for any period of

time to read data from or program data to any

sector in that bank that is not selected for era-

sure. True background erase can thus be

achieved. Because the HY29DL16x features si-

multaneous read/write capability, there is no need

to suspend to read from a sector located within a

bank that does not contain sectors marked for era-

sure. The device is fully erased when shipped

from the factory.

Bank 1

Bank 2

8 x 8KB/4KW

3 x 64KB/32KW

HY29DL162

HY29DL163

28 x 64KB/32KW

8 x 8KB/4KW

7 x 64KB/32KW

24 x 64KB/32KW

The device features simultaneous read/write op-

eration which allows the host system to invoke a

program or erase operation in one bank and im-

mediately and simultaneously read data from the

other bank, except if that bank has any sectors

marked for erasure, with zero latency. This re-

leases the system from waiting for the completion

of program or erase operations, thus improving

overall system performance.

The HY29DL16x can be programmed and erased

in-system with a single 2.7 - 3.6 volt V_CCsupply.

Internally generated and regulated voltages are

provided for program and erase operations, so that

the device does not require a higher voltage V_PP

power supply to perform those functions. The de-

vice can also be programmed in standard EPROM

programmers. Access times as low as 70 ns are

offered for timing compatibility with the zero wait

state requirements of high speed microproces-

sors. To eliminate bus contention, the HY29DL16x

has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Addresses and data needed for the programming

and erase operations are internally latched during

write cycles. The host system can detect comple-

tion of a program or erase operation by observing

the RY/BY# pin or by reading the DQ[7] (Data#

Polling) and DQ[6] (Toggle) status bits. Hardware

data protection measures include a low V_CCde-

tector that automatically inhibits write operations

during power transitions.

The device is compatible with the JEDEC single-

power-supply Flash command set standard. Com-

mands are written to the command register using

standard microprocessor write timings, from where

they are routed to an internal state-machine that

controls the erase and programming circuits.

After a program or erase cycle has been com-

pleted, or after assertion of the RESET# pin (which

terminates any operation in progress), the device

is ready to read data or to accept another com-

r1.3/June 01

2

HY29DL162/HY29DL163

mand. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Two power-saving features are embodied in the

HY29DL16x. When addresses have been stable

for a specified amount of time, the device enters

the automatic sleep mode. The host can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

The Secured Sector is an extra 64 Kbyte sector

capable of being permanently locked at the fac-

tory or by customers. The Secured Indicator Bit

(accessed via the Electronic ID mode) is perma-

nently set to a 1 if the part is factory locked, and

permanently set to a 0 if customer lockable. This

way, customer lockable parts can never be used

to replace a factory locked part. Factory locked

parts provide several options. The Secured Sec-

tor may store a secure, random 16-byte ESN (Elec-

tronic Serial Number), customer code programmed

at the factory, or both. Customer Lockable parts

may utilize the Secured Sector as bonus space,

reading and writing like any other Flash sector, or

may permanently lock their own code there.

Common Flash Memory Interface (CFI)

To make Flash memories interchangeable and to

encourage adoption of new Flash technologies,

major Flash memory suppliers developed a flex-

ible method of identifying Flash memory sizes and

configurations in which all necessary Flash device

parameters are stored directly on the device.

Parameters stored include memory size, byte/word

configuration, sector configuration, necessary volt-

ages and timing information. This allows one set

of software drivers to identify and use a variety of

different, current and future Flash products. The

standard which details the software interface nec-

essary to access the device to identify it and to

determine its characteristics is the Common Flash

Memory Interface (CFI) Specification. The

HY29DL16x is fully compliant with this specification.

The WP#/ACC pin provides access to two func-

tions. The Write Protect function provides a hard-

ware method of protecting certain boot sectors

without using a high voltage. The Accelerate func-

tion speeds up programming operations, and is

intended primarily to allow faster manufacturing

throughput.

BLOCK DIAGRAM

DQ[15:0]

A[19:0], A[-1]

STATE

CONTROL

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

I/O BUFFERS

DATA LATCH

Y-GATING

COMMAND

REGISTER

CFI

CONTROL

CFI DATA

MEMORY

WE#

CE#

I/O CONTROL

OE#

PROGRAM

VOLTAGE

GENERATOR

RESET#

BYTE#

RY/BY#

WP#/ACC

Y-DECODER

X-DECODER

16 Mb FLASH

MEMORY

ARRAY

A[19:0], A[-1]

TIMER

(2 Banks,

39 Sectors)

V_CC

DETECTOR

0.5 Mb FLASH

Security Sector

r1.3/June 01

3

HY29DL162/HY29DL163

PIN CONFIGURATIONS

A[15]

A[14]

A[13]

A[12]

A[11]

A[10]

A[9]

1

2

3

4

5

6

7

48

47

46

45

44

43

42

A[16]

BYTE#

V _SS

DQ[15]/A[-1]

DQ[7]

DQ[14]

DQ[6]

A[8]

A[19]

8

9

41

40

DQ[13]

DQ[5]

N C

10

11

39

38

DQ[12]

DQ[4]

W E #

RESET#

N C

12

13

37

36

V _CC

DQ[11]

TSOP48

W P # / A C C

RY/BY#

A[18]

14

15

16

17

18

19

20

35

34

33

32

31

30

29

DQ[3]

DQ[10]

DQ[2]

DQ[9]

DQ[1]

DQ[8]

DQ[0]

A[17]

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

21

22

23

24

28

27

26

25

OE#

V _SS

CE#

A[0]

48-Ball FBGA (Top View, Balls Facing Down)

A6

B6

C6

D6

E6

F6

G6

H6

A[13]

A[12]

A[14]

A[15]

A[16]

BYTE# DQ[15]/A[-1]

V_SS

A5

B5

C5

D5

E5

F5

G5

H5

A[9]

A[8]

A[10]

A[11]

DQ[7]

DQ[14]

DQ[13]

DQ[6]

A4

B4

C4

NC

D4

E4

F4

G4

V_{C C}

H4

W E #

RESET#

A[19]

DQ[5]

DQ[12]

DQ[4]

A3

B3

C3

D3

NC

E3

F3

G3

H3

RY/BY#

WP#/ACC

A[18]

DQ[2]

DQ[10]

DQ[11]

DQ[3]

A2

B2

C2

D2

E2

F2

G2

H2

A[7]

A[17]

A[6]

A[5]

DQ[0]

DQ[8]

DQ[9]

DQ[1]

A1

B1

C1

D1

E1

F1

G1

H1

A[3]

A[4]

A[2]

A[1]

A[0]

CE#

OE#

V_SS

r1.3/June 01

4

HY29DL162/HY29DL163

SIGNAL DESCRIPTIONS

Name

Type

Description

Address, active High. In word mode, these 20 inputs select one of 1,048,576

(1M) words within the array for read or write operations. In byte mode, these

inputs are combined withthe DQ[15]/A[-1] input (LSB) to select one of 2,097,152

(2M) bytes within the array for read or write operations.

A[19:0]

Inputs

Data Bus, active High. In word mode, these pins provide a 16-bit data path

DQ[15]/A[-1], Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path

DQ[14:0]

BYTE#

CE#

Tri-state

and DQ[15]/A[-1] is used as the LSB of the 21-bit byte address input. DQ[14:8]

are unused and remain tri-stated in byte mode.

Byte Mode, active Low. Controls the Byte/Word configuration of the device.

Low selects Byte mode, High selects Word mode.

Input

Chip Enable, active Low. This input must be asserted to read data from or

write data to the HY29DL16x. When High, the data bus is tri-stated and the

device is placed in the Standby mode.

Input

Output Enable, active Low. This input must be asserted for read operations

and negated for write operations. BYTE# determines whether a byte or a word

is read during the read operation. When High, data outputs from the device are

disabled and the data bus pins are placed in the high impedance state.

OE#

WE#

Input

Write Enable, active Low. Controls writing of command sequences in order to

program data or erase sectors of the memory array. A write operation takes

place when WE# is asserted while CE# is Low and OE# is High. BYTE#

determines whether a byte or a word is written during the write operation.

Hardware Reset, active Low. Provides a hardware method of resetting the

HY29DL16x to the read array state. When the device is reset, it immediately

terminates any operationinprogress. The data bus is tri-stated and all read/write

commands are ignored while the input is asserted. While RESET# is asserted,

the device will be in the Standby mode.

RESET#

RY/BY#

Input

Ready/Busy Status. Indicates whether a write or erase command is in

progress or has been completed. Valid after the rising edge of the final WE#

Open Drain pulse of a command sequence. It remains Low while the device is actively

programming data or erasing, and goes High when it is ready to read array data.

Output

Write Protect, active Low/Accelerate (V_HH).

Write Protect Function: Placing this pin at V_ILdisables program and erase

operations in two of the eight 8 Kbyte/4 Kword boot sectors. The affected

sectors are S0 and S1 in a bottom-boot device, or S37 and S38 in a top-boot

device. If the pin is placed at V_IH, the protection state of those two sectors

reverts to whether they were last set to be protected or unprotected using the

method described in the Sector Group Protection and Unprotection sections.

Accelerate Function: If V_HHis applied to this input, the device enters the Unlock

Input

WP#/ACC

Bypass mode, temporarily unprotects any protected sectors, and uses the

higher voltage on the pin to reduce the time required for program operations.

The system would then use the two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HHfrom the pin returns the

device to normal operation.

This pin must not be at V_HHfor operations other than accelerated programming,

or device damage may result. Leaving the pin unconnected may result in

inconsistent device operation.

3-volt (nominal) power supply.

Power and signal ground.

V_CC

V_SS

--

r1.3/June 01

5

HY29DL162/HY29DL163

CONVENTIONS

Unless otherwise noted, a positive logic (active

High) convention is assumed throughout this docu-

ment, whereby the presence at a pin of a higher,

more positive voltage (V_IH) causes assertion of the

signal. A ‘#’ symbol following the signal name,

e.g., RESET#, indicates that the signal is asserted

in the Low state (V_IL). See DC specifications for

V_IHand V_ILvalues.

Whenever a signal is separated into numbered

bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of

bits may also be shown collectively, e.g., as

DQ[7:0].

The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .

. . , E, F) indicates a number expressed in hexadeci-

mal notation. The designation 0bXXXX indicates a

number expressed in binary notation (X = 0, 1).

MEMORY ARRAY ORGANIZATION

The 16 Mbit Flash memory array is organized into

39 blocks called sectors (S0, S1, . . . , S38). A

sector or several contiguous sectors are defined

as a sector group. A sector is the smallest unit

that can be erased and a sector group is the small-

est unit that can be protected to prevent acciden-

customers to utilize the sector in any manner they

choose, and has the Sec²Indicator bit permanently

set to a ‘0’. Thus, the Sec²Indicator bit prevents

customer-lockable devices from being used to re-

place devices that are factory locked. The bit pre-

vents cloning of a factory locked part and thus

ensures the security of the ESN once the product

is shipped to the field.

The system accesses the Sec²through a com-

mand sequence (see “Enter/Exit Secured Sector

Command Sequence”). After the system has writ-

ten the Enter Secured Sector command sequence,

it may read the Sec²by using the addresses nor-

mally occupied by the boot sectors, as specified

in Table 4. This mode of operation continues until

the system issues the Exit Secured Sector com-

mand sequence, or until power is removed from

the device. On power-up, or following a hardware

reset, the device reverts to addressing the boot

sectors.

tal or unauthorized erasure.

Sectors are also

combined into two ‘super’ groups designated as

banks.

In the HY29DL16x, eight of the sectors, which com-

prise the boot block, are sized at eight Kbytes (four

Kwords), while the remaining 31 sectors are sized

at 64 Kbytes (32 Kwords). The boot block can be

located at the bottom of the address range

(HY29DL16xB) or at the top of the address range

(HY29DL16xT).

Tables 1 and 2 define the sector addresses and

corresponding array address ranges for the top

and bottom boot block versions of the HY29DL16x.

Table 3 specifies the bank organizations and cor-

responding bank addresses. See Tables 7 and 8

for sector group definitions.

Sec²Programmed and Protected At the Factory

In a factory-locked device, the Sec²is protected

when the device is shipped from the factory and

cannot be modified in any way. The device is avail-

able preprogrammed with one of the following:

Secured Sector Flash Memory Region

The Secured Sector (Sec²) feature provides a 64

Kbyte (32 Kword) Flash memory region that en-

ables permanent part identification through an

Electronic Serial Number (ESN). An associated

‘Sec²Indicator’ bit, which is permanently set at

the factory and cannot be changed, indicates

whether or not the Sec²is locked when shipped

from the factory.

The device is offered with the Sec²either factory

locked or customer lockable. The factory-locked

version is always protected when shipped from

the factory, and has the Sec²Indicator bit perma-

nently set to a ‘1’. The customer-lockable version

is shipped with the Sec²unprotected, allowing

n A random, secure ESN only

n Customer code

n Both a random, secure ESN and customer

code

In devices that have an ESN, it will be located at

the bottom of the lowest 8 Kbyte boot sector: start-

ing at byte address 0x000000 and ending at

0x00000F for a Bottom Boot device, and starting

at byte address 0x1F0000 and ending at 0x1F000F

for a Top Boot device.

r1.3/June 01

6

HY29DL162/HY29DL163

Table 1. HY29DL16xT (Top Boot Block) Memory Array Organization

Sector Address ¹

Sect-

Size

Byte Mode

Address Range ²

Word Mode

or (KB/KW)

Address Range ³

A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]

S0

S1

64/32

8/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

0x000000 - 0x00FFFF 0x00000 - 0x07FFF

0x010000 - 0x01FFFF 0x08000 - 0x0FFFF

0x020000 - 0x02FFFF 0x10000 - 0x17FFF

0x030000 - 0x03FFFF 0x18000 - 0x1FFFF

0x040000 - 0x04FFFF 0x20000 - 0x27FFF

0x050000 - 0x05FFFF 0x28000 - 0x2FFFF

0x060000 - 0x06FFFF 0x30000 - 0x37FFF

0x070000 - 0x07FFFF 0x38000 - 0x3FFFF

0x080000 - 0x08FFFF 0x40000 - 0x47FFF

0x090000 - 0x09FFFF 0x48000 - 0x4FFFF

0x0A0000 - 0x0AFFFF 0x50000 - 0x57FFF

0x0B0000 - 0x0BFFFF 0x58000 - 0x5FFFF

0x0C0000 - 0x0CFFFF 0x60000 - 0x67FFF

0x0D0000 - 0x0DFFFF 0x68000 - 0x6FFFF

0x0E0000 - 0x0EFFFF 0x70000 - 0x77FFF

0x0F0000 - 0x0FFFFF 0x78000 - 0x7FFFF

0x100000 - 0x10FFFF 0x80000 - 0x87FFF

0x110000 - 0x11FFFF 0x88000 - 0x8FFFF

0x120000 - 0x12FFFF 0x90000 - 0x97FFF

0x130000 - 0x13FFFF 0x98000 - 0x9FFFF

0x140000 - 0x14FFFF 0xA0000 - 0xA7FFF

0x150000 - 0x15FFFF 0xA8000 - 0xAFFFF

0x160000 - 0x16FFFF 0xB0000 - 0xB7FFF

0x170000 - 0x17FFFF 0xB8000 - 0xBFFFF

0x180000 - 0x18FFFF 0xC0000 - 0xC7FFF

0x190000 - 0x19FFFF 0xC8000 - 0xCFFFF

0x1A0000 - 0x1AFFFF 0xD0000 - 0xD7FFF

0x1B0000 - 0x1BFFFF 0xD8000 - 0xDFFFF

0x1C0000 - 0x1CFFFF 0xE0000 - 0xE7FFF

0x1D0000 - 0x1DFFFF 0xE8000 - 0xEFFFF

0x1E0000 - 0x1EFFFF 0xF0000 - 0xF7FFF

0x1F0000 - 0x1F1FFF 0xF8000 - 0xF8FFF

0x1F2000 - 0x1F3FFF 0xF9000 - 0xF9FFF

0x1F4000 - 0x1F5FFF 0XFA000 - 0xFAFFF

0x1F6000 - 0x1F7FFF 0xFB000 - 0xFBFFF

0x1F8000 - 0x1F9FFF 0xFC000 - 0xFCFFF

0x1FA000 - 0x1FBFFF 0xFD000 - 0xFDFFF

0x1FC000 - 0x1FDFFF 0XFE000 - 0xFEFFF

0x1FE000 - 0x1FFFFF 0xFF000 - 0xFFFFF

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

Notes:

8/4

0

1

8/4

0

1

0

8/4

0

1

8/4

1

0

8/4

1

0

1

8/4

1

0

8/4

1

1. ‘X’ indicates don’t care.

2. ‘0xN. . . N’ indicates an address in hexadecimal notation.

3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].

r1.3/June 01

7

HY29DL162/HY29DL163

Table 2. HY29DL16xB (Bottom Boot Block) Memory Array Organization

Sector Address ¹

Sect- Size

or (KB/KW)

Byte Mode

Word Mode

Address Range ²

Address Range ³

A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

8/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x000000 - 0x001FFF 0x00000 - 0x00FFF

0x002000 - 0x003FFF 0x01000 - 0x01FFF

0x004000 - 0x005FFF 0X02000 - 0x02FFF

0x006000 - 0x007FFF 0x03000 - 0x03FFF

0x008000 - 0x009FFF 0x04000 - 0x04FFF

0x00A000 - 0x00BFFF 0x05000 - 0x05FFF

0x00C000 - 0x00DFFF 0X06000 - 0x06FFF

0x00E000 - 0x00FFFF 0x07000 - 0x07FFF

0x010000 - 0x01FFFF 0x08000 - 0x0FFFF

0x020000 - 0x02FFFF 0x10000 - 0x17FFF

0x030000 - 0x03FFFF 0x18000 - 0x1FFFF

0x040000 - 0x04FFFF 0x20000 - 0x27FFF

0x050000 - 0x05FFFF 0x28000 - 0x2FFFF

0x060000 - 0x06FFFF 0x30000 - 0x37FFF

0x070000 - 0x07FFFF 0x38000 - 0x3FFFF

0x080000 - 0x08FFFF 0x40000 - 0x47FFF

0x090000 - 0x09FFFF 0x48000 - 0x4FFFF

0x0A0000 - 0x0AFFFF 0x50000 - 0x57FFF

0x0B0000 - 0x0BFFFF 0x58000 - 0x5FFFF

0x0C0000 - 0x0CFFFF 0x60000 - 0x67FFF

0x0D0000 - 0x0DFFFF 0x68000 - 0x6FFFF

0x0E0000 - 0x0EFFFF 0x70000 - 0x77FFF

0x0F0000 - 0x0FFFFF 0x78000 - 0x7FFFF

0x100000 - 0x10FFFF 0x80000 - 0x87FFF

0x110000 - 0x11FFFF 0x88000 - 0x8FFFF

0x120000 - 0x12FFFF 0x90000 - 0x97FFF

0x130000 - 0x13FFFF 0x98000 - 0x9FFFF

0x140000 - 0x14FFFF 0xA0000 - 0xA7FFF

0x150000 - 0x15FFFF 0xA8000 - 0xAFFFF

0x160000 - 0x16FFFF 0xB0000 - 0xB7FFF

0x170000 - 0x17FFFF 0xB8000 - 0xBFFFF

0x180000 - 0x18FFFF 0xC0000 - 0xC7FFF

0x190000 - 0x19FFFF 0xC8000 - 0xCFFFF

0x1A0000 - 0x1AFFFF 0xD0000 - 0xD7FFF

0x1B0000 - 0x1BFFFF 0xD8000 - 0xDFFFF

0x1C0000 - 0x1CFFFF 0xE0000 - 0xE7FFF

0x1D0000 - 0x1DFFFF 0xE8000 - 0xEFFFF

0x1E0000 - 0x1EFFFF 0xF0000 - 0xF7FFF

0x1F0000 - 0x1FFFFF 0xF8000 - 0xFFFFF

8/4

0

1

0

8/4

0

1

8/4

1

0

8/4

1

0

1

8/4

1

0

8/4

1

64/32

X

S10 64/32

S11 64/32

S12 64/32

S13 64/32

S14 64/32

S15 64/32

S16 64/32

S17 64/32

S18 64/32

S19 64/32

S20 64/32

S21 64/32

S22 64/32

S23 64/32

S24 64/32

S25 64/32

S26 64/32

S27 64/32

S28 64/32

S29 64/32

S30 64/32

S31 64/32

S32 64/32

S33 64/32

S34 64/32

S35 64/32

S36 64/32

S37 64/32

S38 64/32

Notes:

1. ‘X’ indicates don’t care.

2. ‘0xN. . . N’ indicates an address in hexadecimal notation.

3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].

r1.3/June 01

8

HY29DL162/HY29DL163

Table 3. HY29DL16x Bank Options

Bank 1

Reference Size (Mbit) Sectors Bank Address Size (Mb)

Bank 2

Device

Sectors Bank Address

S0 - S27 A[19:17] ≤ 110

HY29DL162T

HY29DL163T

HY29DL162B

HY29DL163B

Table 1

Table 2

2

4

2

4

S28 - S38 A[19:17] = 111

S24 - S38 A[19:18] = 11

S0 - S10 A[19:17] = 000

S0 - S14 A[19:18] = 00

14

12

14

12

S0 - S23

A[19:18] ≤ 10

S11 - S38 A[19:17] ≥ 001

S15 - S38 A[19:18] ≥ 01

Table 4. HY29DL16x Secure Sector Addressing

Sector Size

KB/KW

Sector Address

Byte Mode

Word Mode

Device

A[19:12] ¹

Address Range ^{2, 3}

HY29DL162T/163T

HY29DL162B/163B

64/32

1 1 1 1 1 X X X

0 0 0 0 0 X X X

0x1F0000 - 0x1FFFFF 0xF8000 - 0xFFFFF

0x000000 - 0x00FFFF 0x00000 - 0x07FFF

Notes:

1. ‘X’ indicates don’t care.

2. ‘0xN. . . N’ indicates an address in hexadecimal notation.

3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].

Sec²NOT Programmed or Protected at the Factory

device pin to a high voltage. Note that this

method is only applicable to the Secure Sec-

tor.

If the security feature is not required, the Sec²can

be treated as an additional Flash memory space

of 64 Kbytes. The Sec²can be read, programmed,

and erased as often as required. The Sec²area

can be protected using the following procedure:

n Once the Secure Sector is locked and verified,

the system must write the Exit Secure Sector

command sequence to return to reading and

writing the remainder of the array.

n Write the three-cycle Enter Secure Sector Re-

Sec²protection must be used with caution since,

once protected, there is no procedure available

for unprotecting the Sec²area and none of the

bits in the Sec²memory space can be modified in

any way.

gion command sequence

n Then follow the sector protect algorithm shown

in Figure 1, except that RESET# may be at

either V_IHor V_ID. This allows in-system protec-

tion of the Secure Sector without raising any

BUS OPERATIONS

Device bus operations are initiated through the

internal command register, which consists of sets

of latches that store the commands, along with

the address and data information, if any, needed

to execute the specific command. The command

register itself does not occupy any addressable

memory location. The contents of the command

register serve as inputs to an internal state ma-

chine whose outputs control the operation of the

device. Table 5 lists the normal bus operations,

the inputs and control levels they require, and the

resulting outputs. Certain bus operations require

a high voltage on one or more device pins. Those

are described in Table 6.

Read Operation

Data is read from the HY29DL16x by using stan-

dard microprocessor read cycles while placing the

byte or word address on the device’s address in-

puts. The host system must drive the CE# and

OE# pins Low and drive WE# High for a valid read

operation to take place. The BYTE# pin deter-

mines whether the device outputs array data in

words (DQ[15:0]) or in bytes (DQ[7:0]).

r1.3/June 01

9

HY29DL162/HY29DL163

Table 5. HY29DL16x Normal Bus Operations¹

DQ[15:8] ³

Operation

CE#

OE# WE# RESET# WP#/ACC Address ²DQ[7:0]

BYTE# = H BYTE# = L

Read

L

H

L

H

L/H

Note 4

L/H

A_IN

X

D_OUT

D_IN

D_OUT

D_IN

High-Z

Write

Output Disable

H

High-Z

CE# Normal

Standby

H

X

H

V_CC± 0.3V

L

H

X

High-Z

CE# Deep Standby V_CC± 0.3V

Hardware Reset

X

L/H

(Normal Standby)

Hardware Reset

(Deep Standby)

X

V_SS± 0.3V

L/H

X

High-Z

Notes:

1. L = V_IL, H = V_IH, X = Don’t Care (L or H), D_OUT= Data Out, D_IN= Data In. See DC Characteristics for voltage levels.

2. Address is A[19:0, -1] in Byte Mode and A[19:0] in Word Mode.

3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

4. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the protection state of the two

outermost boot sectors depends on whether they were last protected or unprotected using the method described in

“Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V_HH, all sectors will be unprotected.

Table 6. HY29DL16x Bus Operations Requiring High Voltage ^{1, 2}

DQ[15:8]

Operation ³

CE# OE# WE# RESET# A[19:12] A[9] A[6] A[1] A[0] DQ[7:0]

BYTE# BYTE#

= H

= L ⁵

X

Sector Group Protect

Sector Unprotect

L

H

L

V_ID

SGA ⁴

X

L

H

L

D_IN

X

H

X

Temporary Sector

Unprotect^{6, 7}

Manufacturer Code

HY29DL162B

--

L

--

L

--

V_ID

H

--

X

--

L

--

L

--

L

--

X

--

H

V_ID

0xAD

0x2E

0x2D

0x2B

0x28

High-Z

HY29DL162T

Device

L

H

X

V_ID

L

H

0x22 High-Z

Code

HY29DL163B

HY29DL163T

Sector

Protect

State

Unprotected

Protected

0x00

0x01

L

H

SA ⁴

X

V_ID

L

H

L

X

High-Z

Factory

Locked

Not Factory

Locked

Secure

Sector

Indicator

Bit

0x80

0x00

H

Notes:

1. L = V_IL, H = V_IH, X = Don’t Care (L OR H), V_ID= 10V nominal. See DC Characteristics for voltage levels.

2. Address bits not specified are Don’t Care.

3. See text and Appendix for additional information.

4. SA = Sector Address, SGA = Sector Group Address. See Tables 1, 2, 7, and 8.

5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

6. Normal read, write and output disable operations are used in this mode. See Table 5.

7. If WP#/ACC = V_IL, the two outermost boot sectors remain protected.

r1.3/June 01

10

HY29DL162/HY29DL163

The HY29DL16x is automatically set for reading

array data after device power-up and after a hard-

ware reset to ensure that no spurious alteration of

the memory content occurs during the power tran-

sition. No command is necessary in this mode to

obtain array data, and both banks of the device

remain enabled for read accesses until the com-

mand register contents are altered.

The “Device Commands” section of this data sheet

provides details on the specific device commands

implemented in the HY29DL16x.

Accelerated Program Operation

This device offers improved performance for pro-

gramming operations through the ‘Accelerate

(ACC)’ function. This is one of two functions pro-

vided by the WP#/ACC pin and is intended prima-

rily to allow faster manufacturing throughput at the

factory.

This device features the capability of reading data

from one bank of the memory while a program or

erase operation is in progress in the other bank.

If the host reads from an address within an eras-

ing or erase-suspended sector, or from a bank

where a programming operation is taking place,

the device outputs status data instead of array data

(see Write Operation Status section). After com-

pleting an Automatic Program or Automatic Erase

algorithm within a bank, that bank automatically

returns to the read array data mode.

If V_HHis applied to this input, the device enters the

Unlock Bypass mode, temporarily unprotects any

protected sectors, and uses the higher voltage on

the pin to reduce the time required for program

operations. The host system would then use the

two-cycle program command sequence as re-

quired by the Unlock Bypass mode. Removing

V

_HHfrom the pin returns the device to normal op-

eration.

When the host issues an Erase Suspend com-

mand, the bank specified in the command enters

the Erase- Suspended Read mode. While in that

mode, the host can read data from, or program

data into, any sector in that bank except the

sector(s) being erased. After completing a pro-

gramming operation in the Erase Suspend mode,

the system may once again read array data with

the same exception noted above.

This pin must not be at V_HHfor operations other

than accelerated programming, or device damage

may result. Leaving the pin floating or uncon-

nected may result in inconsistent device opera-

tion.

Write Protect Function

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using V_ID. This is the second function provided by

the WP#/ACC pin.

The host must issue a hardware reset or the soft-

ware reset command to return a sector to the read

array data mode if DQ[5] goes high during a pro-

gram or erase cycle, or to return the device to the

read array data mode while it is in the Electronic

ID mode.

Placing this pin at V_ILdisables program and erase

operations in two of the eight 8 Kbyte (4 Kword)

boot sectors. The affected sectors are sectors S0

and S1 in a bottom-boot device, or S37 and S38

in a top-boot device. If the pin is placed at V_IH, the

protection state of those two sectors reverts to

whether they were last set to be protected or un-

protected using the method described in the Sec-

tor Group Protection and Unprotection sections.

Write Operation

Certain operations, including programming data

and erasing sectors of memory, require the host

to write a command or command sequence to the

HY29DL16x. Writes to the device are performed

by placing the byte or word address on the device’s

address inputs while the data to be written is input

on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE#

= Low). The host system must drive the CE# and

WE# pins Low and drive OE# High for a valid write

operation to take place. All addresses are latched

on the falling edge of WE# or CE#, whichever

happens later. All data is latched on the rising

edge of WE# or CE#, whichever happens first.

Standby Operation

When the system is not reading or writing to the

device, it can place the device in the Standby

mode. In this mode, current consumption is greatly

reduced, and the data bus outputs are placed in

the high impedance state, independent of the OE#

input. The Standby mode can invoked using two

methods.

r1.3/June 01

11

HY29DL162/HY29DL163

sertion of RESET#, it should be reinitiated once

the device is ready to accept another command

sequence to ensure data integrity.

The device enters the CE# controlled Deep

Standby mode when the CE# and RESET# pins

are both held at V_CC± 0.3V. Note that this is a

more restricted voltage range than V_IH. If both CE#

Current is reduced for the duration of the RESET#

pulse as described in the Standby Operation sec-

tion above.

and RESET# are held at V_IH, but not within V_CC

±

0.3V, the device will be in the Normal Standby

mode, but the standby current will be greater.

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains Low (busy) until

the internal reset operation is complete, which re-

quires a time of t_READY(during Automatic Algo-

rithms). The system can thus monitor RY/BY# to

determine when the reset operation completes,

and can perform a read or write operation t_RBafter

RY/BY# goes High. If RESET# is asserted when

a program or erase operation is not executing (RY/

BY# pin is High), the reset operation is completed

within a time of t_RP. In this case, the host can per-

form a read or write operation t_RHafter the RE-

SET# pin returns High .

The device enters the RESET# controlled Deep

Standby mode when the RESET# pin is held at

V_SS± 0.3V. If RESET# is held at V_ILbut not within

V_SS± 0.3V, the standby current will be greater.

See RESET# section for additional information on

the reset operation.

The device requires standard access time (t_CE) for

read access when the device is in any of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the

device, enabling the system to read the boot-up

firmware from the Flash memory.

Sleep Mode

The Sleep mode automatically minimizes device

power consumption. This mode is automatically

entered when addresses remain stable for t_ACC

+

Sector Group Protect Operation

30 ns (typical) and is independent of the state of

the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data

when addresses are changed. While in Sleep

mode, output data is latched and always available

to the system.

The hardware sector group protection feature dis-

ables both program and erase operations in any

combination of sector groups. A sector group con-

sists of a single sector or a group of adjacent sec-

tors, as specified in Tables 7 and 8. This function

can be implemented either in-system or by using

programming equipment. It requires a high volt-

age (V_ID) on the RESET# pin and uses standard

microprocessor bus cycle timing to implement

sector protection. The flow chart in Figure 1 illus-

trates the algorithm.

NOTE: Sleep mode is entered only when the device is

in Read mode. It is not entered if the device is executing

an automatic algorithm, if it is in erase suspend mode,

or during receipt of a command sequence.

Output Disable Operation

When the OE# input is at V_IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

The HY29DS16x is shipped with all sector groups

unprotected. It is possible to determine whether

a sector is protected or unprotected. See the Elec-

tronic ID Mode section for details.

Reset Operation

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

the duration of the RESET# pulse. The device also

resets the internal state machine to reading array

data. If an operation was interrupted by the as-

Sector Unprotect Operation

The hardware sector unprotection feature re-en-

ables both program and erase operations in pre-

viously protected sector groups. This function can

be implemented either in-system or by using pro-

gramming equipment. Note that to unprotect any

sector, all unprotected sector groups must first be

protected prior to the first sector unprotect write

r1.3/June 01

12

HY29DL162/HY29DL163

Table 7. Sector Groups - Top Boot Versions

Table 8. Sector Groups - Bottom Boot Versions

Sectors

(Table 1)

Group Address Block Size

Sectors

(Table 2)

Group Address Block Size

Group

A[19:12]

KB/KW

A[19:12]

KB/KW

SG0

S0

0 0 0 0 0 X X X

0 0 0 0 1 X X X

0 0 0 1 0 X X X 192/96

0 0 0 1 1 X X X

64/32

SG0

SG1

SG2

SG3

SG4

SG5

SG6

SG7

S0

S1

S2

S3

S4

S5

S6

S7

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0

0 0 0 0 0 1 0 1

0 0 0 0 0 1 1 0

0 0 0 0 0 1 1 1

0 0 0 0 1 X X X

8/4

SG1

S1 - S3

SG2

SG3

SG4

SG5

SG6

SG7

S4 - S7

0 0 1 X X X X X 256/128

S8 -S11 0 1 0 X X X X X 256/128

S12 - S15 0 1 1 X X X X X 256/128

S16 - S19 1 0 0 X X X X X 256/128

S20 - S23 1 0 1 X X X X X 256/128

S24 - S27 1 1 0 X X X X X 256/128

1 1 1 0 0 X X X

SG8

S8 - S10 0 0 0 1 0 X X X 192/96

0 0 0 1 1 X X X

SG8

S28 - S30 1 1 1 0 1 X X X 192/96

1 1 1 1 0 X X X

SG9

SG10

SG11

SG12

SG13

SG14

S11 - S14 0 0 1 X X X X X 256/128

S15 - S18 0 1 0 X X X X X 256/128

S19 - S22 0 1 1 X X X X X 256/128

S23 - S26 1 0 0 X X X X X 256/128

S27 - S30 1 0 1 X X X X X 256/128

S31 - S34 1 1 0 X X X X X 256/128

1 1 1 0 0 X X X

SG9

S31

S32

S33

S34

S35

S36

S37

S38

1 1 1 1 1 0 0 0

1 1 1 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8/4

SG10

SG11

SG12

SG13

SG14

SG15

SG16

SG15

SG16

S35 - S37 1 1 1 0 1 X X X 192/96

1 1 1 1 0 X X X

S38

1 1 1 1 1 X X X

64/32

START

RESET# = V_ID

Wait 1 us

Wait 150 us

RESET# = V_IH

Write 0x40 to Address

Wait 1 us

Write Reset Command

SECTOR GROUP

Read from Address

PROTECT COMPLETE

Write 0x60 to device

TRYCNT = 1

NO

YES

Data = 0x01?

YES

TRYCNT = 25?

NO

Set Address:

A[19:12] = Group to Protect

A[6] = 0, A[1] = 1, A[0] = 0

Protect Another

Group?

DEVICE FAILURE

Increment TRYCNT

Write 0x60 to Address

YES

Figure 1. Sector Group Protect Algorithm

r1.3/June 01

13

HY29DL162/HY29DL163

cycle. Also, the unprotect procedure will cause

all sectors to become unprotected, thus, sector

groups that require protection must be protected

again after the unprotect procedure is run.

Electronic ID Operation (High Voltage Method)

The Electronic ID mode provides manufacturer and

device identification, sector protection verification

and Sec²region protection status through identi-

fier codes output on DQ[7:0]. This mode is in-

tended primarily for programming equipment to au-

tomatically match a device to be programmed with

its corresponding programming algorithm.

This procedure requires V_IDon the RESET# pin

and uses standard microprocessor bus cycle tim-

ing to implement sector unprotection. The flow

chart in Figure 2 illustrates the algorithm.

Two methods are provided for accessing the Elec-

tronic ID data. The first requires V_IDon address

pin A[9], with additional requirements for obtain-

ing specific data items listed in Table 6. The Elec-

tronic ID data can also be obtained by the host

through specific commands issued via the com-

mand register, as described later in the ‘Device

Commands’ section of this data sheet.

Temporary Sector Unprotect Operation

This feature allows temporary unprotection of pro-

tected sectors to allow changing the data in-sys-

tem. Temporary Sector Unprotect mode is acti-

vated by setting the RESET# pin to V_ID. While in

this mode, formerly protected sectors can be pro-

grammed or erased by invoking the appropriate

commands (see Device Commands section).

Once V_IDis removed from RESET#, all the previ-

ously protected sector groups are protected again.

Figure 3 illustrates the algorithm.

While in the high-voltage Electronic ID mode, the

system may read at specific addresses to obtain

certain device identification and status informa-

tion:

NOTE: If WP#/ACC = V_IL, the two outermost boot sec-

tors remain protected.

n A read cycle at address 0xXXX00 retrieves the

manufacturer code.

n A read cycle at address 0xXXX01 in word mode

or 0xXXX02 in byte mode returns the device

code.

START

(Note: All sector groups

Set Address:

A[19:12] = Group GNUM

must be protected prior to

A[6] = 1, A]1] = 1, A]0] = 0

sector unprotect)

RESET# = V_IH

Write 0x40 to Address

TRYCNT = 1

Write Reset Command

GNUM

= 0

Wait 1 us

SECTOR GROUP

UNPROTECT COMPLETE

RESET# = V_ID

Read from Address

Wait 1 us

NO

YES

Data = 0x00?

TRYCNT = 1000?

Write 0x60 to device

NO

YES

Set Address:

A[6] = 1, A]1] = 1, A]0] = 0

Increment TRYCNT

YES

DEVICE FAILURE

GNUM

= 16?

Write 0x60 to Address

Wait 15 ms

NO

GNUM

=

+ 1

Figure 2. Sector Unprotect Algorithm

r1.3/June 01

14

HY29DL162/HY29DL163

n A read cycle containing a sector address (SA)

within the designated bank in A[19:12] and the

address 0x04 in A[6:0, A-1] in byte mode, or

0x02 in A[7:0] in word mode, returns 0x01 if

that sector is protected, or 0x00 if it is unpro-

tected.

START

RESET# = V_ID

(All protected sectors

become unprotected)

n A read cycle at address 0xXXX03 in word mode

or 0xXXX06 in byte mode returns 0x80 if the

Sec²region is protected and locked at the fac-

tory and 0x00 if it is not.

Perform Program or Erase

Operations

RESET# = V_IH

(All previously protected

sectors return to protected

state)

TEMPORARY SECTOR

UNPROTECT COMPLETE

Figure 3. Temporary Sector Unprotect

Algorithm

DEVICE COMMANDS

Device operations are initiated by writing desig-

nated address and data command sequences into

the device. Addresses are latched on the falling

edge of WE# or CE#, whichever happens later.

Data is latched on the rising edge of WE# or CE#,

whichever happens first.

Table 9. Composition of Command Sequences

Number of Bus Cycles

Unlock Command Data

Command

Sequence

Read

0

2

0

1

Note 1

Reset

0

1

0

Enter Sec²Region

Exit Sec²Region

Byte/Word Program

Unlock Bypass

A command sequence is composed of one, two

or three of the following sub-segments: an unlock

cycle, a command cycle and a data cycle. Table

9 summarizes the composition of the valid com-

mand sequences implemented in the HY29DL16x,

and these sequences are fully described in Table

10 and in the sections that follow.

Unlock Bypass

Reset

Unlock Bypass

0

1

Byte/Word Program

Writing incorrect address and data values or writ-

ing them in the improper sequence resets the

HY29DL16x to the Read mode.

Chip Erase

Sector Erase

Erase Suspend

Erase Resume

Electronic ID

CFI Query

4

0

2

0

1

1 (Note 2)

0

Reading Data

Note 3

Note 4

The device automatically enters the Read mode

after device power-up, after the RESET# input is

asserted and upon the completion of certain com-

mands. Commands are not required to retrieve

data in this mode. See Read Operation section

for additional information.

Notes:

1. Any number of Flash array read cycles are permitted.

2. Additional data cycles may follow. See text.

3. Any number of Electronic ID read cycles are permitted.

4. Any number of CFI data read cycles are permitted.

Reset Command

Writing the Reset command resets the sectors to

the Read or Erase-Suspend mode. Address bits

are don’t cares for this command.

r1.3/June 01

15

HY29DL162/HY29DL163

E l e c t r o n i c I D

6

r1.3/June 01

16

HY29DL162/HY29DL163

Legend and notes for Table 10:

Legend:

X = Don’t Care

RA/RD = Memory address/data for the read operation

PA/PD = Memory address/data for the program operation

SA = A[19:12], sector address of the sector to be erased or verified (see Note 3 and Tables 1 and 2).

BA = A[19:18] or A[19:17], depending on the device version, bank address, see Note 3 and Table 3.

Notes:

1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.

2. All bus cycles are write operations unless otherwise noted.

3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[19:11] are don’t care except as follows:

•

For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed.

Where ‘SA’ is indicated, A[19:12] are the sector address.

Where ‘BA’ is indicated, A[19:18] or A[19:17], depending on the device version, are the bank address.

4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-

erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode.

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. The fourth bus cycle is a read cycle.

7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or in

the CFI Query mode. It must also be issued to return to read mode if DQ[5] goes High during a program or erase

operation. It is not required for normal read operations.

8

This command is valid only when the device is in Read mode or in Electronic ID mode.

9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

tween the cycles that specify the sectors to be

As described above, a Reset command is not nor-

mally required to begin reading array data. How-

ever, a Reset command must be issued in order

to read array data in the following cases:

erased (see Sector Erase command descrip-

tion). This aborts the command and resets the

device to the Read mode. Once erasure be-

gins, however, the device ignores the Reset

command until the operation is complete.

n If the device is in the Electronic ID mode, a

Reset command must be written to return to

the Read mode. If the device was in the Erase

Suspend mode when the device entered the

Electronic ID mode, writing the Reset command

returns the device to the Erase Suspend mode.

n In a Program command sequence, the Reset

command may be written between the se-

quence cycles before programming actually be-

gins. This aborts the command and resets the

device to the Read mode, or to the Erase Sus-

pend mode if the Program command sequence

is written while the device is in the Erase Sus-

pend mode. Once programming begins, how-

ever, the device ignores the Reset command

until the operation is complete.

Note: When in the Electronic ID bus operation mode,

the device returns to the Read mode when V_IDis re-

moved from the A[9] pin. The Reset command is not

required in this case.

n If the device is in the CFI Query mode, a Reset

command must be written to return to the ar-

ray Read mode.

n The Reset command may be written between

the cycles in an Electronic ID command se-

quence to abort that command. As described

above, once in the Electronic ID mode, the

Reset command must be written to return to

the array Read mode.

n If DQ[5] (Exceeded Time Limit) goes High dur-

ing a program or erase operation, a Reset com-

mand must be invoked to return the sectors to

the Read mode (or to the Erase Suspend mode

if the device was in Erase Suspend when the

Program command was issued).

Enter /Exit Sec²Command Sequence

The Reset command may also be used to abort

certain command sequences:

The system can access the Sec²region of the

device by issuing the Enter Sec²Region command

sequence. The device continues to access the

Sec²region until the system issues the Exit Sec²

Region command sequence, which returns the

device to normal operation.

n In a Sector Erase or Chip Erase command se-

quence, the Reset command may be written

at any time before erasing actually begins, in-

cluding, for the Sector Erase command, be-

r1.3/June 01

17

HY29DL162/HY29DL163

Note: A hardware reset will reset the device to the read

array mode.

instead of the standard four-cycle program se-

quence to invoke a programming operation. The

first cycle in this sequence contains the Unlock

Bypass Program command, 0xA0, and the sec-

ond cycle specifies the program address and data,

thus eliminating the initial two unlock cycles re-

quired in the standard Program command se-

quence. Additional data is programmed in the

same manner.

Program Command

The system programs the device a word or byte

at a time by issuing the appropriate four-cycle Pro-

gram command sequence, as shown in Table 10.

The sequence begins by writing two unlock cycles,

followed by the program setup command and,

lastly, the program address and data. This ini-

tiates the Automatic Program algorithm that auto-

matically provides internally generated program

pulses and verifies the programmed cell margin.

The host is not required to provide further con-

trols or timings during this operation. When the

Automatic Program algorithm is complete, that

bank returns to the Read mode. Several meth-

ods are provided to allow the host to determine

the status of the programming operation, as de-

scribed in the Write Operation Status section.

While the Automatic Program algorithm is in

progress in one bank, the host may read data from

the non-programming bank.

During the Unlock Bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset com-

mands are valid. To exit the Unlock Bypass mode,

the host must issue the two-cycle Unlock Bypass

Reset command sequence shown in Table 10.

The bank specified in the first cycle of that com-

mand then returns to the Read array data mode.

Figure 4 illustrates the procedures for the normal

and unlock bypass program operations.

Note: The device automatically enters the Unlock By-

pass mode when it is placed in Accelerate mode via the

WP#/ACC pin.

Chip Erase Command

Commands written to the device during execution

of the Automatic Program algorithm are ignored.

Note that a hardware reset immediately terminates

the programming operation. To ensure data in-

tegrity, the aborted program command sequence

should be reinitiated once the reset operation is

complete.

The Chip Erase command sequence consists of

two unlock cycles, followed by a set-up command,

two additional unlock cycles and then the Chip

Erase command. This sequence invokes the Au-

tomatic Erase algorithm that automatically

preprograms (if necessary) and verifies the entire

memory for an all zero data pattern prior to elec-

trical erase. The host system is not required to pro-

vide any controls or timings during these operations.

Programming is allowed in any sequence. Only

erase operations can convert a stored ‘0’ to a ‘1’.

Thus, a bit cannot be programmed from a ‘0’ back

to a ‘1’. Attempting to do so may cause that bank

to halt the operation and set DQ[5] to ‘1’, or cause

the Data# Polling algorithm to indicate the opera-

tion was successful. However, a succeeding read

will show that the data is still ‘0’.

If all sectors in the device are protected, the de-

vice returns to reading array data after approxi-

mately 100 µs. If at least one sector is unpro-

tected, the erase operation erases the unprotected

sectors, and ignores the command for the sectors

that are protected. However, even if every sector

in one of the banks is protected, reads from that

bank are not permitted until the completion of the

Automatic Erase algorithm for the unprotected

sectors in the other bank.

Unlock Bypass/Bypass Program/Bypass Reset

Commands

Unlock Bypass provides a faster method than the

normal Program command for the host system to

program bytes or words to a bank. As shown in

Table 10, the Unlock Bypass command sequence

consists of two unlock write cycles followed by a

third write cycle containing the Unlock Bypass

command, 0x20. That bank then enters the Un-

lock Bypass mode. In this mode, a two-cycle Un-

lock Bypass Program command sequence is used

Commands written to the device during execution

of the Automatic Erase algorithm are ignored. Note

that a hardware reset immediately terminates the

chip erase operation. To ensure data integrity,

the aborted Chip Erase command sequence

should be reissued once the reset operation is

complete.

r1.3/June 01

18

HY29DL162/HY29DL163

START

Check Programming Status

(See Write Operation Status

Section)

DQ[5] Error Exit

NO

Enable Fast

Programming?

Programming Verified

YES

NO

Last Word/Byte

Done?

Issue UNLOCK BYPASS

Command to Bank

YES

Setup Next Address/Data for

Program Operation

NO

Bank in Unlock

Bypass Mode?

YES

NO

Bank in Unlock

Bypass Mode?

Issue UNLOCK BYPASS

RESET Command to Bank

Issue NORMAL PROGRAM

Command

YES

Issue UNLOCK BYPASS

PROGRAM Command

PROGRAMMING

COMPLETE

GO TO ERROR

RECOVERY PROCEDURE

Figure 4. Normal and Unlock Bypass Programming Procedures

When the Automatic Erase algorithm is complete,

mand, two additional unlock cycles and then the

Sector Erase command, which specifies which

sector is to be erased. This sequence invokes

the Automatic Erase algorithm that automatically

preprograms (if necessary) and verifies the speci-

fied sector for an all zero data pattern prior to elec-

trical erase. The host system is not required to

provide any controls or timings during these op-

erations.

the device returns to the reading array data mode.

Several methods are provided to allow the host to

determine the status of the erase operation, as

described in the Write Operation Status section.

Figure 5 illustrates the chip erase procedure.

Sector Erase Command

The Sector Erase command sequence consists

of two unlock cycles, followed by a set-up com-

After the sector erase data cycle (the sixth cycle)

of the command sequence is issued, a sector

erase time-out of 50 µs (min) begins, measured

from the rising edge of the final WE# pulse in the

command sequence. During this time, an addi-

tional sector address and sector erase data cycle

may be written into an internal sector erase buffer.

This buffer may be loaded in any sequence, and

the number of sectors designated for erasure may

be from one sector to all sectors. The only re-

striction is that the time between these additional

cycles must be less than 50 µs, otherwise era-

sure may begin before the last address and com-

mand are accepted. To ensure that all commands

are accepted, it is recommended that host pro-

cessor interrupts be disabled during the time that

START

Issue CHIP ERASE

Command Sequence

Check Erase Status

DQ[5] Error Exit

(See Write Operation Status

Section)

Normal Exit

GO TO

CHIP ERASE COMPLETE

ERROR RECOVERY

Figure 5. Chip Erase Procedure

r1.3/June 01

19

HY29DL162/HY29DL163

the additional sector erase commands are being

issued and then be re-enabled afterwards.

for the sectors that are protected. If sectors in a

bank are designated for erasure, read array op-

erations from that bank cannot take place until the

Automatic Erase algorithm terminates, even if all

of those sectors are protected. However, the

HY29DL16x’s simultaneous read feature allows

data to be read from a bank that does not contain

any sectors that are designated for erasure while

the erase algorithm is in progress in the other bank.

The system can monitor DQ[3] to determine if the

50 µs sector erase time-out has expired, as de-

scribed in the Write Operation Status section. If

the time between additional sector erase com-

mands can be assured to be less than the time-

out, the system need not monitor DQ[3].

Any command other than Sector Erase or Erase

Suspend during the time-out period resets the

bank(s) to reading array data. The system must

then rewrite the command sequence, including any

additional sector addresses. Once the sector

erase operation itself has begun, only the Erase

Suspend command is valid. All other commands

are ignored.

When the Automatic Erase algorithm is complete,

the device returns the erased sector(s) to the Read

array data mode. Several methods are provided

to allow the host to determine the status of the

erase operation, as described in the Write Opera-

tion Status section.

Figure 6 illustrates the sector erase procedure.

As for the Chip Erase command, note that a hard-

ware reset immediately terminates the erase op-

eration. To ensure data integrity, the aborted Sec-

tor Erase command sequence should be reissued

once the reset operation is complete.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system

to interrupt a sector erase operation to program

data into, or to read data from, any sector not

designated for erasure. (The HY29DL16x’s simul-

taneous read feature allows data to be read from

a bank that does not contain any sectors marked

for erasure even while the erase operation is not

suspended). The command, which requires the

If all sectors designated for erasing are protected,

the device returns to reading array data after ap-

proximately 100 µs. If at least one designated

sector is unprotected, the erase operation erases

the unprotected sectors, and ignores the command

START

Check Erase Status

DQ[5] Error Exit

(See Write Operation Status

Section)

Normal Exit

Write First Five Cycles of

SECTOR ERASE

Command Sequence

GO TO

ERASE COMPLETE

ERROR RECOVERY

Setup First (or Next) Sector

Address for Erase Operation

Write Last Cycle (SA/0x30)

of SECTOR ERASE

Command Sequence

Sectors which require erasure

but which were not specified in

this erase cycle must be erased

later using a new command

sequence

NO

Sector Erase

Time-out (DQ[3])

Expired?

Erase An

Additional Sector?

YES

NO

Figure 6. Sector Erase Procedure

r1.3/June 01

20

HY29DL162/HY29DL163

suspended state just as in the standard program-

ming operation.

bank address, causes the erase operation to be

suspended in all sectors designated for erasure

in the specified bank. This command is valid only

during the sector erase operation, including dur-

ing the 50 µs time-out period at the end of the

command sequence, and is ignored if it is issued

during chip erase or programming operations.

The host may also write the Electronic ID com-

mand sequence when the bank is in the Erase

Suspend mode. The device allows reading Elec-

tronic ID codes even at addresses within erasing

sectors, since the codes are not stored in the

memory array. When the device exits the Elec-

tronic ID mode, the bank reverts to the Erase Sus-

pend mode, and is ready for another valid opera-

tion. See the Electronic ID Command section for

more information.

The HY29DL16x requires a maximum of 20 µs to

suspend the erase operation if the erase suspend

command is issued during active sector erasure.

However, if the command is written during the

sector erase time-out, the time-out is terminated

and the erase operation is suspended immediately.

Once the erase operation has been suspended in

the bank, the system can read array data from or

program data into any sector in that bank that is

not designated for erasure. Normal read and write

timings and command definitions apply. Reading

at any address within erase-suspended sectors

produces status data on DQ[7:0]. The host can

use DQ[7], or DQ[6] and DQ[2] together, to deter-

mine if a sector is actively erasing or is erase-sus-

pended. See ‘Write Operation Status’ for infor-

mation on these status bits.

The system must write the Erase Resume com-

mand to the erase-suspended bank to exit the

Erase Suspend mode and continue the sector

erase operation. Further writes of the Resume

command are ignored. Another Erase Suspend

command can be written after the device has re-

sumed erasing.

Table 11 summarizes the erase operations in the

HY29DL16x.

Electronic ID Command

The Electronic ID mode provides manufacturer and

device identification and sector protection verifi-

cation through identifier codes output on DQ[7:0].

This mode is intended primarily for programming

equipment to automatically match a device to be

programmed with its corresponding programming

algorithm.

After an erase-suspended program operation is

complete, the bank returns to the erase-suspended

read state and the host can initiate another pro-

gramming operation (or read operation) within non-

suspended sectors. The host can determine the

status of a program operation during the erase-

Table 11. HY29DL16x Erase Operations Summary⁷

Output from Read Operation³

Erase Suspend

Allowed?

Programming

Allowed?¹

ES Sector ⁴

Non-ES Sector

5

Operation in Progress

No erase

Bank 1 Bank 2 Bank 1 Bank 2 Bank 1 Bank 2 Bank 1 Bank 2

n/a

No

n/a

No

Yes

No

Yes ²

Yes ⁶

Yes ²

Yes

No

Yes ⁶

Yes ²

n/a

Data

Status

Data

Status

Data

Chip Erase

Sector Erase in Bank 1 Only

Sector Erase in Bank 2 Only

Sector Erase in Banks 1 and 2

Yes

No

Yes

No

Yes

Status

n/a

Status

n/a

Status

Data

Notes:

1. Only one simultaneous programming operation is permitted.

2. Allowed only when the bank is in erase suspend state and only into a sector that is not designated for erasure.

3. Output may differ if program operation is in progress. See Write Operation Status section for additional information.

4. Read from a sector that is designated for erasure while the bank is in erase suspend state.

5. Read from a sector that is not designated for erasure while the bank is in erase suspend state, or read from any sector

in a bank where an erase operation has not been commanded, or any read for the Chip Erase operation.

6. Erase operation in the other bank must be suspended.

7. n/a = not applicable. Condition cannot exist.

Data = array data from addressed location.

Status = write operation status (see Write Operation Status section for additional information).

r1.3/June 01

21

HY29DL162/HY29DL163

Two methods are provided for accessing the Elec-

tronic ID data. The first requires V_IDon address

pin A[9], as described previously in the Device

Operations section.

Query Command and Common Flash Inter-

face (CFI) Mode

The HY29DL16x is capable of operating in the

Common Flash Interface (CFI) mode. This mode

allows the host system to determine the manufac-

turer of the device, its operating parameters, its

configuration and any special command codes that

the device may accept. With this knowledge, the

system can optimize its use of the chip by using

appropriate timeout values, optimal voltages and

commands necessary to use the chip to its full

advantage.

The Electronic ID data can also be obtained by

the host through specific commands issued via

the command register, as shown in Table 10. This

method does not require V_ID. The Electronic ID

command sequence may be written to an address

within a bank that is in the read mode or in the

Erase Suspend mode. The command may not be

written while the device is actively programming

or erasing in the other bank.

Two commands are employed in association with

CFI mode. The first places the device in CFI mode

(Query command) and the second takes it out of

CFI mode (Reset command). These are described

in Table 10.

The Electronic ID command sequence is initiated

by writing two unlock cycles, followed by a third

write cycle that contains the bank address and the

Electronic ID command. The addressed bank then

enters the Electronic ID mode, and the system may

read at any address in that bank any number of

times, without initiating another command se-

quence.

The single cycle Query command is valid only

when the device is in the Read mode, including

during Erase Suspend and Standby states and

while in Electronic ID command mode, but is ig-

nored otherwise. The command is not valid while

the HY29DL16x is in the Electronic ID bus opera-

tion mode. The command places the Bank desig-

nated in the ‘Bank Address’ field of the command

in the CFI Query mode. Array data may be read

from the other bank while the designated bank is

in the CFI Query mode. Read cycles at appropri-

ate addresses within the designated bank while in

the Query mode provide CFI data as described

later in this section. Write cycles are ignored, ex-

cept for the Reset command.

n A read cycle at address 0x(BA)X00, where BA

is the Bank Address, retrieves the manufac-

turer code.

n A read cycle at address 0x(BA)X01 in word

mode or 0x(BA)X02 in byte mode returns the

device code.

n A read cycle containing a sector address (SA)

within the designated bank in A[19:12] and the

address 0x04 in A[6:0, A-1] in byte mode, or

0x02 in A[7:0] in word mode, returns 0x01 if

that sector is protected, or 0x00 if it is unpro-

tected.

The Reset command returns the device from the

CFI mode to the array Read mode, or to the Erase

Suspend mode if the device was in that mode prior

to entering CFI mode, or to the Electronic ID mode

if the device was in that mode prior to entering

CFI mode. The command is valid only when the

device is in the CFI mode and as otherwise de-

scribed for the normal Reset command.

n A read cycle at address 0x(BA)X03 in word

mode or 0x(BA)X06 in byte mode returns 0x80

if the Sec²region is protected and locked at

the factory and 0x00 if it is not.

Array data may be read from the other bank while

the designated bank is in the Electronic ID mode.

The system must write the Reset command to exit

the Electronic ID mode and return the bank to the

normal Read mode, or to the Erase-Suspended

read mode if the bank was in that mode when the

Electronic ID command was invoked. In the latter

case, an Erase Resume command to that bank

will continue the suspended erase operation.

Tables 12 - 15 specify the data provided by the

HY29DL16x during CFI mode. Data at unspeci-

fied addresses reads out as 0x00. Note that a

value of 0x00 for a data item normally indicates

that the function is not supported. All values in

these tables are in hexadecimal.

r1.3/June 01

22

HY29DL162/HY29DL163

Table 12. CFI Mode: Identification Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

10

11

12

0051

0052

0059

20

22

24

51

52

59

Query-unique ASCII string "QRY"

Primary vendor command set and control interface ID

code

13

14

0002

0000

26

28

02

00

15

16

0040

0000

2A

2C

40

00

Address for primary algorithm extended query table

Alternate vendor command set and control interface ID

code (none)

17

18

0000

2E

30

00

Address for secondary algorithm extended query table

(none)

19

1A

0000

32

34

00

Table 13. CFI Mode: System Interface Data Values

Word Mode

Byte Mode

Description

Address

1B

Data

0027

0036

0000

0004

0000

000A

000F

0005

0000

0004

0000

Address

36

Data

27

36

00

04

00

0A

0F

05

00

04

00

V_CCsupply, minimum (2.7V)

V_CCsupply, maximum (3.6V)

1C

1D

1E

38

V_PPsupply, minimum (none)

3A

V_PPsupply, maximum (none)

3C

3E

Typical timeout for single word/byte write (2^Nµs)

Typical timeout for maximum size buffer write (2^Nµs)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write (2^Nx Typ)

Maximum timeout for maximum size buffer write (2^Nx Typ)

Maximum timeout for individual block erase (2^Nx Typ)

Maximum timeout for full chip erase (not supported)

1F

20

40

21

42

22

44

23

46

24

48

25

4A

26

4C

r1.3/June 01

23

HY29DL162/HY29DL163

Table 14. CFI Mode: Device Geometry Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

Device size (2^Nbytes)

27

0015

4E

15

28

29

0002

0000

50

52

02

00

Flash device interface code (02 = asynchronous x8/x16)

Maximum number of bytes in multi-byte write (not

supported)

2A

2B

0000

54

56

00

Number of erase block regions

2C

0002

58

02

2D

2E

2F

30

0007

0000

0020

0000

5A

5C

5E

60

07

00

20

00

Erase block region 1 information

[2E, 2D] = # of blocks in region - 1

[30, 2F] = size in multiples of 256-bytes

31

32

33

34

001E

0000

0001

62

64

66

68

1E

00

01

Erase block region 2 information

Table 15. CFI Mode: Vendor-Specific Extended Query Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

40

41

42

0050

0052

0049

80

82

84

50

52

49

Query-unique ASCII string "PRI"

Major version number, ASCII

43

44

45

46

47

48

49

0031

0030

0000

0002

0001

0004

86

88

8A

8C

8E

90

92

31

30

00

02

01

04

Minor version number, ASCII

Address sensitive unlock (0 = required, 1 = not required)

Erase suspend (2 = to read and write

)

Sector protect (N = # of sectors/group)

Temporary sector unprotect (1 = supported)

Sector protect/unprotect scheme (4 = Am29LV800A method)

001C or

0018

1C or

18

Simultaneous R/W operation

(xx = number of sectors in Bank 2: HY29DL162 = 1C, HY29DL163 = 18)

4A

94

Burst mode type (0 = not supported)

Page mode type (0 = not supported)

ACC Supply minimum (8.5V)

ACC Supply maximum (9.5V)

4B

4C

4D

4E

0000

0085

0095

96

98

9A

9C

00

85

95

0002 (BB)

0003 (TB)

02 (BB)

03 (TB)

Top/bottom boot version (BB = Bottom Boot, TB = Top Boot)

4F

9E

r1.3/June 01

24

HY29DL162/HY29DL163

WRITE OPERATION STATUS

The HY29DL16x provides a number of facilities to

determine the status of a program or erase op-

eration. These are the RY/BY# (Ready/Busy#)

pin and certain bits of a status word which can be

read from the device during the programming and

erase operations. Table 16 summarizes the sta-

tus indications and further detail is provided in the

subsections which follow.

DQ[7] - Data# Polling

The Data# Polling bit, DQ[7], indicates to the host

system whether an Automatic Algorithm is in

progress or completed, or whether a bank is in

Erase Suspend mode. Data# Polling is valid after

the rising edge of the final WE# pulse in the pro-

gram or erase command sequence.

While a programming operation is in progress, the

device outputs the complement of the value pro-

grammed to DQ[7]. When the programming op-

eration is complete, the device outputs the value

programmed to DQ[7]. If a program operation is

attempted within a protected sector, Data# Poll-

ing on DQ[7] is active for approximately 1 µs, then

the device returns to reading array data. The host

system must do a read at the program address to

obtain valid programming status information on this

bit.

RY/BY# - Ready/Busy#

RY/BY# is an open-drain output pin that indicates

whether a programming or erase Automatic Algo-

rithm is in progress or has completed. A pull-up

resistor to V_CCis required for proper operation. RY/

BY# is valid after the rising edge of the final WE#

pulse in the corresponding command sequence,

including during the sector erase time-out.

If the output is Low (busy), the device is actively

erasing or programming, including programming

while in the Erase Suspend mode. If the output is

High (ready), the device has completed the op-

eration and is ready to read array data, is in the

standby mode, or at least one bank is in the erase-

suspend read mode.

During an erase operation, Data# Polling produces

a “0” on DQ[7]. When the erase operation is com-

plete, or if the bank enters the Erase Suspend

mode, Data# Polling produces a “1” on DQ[7]. The

host must read at an address within any of the

non-protected sectors designated for erasure to

Table 16. Write and Erase Operation Status Summary

1

Mode

Operation

Programming in progress

Programming completed

Erase in progress

DQ[7]

DQ[7]#

Data

0

DQ[6]

Toggle

Data ⁴

Toggle

Data ⁴

DQ[5]

0/1 ²

DQ[3]

N/A

DQ[2]

N/A

RY/BY#

0

1

0

1

Data

0/1 ²

Data

1 ³

Data

Normal

Toggle

Data ⁴

Erase completed ⁵

Data

Read within erase suspended

sector

1

No toggle

Data

0

N/A

Toggle

Data

1

Read within non-erase

suspended sector

Erase

Data

Suspend

Programming in progress ⁶

Programming completed ⁶

DQ[7]#

Data

Toggle

Data ⁴

0/1 ²

N/A

0

1

Data

Notes:

1. A valid address within the bank where an Automatic algorithm is in progress is required when reading status information

except RY/BY#. For a programming operation, the address used for the read cycle should be the program address. For

an erase operation, the address used for the read cycle should be any address within a non-protected sector marked for

erasure (any address for the chip erase operation).

2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.

3. A ‘1’ during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress. DQ[3] is not

applicable to the chip erase operation.

4. Equivalent to ‘No Toggle’ because data is obtained in this state.

5. Data (DQ[7:0]) = 0xFF immediately after erasure.

6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).

r1.3/June 01

25

HY29DL162/HY29DL163

obtain valid erase status information on DQ[7]. If

all sectors designated for erasing are protected,

Data# Polling on DQ[7] is active for approximately

100 µs, then the bank returns to reading array data.

the final WE# pulse in the Program or Erase com-

mand sequence, including during the sector erase

time-out. The system may use either OE# or CE#

to control the read cycles.

When the system detects that DQ[7] has changed

from the complement to true data (or “0” to “1” for

erase), it should do an additional read cycle to

ensure that valid data is read on DQ[7:0] or

DQ[15:0]. This is because DQ[7] may change

asynchronously with respect to the other data bits

while Output Enable (OE#) is asserted low.

During an Automatic Program algorithm operation

(including programming while in Erase Suspend

mode), successive read cycles at any address in

the bank where the program operation is taking

place cause DQ[6] to toggle. DQ[6] stops tog-

gling when the operation is complete. If a pro-

gram address falls within a protected sector, DQ[6]

toggles for approximately 1 µs after the Program

command sequence is written, then returns to

reading array data.

Figure 7 shows the Data# Polling test algorithm.

DQ[6] - Toggle Bit I

While erasing, successive read cycles within any

sector designated for erasure (or any sector for

the chip erase operation) cause DQ[6] to toggle.

DQ[6] stops toggling when the erase operation is

complete or when the device is placed in the Erase

Suspend mode. The host may use DQ[2] to de-

termine which sectors are erasing or erase-sus-

pended (see below).

Toggle Bit I on DQ[6] indicates whether an Auto-

matic Program or Erase algorithm is in progress

or complete, or whether the device has entered

the Erase Suspend mode. Toggle Bit I may be

read at any address within the programming or

erasing bank and is valid after the rising edge of

START

After an Erase command sequence is written, if

all the sectors designated for erasure are pro-

tected, DQ[6] toggles for approximately 100 µs,

and the device then returns to reading array data.

Read DQ[7:0]

at Valid Address (Note 1)

Test for DQ[7] = 1?

for Erase Operation

DQ[2] - Toggle Bit II

DQ[7] = Data?

YES

Toggle Bit II, DQ[2], when used with DQ[6], indi-

cates whether a particular sector is actively eras-

ing or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the

final WE# pulse in the command sequence. The

device toggles DQ[2] with each OE# or CE# read

cycle.

NO

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

DQ[2] toggles when the host reads at addresses

within sectors that have been designated for era-

sure, but cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ[6],

by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but can-

not distinguish which sectors are designated for

erasure. Thus, both status bits are required for

sector and mode information.

Test for DQ[7] = 1?

for Erase Operation

DQ[7] = Data?

(Note 2)

YES

NO

PROGRAM/ERASE

EXCEEDED TIME ERROR

PROGRAM/ERASE

COMPLETE

Notes:

Figure 8 illustrates the operation of Toggle Bits I

and II.

1. During programming , the program address. During sector erase , an

address within any non-protected sector specified for erasure. During

chip erase , an address within any non-protected sector.

2. Recheck DQ[7] since it may change asynchronously to DQ[5].

Figure 7. Data# Polling Test Algorithm

26

r1.3/June 01

HY29DL162/HY29DL163

DQ[5] - Exceeded Timing Limits

sector erase time-out expires and the sector erase

operation commences, DQ[3] switches from a ‘0’

to a ‘1’. Refer to the “Sector Erase Command”

section for additional information. Note that the

sector erase timer does not apply to the Chip Erase

command.

DQ[5] is set to a ‘1’ when the program or erase

time has exceeded a specified internal pulse count

limit. This is a failure condition that indicates that

the program or erase cycle was not successfully

completed. DQ[5] status is valid only while DQ[7]

or DQ[6] indicate that the Automatic Algorithm is

in progress.

After the initial Sector Erase command sequence

is issued, the system should read the status on

DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to

ensure that the device has accepted the command

sequence, and then read DQ[3]. If DQ[3] is a ‘1’,

the internally controlled erase cycle has begun and

all further sector erase data cycles or commands

(other than Erase Suspend) are ignored until the

erase operation is complete. If DQ[3] is a ‘0’, the

device will accept a sector erase data cycle to mark

an additional sector for erasure. To ensure that

the data cycles have been accepted, the system

software should check the status of DQ[3] prior to

and following each subsequent sector erase data

cycle. If DQ[3] is high on the second status check,

the last data cycle might not have been accepted.

The DQ[5] failure condition will also be signaled if

the host tries to program a ‘1’ to a location that is

previously programmed to ‘0’, since only an erase

operation can change a ‘0’ to a ‘1’.

For both of these conditions, the host must issue

a Reset command to return the device to the Read

mode.

DQ[3] - Sector Erase Timer

After writing a Sector Erase command sequence,

the host may read DQ[3] to determine whether or

not an erase operation has begun. When the

START

DQ[5] = 1?

Read DQ[7:0]

NO

Read DQ[7:0]

at Valid Address (Note 1)

YES

Read DQ[7:0]

at Valid Address (Note 1)

Read DQ[7:0]

at Valid Address (Note 1)

YES

NO

DQ[6] Toggled?

(Note 2)

NO

DQ[6] Toggled?

DQ[2] Toggled?

NO

(Note 4)

NO

(Note 3)

YES

PROGRAM/ERASE

COMPLETE

PROGRAM/ERASE

EXCEEDED TIME ERROR

SECTOR BEING READ

IS IN ERASE SUSPEND

SECTOR BEING READ

IS NOT IN ERASE SUSPEND

Notes

:

1. During programming, the program address.

During sector erase, an address within any sector scheduled for erasure.

2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.

3. Use this path if testing for Program/Erase status.

4. Use this path to test whether sector is in Erase Suspend mode.

Figure 8. Toggle Bit I and II Test Algorithm

r1.3/June 01

27

HY29DL162/HY29DL163

HARDWARE DATA PROTECTION

The HY29DL16x provides several methods of pro-

tection to prevent accidental erasure or program-

ming which might otherwise be caused by spuri-

ous system level signals during V_CCpower-up and

power-down transitions, or from system noise.

These methods are described in the sections that

follow.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by asserting any one of

the following conditions: OE# = V_IL, CE# = V_IH, or

WE# = V_IH. To initiate a write cycle, CE# and WE#

must be a logical zero while OE# is a logical one.

Command Sequences

Commands that may alter array data require a

sequence of cycles as described in Table 10. This

provides data protection against inadvertent writes.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automatically reset to the Read mode on power-

up.

Low V_CCWrite Inhibit

To protect data during V_CCpower-up and power-

down, the device does not accept write cycles

when V_CCis less than V_LKO(typically 2.4 volts). The

command register and all internal program/erase

circuits are disabled, and the device resets to the

Read mode. Writes are ignored until V_CCis greater

than V_LKO. The system must provide the proper

signals to the control pins to prevent unintentional

Sector Protection

Additional data protection is provided by the

HY29DL16x’s sector protect features, described

previously, which can be used to protect sensitive

areas of the Flash array from accidental or unau-

thorized attempts to alter the data.

writes when V_CCis greater than V_LKO

.

r1.3/June 01

28

HY29DL162/HY29DL163

ABSOLUTE MAXIMUM RATINGS¹

Symbol

Parameter

Value

Unit

ºC

T_STG

T_BIAS

Storage Temperature

-65 to +150

-55 to +125

Ambient Temperature with Power Applied

Voltage on Pin with Respect to V_SS:

ºC

2

V_CC

-0.5 to +4.0

-0.5 to +9.5

-0.5 to +12.5

-0.5 to (V_CC+ 0.5)

V

V_IN2

WP#/ACC³

A[9], OE#, RESET# ³

All Other Pins ²

I_OS

Output Short Circuit Current ⁴

200

mA

Notes:

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V_SSto

-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V_CC+ 0.5 V. During voltage

transitions, input or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns. See Figure 10.

3. Minimum DC input voltage on pins WP#/ACC, A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#

and RESET# may undershoot V_SSto -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pins

A[9], OE#, and RESET#] is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. Maximum DC input voltage

on pin WP#/ACC is +9.5 V which may overshoot to 12.0 V for periods up to 20 ns.

4. No more than one output at a time may be shorted to V_SS. Duration of the short circuit should be less than one second.

RECOMMENDED OPERATING CONDITIONS¹

Symbol

Parameter

Value

Unit

Ambient Operating Temperature:

T_A

Commercial Temperature Devices

Industrial Temperature Devices

0 to +70

-40 to +85

ºC

V_CC

Operating Supply Voltage

+2.7 to +3.6

V

Notes:

1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.

20 ns

V_CC+ 2.0 V

0.8 V

- 0.5 V

V_CC+ 0.5 V

2.0 V

- 2.0 V

20 ns

Figure 9. Maximum Undershoot Waveform

Figure 10. Maximum Overshoot Waveform

r1.3/June 01

29

HY29DL162/HY29DL163

DC CHARACTERISTICS

Parameter

Description

Test Setup ²

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

I_LI

I_LIT

I_LO

Input Load Current

A[9] Input Load Current

Output Leakage Current

A[9] = 12.5 V

V_OUT= V_SSto V_CC

CE# = V_IL,

OE# = V_IH,

Byte Mode

CE# = V_IL,

OE# = V_IH,

Word Mode

CE# = V_IL,

OE# = V_IH,

Byte Mode

CE# = V_IL,

OE# = V_IH,

Word Mode

±1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

5 MHz

1 MHz

5 MHz

1 MHz

10

2

16

4

mA

I_CC1

V_CCActive Read Current¹

10

2

16

4

21

16

21

45

34

45

V_CCActive Read While Write

(Program or Erase) Current¹

I_CC2

16

15

34

35

mA

3, 4

I_CC3

I_CC4

V_CCActive Write Current

V_CCCE# Controlled Deep

Standby Current

V_CCRESET# Controlled Deep

Standby Current

Automatic Sleep Mode

Current⁵

V_CCCE# Controlled Normal

Standby Current

V_CCRESET# Controlled

Normal Standby Current²

CE# = V_IL,OE# = V_IH

CE# = V_CC± 0.3 V,

RESET# = V_CC± 0.3 V

0.2

50

5

µA

I_CC5

I_CC6

I_CC7

I_CC8

I_ACC

RESET# = V_SS± 0.3 V

V_IH= V_CC± 0.3 V,

V_IL= V_SS± 0.3 V

5

CE# = RESET# = V_IH

RESET# = V_IL

300

50

V_HH

V_CC

5

15

10

30

0.8

mA

V

Accelerated Program Current, CE# = V_IL,

Byte or Word Mode

OE# = V_IH

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.5

0.7 x V_CC

V_CC+ 0.3

V

Voltage for Electronic ID and

Temporary Sector Unprotect

Voltage for Program

Acceleration

V_ID

V_CC= 3.0V ± 10%

8.5

12.5

9.5

V

V_HH

V_CC= V_CCMin,

I_OL= 4.0 mA

V_CC= V_CCMin,

I_OH= -2.0 mA

V_CC= V_CCMin,

I_OH= -100 µA

V_OL1

V_OH1

V_OH2

Output Low Voltage

0.45

0.85 x V_CC

Output High Voltage

V_CC- 0.4

2.3

V

V_LKO

Low V_CCLockout Voltage⁴

2.5

Notes:

1. The I_CCcurrent is listed is typically less than 2 mA/MHz with OE# at V_IH. Typical V_CCis 3.0 V.

2. All parameters are tested with V_CC= V_CCMax unless otherwise noted.

3. I_CCactive while the Automatic Erase or Automatic Program algorithm is in progress.

4. Not 100% tested.

5. Automatic sleep mode is enabled when addresses remain stable for t_ACC+ 30 ns (typical).

r1.3/June 01

30

HY29DL162/HY29DL163

DC CHARACTERISTICS

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz.

Figure 11. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

6

Frequency in MHz

Note: T = 25 °C.

Figure 12. Typical I_CC1Current vs. Frequency

r1.3/June 01

31

HY29DL162/HY29DL163

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Centerline is High Impedance State

(High Z)

TEST CONDITIONS

Table 17. Test Specifications

+ 3.3V

Test

Condition

Output Load

- 70 - 90

- 80 - 12

Unit

Figure 13

100

2.7

KOhm

Output Load Capacitance (C_L)

Input Rise and Fall Times

Input Signal Low Level

30

pF

ns

V

5

DEVICE

UNDER

TEST

0.0

3.0

All diodes

are

1N3064

or

equivalent

Input Signal High Level

V

6.2

C_L

Input Timing Measurement

Signal Level

KOhm

1.5

V

Output Timing Measurement

Signal Level

Note: Timing measurements are made at the reference

levels specified above regardless of where the illustrations

in the timing diagrams appear to indicate the measurement

is made

Figure 13. Test Setup

3.0 V

0.0 V

I

nput

1.5 V

Measurement Level

1.5 V

Output

Figure 14. Input Waveforms and Measurement Levels

r1.3/June 01

32

HY29DL162/HY29DL163

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

Unit

Description

Test Setup

JEDEC

Std

- 70 - 80 - 90 - 12

t_AVAV

t_RCRead Cycle Time ¹

Min 70

80

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max 70

80

90

120

t_ELQV

t_EHQZ

t_GLQV

t_GHQZ

t_CEChip Enable to Output Delay

t_DFChip Enable to Output High Z¹

t_OEOutput Enable to Output Delay

t_DFOutput Enable to Output High Z¹

OE# = V_ILMax 70

Max 30

80

30

25

90

40

30

120

50

ns

CE# = V_ILMax 25

Max 25

30

Read

Min

0

Output Enable

t_OEH

Toggle and

Data# Polling

Hold Time ¹

Min

10

ns

Output Hold Time from Addresses, CE#

or OE#, Whichever Occurs First

t_AXQX

t_OH

0

1

Notes:

1. Not 100% tested.

t_RC

Addresses

CE#

Addresses Stable

t_ACC

t_OE

OE#

t_OEH

t_DF

WE#

t_CE

t_OH

Outputs

RESET#

Output Valid

RY/BY#

0 V

Figure 15. Read Operation Timings

r1.3/June 01

33

HY29DL162/HY29DL163

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Speed Option

Description

Test Setup

Unit

JEDEC

Std

- 70 - 80 - 90 - 12

RESET# Pin Low (During Automatic

Algorithms) to Read or Write ¹

t_READY

Max

20

µs

ns

RESET# Pin Low (NOT During

t_READY

500

Automatic Algorithms) to Read or Write¹

t_RPRESET# Pulse Width

Min

Max

Min

500

50

20

0

ns

µs

ns

t_RHRESET# High Time Before Read ¹

t_RPDRESET# Low to Standby Mode

t_RBRY/BY# Recovery Time

Notes:

1. Not 100% tested.

RY/BY#

0 V

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT During Automatic Algorithms

t_Ready

RY/BY#

CE#, OE#

RESET#

t_RB

t_RP

Reset Timings During Automatic Algorithms

Figure 16. RESET# Timings

r1.3/June 01

34

HY29DL162/HY29DL163

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Option

Unit

Description

JEDEC

Std

- 70 - 80 - 90 - 12

t_ELFLCE# to BYTE# Switching Low

Max

5

ns

t_ELFHCE# to BYTE# Switching High

Max

t_FLQZBYTE# Switching Low to Output High-Z

t_FHQVBYTE# Switching High to Output Active

Max 25

Min 70

25

80

30

90

30

120

CE#

OE#

BYTE#

switching

from word to

byte mode

t_ELFL

Data Output DQ[14:0]

Data Output DQ[7:0]

Address Input A-1

DQ[14:0]

Output DQ[15]

DQ[15]/A-1

t_FLQZ

BYTE#

switching

Data Output DQ[7:0]

Data Output DQ[14:0]

Data Output DQ[15]

DQ[14:0]

from byte to

word mode

Address Input A-1

DQ[15]/A-1

t_ELFH

t_FHQV

Figure 17. BYTE# Timings for Read Operations

CE#

Falling edge of the last WE# signal

WE#

t_SET(t_AS

)

BYTE#

t_HOLD(t_AH

)

Note: Refer to the Program/Erase Operations table for t_ASand t_AHspecifications.

Figure 18. BYTE# Timings for Write Operations

r1.3/June 01

35

HY29DL162/HY29DL163

AC CHARACTERISTICS

Program and Erase Operations

Parameter

Speed Option

Description

Unit

JEDEC Std

- 70 - 80 - 90 - 12

t_AVAV

t_AVWL

t_WLAX

t_WCWrite Cycle Time ¹

t_ASAddress Setup Time

t_AHAddress Hold Time

t_ASTAddress Setup Time for Toggle Bit Test

t_AHTAddress Hold Time for Toggle Bit Test

t_DSData Setup Time

t_DHData Hold Time

t_GHWLRead Recovery Time Before Write

t_CSCE# Setup Time

Min

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Min

70

80

90

120

ns

µs

0

45

50

15

0

t_DVWH

t_WHDX

t_GHWL

t_ELWL

t_WHEH

35

30

35

30

45

35

50

0

20

t_CHCE# Hold Time

t_OEPHOE# High Time for Toggle Bit Test

t_CEPHCE# High Time for Toggle Bit Test

t_WPWrite Pulse Width

t_WPHWrite Pulse Width High

t_SR/WLatency Between Read and Write Operations

t_WLWH

t_WHWL

30

0

10

150

15

210

10

150

20

60

16

48

Byte Mode

Programming Operation ^{1, 2, 3}

µs

t_WHWH1t_WHWH1

Word Mode

Accelerated Programming

Byte or

Word Mode

Operation ^{1, 2, 3}(WP#/ACC = V_HH)

sec

cycles

µs

Byte Mode

Word Mode

Chip Programming Operation ^{1, 2, 3, 5}

0.5

7.5

16

t_WHWH2t_WHWH2Sector Erase Operation ^{1, 2, 4}

t_WHWH3t_WHWH3Chip Erase Operation ^{1, 2, 4}

1,000,000

100,000

Erase and Program Cycle Endurance ¹

t_VCSV_CCSetup Time ¹

t_RBRecovery Time from RY/BY#

t_BUSYWE# High to RY/BY# Delay

50

0

90

ns

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V_CC= 2.0 volts, 100,000 cycles. In addition,

programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-

tions of 90 °C, V_CC= 1.8 volts, 100,000 cycles.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the Program

command. See Table 10 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes

are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most

bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the

maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.

r1.3/June 01

36

HY29DL162/HY29DL163

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_{W C}

t_AS

t_AH

Addresses

CE#

0x555

PA

t_{G H W L}

OE#

t_CH

t_{W P}

WE#

t_CS

t_{W P H}

t_DH

t_DS

t_{W H W H 1}

Data

0xA0

PD

t_BUSY

Status

D_OUT

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = Program Address, PD = Program Data, D_OUTis the true data at the program address.

2. Commands shown are for Word mode operation.

3. V_CCshown only to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid command sequence.

Figure 19. Program Operation Timings

r1.3/June 01

37

HY29DL162/HY29DL163

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_{W C}

t_AS

t_AH

Addresses

CE#

0x2AA

SA

VA

Address = 0x555

for chip erase

t_{G H W L}

OE#

t_CH

t_{W P}

WE#

t_{W H W H 2}or

t_{W H W H 3}

t_CS

t_{W P H}

t_DS

Data = 0x10

for chip erase

t_DH

Data

0x55

0x30

t_BUSY

Status

D_OUT

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),

_OUTis the true data at the read address. (0xFF after an erase operation).

D

2. Commands shown are for Word mode operation.

3. V_CCshown only to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid command sequence.

Figure 20. Sector/Chip Erase Operation Timings

r1.3/June 01

38

HY29DL162/HY29DL163

AC CHARACTERISTICS

t_{W C}

t_RC

t_{W C}

Valid PA

Valid RA

t_ACC

Valid PA

Addresses

t_AS

t_CPH

CE#

OE#

t_AH

t_CP

t_CE

t_{G H W L}

t_OEH

t_DF

WE#

t_{W P H}

t_{W P}

t_DS

t_OH

t_OE

t_DH

Valid D_IN

Valid D_OUT

Valid D_IN

Data Bus

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

t_SR/W

Notes:

1. PA = Program Address, RA = Read Address, D_OUTis the data at the read address.

Figure 21. Back-to-Back Read/Write Operation Timings

r1.3/June 01

39

HY29DL162/HY29DL163

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CH

CE#

OE#

WE#

t_CE

t_DF

t_OEH

t_OE

t_OH

Complement

Status Data

Complement

True

Valid Data

DQ[7]

DQ[6:0]

RY/BY#

Status Data

Data

t_BUSY

Notes:

1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).

2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.

Figure 22. Data# Polling Timings (During Automatic Algorithms)

t_ACC

t_RC

Addresses

CE#

VA

t_CE

VA

t_AHT

t_AST

t_CEPH

t_OEPH

t_CH

t_OE

OE#

t_DF

t_OEH

WE#

t_OH

Valid Status

(first read)

Valid Status

(second read)

Valid Status

Valid Data

DQ[6], [2]

(stops toggling)

t_BUSY

RY/BY#

Notes:

1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section).

2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.

Figure 23. Toggle Polling Timings (During Automatic Algorithms)

r1.3/June 01

40

HY29DL162/HY29DL163

AC CHARACTERISTICS

Enter Erase

Suspend

Program

Enter Automatic

Erase

Suspend

Erase

Resume

WE#

Erase

Suspend

Read

Erase

Suspend

Program

Erase

Suspend

Read

Erase

Complete

DQ[6]

DQ[2]

Notes:

1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an

erase-suspended sector.

Figure 24. DQ[2] and DQ[6] Operation

Sector Group Protect/Unprotect, Temporary Sector Unprotect, Accelerated Program

Parameter

Speed Option

Description

Unit

JEDEC Std

- 70 - 80 - 90 - 12

t_VIDRV_IDTransition Time for Temporary Sector Unprotect¹

t_VHHV_HHTransition Time for Accelerated Programming ¹

Min

500

250

4

ns

µs

t_RSPRESET# Setup Time for Temporary Sector Unprotect Min

t_RRBRESET# Hold Time for Temporary Sector Unprotect

Min

4

RESET# Setup Time for Sector Group Protect and

Unprotect

t_VRST

Min

1

µs

t_PROTSector Group Protect Time

t_UNPRSector Unprotect Time

Max

Min

150

15

1

µs

ms

µs

t_VERWProtect/Unprotect Verify Wait Time

Notes:

1. Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

CE#

WE#

t_RSP

t_RRB

RY/BY#

Figure 25. Temporary Sector Unprotect Timings

r1.3/June 01

41

HY29DL162/HY29DL163

AC CHARACTERISTICS

V_{H H}

WP#/ACC

V_ILor V_IH

t_VHH

Figure 26. Accelerated Programming Timings

V_ID

V_IH

RESET#

SA, A[6],

A[1], A[0]

Don't Care

Sector Protect/Unprotect

0x60 0x60

Valid *

Verify

0x40

Valid *

Status

Data

t_VRST

t_PROT

t_{V E R W}

CE#

WE#

OE#

t_{U N P R}

Note: For Sector Group Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0.

Figure 27. Sector Group Protect and Unprotect Timings

r1.3/June 01

42

HY29DL162/HY29DL163

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Description

JEDEC Std

Speed Option

Unit

- 70 - 80 - 90 - 12

t_AVAV

t_AVEL

t_ELAX

t_DVEH

t_EHDX

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WCWrite Cycle Time ¹

t_ASAddress Setup Time

t_AHAddress Hold Time

t_DSData Setup Time

Min

Typ

70

80

90

120

ns

0

45

35

45

35

45

50

ns

t_DHData Hold Time

0

ns

t_GHELRead Recovery Time Before Write

t_WSWE# Setup Time

ns

t_WHWE# Hold Time

ns

t_CPCE# Pulse Width

30

45

50

ns

t_CPHCE# Pulse Width High

30

10

ns

µs

Byte Mode

Word Mode

Max

Typ

150

15

µs

Programming Operation ^{1, 2, 3}

µs

t_WHWH1t_WHWH1

Max

Typ

210

10

µs

Accelerated Programming

Byte or

Word Mode

Operation ^{1, 2, 3}(WP#/ACC = V_HH)

Max

Typ

150

20

µs

sec

Byte Mode

Word Mode

Max

Typ

60

Chip Programming Operation ^{1, 2, 3, 5}

16

Max

Typ

48

0.5

7.5

t_WHWH2t_WHWH2Sector Erase Operation ^{1, 2, 4}

t_WHWH3t_WHWH3Chip Erase Operation ^{1, 2, 4}

Max

Typ

16

sec

Typ

Min

1,000,000

100,000

90

cycles

ns

Erase and Program Cycle Endurance ¹

t_BUSYCE# to RY/BY# Delay

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V_CC= 3.0 volts, 100,000 cycles. In addition,

programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-

tions of 90 °C, V_CC= 2.7 volts, 100,000 cycles.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the Program

command. See Table 10 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes

are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most

bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum

byte program time specified is exceeded. See Write Operation Status section for additional information.

r1.3/June 01

43

HY29DL162/HY29DL163

AC CHARACTERISTICS

PA for Program

SA for Sector Erase

0x555 for Chip Erase

0x555 for Program

0x2AA for Erase

Addresses

VA

t_{W C}

t_AS

t_AH

WE#

t_GHEL

t_{W H}

OE#

t_CP

t_CPH

t_{W H W H 1}or t_{W H W H 2}or t_{W H W H 3}

t_{W S}

CE#

t_DS

t_DH

t_BUSY

Data

Status

D _OUT

0xA0 for Program

0x55 for Erase

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

RY/BY#

t_RH

RESET#

Notes:

1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write

Operation Status section), D_OUT= array data read at VA.

2. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.

3. Word mode addressing shown.

4. RESET# shown only to illustrate t_RHmeasurement references. It cannot occur as shown during a valid command

sequence.

Figure 28. Alternate CE# Controlled Write Operation Timings

r1.3/June 01

44

HY29DL162/HY29DL163

Latchup Characteristics

Description

Minimum

Maximum

Unit

Input voltage with respect to V_SSon all pins except I/O pins

(including A[9], OE# and RESET#)

- 1.0

12.5

V

Input voltage with respect to V_SSon all I/O pins

- 1.0

V_CC+ 1.0

100

V

V_CCCurrent

- 100

mA

Notes:

1. Includes all pins except V_CC. Test conditions: V_CC= 1.8 V, one pin at a time.

TSOP Pin Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Test Setup

V_IN= 0

Typ

Max

7.5

12

Unit

6

pF

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

Control Pin Capacitance

9

Notes:

1. Sampled, not 100% tested.

2. Test conditions: T_A= 25 ºC, f = 1.0 MHz.

Data Retention

Parameter

Test Conditions

Minimum

Unit

Years

150 ºC

125 ºC

10

20

Minimum Pattern Data Retention Time

PACKAGE DRAWINGS

Physical Dimensions

TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)

0.95

1.05

Pin 1 ID

1

48

0.50 BSC

11.90

12.10

24

25

18.30

18.50

0.05

0.15

19.80

20.20

0.08

0.20

1.20

MAX

0.10

0.21

0^o

5^o

0.25MM (0.0098") BSC

0.50

0.70

r1.3/June 01

45

HY29DL162/HY29DL163

PACKAGE DRAWINGS

Physical Dimensions

FBGA48 - 48-Ball Fine-Pitch Ball Grid Array, 8 x 9 mm (measurements in millimeters)

Note: Unless otherwise specified, tolerance = ± 0.05 mm

0.10

C

9.00 ± 0.10

A

1.80

± 0.10

A1 CORNER

INDEX AREA

2.10 ± 0.10

8.00 ± 0.10

C

0.10

C

B

C

0.10

C

0.76

TYP

1.10

MAX

Seating

Plane

0.20

MIN

C

0.08

C

5.60 BSC

H

G

F

E

D

C

B

A

6

5

4

3

2

1

0.40

BSC

4.00 BSC

C

0.80 TYP

0.40

BSC

Ø

0.30 ± 0.05

Pin A1

Index Mark

Ø 0.15

Ø 0.08

M

C

A B

C

r1.3/June 01

46

HY29DL162/HY29DL163

ORDERING INFORMATION

Hynix products are available in several speeds, packages and operating temperature ranges. The

ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid

Combinations’ table, which lists the configurations that are planned to be supported in volume. Please

contact your local Hynix representative or distributor to confirm current availability of specific configura-

tions and to determine if additional configurations have been released.

HY29DL16x

X

-

X

SPECIAL INSTRUCTIONS

TEMPERATURE RANGE

Blank = Commercial ( 0 to +70 °C)

I = Industrial (-40 to +85 °C)

SPEED OPTION

70 = 70 ns

80 = 80 ns

90 = 90 ns

12 = 120 ns

PACKAGE TYPE

T = 48-Pin Thin Small Outline Package (TSOP)

F = 48-Ball Fine-Pitch Ball Grid Array (FBGA), 8 x 9 mm

BOOT BLOCK LOCATION

T = Top Boot Block Option

B = Bottom Boot Block Option

DEVICE NUMBER

HY29DL162 = 16 Megabit (2M x 8/1M x 16) CMOS 3 Volt-Only Sector

Erase Flash Memory with 2Mb/14Mb Bank Split

HY29DL163 = 16 Megabit (2M x 8/1M x 16) CMOS 3 Volt-Only Sector

Erase Flash Memory with 4Mb/12Mb Bank Split

VALID COMBINATIONS

Package and Speed

FBGA

80 ns

TSOP

Temperature

Commercial

Industrial

70 ns

F-70

90 ns

F-90

120ns

F-12

70 ns

T-70

80 ns

T-80

90 ns

T-90

120ns

T-12

F-80

F-70I

F-80I

F-90I

F-12I

T-70I

T-80I

T-90I

T-12I

Note:

1. The complete part number is formed by appending the suffix shown in the table to the Device Number. For example, the

part number for a 120 ns, Industrial temperature range, 2Mb/14Mb bank-split device in the TSOP package with the top

boot block option is HY29DL162TT-12I.

2. Please contact your local Hyundai representative or distributor for current product availability.

r1.3/June 01

47

HY29DL162/HY29DL163

Important Notice

No part of this document may be copied or reproduced in any

form or by any means without the prior written consent of Hynix

Semiconductor Inc. or Hynix Semiconductor America (collec-

tively “Hynix”).

tions of Sale only. Hynix makes no warranty, express, statu-

tory, implied or by description, regarding the information set

forth herein or regarding the freedom of the described devices

from intellectual property infringement. Hynix makes no war-

ranty of merchantability or fitness for any purpose.

The information in this document is subject to change without

notice. Hynix shall not be responsible for any errors that may

appear in this document and makes no commitment to update

or keep current the information contained in this document.

Hynix advises its customers to obtain the latest version of the

device specification to verify, before placing orders, that the

information being relied upon by the customer is current.

Hynix’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific writ-

ten agreement pertaining to such intended use is executed

between the customer and Hynix prior to use. Life support

devices or systems are those which are intended for surgical

implantation into the body, or which sustain life whose failure to

perform, when properly used in accordance with instructions

for use provided in the labeling, can be reasonably expected to

result in significant injury to the user.

Devices sold by Hynix are covered by warranty and patent in-

demnification provisions appearing in Hynix Terms and Condi-

Revision Record

Rev. Date

Details

1.0

5/00

Original issue.

Corrected description of CFI Query and Reset commands in CFI mode description section.

Minor typographical corrections.

1.1

7/00

Change to Hynix format.

Removed 'BA' as requirement for several operations in Table 6 and corrected description of Electronic ID Operation

(High Voltage Method).

Added Bank Address to CFI Query command and changed operational description in CFI section.

Removed high voltage sector group protect/unprotect method and all references to such.

1.2

1.3

4/01

6/01

Changed program and erase parameter values. Corrected error in CFI Table 13.

Memory Sales and Marketing Division

Hynix Semiconductor Inc.

10 Fl., Hynix Youngdong Building

89, Daechi-dong

Flash Memory Business Unit

Hynix Semiconductor America Inc.

3101 North First Street

San Jose, CA 95134

USA

Kangnam-gu

Seoul, Korea

Telephone: (408) 232-8800

Fax: (408) 232-8805

Telephone: +82-2-580-5000

Fax: +82-2-3459-3990

http://www.us.hynix.com

http://www.hynix.com

r1.3/June 01

48


型号：	HY29DL162BT-70I
厂家：	HYNIX SEMICONDUCTOR
描述：	16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory 16兆位（ 2M ×8 / 1M ×16）低电压，双组，同步读/写闪存闪存存储内存集成电路光电二极管
文件：	总48页 (文件大小：548K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY29DL162BT-70I [HYNIX]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E