HY57V161610ETP-8_技术文档

HY57V161610E

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic appli-

cations which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.

HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized

with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-

ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A

burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a

new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3.0V to 3.6V power supply

4096 refresh cycles / 64ms

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 1, 2, 3 Clocks

JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin

pitch(Lead Free)

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by UDQM/LDQM

Internal two banks operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V161610ETP-5

HY57V161610ETP-55

HY57V161610ETP-6

HY57V161610ETP-7

HY57V161610ETP-8

HY57V161610ETP-10

HY57V161610ETP-15

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

66MHz

400mil

50pin TSOP II

2Banks x 512Kbits x 16

LVTTL

Note :

1. VDD(min) of HY57V161610ETP-5/55 is 3.15V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for

use of circuits described. No patent licenses are implied

Rev. 0.1 / Nov. 2003

1

HY57V161610E

PIN CONFIGURATION

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VDDQ

LDQM

/WE

/CAS

/RAS

/CS

1

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

VSS

2

DQ15

DQ14

VSSQ

DQ13

DQ12

VDDQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

NC

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

50Pin TSOPII

400mil x 825mil

0.8mm pin pitch

UDQM

CLK

CKE

NC

BA

A9

A10

A8

A0

A7

A1

A6

A2

A5

A3

A4

VDD

VSS

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are referenced to the SDRAM on the rising

edge of CLK.

CLK

CKE

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one of the

states among power down, suspend or self refresh.

Clock Enable

CS

BA

Chip Select

Command input enable or mask except CLK, CKE and DQM

Select either one of banks during both RAS and CAS activity.

Bank Address

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

A0 ~ A10

Address

Row Address Strobe,

Column Address Strobe, Write

Enable

RAS, CAS and WE define the operation.

Refer function truth table for details

RAS, CAS, WE

LDQM, UDQM

DQ0 ~ DQ15

VDD/VSS

Data Input/Output Mask

Data Input/Output

DQM control output buffer in read mode and mask input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuit and input buffer

Power supply for DQ

VDDQ/VSSQ

NC

No connection

Rev. 0.1 / Nov. 2003

2

HY57V161610E

FUNCTIONAL BLOCK DIAGRAM

1Mx16 Synchronous DRAM

Self Refresh Counter

Refresh

Interval Timer

Refresh

Counter

512Kx16

Bank 0

Address[0:10]

Sense AMP & I/O gates

Column Decoder

DQ0

DQ1

DQ2

DQ3

CLK

CKE

Address

Register

Precharge

Row Active

BA(A11)

DQ4

DQ5

DQ6

DQ7

DQ8

Column Addr.

Latch & Counter

Column Active

CS

RAS

CAS

WE

Overflow

Burst Length

Counter

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQM

LDQM

Column Decoder

Sense AMP & I/O gates

512Kx16

Bank 1

Mode Register

Test Mode

I/O Control

Rev. 0.1 / Nov. 2003

3

HY57V161610E

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

50

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

VDD

V

IOS

mA

W

PD

1

Soldering Temperature·Time

TSOLDER

260·10

°C ·Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION (TA=0°C to 70°C)

Parameter

Power Supply Voltage

Input high voltage

Symbol

VDD, VDDQ

Min

3.0

Typ.

3.3

3.0

0

Max

3.6

Unit

V

Note

1, 2, 3

1, 4

VIH

VIL

2.0

VDD + 0.3

0.8

V

Input low voltage

-0.3

V

1, 5

Note :

1.All voltages are referenced to VSS = 0V.

2.VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2

3.VDD(min) of HY57V161610ETP-5/55 is 3.15V

4.Vih(Max) : 4.6V AC pulse width with < 3ns of duration.

5.Vil(min) : -1.5V AC pulse width with < 3ns of duration.

AC OPERATING CONDITION (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V)

Parameter

AC input high / low level voltage

Symbol

VIH / VIL

Vtrip

Value

2.4/0.4

1.4

Unit

V

Note

Input timing measurement reference level voltage

Input rise / fall time

V

tR / tF

Voutref

CL

1

ns

V

Output timing measurement reference level

Output load capacitance for access time measurement

1.4

30

pF

1

Note :

1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).

For details, refer to AC/DC output load circuit.

2. VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2 and tCK2=8.9ns

3. VDD(min) of HY57V161610ETP-5/55 is 3.15V‘

Rev. 0.1 / Nov. 2003

4

HY57V161610E

CAPACITANCE (TA=25°C, f=1MHz)

Parameter

Symbol

CI1

Min

2.5

Max

4

Unit

pF

CLK

A0 ~ A10, BA

Input capacitance

CI2

5

pF

CKE, CS, RAS, CAS, WE, UDQM, LDQM

Data input / output capacitance

DQ0 ~ DQ15

CI/O

4

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 Ω

Output

30pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I ^{(TA=0°C to 70°C)}

Parameter

Power Supply Voltage

Input leakage current

Output leakage current

Output high voltage

Output low voltage

Symbol

Min.

3.0

-1

Max

3.6

1

Unit

V

Note

VDD

IL

1, 2

3

uA

V

IO

-1

1

4

VOH

VOL

2.4

-

IOH = -4mA

IOL =+4mA

0.4

V

Note :

1.VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2 and tCK2=8.9ns.

2.VDD(min) of HY57V161610ETP-5/55 is 3.15V

3.VIN = 0 to 3.6V, All other pins are not under test = 0V

4.DOUT is disabled, VOUT=0 to 3.6V

Rev. 0.1 / Nov. 2003

5

HY57V161610E

DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V^Note1,2

)

Speed

-7

Parameter

Symbol

Test Condition

Unit

mA

Note

-5

-55

-6

-8

-10

-15

Burst Length=1, One bank active

tRAS ≥ tRAS(min),tRP ≥ tRP(min),

IO=0mA

Operating Current

IDD1

130

120

110

100

2

1

IDD2P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

Precharge Standby

Current

in power down mode

mA

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

Input signals are changed one time

during 2Clks. All other pins ≥ VDD-0.2V

or ≤ 0.2V

IDD2N

25

Precharge Standby

Current

in non power down

mode

mA

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

15

IDD3P

3.0

CKE ≤ VIL(max), tCK = min

CKE ≤ VIL(max), tCK = ∞

Active Standby Current

in power down mode

IDD3PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

min

Input signals are changed one time

during 2CLKs. All other pins ≥ VDD-

0.2V or ≤ 0.2V

IDD3N

IDD3NS

IDD4

50

Active Standby Current

in non power down

mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable

30

CL=3

130

120

110

-

110

-

110

90

-

80

-

tCK ≥ tCK(min),

Burst Mode Operating

Current

tRAS ≥ tRAS(min),

CL=2

-

mA

3

IO=0mA

All banks active

CL=1

-

70

100

Auto Refresh Current

Self Refresh Current

IDD5

IDD6

tRRC ≥ tRRC(min), All banks active

CKE ≤ 0.2V

130

110

mA

2

Note :

1.VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2 and tCK2=8.9ns.

2.VDD(min) of HY57V161610ETP-5/55 is 3.15V

3.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.

Rev. 0.1 / Nov. 2003

6

HY57V161610E

AC CHARACTERISTICS (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V^Note1,2

)

-5

-55

-6

-7

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Min

6

Max

Min

7

Max

CL=3

tCK3

tCK2

tCK1

tCHW

tCLW

tAC3

tAC2

tAC1

tOH

5

-

5.5

-

6

-

System clock

cycle time

CL=2

CL=1

10

-

10

-

ns

3

-

Clock high pulse width

Clock low pulse width

CL=3

2

-

2.5

-

ns

4

2

-

4.5

5

-

5.5

6

-

Access time

CL=2

-

ns

3

from clock

CL=1

Data-out hold time

Data-Input setup time

Data-Input hold time

Address setup time

Address hold time

CKE setup time

-

1.5

1

2

1.5

1

2

-

2.5

1.75

1

ns

tDS

1.5

1

-

4

tDH

-

tAS

1.5

1

1.5

1

1.5

1

-

1.75

1

tAH

-

tCKS

tCKH

tCS

1.5

1

1.5

1

1.5

1

-

1.75

1

CKE hold time

-

Command setup time

Command hold time

1.5

1

1.5

1

1.5

1

-

1.75

1

tCH

-

CLK to data output in low Z-

time

tOLZ

tOHZ

2

-

2

-

ns

CLK to data output in high

Z-time

5

5.5

6

7

Rev. 0.1 / Nov. 2003

7

HY57V161610E

AC CHARACTERISTICS (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V^Note1,2

)

- continued -

-8

-10

-15

Parameter

Symbol

Unit

Note

Min

8

Max

Min

10

12

-

Max

Min

15

3

Max

CL=3

tCK3

tCK2

tCK1

tCHW

tCLW

tAC3

tAC2

tAC1

tOH

-

System clock cycle

time

CL=2

CL=1

12

-

ns

3

-

Clock high pulse width

Clock low pulse width

3

-

3

-

ns

4

3

-

3

-

3

-

CL=3

CL=2

CL=1

-

6

-

7

-

7

14

-

Access time from

clock

-

ns

3

-

Data-out hold time

Data-Input setup time

Data-Input hold time

Address setup time

Address hold time

CKE setup time

2.5

2

-

2.5

1

-

2.5

1

ns

tDS

-

4

tDH

1

-

tAS

2

-

2.5

1

-

2.5

1

-

tAH

1

-

tCKS

tCKH

tCS

2

-

2.5

1

-

2.5

1

-

CKE hold time

1

-

Command setup time

Command hold time

2

-

2.5

1

-

2.5

1

-

tCH

1

-

CLK to data output in low Z-time

CLK to data output in high Z-time

tOLZ

tOHZ

2

-

2

-

2

-

2

8

3

10

3

15

Note :

1.VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2 and tCK2=8.9ns.

2.VDD(min) of HY57V161610ETP-5/55 is 3.15V

3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610ET-6 and HY57V161610ETP-7.

4.Assume tR / tF (input rise and fall time ) is 1ns.

Rev. 0.1 / Nov. 2003

8

HY57V161610E

AC CHARACTERISTICS (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V^Note1,2))

-5

-55

-6

-7

Paramter

Symbol

Unit

Note

Min

55

15

40

3

Max

Min

55

16.5

38.5

3

Max

Min

60

18

40

3

Max

Min

70

20

45

3

Max

Operation

Auto Refresh

tRC

tRRC

tRCD

tRAS

tRP

-

ns

RAS cycle time

-

ns

RAS to CAS delay

RAS active time

-

ns

100K

ns

RAS precharge time

-

CLK

ms

RAS to RAS bank active delay

CAS to CAS bank active delay

Write command to data-in delay

Data-in to precharge command

Data-in to active command

DQM to data-in Hi-Z

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

tPROZ

tPDE

tSRE

tREF

2

1

-

1

-

0

-

0

-

1

-

1

-

5

4

-

4

-

2

-

2

-

DQM to data mask

0

-

0

-

MRS to new command

Precharge to data output Hi-Z

Power down exit time

2

-

2

-

3

-

3

-

1

-

1

-

Self refresh exit time

1

-

1

-

3

Refresh Time

64

-

64

-

64

Rev. 0.1 / Nov. 2003

9

HY57V161610E

AC CHARACTERISTICS (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V^Note1,2

)

- continued

-8

-10

-15

Paramter

Symbol

Unit

Note

Min

70

20

45

3

Max

Min

70

80

20

45

2

Max

Min

70

80

20

45

2

Max

Operation

Auto Refresh

tRC

tRRC

tRCD

tRAS

tRP

-

ns

RAS cycle time

-

ns

RAS to CAS delay

RAS active time

-

ns

100K

ns

RAS precharge time

-

CLK

ms

RAS to RAS bank active delay

CAS to CAS bank active delay

Write command to data-in delay

Data-in to precharge command

Data-in to active command

DQM to data-in Hi-Z

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

tPROZ

tPDE

tSRE

tREF

2

1

-

1

-

1

-

0

-

0

-

0

-

1

-

1

-

1

-

4

-

3

-

3

-

2

-

2

-

2

-

DQM to data mask

0

-

0

-

0

-

MRS to new command

Precharge to data output Hi-Z

Power down exit time

2

-

2

-

2

-

3

-

3

-

3

-

1

-

1

-

1

-

Self refresh exit time

1

-

1

-

1

-

3

Refresh Time

-

64

-

64

-

64

-

Note :

1. VDD(min) is 3.15V when HY57V161610ETP-7 operates at CAS latency=2 and tCK2=8.9ns.

2.VDD(min) of HY57V161610ETP-5/55 is 3.15V

3. A new command can be given tRRC after self refresh exit.

DEVICE OPERATING OPTION TABLE

HY57V161610ETP-5

CAS Latency

3CLKs

tRCD

3CLKs

tRAS

8CLKs

7CLKs

tRC

tRP

tAC

4.5ns

5ns

tOH

200MHz

183MHz

166MHz

11CLKs

10CLKs

3CLKs

1.5ns

2ns

3CLKs

5.5ns

2ns

Rev. 0.1 / Nov. 2003

10

HY57V161610E

HY57V161610ETP-55

CAS Latency

tRCD

3CLKs

tRAS

7CLKs

tRC

tRP

tAC

5ns

tOH

2ns

183MHz

166MHz

143MHz

3CLKs

10CLKs

3CLKs

5.5ns

2ns

2.5ns

HY57V161610ETP-6

CAS Latency

tRCD

3CLKs

2CLKs

tRAS

7CLKs

6CLKs

tRC

tRP

tAC

5.5ns

6ns

tOH

2ns

166MHz

143MHz

125MHz

3CLKs

10CLKs

9CLKs

3CLKs

2.5ns

HY57V161610ETP-7

CAS Latency

tRCD

3CLKs

2CLKs

tRAS

7CLKs

6CLKs

5CLKs

tRC

tRP

tAC

5.5ns

6ns

tOH

143MHz

125MHz

100MHz

3CLKs

2CLKs

10CLKs

9CLKs

7CLKs

3CLKs

2CLKs

2.5ns

7ns

HY57V161610ETP-8

CAS Latency

tRCD

3CLKs

2CLKs

tRAS

6CLKs

5CLKs

4CLKs

tRC

tRP

tAC

6ns

7ns

tOH

125MHz

100MHz

83MHz

3CLKs

2CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

2.5ns

HY57V161610ETP-10

CAS Latency

tRCD

2CLKs

tRAS

5CLKs

4CLKs

tRC

tRP

tAC

7ns

tOH

100MHz

83MHz

3CLKs

2CLKs

7CLKs

6CLKs

2CLKs

2.5ns

HY57V161610ETP-15

CAS Latency

1CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

66MHz

2CLKs

4CLKs

6CLKs

2CLKs

14ns

2.5ns

Rev. 0.1 / Nov. 2003

11

HY57V161610E

COMMAND TRUTH TABLE

A10/

AP

Command

Mode Register Set

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

A0~A9

BA

Note

H

X

L

H

L

X

H

L

X

H

L

X

H

X

OP code

No Operation

X

Bank Active

L

Row Address

V

Read

L

H

L

Column

Address

L

H

L

H

L

Read with Auto precharge

Write

Column

Address

H

X

V

Write with Auto precharge

Precharge All Bank

Precharge selected Bank

Burst Stop

H

L

X

V

X

L

H

L

X

H

X

L

X

V

X

U/LDQM

X

Auto Refresh

H

X

L

H

L

A9 Pin High

(Other Pins OP code)

Burst-READ-Single-WRITE

H

L

X

Entry

Exit

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

1

X

Self Refresh

L

H

L

H

L

X

H

L

Entry

Exit

Precharge power

down

X

H

L

H

L

Entry

Exit

H

L

X

Clock Suspend

H

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.

2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code,

NOP=No Operation.

Rev. 0.1 / Nov. 2003

12

HY57V161610E

PACKAGE INFORMATION

400mil 50pin Thin Small Outline Package (TC)

1Mx16 Synchronous DRAM

UNIT : mm(inch)

11.938(0.4700)

11.735(0.4620)

10.262(0.4040)

10.059(0.3960)

0.45(0.0177)

0.8(0.0315 BSC)

0.30(0.0118)

1.2(0.0472)

1.0(0.0394)

0.150(0.0059)

0.050(0.0020)

21.057(0.8290)

20.879(0.8220)

0.646 REF

GAGE PLANE

0~5deg

0.210(0.0083)

0.120(0.0118)

0.597(0.0235)

0.406(0.0160)

Rev. 0.1 / Nov. 2003

13


型号：	HY57V161610ETP-8
厂家：	HYNIX SEMICONDUCTOR
描述：	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50 动态存储器光电二极管
文件：	总13页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V161610ETP-8 [HYNIX]

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