HY57V561620FLT-H [HYNIX]
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | HY57V561620FLT-H |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 动态存储器 |
| 文件： | 总13页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY57V561620(L)T
4Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.
The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3V ± 0.3V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
8192 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
All inputs and outputs referenced to positive edge of
system clock
•
•
Data mask function by UDQM and LDQM
Internal four banks operation
•
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V561620T-HP
HY57V561620T-H
HY57V561620T-8
HY57V561620T-P
HY57V561620T-S
HY57V561620LT-HP
HY57V561620LT-H
HY57V561620LT-8
HY57V561620LT-P
HY57V561620LT-S
133MHz
133MHz
125MHz
100MHz
100MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Normal
4Banks x 4Mbits
x16
LVTTL
400mil 54pin TSOP II
Lower
Power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 1.8 / Apr.01
HY57V561620(L)T
PIN CONFIGURATION
VDD
DQ0
1
2
3
4
5
6
7
8
9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ1
DQ2
V
SSQ
V
DDQ
DQ3
DQ4
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ5 10
DQ6 11
V
12
DQ7 13
14
V
DDQ
DQ8
SSQ
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
V
V
SS
NC
DD
LDQM 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A1 24
A2 25
A3 26
A5
A4
V
SS
V
DD
27
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
CS
Clock Enable
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
A0 ~ A12
Bank Address
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers
Power supply for output buffers
VDDQ/VSSQ
NC
No connection
Revision 1.8 / Apr.01
HY57V561620(L)T
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x16 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Internal Row
Counter
4Mx16 Bank 3
4Mx16 Bank 2
CLK
Row
Pre
Decoders
Row Active
CKE
CS
4Mx16 Bank 1
4Mx16 Bank 0
DQ0
DQ1
RAS
CAS
WE
Memory
Cell
Array
Column
Active
Column
Pre
UDQM
LDQM
Decoders
DQ14
DQ15
Y decoders
Column Add
Counter
Bank Select
A0
A1
Address
Register
Burst
Counter
A12
BA0
BA1
CAS Latency
Pipe Line Control
Mode Registers
Data Out Control
Revision 1.8 / Apr.01
HY57V561620(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
V
VDD, VDDQ
IOS
V
mA
PD
1
W
Soldering Temperature × Time
TSOLDER
260 × 10
°C × Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD, VDDQ
VIH
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 0.3
0.8
V
V
V
1
1,2
1,3
VIL
VSSQ-2.0
Note :
1. All voltages are referenced to VSS = 0V
2. VIH (max) is acceptable 5.6V AC pulse width with £3ns of duration
3. VIL (max) is acceptable -2.0V AC pulse width with £3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
tR / tF
Voutref
CL
ns
V
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
1.4
50
pF
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Revision 1.8 / Apr.01
HY57V561620(L)T
CAPACITANCE (TA=25°C, f=1MHz)
-H
-8/P/S
Unit
Parameter
Pin
Symbol
Min
Max
Min
Max
Input capacitance
CLK
CI1
CI2
2.5
2.5
3.5
3.8
2.5
2.5
4.0
5.0
pF
pF
A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,
WE, UDQM, LDQM
Data input / output capacitance
DQ0 ~ DQ15
CI/O
4.0
6.5
4.0
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
W
RT=250
50pF
Output
Output
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
Output leakage current
Output high voltage
Output low voltage
ILI
-1
-1
2.4
-
1
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -4mA
IOL =+4mA
0.4
V
Note :
1. VIN = 0 to 3.6V, All other pins are not under test = 0V
2. DOUT is disabled, VOUT=0 to 3.6V
Revision 1.8 / Apr.01
HY57V561620(L)T
DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V)
Speed
-8
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
-HP
-H
-P
-S
Burst Length=1, One bank active
tRAS ³ tRAS(min),tRP ³ tRP(min), IO=0mA
Operating Current
IDD1
120
120
110
100
100
1
IDD2P
2
2
CKE £ VIL(max), tCK = min.
CKE £ VIL(max), tCK = ¥
Precharge Standby Current
in power down mode
IDD2PS
CKE ³ VIH(min), CS ³ VIH(min), tCK = min
Input signals are changed one time during 2clks.
All other pins ³ VDD-0.2V or £ 0.2V
IDD2N
20
10
Precharge Standby Current
in non power down mode
mA
mA
CKE ³ VIH(min), tCK = ¥
Input signals are stable.
IDD2NS
IDD3P
3
3
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Active Standby Current
in power down mode
IDD3PS
CKE ³ VIH(min), CS ³ VIH(min), tCK = min
Input signals are changed one time during 2clks.
All other pins ³ VDD-0.2V or £ 0.2V
IDD3N
25
15
Active Standby Current
in non power down mode
mA
mA
CKE ³ VIH(min), tCK = ¥
Input signals are stable
IDD3NS
tCK ³ tCK(min),
tRAS ³ tRAS(min), IO=0mA
All banks active
Burst Mode Operating
Current
IDD4
IDD5
IDD6
150
260
150
260
140
120
250
120
250
1
Auto Refresh Current
Self Refresh Current
tRRC ³ tRRC(min), All banks active
CKE £ 0.2V
260
3
mA
mA
mA
2
3
4
1.5
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V561620T-HP/H/8/P/S
4. HY57V561620LT-HP/H/8/P/S
Revision 1.8 / Apr.01
HY57V561620(L)T
AC CHARACTERISTICS I
-HP
-H
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
7.5
10
2.5
2.5
-
Max
Min
7.5
10
2.5
2.5
-
Max
Min
8
Max
Min
10
10
3
Max
Min
10
12
3
Max
CAS Latency = 3
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock cycle
time
1000
1000
1000
1000
1000
CAS Latency = 2
10
3
Clock high pulse width
Clock low pulse width
-
-
-
-
-
-
-
-
1
1
-
-
3
3
3
CAS Latency = 3
Access time from
5.4
5.4
-
6
6
-
6
6
-
6
6
-
2
clock
CAS Latency = 2
-
6
-
6
-
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
3
3
2
1
2
1
2
1
2
1
1
3
3
3
2
1
2
1
2
1
2
1
1
3
3
tDS
2
-
-
-
1
1
1
1
1
1
1
1
tDH
-
-
1
-
-
-
tAS
-
-
2
-
-
-
tAH
-
-
1
-
-
-
CKE setup time
tCKS
tCKH
tCS
-
-
2
-
-
-
CKE hold time
-
-
1
-
-
-
Command setup time
Command hold time
CLK to data output in low Z-time
-
-
2
-
-
-
tCH
-
-
1
-
-
-
tOLZ
tOHZ3
tOHZ2
-
-
1
-
-
-
CAS Latency = 3
2.7
3
5.4
6
2.7
3
5.4
6
3
6
6
6
6
6
6
CLK to data output
in high Z-time
CAS Latency = 2
3
Note :
1. Assume tR / tF (input rise and fall time ) is 1ns.
2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v
Revision 1.8 / Apr.01
HY57V561620(L)T
AC CHARACTERISTICS II
-HP
-H
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
65
65
20
45
20
15
1
Max
Min
65
65
20
45
20
15
1
Max
Min
68
68
20
48
20
16
1
Max
Min
70
70
20
50
20
20
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
RAS cycle time
tRC
-
-
-
-
-
ns
ns
Auto Refresh
tRRC
tRCD
tRAS
tRP
-
-
-
-
-
RAS to CAS delay
-
-
-
-
-
ns
RAS active time
100K
100K
100K
100K
100K
ns
RAS precharge time
-
-
-
-
-
-
-
-
-
-
ns
RAS to RAS bank active delay
CAS to CAS delay
tRRD
tCCD
tWTL
tDPL
ns
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
Write command to data-in delay
Data-in to precharge command
Data-in to active command
DQM to data-out Hi-Z
DQM to data-in mask
0
-
0
-
0
-
0
-
0
-
2
-
2
-
2
-
2
-
2
-
tDAL
5
-
5
-
5
-
4
-
4
-
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tPDE
tSRE
tREF
2
-
2
-
2
-
2
-
2
-
0
-
0
-
0
-
0
-
0
-
MRS to new command
2
-
2
-
2
-
2
-
2
-
CAS Latency = 3
Precharge to data
3
-
3
-
3
-
3
-
3
-
output Hi-Z
CAS Latency = 2
-
-
-
-
-
-
2
-
2
-
Power down exit time
Self refresh exit time
Refresh Time
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
64
-
64
-
64
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit.
Revision 1.8 / Apr.01
HY57V561620(L)T
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
66MHz and 100MHz Pull-up
100MHz
Min
100MHz
Max
66MHz
Min
Voltage
0
0.5
1
1.5
2
2.5
3
3.5
0
-100
-200
-300
-400
-500
-600
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-2.4
I (mA)
-27.3
0.0
-74.1
-0.7
-7.5
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
Voltage (V)
Ioh Min (100MHz)
Ioh Min (66MHz)
Ioh Min (66 and 100MHz)
IOL Characteristics (Pull-down)
66MHz and 100MHz Pull-down
250
200
150
100
50
100MHz
Min
100MHz
Max
66MHz
Min
Voltage
(V)
0.0
I (mA)
0.0
I (mA)
0.0
I (mA)
0.0
0.4
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
0.65
0.85
1.0
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
1.4
1.5
0
1.65
1.8
0
0.5
1
1.5
2
2.5
3
3.5
Voltage (V)
1.95
3.0
I (mA) 100 min
I (mA) 66 min
I (mA) 100 max
3.45
** IBIS spec. is also applied to 133MHz device.
Revision 1.8 / Apr.01
HY57V561620(L)T
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
I(mA)
20
15
10
5
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Volta ge
I (mA)
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)
I (mA)
- 3
- 2.5
- 2
- 1.5
- 1
- 0.5
0
0
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
- 10
- 20
- 30
- 40
- 50
- 60
Volta ge
0.0
I (mA)
0.0
0.0
Revision 1.8 / Apr.01
HY57V561620(L)T
DEVICE OPERATING OPTION TABLE
HY57V561620(L)T-HP
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
2.7ns
3ns
6ns
3ns
HY57V561620(L)T-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
3CLKs
3CLKs
3CLKs
3CLKs
6CLKs
6CLKs
6CLKs
9CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
6ns
2.7ns
3ns
6ns
3ns
HY57V561620(L)T-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
4CLKs
9CLKs
9CLKs
6CLKs
3CLKs
3CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V561620(L)T-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V561620(L)T-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10.0ns)
83MHz(12.0ns)
66MHz(15.0ns)
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
Revision 1.8 / Apr.01
HY57V561620(L)T
COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
BA
Note
Mode Register Set
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
1
No Operation
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
UDQM, LDQM
Auto Refresh
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
Entry
L
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
H
L
Exit
H
H
L
Entry
Clock
Suspend
H
L
L
X
X
Exit
H
X
Note :
1. OP Code : Operand Code
2. V = Valid, X = Dont’ care, H = Logic High, L= Logic Low, RA = Row Address, CA = Column Address.
Revision 1.8 / Apr.01
HY57V561620(L)T
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
Unit : mm(Inch)
Revision 1.8 / Apr.01
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