HY57V643220DLT-55_技术文档

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

Document Title

4Bank x 512K x 32bits Synchronous DRAM

Revision History

Revision

History

No.

Draft Date

Remark

0.1

0.2

Initial Draft

May. 2004

July 2004

Preliminary

Removed Preliminary

1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF

in AC OPERATING TEST CONDITION

2. Updated the tolerance zone of the leads and the description of the package

type in PACKAGE DIMENSION

0.3

Sep. 2004

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / Sep. 2004

1

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory

applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of

524,228x32.

HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs

and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve

very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

•

Voltage : VDD, VDDQ 3.3V supply voltage

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 Refresh cycles / 64ms

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM 0, 1, 2 and DQM 3

Internal four banks operation

•

ORDERING INFORMATION

Part No.

Clock

Frequency

Organization

Interface

Package

HY57V643220D(L/S)T(P)-45

HY57V643220D(L/S)T(P)-5

HY57V643220D(L/S)T(P)-55

HY57V643220D(L/S)T(P)-6

HY57V643220D(L/S)T(P)-7

222MHz

200MHz

183MHz

166MHz

143MHz

4Banks x 512Kbits

x32

86pin TSOP-II

(Lead Free)

LVTTL

Note

1. HY57V643220DT(P)

2. HY57V643220DLT(P)

Series : Normal Power

Series : Low Power

3. HY57V643220DST(P) Series : Super Low Power

4. HY57V643220D(L/S)T Series : Leaded

5. HY57V643220D(L/S)TP Series : Lead Free

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / Sep. 2004

2

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

86PIN TSOP II CONFIGURATION

1

2

3

86

85

84

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

VDDQ

DQ10

DQ9

VDDQ

DQ8

NC

DQ5

DQ6

VSSQ

DQ7

NC

VSS

DQM1

NC

VDD

DQM0

/WE

/CAS

/RAS

/CS

NC

BA0

BA1

A10/AP

NC

CLK

CKE

A9

A8

A7

A6

86Pin TSOP II

400Mil x 875mil

0.5mm Pin Pitch

67

66

65

20

21

22

A5

A4

A0

A1

A3

DQM3

VSS

NC

A2

DQM2

VDD

NC

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VSSQ

DQ24

VSS

VDDQ

DQ23

VDD

41

42

43

46

45

44

Rev. 0.3 / Sep. 2004

3

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

Pin FUNCTION DESCRIPTIONS

Pin Name

DESCRIPTION

The system clock input. All other inputs are registered to the

SDRAM on the rising edge of CLK.

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will

be one of the states among power down, suspend or self refresh

CKE

CS

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A10

Bank Address

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0~3

Controls output buffers in read mode and masks input data in write

mode

Data Input/Output Mask

DQ0 ~ DQ31

VDD/VSS

Data Input/Output

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

Data Output Power/

Ground

VDDQ/VSSQ

NC

Power supply for output buffers

No connection

No Connection

Rev. 0.3 / Sep. 2004

4

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM

512Kbit x 4banks x 32 I/O Low Power Synchronous DRAM

Internal Row

Counter

Self refresh

logic & timer

512Kx32 BANK 3

512Kx32 BANK 2

512Kx32 BANK 1

512Kx32 BANK 0

CLK

Row

Pre

Decoder

Row Active

CKE

CS

DQ0

RAS

CAS

Refresh

Memory

Cell

Array

Column Active

Column

Pre

WE

Decoder

DQ31

DQM0~3

Y-Decoder

Column Add

Counter

Bank Select

Address

Register

A0

A1

Burst

Counter

Pipe Line

Control

A10

BA1

BA0

CAS Latency

Mode Register

Data Out Control

Rev. 0.3 / Sep. 2004

5

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1

0

BA0

0

A11

0

A10

0

A9

A8

0

A7

0

A6

A5

A4

A3

BT

A2

A1

A0

OP Code

CAS Latency

Burst Length

OP Code

A9

0

Write Mode

Burst Read and Burst Write

Burst Read and Single Write

Burst Type

1

A3

0

Burst Type

Sequential

Interleave

1

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

R e s e r v e d

1

Burst Length

A2

A1

A0

A3 = 0

A3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

4

8

0

1

0

2

0

1

3

4

1

0

Reserved

R e s e r v e d

Reserved

8

1

0

1

Reserved

Full Page

Reserved

1

0

1

Rev. 0.3 / Sep. 2004

6

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

ABSOLUTE MAXIMUM RATING

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

-40 ~ 85

^oC

V

Storage Temperature

TSTG

VIN, VOUT

VDD

-55 ~ 125

-1.0 ~ 4.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Short Circuit Output Current

Power Dissipation

V

VDDQ

IOS

V

mA

W

PD

1

Soldering Temperature ^.Time

260 ^.10

^oC ^.Sec

TSOLDER

DC OPERATING CONDITION (TA= -40 to 85^oC )

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

Typ

3.3

-

Max

Unit

Note

1

3.6

VDDQ+0.3

0.8

V

2.0

1, 2

1, 3

VIL

-0.3

Note : 1. All voltages are referenced to VSS = 0V

2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration

AC OPERATING TEST CONDITION (TA= -40 to 85 ^oC, VDD=3.3±0.3V, VSS=0V)

Parameter

AC Input High/Low Level Voltage

Symbol

VIH / VIL

Vtrip

Value

2.4/0.4

1.4

Unit

Note

V

Input Timing Measurement Reference Level Voltage

Input Rise/Fall Time

tR / tF

Voutref

CL

1

ns

V

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

1.4

30

pF

o

CAPACITANCE (TA= -40 to 85 C, f=1MHz, VDD=3.3V)

Parameter

Symbol

Min

Max

Unit

CLK

CI1

2.5

3.5

pF

Input capacitance

A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE,

DQM 0~3

CI2

2.5

4

3.8

6.5

pF

Data input / output capacitance

DQ0 ~ DQ31

CI/O

Rev. 0.3 / Sep. 2004

7

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

Note 1.

Vtt=1.4V

RT=500 Ω

RT=50 Ω

Output

Z0 = 50Ω

Output

30pF

DC Output Load Circuit

AC Output Load Circuit

o

DC CHARACTERRISTICS I (TA= 0 to 70 C)

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

ILO

-1

2.4

-

1

uA

V

1

2

IOH = -2mA

IOL = +2mA

VOH

VOL

-

0.4

V

Note :

1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Rev. 0.3 / Sep. 2004

8

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

o

DC CHARACTERISTICS II (TA= 0 to 70 C)

Speed

55

Sym-

bol

Parameter

Test Condition

Unit Note

45

5

6

7

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA

Operating Current

IDD1

220 200 190 180 170 mA

1

Precharge Standby Cur- IDD2P CKE ≤ VIL(max), tCK = 15ns

2

mA

rent

IDD2PS CKE ≤ VIL(max), tCK = ∞

in Power Down Mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= 15ns

Precharge Standby Cur-

rent

in Non Power Down

Mode

IDD2N Input signals are changed one time

during 2clks.

17

mA

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

IDD2NS

12

Input signals are stable.

IDD3P CKE ≤ VIL(max), tCK = 15ns

IDD3PS CKE ≤ VIL(max), tCK = ∞

3

Active Standby Current

in Power Down Mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= 15ns

IDD3N Input signals are changed one time

during 2clks.

40

30

Active Standby Current

in Non Power Down

Mode

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

IDD3NS

Input signals are stable.

Burst Mode Operating

Current

tCK ≥ tCK(min), IOL=0mA

IDD4

IDD5

CL=3

290 280 260 240 210 mA

260 250 235 220 210 mA

1

All banks active

tRC ≥ tRC(min), All banks active

Normal

Auto Refresh Current

2

3

4

2

mA

Low Power

0.8

Self Refresh Current

IDD6

CKE ≤ 0.2V

Super Low

Power

450

uA

5

Note :

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY57V643220DT(P) Series

4. HY57V643220DLT(P) Series

5. HY57V643220DST(P) Series

Rev. 0.3 / Sep. 2004

9

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

45

5

55

6

7

Parameter

Symbol

Unit Note

Min Max Min Max Min Max Min Max Min Max

CAS

Latency=3

tCK3

tCK2

4.5

10

5.0

10

5.5

10

6.0

10

7.0

10

ns

System Clock

Cycle Time

1000

CAS

Latency=2

Clock High Pulse Width

Clock Low Pulse Width

CAS

tCHW

tCLW

1.75

-

2.0

-

2.25

-

2.5

-

3.0

-

ns

1

tAC3

tAC2

-

4.5

6.0

-

4.5

6.0

-

5.0

6.0

-

5.5

6.0

-

5.5

6.0

ns

Latency=3

Access Time

From Clock

2

CAS

Latency=2

Data-out Hold Time

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

CKE Setup Time

tOH

tDS

tDH

tAS

1.5

1.3

0.8

1.3

0.8

1.3

0.8

1.3

0.8

-

1.5

1.0

1.5

1.0

1.5

1.0

1.5

1.0

-

2.0

1.5

1.0

1.5

1.0

1.5

1.0

1.5

1.0

-

2.0

1.5

1.0

1.5

1.0

1.5

1.0

1.5

1.0

-

2.0

1.75

1.0

-

ns

1

1.75

1.0

tAH

tCKS

tCKH

tCS

1.75

1.0

CKE Hold Time

Command Setup Time

Command Hold Time

1.75

1.0

tCH

CLK to Data Output in

Low-Z Time

tOLZ

1.0

-

1.0

-

1.0

-

1.0

-

1.0

-

ns

CAS

Latency=3

tOHZ3

tOHZ2

-

4.0

6.0

-

4.5

6.0

-

5.0

6.0

-

5.5

6.0

-

5.5

6.0

CLK to

Data Output

in High-Z Time

CAS

Latency=2

Note :

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns,

then (tR/2-0.5)ns should be added to the parameter.

Rev. 0.3 / Sep. 2004

10

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

45

5

55

6

7

Sym-

bol

Parameter

Unit Note

Min Max Min Max Min Max Min Max Min Max

RAS

Cycle Time

Operation

tRC

58.5

-

55

-

55

-

60

-

63

-

ns

RAS

Cycle Time

Auto Refresh

tRRC

58.5

18

-

55

15

-

55

-

60

18

-

63

20

-

ns

RAS to CAS Delay

RAS Active Time

tRCD

tRAS

tRP

16.5

40.5 100K 38.7 100K 38.7 100K 42 100K 42 100K ns

RAS Precharge Time

18

9

-

15

10

1

-

16.5

11

1

-

18

12

1

-

20

14

1

-

ns

RAS to RAS Bank Active

Delay

tRRD

tCCD

tWTL

CAS to CAS Delay

1

CLK

Write Command to

Data-In Delay

0

Data-in to Precharge

Command

tDPL

TBD

-

TBD

-

TBD

-

1

-

1

-

CLK

Data-In to Active Command

DQM to Data-Out Hi-Z

DQM to Data-In Mask

MRS to New Command

CAS

tDAL

tDQZ

tDQM

tMRD

tDPL + tRP

2

0

2

-

2

0

2

-

2

0

2

-

2

0

2

-

2

0

2

-

CLK

tPROZ3

tPROZ2

3

-

3

2

-

3

2

-

3

2

-

3

2

-

CLK

Precharge to

Data Output

High-Z

Latency=3

CAS

Latency=2

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tDPE

tSRE

tREF

1

-

1

-

1

-

1

-

1

-

CLK

ms

1

64

Note :

1. A new command can be given tRC after self refresh exit.

Rev. 0.3 / Sep. 2004

11

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

COMMAND TRUTH TABLE

Command

CKEn-1

CKEn

CS

L

RAS

CAS

L

WE

L

DQM

ADDR

A10/AP

BA

Note

Mode Register Set

H

X

L

X

H

L

X

OP code

H

L

X

No Operation

X

H

Bank Active

L

H

RA

V

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

L

X

V

X

L

H

L

H

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

X

A9 ball High

MRS

Mode

Burst-Read-Single-WRITE

H

L

X

(Other balls OP code)

Entry

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

Self Refresh¹

Exit

X

L

H

L

H

L

X

H

L

Entry

Precharge

power down

X

H

L

Exit

H

L

Entry

Clock

Suspend

H

L

X

Exit

H

X

Rev. 0.3 / Sep. 2004

12

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

PACKAGE INFORMATION

JEDEC STANDARD 400mil 86pin TSOP-II with 0.5mm pin pitch

Unit : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.21(0.008)

0.18(0.007)

0.597(0.0235) 0.210(0.0083)

0.50(0.0197)

0.05

0.120(0.0047)

0.406(0.0160)

0.05 M

Rev. 0.3 / Sep. 2004

13


型号：	HY57V643220DLT-55
厂家：	HYNIX SEMICONDUCTOR
描述：	4Banks x 512K x 32bits Synchronous DRAM 4Banks X 512K X 32位同步DRAM 动态存储器
文件：	总13页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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