HY57V653220BTC-8_技术文档

HY57V653220B

4 Banks x 512K x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications

which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.

HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V653220BTC-5

HY57V653220BTC-55

HY57V653220BTC-6

HY57V653220BTC-7

HY57V653220BTC-8

HY57V653220BTC-10P

HY57V653220BTC-10

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

4Banks x 512Kbits

x32

Normal

LVTTL

400mil 86pin TSOP II

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev.1.6/Dec. 01

1

HY57V653220B

PIN CONFIGURATION

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

1

VSS

2

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

VDD

VSS

DQM 0

/W E

DQM 1

NC

/CAS

/RAS

/CS

NC

CLK

CKE

A9

86pin TSO P II

400m il x 875m il

0.5m m pin pitch

NC

BA0

A8

BA1

A7

A10/AP

A0

A6

A5

A1

A4

A2

A3

DQM 2

VDD

DQM 3

VSS

NC

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

CS

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A10

Bank Address

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0~3

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

NC

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuits and input buffers

Power supply for output buffers

No connection

Rev.1.6/Dec. 01

2

HY57V653220B

FUNCTIONAL BLOCK DIAGRAM

512Kbit x 4banks x 32 I/O Synchronous DRAM

Self Refresh Logic

& Timer

Internal Row

Counter

512Kx32 Bank 3

512Kx32 Bank 2

CLK

Row

Pre

Row Active

CKE

CS

Decoders

512Kx32 Bank 1

512Kx32 Bank 0

DQ0

DQ1

RAS

CAS

Memory

Cell

Array

WE

Column

Active

Column

Pre

DQM0

DQM1

DQM2

DQM3

Decoders

DQ30

DQ31

Y decoders

Column Add

Counter

Bank Select

A0

A1

Address

Register

Burst

Counter

A10

BA0

BA1

CAS Latency

Pipe Line Control

Mode Registers

Data Out Control

Rev.1.6/Dec. 01

3

HY57V653220B

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

50

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

V

VDD, VDDQ

IOS

V

mA

PD

1

W

Soldering Temperature Time

TSOLDER

260 10

°C Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION ^{(TA=0 to 70°C)}

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input high voltage

Input low voltage

VDD, VDDQ

VIH

3.0

2.0

3.3

3.0

0

3.6

VDDQ + 0.3

0.8

V

1,2

1,3

1,4

VIL

VSSQ - 0.3

Note :

1.All voltages are referenced to VSS = 0V

2.VDD/VDDQ(min) is 3.15V for HY57V653220BTC-5/55/6

3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes

4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes

AC OPERATING CONDITION ^{(TA=0 to 70°C, 3.0V ≤V}DD ≤3.6V, VSS=0V - Note1)

Parameter

Symbol

Value

Unit

Note

AC input high / low level voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

1

V

Input timing measurement reference level voltage

Input rise / fall time

tR / tF

Voutref

CL

ns

V

Output timing measurement reference level

Output load capacitance for access time measurement

1.4

30

pF

2

Note :

1.3.15V ≤VDD ≤3.6V is applied for HY57V653220BC-5/55/6

2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)

For details, refer to AC/DC output load circuit

Rev.1.6/Dec. 01

4

HY57V653220B

CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V)

Parameter

Symbol

Min

Max

Unit

Input capacitance

CLK

CI1

CI2

2.5

4

5

pF

A0 ~ A10, BA0, BA1, CKE, CS, RAS,

CAS, WE, DQM0~3

Data input / output capacitance

DQ0 ~ DQ31

CI/O

4

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=500 Ω

RT=50 Ω

Output

Z0 = 50Ω

Output

30pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I ^{(DC operating conditions unless otherwise noted)}

Parameter

Symbol

Min.

Max

Unit

Note

Input leakage current

Output leakage current

Output high voltage

Output low voltage

ILI

-1

-1.5

2.4

-

1

1.5

-

uA

V

1

2

ILO

VOH

VOL

IOH = -2mA

IOL = +2mA

0.4

V

Note :

1.VIN = 0 to 3.6V, All other pins are not under test = 0V

2.DOUT is disabled, VOUT=0 to 3.6V

Rev.1.6/Dec. 01

5

HY57V653220B

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Speed

-7

Not

Parameter

Symbol

Test Condition

Unit

e

-5

-55

-6

-8

-10P

-10

Burst Length=1, One bank active

tRAS ≥ tRAS(min), tRP ≥ tRP(min),

IOL=0mA

Operating Current

IDD1

200

190

180

170

150

mA

1

IDD2P

2

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

Precharge Standby

Current

in power down mode

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

IDD2N

15

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

Precharge Standby

Current

mA

in non power down mode

CKE ≥ VIH(min), tCK = ∞

IDD2NS

10

Input signals are stable.

IDD3P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

3

Active Standby Current

in power down mode

mA

IDD3PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

IDD3N

40

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

Active Standby Current

in non power down mode

CKE ≥ VIH(min), tCK = ∞

IDD3NS

IDD4

25

Input signals are stable

CL=3

CL=2

280

160

250

260

160

235

240

160

220

210

160

210

2

180

160

190

180

160

190

160

140

190

tCK ≥ tCK(min),

Burst Mode Operating

Current

tRAS ≥ tRAS(min), IOL=0mA

All banks active

1

2

Auto Refresh Current

Self Refresh Current

IDD5

IDD6

tRRC ≥ tRRC(min), All banks active

CKE ≤ 0.2V

mA

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

Rev.1.6/Dec. 01

6

HY57V653220B

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-5

-55

-6

-7

-8

-10P

-10

Parameter

Symbol

Unit Note

Min

5

Max

Min

5.5

10

2.25

-

Max

Min

6

Max

Min

Max

Min

8

10

3

-

Max

Min

10

3

Max

Min

10

12

3.5

-

Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

7

ns

System clock

cycle time

1000

10

2

10

2.5

-

10

Clock high pulse width

Clock low pulse width

tCHW

tCLW

-

3

-

ns

1

2

-

3

-

3

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

-

4.5

5

6

-

5.5

-

5.5

6

-

6

-

6

-

Access time from

clock

2

-

6

-

6

-

6

-

Data-out hold time

1.5

1

-

2

-

2

-

2

1

2

1

2

1

2

1

-

2

3

1

Data-Input setup time

Data-Input hold time

Address setup time

Address hold time

tDS

-

1.5

1

-

1.5

1

1.75

-

2

-

2.5

1

-

tDH

tAS

-

1

-

1

-

1.5

1

-

1.5

1

-

1.5

1

-

1.75

-

2

-

2.5

1

-

tAH

-

1

-

1

-

CKE setup time

tCKS

tCKH

tCS

1.5

1

1.5

1

-

1.5

1

-

1.75

-

2

-

2.5

1

-

CKE hold time

-

1

-

1

-

Command setup time

Command hold time

CLK to data output in low Z-time

1.5

1

-

1.5

1

-

1.5

1

-

1.75

-

2

-

2.5

1

-

tCH

tOLZ

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

-

4.5

6

-

5

6

-

5.5

6

5.5

6

-

6

-

6

CLK to data

output in high Z-

time

-

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

3.Data-out hold time to be measured under 30pF load condition, without Vt termination

Rev.1.6/Dec. 01

7

HY57V653220B

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

-5

-55

-6

-7

-8

-10P

-10

Parameter

Symbol

Unit Note

Min

55

15

40

15

10

1

Max

Min

55

Max

Min

60

18

42

18

12

1

Max

Min

63

20

42

20

14

1

Max

Min

68

20

48

20

16

1

Max

Min

70

20

50

20

1

Max

Min

70

20

50

20

1

Max

Operation

Auto Refresh

tRC

-

ns

RAS cycle time

tRRC

tRCD

tRAS

tRP

55

-

RAS to CAS delay

RAS active time

16.5

-

ns

100K 38.5 100K

100K

ns

RAS precharge time

-

16.5

11

1

-

ns

RAS to RAS bank active delay

CAS to CAS delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

ns

CLK

Write command to data-in delay

Data-in to precharge command

Data-in to active command

DQM to data-out Hi-Z

0

1

4

2

DQM to data-in mask

0

MRS to new command

CAS Latency =

2

tPROZ3

tPROZ2

3

2

-

3

2

-

3

2

-

3

2

-

3

2

-

3

2

-

3

2

-

CLK

3

Precharge to

data output Hi-Z

CAS Latency =

CLK

2

Power down exit time

Self refresh exit time

Refresh Time

tPDE

tSRE

tREF

1

-

1

-

1

-

1

-

1

-

1

-

1

-

CLK

ms

1

64

Note :

1. A new command can be given tRRC after self refresh exit

Rev.1.6/Dec. 01

8

HY57V653220B

DEVICE OPERATING OPTION TABLE

HY57V653220B-5

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

200MHz(5ns)

183MHz(5.5ns)

166MHz(6ns)

3CLKs

8CLKs

7CLKs

11CLKs

10CLKs

3CLKs

4.5ns

5ns

5.5ns

1.5ns

2ns

HY57V653220B-55

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

183MHz(5.5ns)

166MHz(6ns)

143MHz(7ns)

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5ns

5.5ns

2ns

HY57V653220B-6

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

166MHz(6ns)

143MHz(7ns)

125MHz(8ns)

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5.5ns

6ns

2ns

2.5ns

HY57V653220B-7

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

143MHz(7ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.5ns

6ns

2ns

2.5ns

HY57V653220B-8

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

100MHz(10ns)

83MHz(12ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

4CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

6ns

2.5ns

HY57V653220B-10P

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

2.5ns

Rev.1.6/Dec. 01

9

HY57V653220B

HY57V653220B-10

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

3CLKs

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

2.5ns

Rev.1.6/Dec. 01

10

HY57V653220B

COMMAND TRUTH TABLE

A10/

ADDR

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

Note

AP

Mode Register Set

H

X

L

H

L

X

H

L

X

H

L

X

H

X

OP code

No Operation

X

Bank Active

L

RA

V

Read

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

L

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

X

V

X

L

H

L

H

X

L

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

A9 Pin High

(Other Pins OP code)

Burst-READ-Single-WRITE

Entry

H

L

X

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

1

X

Self Refresh

Exit

L

H

L

H

L

X

H

L

Entry

Precharge power

down

X

H

L

Exit

H

L

Entry

Clock

Suspend

Exit

H

L

X

H

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

Rev.1.6/Dec. 01

11

HY57V653220B

PACKAGE INFORMATION

400mil 86pin Thin Small Outline Package

Unit : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

1.194(0.0470)

0.991(0.0390)

0.050(0.0020)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.21(0.008)

0.18(0.007)

0.50(0.0197)

Rev.1.6/Dec. 01

12


型号：	HY57V653220BTC-8
厂家：	HYNIX SEMICONDUCTOR
描述：	4 Banks x 512K x 32Bit Synchronous DRAM 4银行X 512K X 32位同步DRAM 动态存储器
文件：	总12页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V653220BTC-8 [HYNIX]

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