HY5DU113222FM-22_技术文档

HY5DU113222FM(P)

512M(16Mx32) GDDR SDRAM

HY5DU113222FM(P)

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-

sibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Oct. 2004

1

HY5DU113222FM(P)

Revision History

Revision No.

History

Draft Date Remark

0.1

1) Defined target spec.

Oct. 2004

Rev. 0.1 / Oct. 2004

2

HY5DU113222FM(P)

Preliminary

DESCRIPTION

The Hynix HY5DU113222FM(P) is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM which consists

of two 256Mbit(x32) - Multi-chip-, ideally suited for the point-to-point applications which requires high bandwidth.

The Hynix 16Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

•

The Hynix HY5DU113222FM(P) guarantee until

200MHz speed at DLL_off condition

•

Data(DQ) and Write masks(DM) latched on the both

rising and falling edges of the data strobe

•

2.5V VDD and VDDQ wide range max power supply

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

All inputs and outputs are compatible with SSTL_2

interface

•

Write mask byte controls by DM (DM0 ~ DM3)

Programmable /CAS Latency 5 / 4 supported

•

12mm x 12mm, 144ball FBGA with 0.8mm pin pitch

Fully differential clock inputs (CK, /CK) operation

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

The signals of Chip select control the each chip with

CS0 and CS1, individually.

•

Internal 4 bank operations with single pulsed /RAS

tRAS Lock-Out function supported

•

Double data rate interface

Source synchronous - data transaction aligned to

bidirectional data strobe (DQS0 ~ DQS3)

Auto refresh and self refresh supported

4096 refresh cycles / 32ms

•

Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

(Both chips do refresh operation, simultaneously)

•

Half strength and Matched Impedance driver option

controlled by EMRS

ORDERING INFORMATION

Clock

Frequency

Max Data

Rate

Part No.

Power Supply

interface

Package

HY5DU113222FM(P)-2

HY5DU113222FM(P)-22

HY5DU113222FM(P)-25

HY5DU113222FM(P)-28

HY5DU113222FM(P)-33

HY5DU113222FM(P)-36

HY5DU113222FM(P)-4

500MHz

450MHz

400MHz

350MHz

300MHz

275MHz

250MHz

1000Mbps/pin

900Mbps/pin

800Mbps/pin

700Mbps/pin

600Mbps/pin

550Mbps/pin

500Mbps/pin

12mmx12mm

144Ball FBGA

VDD 2.5V

SSTL_2

VDDQ 2.5V

Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.

We'll add "P" character after "FM" for lead free product. For example, the part number of 300MHz Lead free

product is HY5DU113222FM(P) - 33.

Rev. 0.1 / Oct. 2004

3

HY5DU113222FM(P)

PIN CONFIGURATION (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

DQS0

DQ4

DM0

VDDQ

DQ5

VSSQ

NC

DQ3

VDDQ

VSSQ

VSS

DQ2

DQ1

DQ0

VDDQ

VDD

VSS

DQ31

VDDQ

VDD

DQ29

DQ30

VSSQ

DQ28

VDDQ

VSSQ

VSS

VSSQ

NC

DM3

VDDQ

DQ26

VDDQ

DQ15

DQ13

DM1

DQ11

DQ9

DQS3

DQ27

DQ25

DQ24

DQ14

DQ12

DQS1

DQ10

DQ8

DQ6

VSSQ

VDD

VSSQ

VDD

DQ7

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

/WE

NC

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

F

DQ17

DQ19

DQS2

DQ21

DQ22

/CAS

/RAS

/CS0

VDDQ

NC

VSSQ

VSS

VSSQ

VSS

VDDQ

NC

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

G

H

J

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VDDQ

VDD

VDDQ

VDD

K

L

VSS

A10

A2

VSS

VDD

A11

A3

VSS

VDD

A9

VSS

NC2

A5

NC

M

N

P

/CS1

BA0

BA1

NC3

CLK

/CLK

CKE

NC

A0

A1

A4

A6

A7

A8/AP

VREF

Note :

1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.

2. Ball L9(NC2) is reserved for A12.

3. Ball M10(NC3) is reserved for BA2.

ROW and COLUMN ADDRESS TABLE

Items

16Mx32

Organization

Row Address

2M x 32 x 4banks x 2chip

A0 ~ A11

A0 ~ A7, A9

BA0, BA1

A8

Column Address

Bank Address

Auto Precharge Flag

Refresh

4K

Chip Selection

CS0, CS1

Note:

1. 16Mx32 DDR is composed of two 8Mx32 DDR.

2. Multi-chip(16Mx32 DDR) is controlled by CS0 and CS1, individually.

Rev. 0.1 / Oct. 2004

4

HY5DU113222FM(P)

PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CK, /CK

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

CKE

Input

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS0 or CS1 is registered high. CS0 or CS1 provides for external

bank selection on systems with multiple banks. CS0 and CS1 are considered part of the

command code. When it is the operationg state of MRS, Power up sequence, EMRS, it

should be enabled in pairs. Except this case, it can be operated, individually.

/CS0, /CS1

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

A0 ~ A11

Input

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

/RAS, /CAS, /WE

DM0 ~ DM3

Input

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

D Q S 0 ~ D Q S 3

I / O

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

VREF

I/O

Data input / output pin : Data Bus

Supply

NC

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

NC

Rev. 0.1 / Oct. 2004

5

HY5DU113222FM(P)

FUNCTIONAL BLOCK DIAGRAM

(4Banks x 2Mbit x 32 I/O) x 2Chips Double Data Rate Synchronous DRAM

32

Write Data Register

2-bit Prefetch Unit

DS

64

CLK

Bank

Control

2Mx32/Bank0

CLK

/CLK

CKE

DQ[0:31]

2Mx32/Bank1

2Mx32/Bank2

CKE

CS1

64

32

CS0

/RAS

/CAS

/WE

/RAS

/CAS

2Mx32/Bank3

/WE

DM(0~3)

Mode

Register

Row

Decoder

Column

Decoder

Data Strobe

Transmitter

CLK_DLL

DS

Column

Address

Counter

DQS(0~3)

A0~A11

Data Strobe

Receiver

A0~A11

BA0,BA1

Mode Register

CLK, /CLK

BA0,BA1

DLL

Block

Rev. 0.1 / Oct. 2004

6

HY5DU113222FM(P)

SIMPLIFIED COMMAND TRUTH TABLE

CS0/

CS1

A8/

AP

Command

CKEn-1

CKEn

RAS

CAS

WE

ADDR

BA

Note

Extended Mode Register Set

Mode Register Set

Device Deselect

No Operation

H

X

L

OP code

1,2,6

H

L

X

H

L

X

H

X

H

X

1

Bank Active

L

RA

V

1

1,7

1,3,7

1,7

1,4,7

1,5

1

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Read Burst Stop

Auto Refresh

H

L

X

V

H

L

H

X

H

L

H

L

H

L

H

X

H

X

H

X

H

X

V

X

1

Entry

L

1,6

Self Refresh

Exit

H

L

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

L

H

L

H

L

1,6

H

L

1,6

Entry

Precharge Power

Down Mode

H

L

Exit

H

L

Entry

H

L

Active Power

Down Mode

Exit

H

X

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

6. Both of CS0 & CS1 should be enabled simultaneously.

Rev. 0.1 / Oct. 2004

7

HY5DU113222FM(P)

WRITE MASK TRUTH TABLE

/CS0, /CS1, /RAS,

/CAS, /WE

A8/

AP

ADDR

Note

Function

Data Write

CKEn-1

CKEn

DM(0~3)

BA

H

X

L

X

1,2

Data-In Mask

H

Note :

1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data.

2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23;

DM3 corresponds to the data on DQ24-Q31.

Rev. 0.1 / Oct. 2004

8

HY5DU113222FM(P)

OPERATION COMMAND TRUTH TABLE - I

Current

State

/CS0

/CS1

/RAS

/CAS

/WE

Address

Command

Action

NOP or power down³

ILLEGAL⁴

H

L

X

H

X

H

L

X

H

L

X

DSEL

NOP

X

BST

ILLEGAL⁴

H

BA, CA, AP

READ/READAP

IDLE

ILLEGAL⁴

Row Activation

NOP

L

H

L

H

L

H

L

H

L

BA, CA, AP

WRITE/WRITEAP

ACT

BA, RA

L

BA, AP

PRE/PALL

AREF/SREF

MRS *12

DSEL

Auto Refresh or Self Refresh⁵

L

H

L

X

L

OPCODE

Mode Register Set

X

H

X

H

X

H

L

X

NOP

ILLEGAL⁴

Begin read : optional AP⁶

Begin write : optional AP⁶

ILLEGAL⁴

BST

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

READ/READAP*13

WRITE/WRITEAP*13

ACT

ROW

ACTIVE

H

L

H

L

Precharge⁷

L

PRE/PALL

ILLEGAL¹¹

L

H

AREF/SREF

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

X

Continue burst to end

Terminate burst

X

NOP

BST

Term burst, new read:optional AP⁸

ILLEGAL

H

L

BA, CA, AP

BA, RA

BA, AP

X

READ/READAP*13

WRITE/WRITEAP

ACT

L

READ

ILLEGAL⁴

H

L

H

L

PRE/PALL

AREF/SREF

Term burst, precharge

ILLEGAL¹¹

L

H

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

NOP

BST

X

Continue burst to end

L

WRITE

ILLEGAL⁴

Term burst, new read:optional AP⁸

Term burst, new write:optional AP

L

H

L

H

L

BA, CA, AP

READ/READAP*13

WRITE/WRITEAP*13

Rev. 0.1 / Oct. 2004

9

HY5DU113222FM(P)

OPERATION COMMAND TRUTH TABLE - II

Current

State

/CS0

/CS1

/RAS

/CAS

/WE

Address

Command

Action

ILLEGAL⁴

L

H

L

H

L

BA, RA

BA, AP

X

ACT

PRE/PALL

AREF/SREF

Term burst, precharge

WRITE

ILLEGAL¹¹

H

ILLEGAL¹¹

Continue burst to end

ILLEGAL

L

H

L

X

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

X

H

X

NOP

L

BST

ILLEGAL¹⁰

ILLEGAL^4,10

ILLEGAL¹¹

L

H

BA, CA, AP

READ/READAP

READ

WITH

AUTOPRE-

CHARGE

L

H

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

WRITE/WRITEAP

ACT

PRE/PALL

AREF/SREF

H

ILLEGAL¹¹

Continue burst to end

ILLEGAL

L

H

L

X

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

X

H

X

NOP

L

BST

ILLEGAL¹⁰

ILLEGAL^4,10

ILLEGAL¹¹

L

H

BA, CA, AP

READ/READAP

WRITE

AUTOPRE-

CHARGE

L

H

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

WRITE/WRITEAP

ACT

PRE/PALL

AREF/SREF

H

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

NOP

BST

X

NOP-Enter IDLE after tRP

ILLEGAL⁴

ILLEGAL^4,10

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

READ/READAP

WRITE/WRITEAP

ACT

PRE-

CHARGE

ILLEGAL^4,10

H

L

H

L

PRE/PALL

AREF/SREF

MRS

NOP-Enter IDLE after tRP

ILLEGAL¹¹

L

H

L

X

L

OPCODE

Rev. 0.1 / Oct. 2004

10

HY5DU113222FM(P)

OPERATION COMMAND TRUTH TABLE - III

Current

State

/CS0

/CS1

/RAS

/CAS

/WE

Address

Command

Action

H

L

X

H

X

H

X

H

L

X

DSEL

NOP

BST

NOP - Enter ROW ACT after tRCD

ILLEGAL⁴

ILLEGAL^4,10

ILLEGAL^4,9,10

ILLEGAL^4,10

ILLEGAL¹¹

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

READ/READAP

WRITE/WRITEAP

ACT

ROW

ACTIVATING

H

L

H

L

PRE/PALL

L

H

AREF/SREF

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

X

NOP - Enter ROW ACT after tWR

NOP

ILLEGAL⁴

ILLEGAL

X

BST

H

L

BA, CA, AP

BA, RA

READ/READAP

WRITE/WRITEAP

ACT

WRITE

RECOVERING

L

ILLEGAL^4,10

ILLEGAL^4,11

ILLEGAL¹¹

H

L

H

L

BA, AP

X

PRE/PALL

H

AREF/SREF

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

NOP

BST

X

NOP - Enter precharge after tDPL

ILLEGAL⁴

ILLEGAL^4,8,10

ILLEGAL^4,10

ILLEGAL^4,11

ILLEGAL¹¹

L

WRITE

RECOVERING

WITH

AUTOPRE-

CHARGE

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

READ/READAP

WRITE/WRITEAP

ACT

H

L

H

L

PRE/PALL

L

H

AREF/SREF

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

NOP

BST

X

NOP - Enter IDLE after tRC

REFRESHING

ILLEGAL¹¹

L

H

L

H

BA, CA, AP

READ/READAP

Rev. 0.1 / Oct. 2004

11

HY5DU113222FM(P)

OPERATION COMMAND TRUTH TABLE - IV

Current

State

/CS0

/CS1

/RAS

/CAS

/WE

Address

Command

Action

ILLEGAL¹¹

L

H

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

X

WRITE/WRITEAP

ACT

WRITE

PRE/PALL

AREF/SREF

H

ILLEGAL¹¹

L

H

L

X

H

L

X

H

L

X

H

L

OPCODE

MRS

DSEL

NOP

BST

X

NOP - Enter IDLE after tMRD

ILLEGAL¹¹

L

H

L

H

L

BA, CA, AP

BA, RA

BA, AP

READ/READAP

WRITE/WRITEAP

ACT

MODE

REGISTER

ACCESSING

H

L

H

L

PRE/PALL

AREF/SREF

MRS

L

H

L

X

L

OPCODE

Note :

1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,

BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.

2. All entries assume that CKE was active(high level) during the preceding clock cycle.

3. If both banks are idle and CKE is inactive(low level), then in power down mode.

4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of

that bank.

5. If both banks are idle and CKE is inactive(low level), then self refresh mode.

6. Illegal if tRCD is not met.

7. Illegal if tRAS is not met.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Illegal if tRRD is not met.

10. Illegal for single bank, but legal for other banks in multi-bank devices.

11. Illegal for all banks.

12. Both of CS0 & CS1 should be enabled in pairs.

13. One of CS0 & CS1 should be enabled, individually.

Rev. 0.1 / Oct. 2004

12

HY5DU113222FM(P)

CKE FUNCTION TRUTH TABLE

Current

State

CKEn-

1

/CS0

/CS1

CKEn

/RAS

/CAS

/WE

/ADD

Action

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

INVALID

Exit self refresh, enter idle after tSREX*

ILLEGAL

L

SELF

REFRESH¹

L

X

H

L

ILLEGAL

L

X

H

L

ILLEGAL

L

X

H

L

X

H

L

NOP, continue self refresh

INVALID

H

L

X

H

L

Exit power down, enter idle*

ILLEGAL

L

POWER

DOWN²

L

X

H

X

H

L

ILLEGAL

L

X

L

ILLEGAL

L

X

L

X

L

NOP, continue power down mode

See operation command truth table

Enter self refresh*

Exit power down*

ILLEGAL

H

L

H

L

H

L

X

H

L

X

H

L

ALL BANKS

IDLE⁴

L

X

L

ILLEGAL

L

H

L

ILLEGAL

L

ILLEGAL

L

X

NOP

H

L

H

L

See operation command truth table

ANY STATE

OTHER

THAN

ILLEGAL⁵

INVALID

H

L

ABOVE

L

Note :

When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.

1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.

2. All command can be stored after 2 clocks from low to high transition of CKE.

3. Illegal if CK is suspended or stopped during the power down mode.

4. Self refresh can be entered only from the all banks idle state.

5. Disabling CK may cause malfunction of any bank which is in active state.

6. * Both CSO & CSI should be emabled, simultaneouly.

Rev. 0.1 / Oct. 2004

13

HY5DU113222FM(P)

SIMPLIFIED STATE DIAGRAM

MRS

SREF

SREX

MODE

SELF

REFRESH

REGISTER

SET

IDLE

*1

PDEN

PDEX

AREF

ACT

POWER

DOWN

AUTO

REFRESH

POWER

DOWN

PDEN

BST

PDEX

BANK

ACTIVE

READ

READAP

WRITE

READ

*2

WRITE

WITH

AUTOPRE-

CHARGE

READ

WITH

*2

READAP

WRITE

*2

READ

*2

AUTOPRE-

CHARGE

WRITEAP

WRITE

PRE(PALL)

PRE-

CHARGE

Command Input

POWER-UP

Automatic Sequence

POWER APPLIED

Note:

*1.Both of CS0 and CS1 should be enabled in pairs.

*2.Both of CS0 and CS1 should be enabled, individually.

Rev. 0.1 / Oct. 2004

14

HY5DU113222FM(P)

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is

applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS

LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,

where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-

ages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable com-

mand.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-

ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting

the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.

No power sequencing is specified during power up or power down given the following cirteria :

• VDD and VDDQ are driven from a single power converter output.

• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).

• VREF tracks VDDQ/2.

• A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the

input current from the VTT supply into any pin.

If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must

be adhered to during power up :

Voltage description

Sequencing

Voltage relationship to avoid latch-up

< VDD + 0.3V

VDDQ

VTT

After or with VDD

After or with VDDQ

< VDDQ + 0.3V

VREF

< VDDQ + 0.3V

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles(tXSRD) of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

Rev. 0.1 / Oct. 2004

15

HY5DU113222FM(P)

7. Issue 2 or more Auto Refresh commands.

8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Power-Up Sequence

VDD

VDDQ

tVTD

VTT

VREF

/CLK

CLK

tIS tIH

LVCMOS Low Level

CKE

NOP

PRE

EMRS

MRS

NOP

PRE

AREF

MRS

ACT

RD

CMD

DM

CODE

ADDR

A10

CODE

BA0, BA1

DQS

DQ'S

T=200usec

tRP

tMRD

tRP

tRFC

tMRD

tXSRD*

Power UP

VDD and CK stable

EMRS Set

MRS Set

(with A8=L)

MRS Set

Reset DLL

(with A8=H)

READ

Precharge All

Non-Read

Command

2 or more

Auto Refresh

Precharge All

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

Rev. 0.1 / Oct. 2004

16

HY5DU113222FM(P)

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,

burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low

signals of /RAS, /CAS, /CS0 ,/CS1, /WE and BA0. This command can be issued only when all banks are in idle state and

CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to

write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is

determined, the information will be held until resetted by another MRS command.

BA1 BA0 A11 A10

A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

0

RFU

DR

TM

CAS Latency

Burst Length

BA0

0

MRS Type

A7

0

Test Mode

MRS

Normal

1

EMRS

Vendor

test mode

1

Burst Length

A2

A1

A0

A8

0

DLL Reset

No

Sequential

Interleave

Reserved

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

2

1

Yes

4

8

A6

0

A5

0

A4

0

CAS Latency

Reserved

4

Reserved

0

1

0

1

0

1

0

A3

0

Burst Type

Sequential

Interleave

1

0

1

5

1

0

Reserved

1

Rev. 0.1 / Oct. 2004

17

HY5DU113222FM(P)

BURST DEFINITION

Burst Length

2

Starting Address (A2,A1,A0)

Sequential

0, 1

Interleave

0, 1

XX0

XX1

X00

X01

X10

X11

000

001

010

011

100

101

110

111

1, 0

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

4

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

BURST LENGTH & TYPE

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write com-

mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is

set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a

given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Burst Definitionon Table

Rev. 0.1 / Oct. 2004

18

HY5DU113222FM(P)

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

availability of the first burst of output data. The latency can be programmed 5 / 4 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-

ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-

point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,

Class II, and Matched impedance driver, about 30% of Full drive strength.

Rev. 0.1 / Oct. 2004

19

HY5DU113222FM(P)

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-

tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits

shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)

and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller

must wait the specified time before initiating any subsequent operation. Violating either of these requirements will

result in unspecified operation.

BA1 BA0 A11 A10

A9

A8

A7

A6

DS

A5

A4

A3

A2

DS

A1

DS

A0

0

1

RFU*

DLL

A0

0

DLL enable

Enable

BA0

0

MRS Type

MRS

1

Diable

1

EMRS

A6

A1

0

Output Driver Impedance Control

0

1

Full

Half

1

0

RFU*

Weak

1

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.

Rev. 0.1 / Oct. 2004

20

HY5DU113222FM(P)

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

VIN, VOUT

VDD

-55 ~ 125

-0.5 ~ 3.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Output Short Circuit Current

Power Dissipation

V

VDDQ

IOS

V

mA

W

PD

2

^oC ⋅ sec

Soldering Temperature ⋅ Time

TSOLDER

260 ⋅ 10

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

VDD

2.375

2.5

2.7

V

1

VDDQ

Input High Voltage

Input Low Voltage

Termination Voltage

Reference Voltage

VIH

VIL

VREF + 0.15

-0.3

-

VDDQ + 0.3

VREF - 0.15

VREF + 0.04

0.51*VDDQ

V

2

3

VTT

VREF

VREF - 0.04

0.49*VDDQ

VREF

0.5*VDDQ

Note : 1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with ≤ 5ns of duration.

3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same.

Peak to peak noise on VREF may not exceed ± 2% of the DC value.

DC CHARACTERISTICS I (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

ILO

-2

2

uA

V

1

-5

5

2

VOH

VOL

VTT + 0.76

-

IOH = -15.2mA

IOL = +15.2mA

VTT - 0.76

V

Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V

Rev. 0.1 / Oct. 2004

21

HY5DU113222FM(P)

DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Speed

Sym

bol

Parameter

Test Condition

Unit Note

2

22

25

28

33

36

4

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min);

DQ,DM and DQS inputs changing

twice per clock cycle; address and

control inputs changing once per

clock cycle

Operating Current

IDD0

IDD1

mA

1

690 650 610 570 540 520 500

B u r s t le n g t h = 2 , O n e b a n k a c t iv e

tRC ≥ tRC(min), IOL=0mA

Operating Current

Precharge Standby

mA

730 690 650 610 580 560 540

100 100 100 100 100 100 100

Current in Power Down IDD2P CKE ≤ VIL(max), tCK=min

Mode

Precharge Standby

CKE ≥ VIH(min), /CS ≥ VIH(min),

Current in Non Power IDD2N tCK = min, Input signals are

mA

610 580 550 510 480 470 460

140 140 140 120 100 100 100

Down Mode

changed one time during 2clks

Active Standby Cur-

rent in Power Down

Mode

IDD3P CKE ≤ VIL(max), tCK=min

Active Standby Cur-

rent in Non Power

Down Mode

CKE ≥ VIH(min), /CS ≥ VIH(min),

IDD3N tCK=min, Input signals are

changed one time during 2clks

680 640 600 560 540 520 500 mA

1190 1120 1050 980 870 810 800 mA

Burst Mode Operating

Current

tCK≥tCK(min),IOL=0mA

IDD4

1

All banks active

tRC ≥ tRFC(min),

IDD5

Auto Refresh Current

Self Refresh Current

mA

1,2

940 920 900 880 770 760 750

All banks active

CKE ≤ 0.2V

IDD6

16

Four bank interleaving with BL=4,

IDD7 Refer to the following page for

detailed test condition

Operating Current -

Four Bank Operation

mA

1440 1320 1200 1080 970 860 850

Note :

1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Rev. 0.1 / Oct. 2004

22

HY5DU113222FM(P)

AC OPERATING CONDITIONS ^{(TA=0 to 70}^o^{C, Voltage referenced to V}SS = 0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

Input Differential Voltage, CK and /CK inputs

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

VREF + 0.35

V

VREF - 0.35

VDDQ + 0.6

0.7

1

2

Input Crossing Point Voltage, CK and /CK inputs

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Value

Unit

Reference Voltage

VDDQ x 0.5

V

Termination Voltage

VDDQ x 0.5

AC Input High Level Voltage (VIH, min)

AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level Voltage

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

VREF + 0.35

V

VREF - 0.35

V

VREF

VTT

1.5

1

V

Input minimum Signal Slew Rate

V/ns

Ω

Termination Resistor (RT)

50

Series Resistor (RS)

25

Ω

Output Load Capacitance for Access Time Measurement (CL)

30

pF

Rev. 0.1 / Oct. 2004

23

HY5DU113222FM(P)

AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)

2

22

25

28

Unit Note

Parameter

Symbol

Min

23

25

15

8

Max

Min

22

24

14

7

Max

Min

19

21

12

6

Max

Min

17

19

11

6

Max

-

Row Cycle Time

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRRD

tCCD

tRP

CK

ns

-

Auto Refresh Row Cycle Time

Row Active Time

100K

-

Row Address to Column Address Delay for Read

Row Address to Column Address Delay for Write

Row Active to Row Active Delay

Column Address to Column Address Delay

Row Precharge Time

5

-

4

-

3

-

3

-

5

4

1

-

1

-

1

-

1

-

8

-

7

-

6

-

6

-

5

-

4

-

3

-

3

-

Write Recovery Time

tWR

3

-

2

-

2

-

2

-

Last Data-In to Read Command

Auto Precharge Write Recovery + Precharge Time

tDRL

tDAL

tCK

13

2

-

11

2.2

0.45

-0.6

-

9

-

9

-

10

0.55

0.6

0.35

10

0.55

0.6

0.35

2.5

0.45

-0.6

-

10

0.55

0.6

0.35

2.8

0.45

-0.6

-

10

0.55

0.6

0.35

System Clock Cycle Time

CL=5

Clock High Level Width

tCH

0.45

-0.6

-

CK

ns

Clock Low Level Width

tCL

Data-Out edge to Clock edge Skew

DQS-Out edge to Clock edge Skew

DQS-Out edge to Data-Out edge Skew

tAC

tDQSCK

tDQSQ

ns

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

-

1,6

1,5

Data-Out hold time from DQS

Clock Half Period

tQH

tHP

ns

tCH/L

min

tCH/L

min

tCH/L

min

tCH/L

min

Data Hold Skew Factor

Input Setup Time

tQHS

tIS

-

0.35

-

0.35

-

0.35

-

0.35

ns

CK

ns

6

2

0.6

-

0.75

0.4

-

0.75

0.4

-

0.75

0.4

-

0.6

Input Hold Time

tIH

Write DQS High Level Width

Write DQS Low Level Width

Clock to First Rising edge of DQS-In

tDQSH

tDQSL

tDQSS

tDS

0.4

0.6

1.15

-

0.6

1.15

-

0.6

1.15

-

0.6

1.15

-

0.4

0.85

0.35

0.85

0.35

0.85

0.35

0.85

0.35

Data-In Setup Time to DQS-In (DQ & DM)

Data-In Hold Time to DQS-In (DQ & DM)

3

-

tDH

Rev. 0.1 / Oct. 2004

24

HY5DU113222FM(P)

AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)

2

22

25

28

Unit Note

Parameter

Symbol

Min

0.9

0.4

0

Max

Min

0.9

0.4

0

Max

Min

0.9

0.4

0

Max

Min

0.9

0.4

0

Max

Read DQS Preamble Time

tRPRE

tRPST

tWPRES

tWPREH

tWPST

tMRD

1.1

0.6

-

1.1

0.6

-

1.1

0.6

-

1.1

0.6

-

CK

ns

Read DQS Postamble Time

Write DQS Preamble Setup Time

Write DQS Preamble Hold Time

Write DQS Postamble Time

0.35

0.4

2

-

0.35

0.4

2

-

0.35

0.4

2

-

0.35

0.4

2

-

CK

0.6

-

0.6

-

0.6

-

0.6

-

Mode Register Set Delay

200

-

200

-

200

-

200

-

4

Exit Self Refresh to Any Execute Command

tXSC

2tCK

+ tIS

2tCK

+ tIS

2tCK

+ tIS

2tCK

+ tIS

-

Power Down Exit Time

tPDEX

tREFI

CK

us

-

7.8

-

7.8

-

7.8

-

7.8

Average Periodic Refresh Interval

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).

tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and

output pattern effects, and p-channel to n-channel variation of the output drivers.

7.

DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic.

Rev. 0.1 / Oct. 2004

25

HY5DU113222FM(P)

AC CHARACTERISTICS - I (continue)

33

36

4

Unit Note

Parameter

Symbol

Min

15

17

10

6

Max

Min

14

16

9

Max

Min

13

15

8

Max

Row Cycle Time

tRC

tRFC

tRAS

tRCDRD

tRCDWR

tRRD

tCCD

tRP

-

CK

ns

Auto Refresh Row Cycle Time

-

Row Active Time

100K

-

5

-

5

-

Row Address to Column Address Delay for Read

Row Address to Column Address Delay for Write

Row Active to Row Active Delay

Column Address to Column Address Delay

Row Precharge Time

3

-

2

-

2

-

3

1

-

1

-

1

-

6

-

5

-

5

-

3

-

3

-

3

-

Write Recovery Time

tWR

2

-

2

-

2

-

Last Data-In to Read Command

Auto Precharge Write Recovery + Precharge Time

tDRL

tDAL

tCK

9

-

8

-

8

-

3.3

0.45

-0.6

-

10

0.55

0.6

0.35

3.6

0.45

-0.6

-

10

0.55

0.6

0.4

4

10

0.55

0.6

0.4

System Clock Cycle Time

CL=4

0.45

-0.6

-

Clock High Level Width

tCH

CK

ns

Clock Low Level Width

tCL

Data-Out edge to Clock edge Skew

DQS-Out edge to Clock edge Skew

DQS-Out edge to Data-Out edge Skew

tAC

tDQSCK

tDQSQ

ns

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

-

1,6

1,5

Data-Out hold time from DQS

Clock Half Period

tQH

tHP

ns

tCH/L

min

tCH/L

min

tCH/L

min

-

0.35

-

0.4

-

0.4

6

2

Data Hold Skew Factor

Input Setup Time

tQHS

tIS

ns

CK

ns

0.75

0.4

-

0.75

0.4

-

0.75

0.4

-

Input Hold Time

tIH

0.6

1.15

-

0.6

1.15

-

0.6

1.15

-

Write DQS High Level Width

Write DQS Low Level Width

Clock to First Rising edge of DQS-In

tDQSH

tDQSL

tDQSS

tDS

0.4

0.85

0.35

0.85

0.4

0.85

0.4

3

Data-In Setup Time to DQS-In (DQ & DM)

Data-In Hold Time to DQS-In (DQ & DM)

-

0.4

-

0.4

-

tDH

Rev. 0.1 / Oct. 2004

26

HY5DU113222FM(P)

AC CHARACTERISTICS - I (continue)

33

36

4

Unit Note

Parameter

Symbol

Min

0.9

0.4

0

Max

Min

0.9

0.4

0

Max

Min

0.9

0.4

0

Max

Read DQS Preamble Time

tRPRE

tRPST

1.1

0.6

-

1.1

0.6

-

1.1

0.6

-

CK

ns

Read DQS Postamble Time

Write DQS Preamble Setup Time

Write DQS Preamble Hold Time

Write DQS Postamble Time

tWPRES

tWPREH

tWPST

tMRD

0.35

0.4

2

-

0.35

0.4

2

-

0.35

0.4

2

-

CK

0.6

-

0.6

-

0.6

-

Mode Register Set Delay

200

-

200

-

200

-

4

Exit Self Refresh to Any Execute Command

tXSC

2tCK

+ tIS

1tCK