HY5DU561622DT-4 [HYNIX]
DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66;
| 型号： | HY5DU561622DT-4 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总30页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY5DU561622DT
256M(16Mx16) GDDR SDRAM
HY5DU561622DT
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5 / Oct. 2004
HY5DU561622DT
Revision History
Revision
No.
History
Defined Preliminary Specification
Draft Date
Remark
0.1
0.2
0.3
0.4
0.5
Mar. 2004
Jun. 2004
Aug. 2004
Sep. 2004
Oct. 2004
VDD/VDDQ changed 300MHz speed bin to 2.8V from 2.6V
Insert AC Overshoot comment
tRAS_max change
tRAS_min & tQHS change
Rev. 0.5 / Oct. 2004
2
HY5DU561622DT
PRELIMINARY
DESCRIPTION
The Hynix HY5DU561622DT is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth.
The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
•
•
•
•
2.5V +/-5% VDD and VDDQ power supply
supports 250 / 200 / 166MHz
Data inputs on DQS centers when write (centered
DQ)
2.6V VDD/VDDQ wide range min/max power supply
supports 275Mhz
•
•
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
2.8V +/-0.1V VDD and VDDQ power supply
supports 300/350MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
All inputs and outputs are compatible with SSTL_2
interface
•
•
•
Write mask byte controls by LDM and UDM
Programmable /CAS latency 3 / 4 supported
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
•
•
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
•
•
•
•
•
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS
Data outputs on DQS edges when read (edged DQ)
ORDERING INFORMATION
Clock
Frequency
Part No.
Power Supply
Max Data Rate
interface
Package
HY5DU561622DT-28
HY5DU561622DT-33
350MHz
300MHz
700Mbps/pin
600Mbps/pin
VDD=2.8V
VDDQ=2.8V
VDD=2.6V
VDDQ=2.6V
400mil 66pin
TSOP-II
HY5DU561622DT-36
275MHz
550Mbps/pin
SSTL-2
HY5DU561622DT-4
HY5DU561622DT-5
HY5DU561622DT-6
250MHz
200MHz
166MHz
500Mbps/pin
400Mbps/pin
333Mbps/pin
VDD=2.5V
VDDQ=2.5V
Rev. 0.5 / Oct. 2004
3
HY5DU561622DT
PIN CONFIGURATION
V
DQ0
VDDQ
DQ1
DQ2
DD
1
2
3
4
5
6
7
8
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
TOP VIEW
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
V
SSQ
DQ7
NC
V DDQ
DQ8
NC
400 mil X 875mil
66 Pin TSOP
0.65mm Pin Pitch
V
DDQ
LDQS
NC
V
SSQ
-II
UDQS
NC
V
DD
V
V
REF
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
SS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A10/AP
A0
A1
A2
A3
DD
A4
V SS
V
ROW and COLUMN ADDRESS TABLE
Items
16Mx16
Organization
Row Address
Column Address
Bank Address
4M x 16 x 4banks
A0 ~ A12
A0 ~ A8
BA0, BA1
A10
Auto Precharge Flag
Refresh
4K
Rev. 0.5 / Oct. 2004
4
HY5DU561622DT
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CK, /CK
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
CKE
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
/CS
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
BA0, BA1
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
A0 ~ A12
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
/RAS, /CAS, /WE
LDM, UDM
Input
Input
Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corre-
sponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
LDQS, UDQS
I/O
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
VREF
I/O
Data input / output pin : Data Bus
Supply
Supply
Supply
NC
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
NC
Rev. 0.5 / Oct. 2004
5
HY5DU561622DT
FUNCTIONAL BLOCK DIAGRAM
4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM
16
Write Data Register
2-bit Prefetch Unit
DS
32
Bank
Control
CLK
/CLK
CKE
4Mx16/Bank0
4Mx16 /Bank1
4Mx16 /Bank2
4Mx16 /Bank3
64
32
/CS
Command
Decoder
/RAS
/CAS
LDM
UDM
DQ[0:15]
Mode
Register
Row
Decoder
Column Decoder
LDQS,UDQS
A0-12
Address
Buffer
Column Address
Counter
Data Strobe
Transmitter
BA0,BA1
CLK_DLL
Data Strobe
Receiver
DS
CLK,
/CLK
DLL
Block
Mode
Register
Rev. 0.5 / Oct. 2004
6
HY5DU561622DT
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
BA
Note
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
H
L
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
L
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
L
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge Power
Down Mode
H
L
Exit
H
H
L
Entry
H
L
L
Active Power
Down Mode
Exit
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.5 / Oct. 2004
7
HY5DU561622DT
WRITE MASK TRUTH TABLE
A10/
AP
ADDR
Note
Function
Data Write
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
LDM
UDM
BA
H
H
X
X
X
X
L
L
X
X
1,2
1,2
Data-In Mask
H
H
Lower Byte Write /
Upper Byte-In Mask
H
H
X
X
X
X
L
H
L
X
X
1,2
1,2
Upper Byte Write /
Lower Byte-In Mask
H
Note :
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
Rev. 0.5 / Oct. 2004
8
HY5DU561622DT
OPERATION COMMAND TRUTH TABLE - I
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
NOP or power down3
NOP or power down3
ILLEGAL4
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DSEL
NOP
X
X
BST
ILLEGAL4
H
BA, CA, AP
READ/READAP
IDLE
ILLEGAL4
Row Activation
NOP
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
H
L
BA, CA, AP
WRITE/WRITEAP
ACT
BA, RA
L
BA, AP
PRE/PALL
AREF/SREF
MRS
Auto Refresh or Self Refresh5
L
H
L
X
L
L
OPCODE
Mode Register Set
X
H
H
X
H
H
X
H
L
X
X
X
DSEL
NOP
NOP
NOP
ILLEGAL4
Begin read : optional AP6
Begin write : optional AP6
ILLEGAL4
BST
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
X
READ/READAP
WRITE/WRITEAP
ACT
ROW
ACTIVE
H
H
L
H
L
Precharge7
L
PRE/PALL
ILLEGAL11
L
H
AREF/SREF
ILLEGAL11
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE
MRS
DSEL
X
Continue burst to end
Continue burst to end
Terminate burst
X
X
NOP
BST
Term burst, new read:optional AP8
ILLEGAL
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
X
READ/READAP
WRITE/WRITEAP
ACT
L
READ
ILLEGAL4
H
H
L
H
L
L
PRE/PALL
AREF/SREF
Term burst, precharge
ILLEGAL11
L
H
ILLEGAL11
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE
MRS
DSEL
NOP
BST
X
X
X
Continue burst to end
Continue burst to end
L
WRITE
ILLEGAL4
Term burst, new read:optional AP8
Term burst, new write:optional AP
L
L
H
H
L
L
H
L
BA, CA, AP
BA, CA, AP
READ/READAP
WRITE/WRITEAP
Rev. 0.5 / Oct. 2004
9
HY5DU561622DT
OPERATION COMMAND TRUTH TABLE - II
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
ILLEGAL4
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, AP
X
ACT
PRE/PALL
AREF/SREF
Term burst, precharge
WRITE
ILLEGAL11
H
ILLEGAL11
Continue burst to end
Continue burst to end
ILLEGAL
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE
MRS
DSEL
X
H
H
H
X
X
NOP
L
BST
ILLEGAL10
ILLEGAL10
ILLEGAL4,10
ILLEGAL4,10
ILLEGAL11
L
H
BA, CA, AP
READ/READAP
READ
WITH
AUTOPRE-
CHARGE
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP
BA, RA
BA, AP
X
WRITE/WRITEAP
ACT
PRE/PALL
AREF/SREF
H
ILLEGAL11
Continue burst to end
Continue burst to end
ILLEGAL
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE
MRS
DSEL
X
H
H
H
X
X
NOP
L
BST
ILLEGAL10
ILLEGAL10
ILLEGAL4,10
ILLEGAL4,10
ILLEGAL11
L
H
BA, CA, AP
READ/READAP
WRITE
AUTOPRE-
CHARGE
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP
BA, RA
BA, AP
X
WRITE/WRITEAP
ACT
PRE/PALL
AREF/SREF
H
ILLEGAL11
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE
MRS
DSEL
NOP
BST
X
X
X
NOP-Enter IDLE after tRP
NOP-Enter IDLE after tRP
ILLEGAL4
ILLEGAL4,10
ILLEGAL4,10
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
READ/READAP
WRITE/WRITEAP
ACT
PRE-
CHARGE
ILLEGAL4,10
H
H
L
H
L
L
PRE/PALL
AREF/SREF
MRS
NOP-Enter IDLE after tRP
ILLEGAL11
ILLEGAL11
L
H
L
X
L
L
OPCODE
Rev. 0.5 / Oct. 2004
10
HY5DU561622DT
OPERATION COMMAND TRUTH TABLE - III
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
L
X
H
H
X
H
H
X
H
L
X
X
X
DSEL
NOP
BST
NOP - Enter ROW ACT after tRCD
NOP - Enter ROW ACT after tRCD
ILLEGAL4
ILLEGAL4,10
ILLEGAL4,10
ILLEGAL4,9,10
ILLEGAL4,10
ILLEGAL11
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
X
READ/READAP
WRITE/WRITEAP
ACT
ROW
ACTIVATING
H
H
L
H
L
L
PRE/PALL
L
H
AREF/SREF
ILLEGAL11
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE
MRS
DSEL
X
X
NOP - Enter ROW ACT after tWR
NOP - Enter ROW ACT after tWR
NOP
ILLEGAL4
ILLEGAL
ILLEGAL
X
BST
H
L
BA, CA, AP
BA, CA, AP
BA, RA
READ/READAP
WRITE/WRITEAP
ACT
WRITE
RECOVERING
L
ILLEGAL4,10
ILLEGAL4,11
ILLEGAL11
H
H
L
L
L
L
H
L
L
BA, AP
X
PRE/PALL
H
AREF/SREF
ILLEGAL11
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE
MRS
DSEL
NOP
BST
X
X
X
NOP - Enter precharge after tDPL
NOP - Enter precharge after tDPL
ILLEGAL4
ILLEGAL4,8,10
ILLEGAL4,10
ILLEGAL4,10
ILLEGAL4,11
ILLEGAL11
L
WRITE
RECOVERING
WITH
AUTOPRE-
CHARGE
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
X
READ/READAP
WRITE/WRITEAP
ACT
H
H
L
H
L
L
PRE/PALL
L
H
AREF/SREF
ILLEGAL11
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE
MRS
DSEL
NOP
BST
X
X
X
NOP - Enter IDLE after tRC
NOP - Enter IDLE after tRC
REFRESHING
ILLEGAL11
ILLEGAL11
L
L
H
L
H
BA, CA, AP
READ/READAP
Rev. 0.5 / Oct. 2004
11
HY5DU561622DT
OPERATION COMMAND TRUTH TABLE - IV
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP
BA, RA
BA, AP
X
WRITE/WRITEAP
ACT
WRITE
PRE/PALL
AREF/SREF
H
ILLEGAL11
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE
MRS
DSEL
NOP
BST
X
X
X
NOP - Enter IDLE after tMRD
NOP - Enter IDLE after tMRD
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
ILLEGAL11
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
READ/READAP
WRITE/WRITEAP
ACT
MODE
REGISTER
ACCESSING
H
H
L
H
L
L
PRE/PALL
AREF/SREF
MRS
L
H
L
X
L
L
OPCODE
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Rev. 0.5 / Oct. 2004
12
HY5DU561622DT
CKE FUNCTION TRUTH TABLE
Current
State
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit self refresh, enter idle after tSREX
Exit self refresh, enter idle after tSREX
ILLEGAL
L
SELF
REFRESH1
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP, continue self refresh
INVALID
H
L
X
H
H
H
H
H
L
Exit power down, enter idle
Exit power down, enter idle
ILLEGAL
L
POWER
DOWN2
L
L
L
L
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
L
ILLEGAL
L
X
X
L
X
X
L
NOP, continue power down mode
See operation command truth table
Enter self refresh
Exit power down
Exit power down
ILLEGAL
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
L
ALL BANKS
IDLE4
L
L
L
L
X
X
L
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
ILLEGAL
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
H
H
L
H
L
See operation command truth table
ANY STATE
OTHER
THAN
ILLEGAL5
INVALID
INVALID
H
L
ABOVE
L
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 0.5 / Oct. 2004
13
HY5DU561622DT
SIMPLIFIED STATE DIAGRAM
MRS
SREF
SREX
MODE
REGISTER
SET
SELF
REFRESH
IDLE
PDEN
PDEX
AREF
ACT
POWER
DOWN
AUTO
REFRESH
POWER
DOWN
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
READAP
WRITE
WITH
READ
WITH
READAP
WRITE
READ
AUTOPRE-
CHARGE
AUTOPRE-
CHARGE
WRITEAP
WRITEAP
WRITE
PRE(PALL)
PRE(PALL)
PRE-
CHARGE
Command Input
POWER-UP
Automatic Sequence
POWER APPLIED
Rev. 0.5 / Oct. 2004
14
HY5DU561622DT
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-
ages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable com-
mand.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-
ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-
MOS low state. (All the other input pins may be undefined.
No power sequencing is specified during power up or power down given the following cirteria :
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).
• VREF tracks VDDQ/2.
• A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the
input current from the VTT supply into any pin.
If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must
be adhered to during power up :
Voltage description
Sequencing
Voltage relationship to avoid latch-up
< VDD + 0.3V
VDDQ
VTT
After or with VDD
After or with VDDQ
After or with VDDQ
< VDDQ + 0.3V
VREF
< VDDQ + 0.3V
2. Start clock and maintain stable clock for a minimum of 200usec.
3. After stable power and clock, apply NOP condition and take CKE high.
4. Issue Extended Mode Register Set (EMRS) to enable DLL.
5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
6. Issue Precharge commands for all banks of the device.
Rev. 0.5 / Oct. 2004
15
HY5DU561622DT
7.
8.
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
/CLK
CLK
tIS tIH
LVCMOS Low Level
CKE
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
CMD
DM
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
ADDR
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
DQS
DQ'S
T=200usec
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tXSRD*
Power UP
VDD and CK stable
EMRS Set
MRS Set
(with A8=L)
MRS Set
Reset DLL
(with A8=H)
READ
Precharge All
Non-Read
Command
2 or more
Auto Refresh
Precharge All
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Rev. 0.5 / Oct. 2004
16
HY5DU561622DT
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
0
RFU
DR
TM
CAS Latency
Burst Length
BA0
0
MRS Type
MRS
A7
0
Test Mode
Normal
Test
1
EMRS
1
Burst Length
A2
A1
A0
A8
0
DLL Reset
No
Sequential
Interleave
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
1
Yes
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
Reserved
3
0
0
1
0
1
0
0
1
1
1
0
0
4
A3
0
Burst Type
Sequential
Interleave
1
0
1
Reserved
Reserved
Reserved
1
1
0
1
1
1
1
Rev. 0.5 / Oct. 2004
17
HY5DU561622DT
BURST DEFINITION
Burst Length
2
Starting Address (A2,A1,A0)
Sequential
0, 1
Interleave
0, 1
XX0
XX1
X00
X01
X10
X11
000
001
010
011
100
101
110
111
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
4
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Rev. 0.5 / Oct. 2004
18
HY5DU561622DT
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DU561622CT supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/
or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength
driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength.
Rev. 0.5 / Oct. 2004
19
HY5DU561622DT
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-
tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
DS
A5
A4
A3
A2
A1
DS
A0
0
1
RFU*
RFU*
DLL
A0
0
DLL enable
Enable
BA0
0
MRS Type
MRS
1
Diable
1
EMRS
A6
A1
0
Output Driver Impedance Control
0
0
1
1
Full
Half
1
0
RFU*
RFU*
1
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 0.5 / Oct. 2004
20
HY5DU561622DT
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Symbol
TA
Rating
0 ~ 70
Unit
oC
oC
V
TSTG
-55 ~ 125
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
VIN, VOUT
VDD
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
V
VDDQ
IOS
V
mA
W
PD
1
oC ⋅ sec
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VIH
2.375
2.5
2.5
2.625
2.9
V
V
V
V
V
V
V
V
V
V
4
5
2.6
2.7
2.8
2.9
6
2.375
2.5
2.625
4, 1
5, 1
6, 1
2.5
2.6
2.9
2.7
2.8
2.9
VREF + 0.15
-0.3
-
-
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
VIL
2
3
Termination Voltage
Reference Voltage
VTT
VREF - 0.04
0.49*VDDQ
VREF
0.5*VDDQ
VREF
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with ≤ 5ns of duration.
3. VIH (max) is acceptable VDDQ + 1.5V AC pulse width with < 5ns of duration
4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed ± 2% of the dc value.
5. Supports 250/200/166 MHz.
6. Supports 275 MHz.
7. Supports 300/350MHz.
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
ILO
-5
5
uA
uA
V
1
-5
5
2
VOH
VOL
VTT + 0.76
-
-
IOH = -15.2mA
IOL = +15.2mA
VTT - 0.76
V
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN = 0V. 2. DOUT is disabled, VOUT = 0 to 2.7V
Rev. 0.5 / Oct. 2004
21
HY5DU561622DT
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
Unit Note
Parameter Symbol
Test Condition
28
33
36
4
5
6
One bank; Active - Read - Precharge;
Burst Length=4; tRC=tRC(min);
tCK=tCK(min); address and control
inputs changing once per clock cycle;
IOUT=0mA
Operating Current
IDD1
180
180
170
160
150
150
mA
mA
mA
mA
Precharge Power
Down Standby
Current
All banks idle; Power down mode;
CKE=Low, tCK=tCK(min)
IDD2P
20
/CS=High, All banks idle;
tCK=tCK(min);
IDD2F CKE=High; address and control inputs
changing once per clock cycle.
Idle Standby
Current
100
45
100
45
90
40
80
35
70
30
70
30
VIN=VREF for DQ, DQS and DM
Active Power
Down
Standby Current
One bank active; Power down mode ;
IDD3P
CKE=Low, tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank;
Active-Precharge; tRC=tRAS(max);
tCK=tCK(min);
Active Standby
Current
IDD3N DQ, DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per clock
cycle
110
110
100
90
80
80
mA
Burst=2;Reads; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
IDD4R
mA
mA
Operating Current
260
240
260
240
240
220
220
200
200
180
200
180
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
IDD4W
Auto Refresh
Current
IDD5
IDD6
tRC=tRFC(min); All banks active
mA
Self Refresh
Current
CKE=<0.2V; External clock on;
tCK=tCK(min)
4
mA
Rev. 0.5 / Oct. 2004
22
HY5DU561622DT
AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.35
V
V
V
V
VREF - 0.35
VDDQ + 0.6
0.7
1
2
Input Crossing Point Voltage, CK and /CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
V
Termination Voltage
VDDQ x 0.5
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.35
V
VREF - 0.35
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
Ω
Termination Resistor (RT)
50
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 0.5 / Oct. 2004
23
HY5DU561622DT
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
28 33
36
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Row Cycle Time
(Manual Precharge)
tRC
20
-
18
-
16
-
CK
CK
Row Cycle Time
(Auto Precharge)
tRC_APCG
21
-
19
-
18
-
Auto Refresh Row Cycle Time
Row Active Time
tRFC
24
40
6
-
22
40
6
-
20
40
5
-
CK
ns
tRAS
70K
70K
70K
tRCDRD
tRCDWT
tRRD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CK
CK
CK
CK
CK
Row Address to Column Address Delay
Row Active to Row Active Delay
2
2
2
2
2
2
Column Address to Column Address Delay tCCD
1
1
1
Row Precharge Time
tRP
6
6
5
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
tDRL
tDAL
4
2
-
-
-
3
2
9
-
-
-
3
2
8
-
-
-
CK
CK
CK
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
10
CL = 4.0
CL = 3.0
2.8
-
7.0
-
3.3
-
7.0
-
3.6
-
7.0
-
ns
ns
CK
CK
ns
ns
ns
System Clock Cycle Time
tCK
Clock High Level Width
Clock Low Level Width
tCH
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.4
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.4
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.4
tCL
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Data-Out hold time from DQS
Clock Half Period
tQH
tHP
-
-
-
-
-
-
ns
ns
1, 6
1, 5
tCH/L
min
tCH/L
min
tCH/L
min
Data Hold Skew Factor
Input Setup Time
tQHS
tIS
-
0.4
-
-
0.4
-
-
0.4
-
ns
ns
ns
CK
CK
6
2
2
0.75
0.75
0.4
0.75
0.75
0.4
0.75
0.75
0.4
Input Hold Time
tIH
-
-
-
Write DQS High Level Width
Write DQS Low Level Width
tDQSH
tDQSL
0.6
0.6
0.6
0.6
0.6
0.6
0.4
0.4
0.4
Rev. 0.5 / Oct. 2004
24
HY5DU561622DT
28
33
36
Unit
Note
Parameter
Symbol
Min
0.85
0.4
0.4
0.9
0.4
0
Max
Min
0.85
0.4
0.4
0.9
0.4
0
Max
Min
0.85
0.4
0.4
0.9
0.4
0
Max
Clock to First Rising edge of DQS-In
tDQSS
1.15
1.15
1.15
CK
ns
Data-In Setup Time to DQS-In (DQ & DM) tDS
Data-In Hold Time to DQS-In (DQ & DM) tDH
-
-
-
-
-
-
3
3
ns
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
tRPRE
1.1
0.6
-
1.1
0.6
-
1.1
0.6
-
CK
CK
ns
tRPST
tWPRES
tWPREH
tWPST
tMRD
1.5
0.4
2
-
1.5
0.4
2
-
1.5
0.4
2
-
ns
0.6
-
0.6
-
0.6
-
CK
CK
Exit Self Refresh to Any Execute
Command
tXSC
200
-
-
200
-
-
200
-
-
CK
CK
4
Except Read
Command
1tCK
+ tIS
1tCK
+ tIS
1tCK
+ tIS
tPDEX
Power Down Exit Time
Read
2tCK
+ tIS
2tCK
+ tIS
2tCK
+ tIS
tPDEX_RD
tREFI
-
-
-
CK
us
Command
Average Periodic Refresh Interval
-
7.8
-
7.8
-
7.8
Rev. 0.5 / Oct. 2004
25
HY5DU561622DT
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
4
5
6
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Row Cycle Time
(Manual Precharge)
tRC
15
-
12
-
11
-
CK
CK
Row Cycle Time
(Auto Precharge)
tRC_APCG
17
-
14
-
11
-
Auto Refresh Row Cycle Time
Row Active Time
tRFC
18
40
5
-
14
40
4
-
12
40
4
-
CK
ns
tRAS
70K
70K
70K
tRCDRD
tRCDWT
tRRD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CK
CK
CK
CK
CK
Row Address to Column Address Delay
Row Active to Row Active Delay
2
2
2
2
2
2
Column Address to Column Address Delay tCCD
1
1
1
Row Precharge Time
tRP
5
4
4
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
tDRL
tDAL
3
2
8
-
-
-
3
2
7
-
-
-
3
2
6
-
-
-
CK
CK
CK
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
CL = 4.0
CL = 3.0
4.0
-
7.0
-
-
-
-
-
ns
ns
CK
CK
ns
ns
ns
System Clock Cycle Time
tCK
5.0
0.45
0.45
-0.7
-0.7
-
7.0
6.0
0.45
0.45
-0.7
-0.7
-
7.0
Clock High Level Width
Clock Low Level Width
tCH
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.4
0.55
0.55
0.7
0.55
0.55
0.7
tCL
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tAC
tDQSCK
tDQSQ
0.7
0.7
0.45
0.45
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Data-Out hold time from DQS
Clock Half Period
tQH
tHP
-
-
-
-
-
-
ns
ns
1, 6
1, 5
tCH/L
min
tCH/L
min
tCH/L
min
Data Hold Skew Factor
Input Setup Time
tQHS
tIS
-
0.4
-
-
0.5
-
-
0.5
-
ns
ns
ns
CK
CK
6
2
2
0.75
0.75
0.4
0.75
0.75
0.4
0.75
0.75
0.4
Input Hold Time
tIH
-
-
-
Write DQS High Level Width
Write DQS Low Level Width
tDQSH
tDQSL
0.6
0.6
0.6
0.6
0.6
0.6
0.4
0.4
0.4
Rev. 0.5 / Oct. 2004
26
4
5
6
Unit
Note
Parameter
Symbol
Min
0.85
0.4
0.4
0.9
0.4
0
Max
Min
0.75
0.4
0.4
0.9
0.4
0
Max
Min
0.75
0.4
0.4
0.9
0.4
0
Max
Clock to First Rising edge of DQS-In
tDQSS
1.15
1.25
1.25
CK
ns
Data-In Setup Time to DQS-In (DQ & DM) tDS
Data-In Hold Time to DQS-In (DQ & DM) tDH
-
-
-
-
-
-
3
3
ns
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
tRPRE
1.1
0.6
-
1.1
0.6
-
1.1
0.6
-
CK
CK
ns
tRPST
tWPRES
tWPREH
tWPST
tMRD
1.5
0.4
2
-
1.5
0.4
2
-
1.5
0.4
2
-
ns
0.6
-
0.6
-
0.6
-
CK
CK
CK
Exit Self Refresh to Any Execute Command tXSC
200
-
200
-
200
-
4
Except Read
tPDEX
1tCK
+ tIS
1tCK
+ tIS
1tCK
+ tIS
-
-
-
CK
Command
Power Down Exit Time
Read
2tCK
+ tIS
2tCK
+ tIS
2tCK
+ tIS
tPDEX_RD
tREFI
-
-
-
CK
us
Command
Average Periodic Refresh Interval
-
7.8
-
7.8
-
7.8
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
HY5DU561622DT
AC CHARACTERISTICS - II
tRC
tRC_APCG
(AUTO Precharge)
Frequency
CL
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tDAL
Unit
(Manual Precharge)
350MHz
(2.8ns)
4
4
4
4
3
3
20
21
16
18
17
14
11
24
22
20
18
14
12
40ns
40ns
40ns
40ns
40ns
40ns
6
6
5
5
4
4
2
2
2
2
2
2
6
6
5
5
4
4
10
9
tCK
tCK
tCK
tCK
tCK
tCK
300MHz
(3.3ns)
18
16
15
12
11
275MHz
(3.6ns)
8
250MHz
(4.0ns)
8
200MHz
(5.0ns)
7
166MHz
(6.0ns)
6
Rev. 0.5 / Oct. 2004
28
HY5DU561622DT
CAPACITANCE (TA=25oC, f=1MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
Input Capacitance
CK, CK
CCK
CIN
CIO
2.0
2.0
4.0
3.0
3.0
5.0
pF
pF
pF
All other input-only pins
DQ, DQS, DM
Input / Output Capacitanc
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
Ω
RT=50
Output
Ω
Zo=50
VREF
L
C =30pF
Rev. 0.5 / Oct. 2004
29
HY5DU561622DT
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0 ~ 5 Deg.
0.35 (0.0138)
0.25 (0.0098)
0.65 (0.0256) BSC
SEATING PLANE
1.194 (0.0470)
0.991 (0.0390)
0.15 (0.0059)
0.05 (0.0020)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.
Rev. 0.5 / Oct. 2004
30
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