HY5PS121621CFP-25_技术文档

HY5PS121621CFP

512Mb(32Mx16) DDR2 SDRAM

HY5PS121621CFP

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.5/ Mar. 2008

1

1HY5PS121621CFP

Revision Details

Revision No.

History

Draft Date

Remark

0.1

0.2

Defined target spec.

July. 2006

Preliminery

Added Idd values, changed from VDD(Q)=2.1V to VDD(Q)=2.0V,

Aug. 2006

Preliminary

CL from 3 to 7 is supported and removed Default Output V-I

characteristics (page 63, 64 and 65 on Rev.0.1).

1. Changed number(0.30mV --> 0.25mV) of the input AC logic level

table (Page 58)

0.3

1.0

2. Changed Setup/ Hold time (tDS/tDH, Page 67/68)

Inserted IDD value at the IDD table of (-2, -22,-25) speed bin (Page 64) Oct. 2006

1. Changed CL from ‘Reserved’ to 7 at MRS table on page 12 and CL

from 6 to 7 at the table of 2ns/2.2ns on page 67.

1.1

Nov. 2006

2. Changed Rtt from ‘Reserved’ to 50ohm on page 14.

3. Revised IDD value on page 64 and typo.

1.2

1.3

Revised typo connected with tAOND and tAOFD.

Jan. 2007

Feb. 2007

Removed CL7 at AC timing table (-2, -22) on page 68.

1. Insert the thermal characteristics table (P.57)

1.4

1.5

Feb. 2008

Mar. 2008

2. Corrected the definition of rising & falling slew rate (P.59)

1. Changed the thermal characteristics Value (P.57)

Note) The HY5PS121621CFP data sheet follows all of DDR2 JEDEC standard.

Rev. 1.5/ Mar. 2008

2

1HY5PS121621CFP

Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Key Feaures

1.1.2 Ordering Information

1.2 Pin configuration

32M × 16 DDR2 Pin Configuration

1.3 Pin Description

2. Functioanal Description

2.1 Simplified State Diagram

2.2 Functional Block Diagram(32M × 16)

2.3 Basic Function & Operation of DDR2 SDRAM

2.3.1 Power up and Initialization

2.3.2 Programming the Mode and Extended Mode Registers

2.3.2.1 DDR2 SDRAM Mode Register Set(MRS)

2.3.2.2 DDR2 SDRAM Extended Mode Register Set

2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment

2.3.2.4 ODT(On Die Termination)

2.4 Bank Activate Command

2.5 Read and Write Command

2.5.1 Posted CAS

2.5.2 Burst Mode Operation

2.5.3 Burst Read Command

2.5.4 Burst Write Operation

2.5.5 Write Data Mask

2.6 Precharge Operation

2.7 Auto Precharge Operation

2.8 Refresh Commands

2.8.1 Auto Refresh Command

2.8.2 Self Refresh Command

2.9 Power Down

2.10 Asynchronous CKE Low Event

2.11 No Operation Command

2.12 Deselect Command

3. Truth Tables

3.1 Command Truth Table

3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors

3.3 Data Mask Truth Table

4. Operating Conditions

4.1 Absolute Maximum DC Ratings

4.2 Operating Temperature Condition

4.3 Thermal Characteristics

Rev. 1.5/ Mar. 2008

3

1HY5PS121621CFP

5. AC & DC Operating Conditions

5.1 DC Operation Conditions

5.1.1 Recommended DC Operating Conditions(SSTL_1.8)

5.1.2 ODT DC Electrical Characteristics

5.2 DC & AC Logic Input Levels

5.2.1 Input DC Logic Level

5.2.2 Input AC Logic Level

5.2.3 AC Input Test Conditions

5.2.4 Differential Input AC Logic Level

5.2.5 Differential AC output parameters

5.2.6 Overshoot / Undershoot Specification

5.3 Output Buffer Levels

5.3.1 Output AC Test Conditions

5.3.2 Output DC Current Drive

5.3.3 OCD default chracteristics

5.4 Input/Output Capacitance

6. IDD Specifications & Measurement Conditions

7. AC Timing Specifications

7.1 Timing Parameters by Speed Grade

8 Package Dimensions(x16)

Rev. 1.5/ Mar. 2008

4

1HY5PS121621CFP

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD/VDDQ= 2.0V +/- 0.1V(500 / 450 MHz)

• VDD/VDDQ= 1.8V +/- 0.1V(400 / 350 / 300 MHz)

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the

clock

• Programmable CAS latency from 3 to 7 supported

• Programmable additive latency 0, 1, 2, 3, 4,5 and 6 supported

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Self-Refresh High Temperature Entry

• High Temperature Self Refresh rate supported

Ordering Information

Clock

Power Supply

Max Data Rate

Interface

Package

Part No.

Frequency

500Mhz

450Mhz

400Mhz

350Mhz

300MHz

HY5PS121621CFP-2

HY5PS121621CFP-22

HY5PS121621CFP-25

HY5PS121621CFP-28

HY5PS121621CFP-33

1000Mbps/pin

900Mbps/pin

800Mbps/pin

700Mbps/pin

600Mbps/pin

VDD/ VDDQ=2.0V

SSTL_18 84Ball FBGA

VDD/ VDDQ=1.8V

*** HY5PS121621CFP-2 do not guarantee -25/-28/-33 speed bin.

Note)

Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P"

character after "F" for Lead free product.

For example, the part number of 300MHz Lead free product is HY5PS121621CFP-33..

Rev. 1.5/ Mar. 2008

5

1HY5PS121621CFP

1.2 32Mx16 DDR2 PIN CONFIGURATION

7

8

3

9

1

2

VSSQ

UDQS

VSS

VDDQ

VDD

NC

A

B

C

D

E

F

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSQ

DQ8

UDM

VDDQ

DQ11

VSS

DQ15

VDDQ

DQ13

VDDQ

DQ7

DQ14

VDDQ

DQ12

VDD

VSSQ

DQ9

VSSQ

NC

VSSQ

LDQS

VSSQ

DQ0

LDM

DQ6

VSSQ

DQ1

VSSQ

VDDQ

DQ3

VDDQ

DQ5

VDDQ

DQ4

G

H

VSSQ

VSSDL

RAS

CK

VSS

WE

VDD

ODT

VDDL

VREF

CKE

J

K

CAS

A2

CS

A0

A4

A8

NC

BA1

A1

L

M

N

P

NC

VSS

VDD

BA0

A10

A3

VDD

VSS

A6

A5

A11

NC

A9

A7

NC

R

A12

ROW AND COLUMN ADDRESS TABLE

ITEMS

32Mx16

# of Bank

Bank Address

Auto Precharge Flag

Row Address

4

BA0, BA1

A10/AP

A0 - A12

A0-A9

Column Address

Page size

2 KB

Rev. 1.5/ Mar. 2008

6

1HY5PS121621CFP

1.3 PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the

crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the

crossings of CK and CK (both directions of crossing).

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH

operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for

POWER DOWN entry and exit, and for SELF REFRESH entry and exit. CKE must be maintained high

throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE and ODT are disabled

during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an

SSTL_18 input, but will detect an LVCMOS LOW level after Vdd is applied.

CKE

CS

Input

Chip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All commands are masked

when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS

is considered part of the command code.

On Die Termination Control : ODT enables on die termination resistance internal to the DDR2 SDRAM.

When enabled, on die termination is only applied to DQ, LDQS, /LDQS, UDQS, /UDQS, LDM and UDM.

ODT

Input

RAS, CAS, WE

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled

High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS,

Although DM pins are input only, the DM loading matches the DQ and DQS loading.

(LDM, UDM)

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE com-

mand is being applied. Bank address also determines if the mode register or extended mode register is

to be accessed during a MRS or EMRS cycle.

BA0, BA1

Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the

respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE

applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank

is selected by BA0, BA1. The address inputs also provide the op code during MODE REGISTER SET com-

mands.

A0 ~ A12

DQ

Input

Input/Out Data input / output : Bi-directional data bus

put

Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in

write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on

DQ8~DQ15. The data strobes LDQS ,UDQS may be used in single ended mode or paired with optional

complementary signals LDQS, UDQS to provide differential pair signaling to the system during both

reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.

(UDQS),(UDQS) Input/Out

(LDQS),(LDQS)

put

NC

VDDQ

VSSQ

VDDL

VSSDL

VDD

No Connect : No internal electrical connection is present.

Supply

DQ Power Suupply

DQ Ground

DLL Power Supply

DLL Ground

Power Supply

VSS

Ground

VREF

Reference voltage for inputs for SSTL interface.

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)

x16 LDQS/LDQS and UDQS/UDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)

x16 LDQS and UDQS

Rev. 1.5/ Mar. 2008

7

1HY5PS121621CFP

2. Functional Description

2.1 Simplified State Diagram

Initialization

Sequence

CKEL

OCD

calibration

Self

Refreshing

SRF

CKEH

PR

Idle

Setting

MRS

EMRS

MRS

REF

All banks

precharged

Refreshing

CKEL

CKEH

ACT

CKEL

Precharge

Power

Down

Activating

CKEL

Automatic Sequence

Command Sequence

Active

Power

Down

CKEH

CKEL

Bank

Active

Read

Write

Read

WRA

RDA

Read

Reading

Writing

RDA

WRA

RDA

PR, PRA

Writing

with

Autoprecharge

Reading

with

Autoprecharge

PR, PRA

CKEL = CKE low, enter Power Down

Precharging

CKEH = CKE high, exit Power Down, exit Self Refresh

ACT = Activate

WR(A) = Write (with Autoprecharge)

RD(A) = Read (with Autoprecharge)

PR(A) = Precharge (All)

MRS = (Extended) Mode Register Set

SRF = Enter Self Refresh

REF = Refresh

Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions

and the commands to control them, not all details. In particular situations involving more than one bank,

enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured

in full detail.

Rev. 1.5/ Mar. 2008

8

1HY5PS121621CFP

2.2 Functional Block Diagram(32Mx16)

4Banks x 8Mbit x 16 I/O DDR2 SDRAM

Self refresh

logic & timer

refresh

Internal Row

Counter

CLK

Row

Active

8Mx16 Bank3

8Mx16 Bank2

8Mx16 Bank1

8Mx16 Bank0

Row

Pre

Decoders

DLL

CKE

OCD

ODT

Control

DLL Clk

control

ODT

CS

Memory

Cell

Array

control

RAS

CAS

16

Output

Buffers

refresh

& ODT

4bit pre-fetch

Read Data

Register

WE

Column

Active

64

DQ

0~15

Sense Amp

& I/O Gate

U/LDM

ODT

Column Active

latch

4bit pre-fetch

Write Data

Register

Column decoders

Additive Latency

16

Input

bank select

Buffers

Column Add

Counter&latch

Column

Pre Decoders

A0

A1

DS

ODT

control

Address

Registers

DQS

I/O Buffer

DQS

DS

&ODT

A12

BA1

BA0

Mode

Register

DLL Clk OCD

Control

Rev. 1.5/ Mar. 2008

9

1HY5PS121621CFP

2.3 Basic Function & Operation of DDR2 SDRAM

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and

continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of

an Active command, which is then followed by a Read or Write command. The address bits registered coinci-

dent with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank;

A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to

select the starting column location for the burst access and to determine if the auto precharge command is to

be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed infor-

mation covering device initialization, register definition, command descriptions and device operation.

2.3.1 Power up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other

than those specified may result in undefined operation.

Power-up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may

be undefined.)

- VDD, VDDL and VDDQ are driven from a single power converter output, AND

- VTT is limited to 0.95 V max, AND

- Vref tracks VDDQ/2.

or

- Apply VDD before or at the same time as VDDL.

- Apply VDDL before or at the same time as VDDQ.

- Apply VDDQ before or at the same time as VTT & Vref.

at least one of these two sets of conditions must be met.

2. Start clock and maintain stable condition.

3. For the minimum of 200 us after stable power and clock(CK, CK), then apply NOP or deselect & take CKE

high.

4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.

5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0 and BA2, “High” to BA1.)*2

6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “Low” to BA2, “High” to BA0 and BA1.)*2

7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0

and "Low" to BA1-2 and A13~A15.)

8. Issue a Mode Register Set command for “DLL reset”. 9. (To issue DLL reset command, provide "High" to A8

and "Low" to BA0-2, and A13~15.)

9. Issue precharge all command.

10. Issue 2 or more auto-refresh commands.

11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating

parameters without resetting the DLL.)

12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).

Rev. 1.5/ Mar. 2008

10

1HY5PS121621CFP

Initialization Sequence after Power Up

tCHtCL

CK

/CK

tIS

CKE

ODT

ANY

PRE

ALL

PRE

ALL

NOP

EMRS

MRS

REF

MRS

EMRS

CMD

REF

Command

tRFC

tRP

tMRD

tRFC

tMRD

400ns

tRP

Follow OCD

Flowchart

tOIT

min. 200 Cycle

DLL

RESET

DLL

ENABLE

OCD

Default

OCD

CAL. MODE

EXIT

2.3.2 Programming the Mode and Extended Mode Registers

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR)

are user defined variables and must be programmed with a Mode Register Set (MRS) command. Addition-

ally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended

strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be pro-

grammed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or

Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the

user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when

the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be

executed any time after power-up without affecting array contents.

Rev. 1.5/ Mar. 2008

11

1HY5PS121621CFP

2.3.2.1 DDR2 SDRAM Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls

CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to

make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined,

therefore the mode register must be written after power-up for proper operation. The mode register is written

by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~A15.

The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode reg-

ister. The mode register set command cycle time (tMRD) is required to complete the write operation to the

mode register. The mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the precharge state. The mode register is

divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and

8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type

is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn’t support half clock latency mode. A7

is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recov-

ery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.

BA2

A15 ~ A13

A12

BA1

BA0

Address Field

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0*¹

Mode Register

0*¹

0

PD

WR

Burst Length

DLL TM

CAS Latency

BT

Burst Length

A3

0

Burst Type

Sequential

Interleave

A8

0

DLL Reset

No

A7

0

mode

A2 A1 A0 BL

Normal

Test

1

0

1

0

1

4

8

1

Yes

1

Write recovery for autoprecharge

A11 A10 A9 WR(cycles)

CAS Latency

Active power

down exit time

A12

A6

0

A5

0

A4

Latency

0

1

Fast exit(use t^XARD)

Slow exit(use t^XARDS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

0

1

0

1

0

1

0

1

Reserved

2

0

Reserved

3

0

1

Reserved

BA1 BA0

MRS mode

MRS

4

0

1

3

4

5

6

7

0

1

0

1

0

1

5

1

0

EMRS(1)

6

7

1

0

EMRS(2): Reserved

EMRS(3): Reserved

1

Reserved

1

*1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register.

* 2: WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.

WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer

(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with

tRP to determine tDAL.

Rev. 1.5/ Mar. 2008

12

1HY5PS121621CFP

2.3.2.2 DDR2 SDRAM Extended Mode Register Set

EMRS(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,

ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined,

therefore the extended mode register(1) must be written after power-up for proper operation. The extended mode regis-

ter(1) is written by asserting low on CS, RAS, CAS, WE, high on BA0 and low on BA1, while controlling the states of

address pins A0 ~ A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the

extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write

operation to the extended mode register(1). Mode register contents can be changed using the same command and clock

cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or

disable. A1 is used for enabling a half strength output driver. A3~A5 determines the additive latency, A7~A9 are used for

OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and

upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time

the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be

issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn-

chronization to occur may result in a violation of the tAC or tDQSCK parameters.

Rev. 1.5/ Mar. 2008

13

1HY5PS121621CFP

EMRS(1) Programming

Address Field

BA

2

BA

1

A

12

BA

0

A

15 ~

A

1

13

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A0

1

Extended Mode Register

0*

0

1

0*

OCD program

Rtt

Additive latency

D.I.C DLL

Qoff

0

DQS

Rtt

BA1 BA0

MRS mode

MRS

A6 A2 Rtt (NOMINAL)

0

1

0

1

0

1

0

1

0

1

0

1

ODT Disabled

75 ohm

A0

0

DLL Enable

Enable

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

150 ohm

50 ohm

1

Disable

A9 A8 A7

OCD Calibration Program

A5 A4 A3

Additive Latency

0

1

0

1

0

1

0

OCD Calibration mode exit; maintain setting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Drive(1)

Drive(0)

1

2

a

3

Adjust mode

4

b

1

OCD Calibration default

5

6

a: When Adjust mode is issued, AL from previously set value must be applied.

b: After setting to default, OCD mode needs to be exited by setting A9-A7 to

000. Refer to the following 2.2.2.3 section for detailed information

Reserved

a

A12

Qoff (Optional)

Output Driver

Impedence Control

Driver

Size

A1

0

1

Output buffer enabled

Output buffer disabled

0

1

Normal

Half

100%

60%

a. Outputs disabled - DQs, DQSs, DQSs.

This feature is used in conjunction with DIMM

IDD meaurements when IDDQ is not desired to

be included.

A10

0

DQS

Enable

Disable

1

*1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register.

Rev. 1.5/ Mar. 2008

14

1HY5PS121621CFP

EMRS(2)

The extended mode register(2) controls refresh related features. The default value of the extended mode reg-

ister(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper

operation. The extended mode register(2) is written by asserting low on /CS,/RAS,/CAS,/WE, high on BA1

and low on BA0, while controling the states of address pins A0~A15. The DDR2 SDRAM should be in all bank

precharge with CKE already high prior to writing into the extended mode register(2). Mode register contents

can be changed using the same command and clock cycle requirements during normal operation as long as

all bank are in the precharge state.

EMRS(2) Programming:

Address Field

BA2

BA1

A12

BA0

A15 ~

A

13

A11

A10

A

9

A8

A

7

A6

A

5

A4

A

3

A2

A

1

A0

1

Extended Mode

Register(2)

0*

1

SRF

0

0*

High Temp Self-refresh

Rate Enable

BA1 BA0

MRS mode

MRS

A7

0

1

0

1

0

1

0

Enable

Disable

EMRS(1)

EMRS(2)

EMRS(3):Reserved

*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A7, BA0 and BA1 must be

programmed to 0 when setting the mode register during initialization.

Due to the migration natural, user needs to ensure the DRAM part supports higher than 85℃ Tcase tempera-

ture self-refresh entry. JEDEC standard DDR2 SDRAM Module user can look at DDR2 SDRAM Module SPD

fileld Byte 49 bit[0]. If the high temperature self-refresh mode is supported then controller can set the EMRS2

[A7] bit to enable the self-refresh rate in case of higher than 85℃ temperature self-refresh operation. For the

lose part user, please refer to the Hynix web site(www.hynix.com) to check the high temperature self-refresh

rate availability.

EMRS(3) Programming: Reserved ¹

*

BA

2

BA

1

A12

BA

1

0

A

15 ~

A13

A

11

A

10

A

9

A

8

A7

A

6

A5

A

4

A3

A

2

A1

A0

1

0*

1

0*

*1 : EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting

the mode register during initialization.

Rev. 1.5/ Mar. 2008

15

1HY5PS121621CFP

2.3.2.3 Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command

being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termian-

tion) should be carefully controlled depending on system environment.

MRS shoud be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

EMRS: Drive(0)

DQ & DQS High; DQS Low

DQ & DQS Low; DQS High

ALL OK

Test

Need Calibration

EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

Rev. 1.5/ Mar. 2008

16

1HY5PS121621CFP

Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are

driven out by DDR2 SDRAM and drive of RDQS is depedent on EMRS bit enabling RDQS operation. In

Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS signals are driven low. In

drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS signals are driven high. In adjust

mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver charac-

teristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions.

Output driver characteristics for OCD calibration default are specified in Table x. OCD applies only to normal

full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver

characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver

characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in

order to maintain the default or calibrated value.

Off- Chip-Driver program

A9

0

A8

0

A7

0

Operation

OCD calibration mode exit

Drive(1) DQ, DQS, (RDQS) high and DQS low

Drive(0) DQ, DQS, (RDQS) low and DQS high

Adjust mode

0

1

0

1

0

1

0

1

OCD calibration default

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit

burst code to DDR2 SDRAM as in table X. For this operation, Burst Length has to be set to BL = 4 via MRS

command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0

in table X means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is

adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2

SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16

and when the limit is reached, further increment or decrement code has no effect. The default setting may be

any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must

be applied

Table X : Off- Chip-Driver Program

4bit burst code inputs to all DQs

Operation

Pull-down driver strength

DT0

0

DT1

0

DT2

0

DT3

0

Pull-up driver strength

NOP (No operation)

Increase by 1 step

Decrease by 1 step

NOP

NOP (No operation)

NOP

0

1

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

1

0

NOP

0

1

0

1

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

0

1

0

1

0

1

0

1

0

Other Combinations

Reserved

Rev. 1.5/ Mar. 2008

17

1HY5PS121621CFP

For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the fol-

lowing timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by

MRS addressing mode (ie. sequential or interleave).

OCD adjust mode

CMD

OCD calibration mode exit

NOP

EMRS

NOP

EMRS

NOP

CK

WL

WR

DQS

DQS_in

tDS

tDH

DQ_in

DM

DT0

DT2

DT3

D

T1

Drive Mode

Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance.

In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are

turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.

OCD calibration mode exit

Enter Drive mode

CMD

EMRS

NOP

EMRS

CK

Hi-Z

DQS

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)

DQs high for Drive(1)

DQs low for Drive(0)

DQ

tOIT

Rev. 1.5/ Mar. 2008

18

1HY5PS121621CFP

2.3.2.4 ODT (On Die Termination)

On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ,

DQS/DQS, RDQS/RDQS, and DM signal for x4x8 configurations via the ODT control pin. For x16 configura-

tion ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin.

The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM con-

troller to independently turn on/off termination resistance for any or all DRAM devices.

The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in

SELF REFRESH mode.

FUNCTIONAL REPRESENTATION OF ODT

VDDQ

sw1

sw2

Rval2

Rval1

DRAM

Input

Buffer

Input

Rval1

sw1

Rval2

sw2

VSSQ

Switch sw1 or sw2 is enabled by ODT pin.

Selection between sw1 or sw2 is determined by “Rtt (nominal)” in EMRS

Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.

Target Rtt (ohm) = (Rval1) / 2 or (Rval2) / 2

Rev. 1.5/ Mar. 2008

19

1HY5PS121621CFP

ODT timing for active/standby mode

T0

T1

T2

T3

T4

T5

T6

CK

CKE

ODT

t

IS

t

AOFD

t

AOND

Internal

Term Res.

RTT

t

AOF,min

AON,min

t

AOF,max

AON,max

ODT timing for powerdown mode

T0

T1

T2

T3

T4

T5

T6

CK

CKE

ODT

t

IS

t

AOFPD,max

t

AOFPD,min

Internal

Term Res.

RTT

t

AONPD,min

t

AONPD,max

Rev. 1.5/ Mar. 2008

20

1HY5PS121621CFP

ODT timing mode switch at entering power down mode

T-5

T-4

T-3

T-2

T-1

T0

T1

T2

T3

T4

CK

t

ANPD

t

IS

CKE

Entering Slow Exit Active Power Down Mode

or Precharge Power Down Mode.

t

IS

ODT

Active & Standby

mode timings to

be applied.

t

AOFD

Internal

Term Res.

RTT

t

IS

ODT

Power Down

mode timings to

be applied.

t

AOFPDmax

Internal

Term Res.

RTT

t

IS

ODT

t

AOND

Active & Standby

mode timings to

be applied.

Internal

Term Res.

RTT

t

IS

ODT

Power Down

mode timings to

be applied.

t

AONPDmax

Internal

Term Res.

RTT

Rev. 1.5/ Mar. 2008

21

1HY5PS121621CFP

ODT timing mode switch at exiting power down mode

T0

T1

T4

T5

T6

T7

T8

T9

T10

T11

CK

t

IS

t

AXPD

CKE

Exiting from Slow Active Power Down Mode

or Precharge Power Down Mode.

t

IS

ODT

Active & Standby

t

AOFD

mode timings to

be applied.

Internal

Term Res.

RTT

t

IS

ODT

Power Down

mode timings to

t

AOFPDmax

be applied.

Internal

RTT

Term Res.

t

IS

Active & Standby

mode timings to

be applied.

ODT

t

AOND

Internal

Term Res.

RTT

t

IS

ODT

Power Down

mode timings to

be applied.

t

AONPDmax

Internal

RTT

Term Res.

Rev. 1.5/ Mar. 2008

22

1HY5PS121621CFP

2.4 Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge

of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row address A0

through A15 is used to determine which row to activate in the selected bank. The Bank Activate command

must be applied before any Read or Write operation can be executed. Immediately after the bank active

command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W

command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be

programmed into the device to delay when the R/W command is internally issued to the device. The additive

latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are sup-

ported. Once a bank has been activated it must be precharged before another Bank Activate command can

be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-

tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-

mined by the RAS cycle time of the device (t ). The minimum time interval between Bank Activate

RC

commands is t

.

RRD

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2

T0

T1

T2

T3

Tn

Tn+1

Tn+2

Tn+3

. . . . . . . . . .

CK / CK

Internal RAS-CAS delay (>= t_RCDmin

Bank A

)

Bank B

Col. Addr.

Bank A

Row Addr.

Bank A

Bank B

Bank A

Addr.

Bank B

Addr.

. . . . . . . . . .

ADDRESS

Col. Addr.

Row Addr.

CAS-CAS delay time (t_CCD

)

tRCD =1

additive latency delay (_AL

Read Begins

RAS - RAS delay time (>= t_RRD

)

Bank A

Post CAS

Read

Bank B

Post CAS

Read

Bank B

Activate

Bank A

Activate

Bank B

Precharge

Bank A

Activate

Bank A

Precharge

. . . . . . . . . .

COMMAND

Bank Active (>= t_RAS

)

Bank Precharge time (>= t_RP

)

: “H” or “L”

RAS Cycle time (>= t_RC

)

Rev. 1.5/ Mar. 2008

23

1HY5PS121621CFP

2.5 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS

high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether

the access cycle is a read operation (WE high) or a write operation (WE low).

The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a

serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted

to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of

2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addres-

sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-

bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column

address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and

fourth access will also occur within this group segment, however, the burst order is a function of the starting

address, and the burst sequence.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However,

in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by

a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to

CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Rev. 1.5/ Mar. 2008

24

1HY5PS121621CFP

2.5.1 Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the

RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the

time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of

AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater

than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where

read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL

allow seamless bursts (refer to semaless operation timing diagram examples in Read burst and Wirte burst section)

Examples of posted CAS operation

Example 1 Read followed by a write to the same bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK/CK

CMD

Write

A-Bank

Active

A-Bank

Read

A-Bank

WL = RL -1 = 4

CL = 3

AL = 2

DQS/DQS

DQ

> = tRCD

RL = AL + CL = 5

Dout3

Din0

Din1

Din2

Din3

Dout2

Dout0

Dout1

> = tRAC

Example 2 Read followed by a write to the same bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK/CK

CMD

AL = 0

Read

A-Bank

Write

A-Bank

Active

A-Bank

CL = 3

WL = RL -1 = 2

DQS/DQS

DQ

> = tRCD

RL = AL + CL = 3

Dout2

Dout3

Din0

Din1

Din2

Din3

Dout0

Dout1

> = tRAC

Rev. 1.5/ Mar. 2008

25

1HY5PS121621CFP

2.5.2 Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from

memory locations (read cycle). The parameters that define how the burst mode will operate are burst

sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst

mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for

ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the

address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write

operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode

operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is lim-

ited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop com-

mand is not supported on DDR2 SDRAM devices.

Burst Length and Sequence

Burst Length

Starting Address (A2 A1 A0)

Sequential Addressing (decimal)

0, 1, 2, 3

Interleave Addressing (decimal)

0, 1, 2, 3

0 0 0

0 0 1

0 1 0

0 1 1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1, 2, 3, 0

1, 0, 3, 2

4

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

Note: Page length is a function of I/O organization and column addressing

Rev. 1.5/ Mar. 2008

26

1HY5PS121621CFP

2.5.3 Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the

rising edge of the clock. The address inputs determine the starting column address for the burst. The delay

from the start of the command to when the data from the first cell appears on the outputs is equal to the

value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data

(DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data

strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source

synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined

by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the

Extended Mode Register Set (1)(EMRS(1)).

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on

the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in

system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In

single

ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at

VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and

its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.

Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must

be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.

t

CL

CH

CK

DQS

DQS/DQS

DQ

t

RPRE

RPST

Q

t

DQSQmax

t

DQSQmax

t

QH

Figure YY-- Data output (read) timing

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

Posted CAS

READ A

NOP

=< t

DQSCK

DQS/DQS

AL = 2

CL =3

RL = 5

DQs

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

Rev. 1.5/ Mar. 2008

27

1HY5PS121621CFP

Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

READ A

NOP

=< t

DQSCK

DQS/DQS

DQs

CL =3

RL = 3

DOUT A₀

DOUT A₄

DOUT A₁

DOUT A₂

DOUT A₃

DOUT A₅

DOUT A₆

DOUT A₇

Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4

T0

T1

Tn-1

Tn

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

CK/CK

CMD

Post CAS

READ A

Post CAS

WRITE A

NOP

t

(Read to Write turn around time)

RTW

DQS/DQS

DQ’s

RL =5

WL = RL - 1 = 4

DOUT A₀

DIN A₀

DOUT A₁

DOUT A₂

DOUT A₃

DIN A₁

DIN A₂

DIN A₃

The minimum time from the burst read command to the burst write command is defined by a read-to-write-

turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.

Rev. 1.5/ Mar. 2008

28

1HY5PS121621CFP

Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

Post CAS

READ B

Post CAS

READ A

NOP

DQS/DQS

DQs

CL =3

AL = 2

RL = 5

DOUT A₀

DOUT B₀

DOUT A₁

DOUT A₂

DOUT A₃

DOUT B₁

DOUT B₂

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4

operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different

banks as long as the banks are activated.

Rev. 1.5/ Mar. 2008

29

1HY5PS121621CFP

Reads interrupted by a read

Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read inter-

rupt is not allowed.

Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)

CK/CK

Read B

Read A

NOP

CMD

DQS/DQS

DQs

A0

A1

A2

A3

B0

B1

B2

B3

B4

B5

B6

B7

Note

1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write

command or Precharge command is prohibited.

3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read

burst interrupt timings are prohibited.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with Auto Precharge enabled is not allowed to interrupt.

6. Read burst interruption is allowed by another Read with Auto Precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced

to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst

length set in the mode register and not the actual burst (which is shorter because of interrupt).

Rev. 1.5/ Mar. 2008

30

1HY5PS121621CFP

2.5.4 Burst Write Operation

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising

edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined

by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven

low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins

at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write

cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is

completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins

will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the com-

pletion of the burst write to bank precharge is the write recovery time (WR).

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system

design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single

ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.

In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-

plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that

when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied

externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.

t

DQSL

DQSH

DQS

DQS/

DQS

t

WPST

WPRE

DQ

DM

D

t

DH

DS

t

DS

DMin

Data input (write) timing

Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4

T0

CK/CK

T1

T2

T3

T4

T5

T6

T7

Tn

CMD ^{Posted CAS}

NOP

Precharge

WRITE A

Completion of

the Burst Write

DQS/DQS

DQs

< = t

DQSS

> = WR

WL = RL - 1 = 4

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Rev. 1.5/ Mar. 2008

31

1HY5PS121621CFP

Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

Tn

CK/CK

NOP

Precharge

NOP

Bank A

Activate

WRITE A

CMD

Completion of

the Burst Write

< = t

DQSS

DQS/

DQS

WL = RL - 1 = 2

> = tRP

> = WR

DQs

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK/CK

CMD

Write to Read = CL - 1 + BL/2 + tWTR

Post CAS

READ A

NOP

DQS

DQS/

DQS

CL = 3

AL = 2

WL = RL - 1 = 4

RL =5

> = tWTR

DQ

DIN A₀

DOUT A₀

DIN A₁

DIN A₂

DIN A₃

The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +

tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from

the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.

Rev. 1.5/ Mar. 2008

32

1HY5PS121621CFP

Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

Post CAS

Write B

Post CAS

Write A

NOP

DQS

DQS/

DQS

WL = RL - 1 = 4

DQ’s

DIN B₀

DIN B₁

DIN B₂

DIN B₃

DIN A₀

DIN A₁

DIN A₂

DIN A₃

The seamless burst write operation is supported by enabling a write command every other clock for BL = 4

operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different

banks as long as the banks are activated

Rev. 1.5/ Mar. 2008

33

1HY5PS121621CFP

Writes interrupted by a write

Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write inter-

rupt is not allowed.

Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)

CK/CK

NOP

Write A

Write B

NOP

CMD

NOP

DQS/DQS

DQs

A2

B2

B3

B4

B5

B6

B7

A0

A1

A3

B0

B1

Notes:

1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read

command or Precharge command is prohibited.

3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write

burst interrupt timings are prohibited.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with Auto Precharge enabled is not allowed to interrupt.

6. Write burst interruption is allowed by another Write with Auto Precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced

to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts

with the rising clock after the un-interrupted burst end and not from the end of actual burst end.

Rev. 1.5/ Mar. 2008

34

1HY5PS121621CFP

2.5.5 Write data mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent

with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and

though used in a uni-directional manner, is internally loaded identically to data bits to insure matched sys-

tem timing. DM of x4 and x16 bit organization is not used during read cycles. However DM of x8 bit organi-

zation can be used as RDQS during read cycles by EMRS(1) settng.

Data Mask Timing

DQS/

DQS

DQ

DM

tDS tDH

Data Mask Function, WL=3, AL=0, BL = 4 shown

Case 1 : min t^DQSS

CK

Write

COMMAND

tWR

tDQSS

DQS/DQS

DQ

DM

Case 2 : max t^DQSS

tDQSS

DQS/DQS

DQ

DM

Rev. 1.5/ Mar. 2008

35

1HY5PS121621CFP

2.6 Precharge Operation

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-

mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-

charge Command can be used to precharge each bank independently or all banks simultaneously. Three

address bits A10, BA0 and BA1 for 512Mb are used to define which bank to precharge when the command is

issued.

Bank Selection for Precharge by Address Bits

A10

LOW

HIGH

BA1

LOW

BA0

LOW

Precharged Bank(s)

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

All Banks

Remarks

LOW

HIGH

LOW

HIGH

DON’T CARE

Burst Read Operation Followed by Precharge

Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks

For the earliest possible precharge, the precharge command may be issued on the rising edge which is

“Additive latency(AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to

the same bank after the RAS precharge time (t ). A precharge command cannot be issued until t

is sat-

RP

RAS

isfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock

egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to

Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge com-

mand. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.

Rev. 1.5/ Mar. 2008

36

1HY5PS121621CFP

Example 1: Burst Read Operation Followed by Precharge:

RL = 4, AL = 1, CL = 3, BL = 4, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Bank A

Active

Post CAS

READ A

NOP

Precharge

NOP

AL + BL/2 clks

DQS/DQS

DQ’s

> = t

RP

CL = 3

AL = 1

RL =4

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

> = t

RAS

CL =3

> = t

RTP

Example 2: Burst Read Operation Followed by Precharge:

RL = 4, AL = 1, CL = 3, BL = 8, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Post CAS

READ A

NOP

Precharge A

NOP

AL + BL/2 clks

DQS/DQS

DQ’s

CL = 3

AL = 1

RL =4

DOUT A₄

DOUT A₀

DOUT A₅

DOUT A₆

DOUT A₇

DOUT A₁

DOUT A₂

DOUT A₃

> = t

RTP

second 4-bit prefetch

first 4-bit prefetch

Rev. 1.5/ Mar. 2008

37

1HY5PS121621CFP

Example 3: Burst Read Operation Followed by Precharge:

RL = 5, AL = 2, CL = 3, BL = 4, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Bank A

Activate

Posted CAS

READ A

Precharge A

NOP

AL + BL/2 clks

DQS/DQS

DQ’s

> = t

RP

AL = 2

CL =3

RL =5

> = t

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =3

RAS

> = t

RTP

Example 4: Burst Read Operation Followed by Precharge:

RL = 6, AL = 2, CL = 4, BL = 4, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Bank A

Activate

Post CAS

READ A

Precharge A

NOP

AL + BL/2 Clks

DQS/DQS

DQ’s

> = t

RP

AL = 2

CL =4

RL = 6

> = t

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =4

RAS

> = t

RTP

Rev. 1.5/ Mar. 2008

38

1HY5PS121621CFP

Example 5: Burst Read Operation Followed by Precharge:

RL = 4, AL = 0, CL = 4, BL = 8, t

> 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Bank A

Activate

Post CAS

READ A

NOP

Precharge A

AL + 2 Clks + max{tRTP;2 tCK}*

DQS/DQS

> = t

RP

CL =4

RL = 4

AL = 0

DQ’s

DOUT A₀

DOUT A₄

DOUT A₁

DOUT A₂

DOUT A₃

DOUT A₅

DOUT A₆

DOUT A₇

> = t

RAS

> = t

RTP

second 4-bit prefetch

first 4-bit prefetch

* : rounded to next interger

Rev. 1.5/ Mar. 2008

39

1HY5PS121621CFP

Burst Write followed by Precharge

Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge

Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion

of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.

Example 1: Burst Write followed by Precharge: WL = (RL-1) =3

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

CMD

Posted CAS

WRITE A

NOP

Precharge A

NOP

Completion of the Burst Write

> = WR

DQS/DQS

DQs

WL = 3

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4

T0

T1

T2

T3

T4

T5

T6

T7

T 9

CK/CK

CMD

Posted CAS

WRITE A

NOP

Precharge A

NOP

Completion of the Burst Write

> = t_WR

DQS/DQS

DQs

WL = 4

DIN A₀

DIN A₁

DIN A₂

DIN A₃

Rev. 1.5/ Mar. 2008

40

1HY5PS121621CFP

2.7 Auto Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the

Precharge command or the auto-precharge function. When a Read or a Write command is given to the

DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank

to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If

A10 is low when the READ or WRITE command is issued, then normal Read or Write burst operation is

executed and the bank remains active at the completion of the burst sequence. If A10 is high when the

Read or Write command is issued, then the auto-precharge function is engaged. During auto-precharge, a

Read command will execute as normal with the exception that the active bank will begin to precharge on

the rising edge which is CAS latency (CL) clock cycles before the end of the read burst.

Auto-precharge is also implemented during Write commands. The precharge operation engaged by the

Auto precharge command will not begin until the last data of the burst write sequence is properly stored in

the memory array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles

(dependent upon CAS latency) thus improving system performance for random data access. The RAS

lockout circuit internally delays the Precharge operation until the array restore operation has been com-

pleted (tRAS satisfied) so that the auto precharge command may be issued with any read or write com-

mand.

Burst Read with Auto Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The

DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than

the read with AP command if tRAS(min) and tRTP are satisfied.

If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until

tRAS(min) is satisfied.

If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until

tRTP(min) is satisfied.

In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge

happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP

to the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from

Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where “*” means: “rounded up to the next integer”.

In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.

A new bank activate (command) may be issued to the same bank if the following two conditions are satis-

fied simultaneously.

(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Rev. 1.5/ Mar. 2008

41

1HY5PS121621CFP

Example 1: Burst Read Operation with Auto Precharge:

RL = 4, AL = 1, CL = 3, BL = 8, t

<= 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

Bank A

Activate

Post CAS

READ A

NOP

CMD

Autoprecharge

AL + BL/2 clks

> = t

RP

DQS/DQS

CL = 3

AL = 1

RL =4

DQ’s

DOUT A₄

DOUT A₀

DOUT A₅

DOUT A₆

DOUT A₇

DOUT A₁

DOUT A₂

DOUT A₃

> = t

RTP

second 4-bit prefetch

first 4-bit prefetch

t

RTP

Precharge begins here

Example 2: Burst Read Operation with Auto Precharge:

RL = 4, AL = 1, CL = 3, BL = 4, t

> 2 clocks

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T 8

CK/CK

Bank A

Activate

Post CAS

READ A

Autoprecharge

NOP

CMD

> = AL + tRTP + tRP

DQS/DQS

DQ’s

CL = 3

AL = 1

RL =4

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

4-bit prefetch

t

RP

RTP

Precharge begins here

Rev. 1.5/ Mar. 2008

42

1HY5PS121621CFP

Example 3: Burst Read with Auto Precharge Followed by an activation to the Same

Bank(tRC Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

<= 2 clocks)

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

A10 = 1

Bank A

Activate

Post CAS

READ A

NOP

> = tRAS(min)

Auto Precharge Begins

DQS/DQS

DQ’s

> = t_RP

AL = 2

CL =3

RL = 5

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =3

> = t_RC

Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same

Bank(tRP Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

<= 2 clocks)

RTP

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

A10 = 1

Bank A

Activate

Post CAS

READ A

NOP

> = tRAS(min)

Auto Precharge Begins

DQS/DQS

DQ’s

> = t_RP

AL = 2

CL =3

RL = 5

DOUT A₀

DOUT A₁

DOUT A₂

DOUT A₃

CL =3

> = t_RC

Rev. 1.5/ Mar. 2008

43

1HY5PS121621CFP

Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The

DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write

recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be

reactivated if the following two conditions are satisfied.

(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, BL = 4, tRP=3

T0

T1

T2

T3

T4

T5

T6

T7

Tm

CK/CK

A10 = 1

Bank A

Active

Post CAS

NOP

CMD_{WRA BankA}

NOP

Auto Precharge Begins

NOP

Completion of the Burst Write

DQS/DQS

DQs

> = t_RP

> = WR

WL =RL - 1 = 2

DIN A₀

DIN A₁

DIN A₂

DIN A₃

> = t_RC

Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, BL = 4, tRP=3

T0

T3

T4

T5

T6

T7

T8

T9

T12

CK/CK

A10 = 1

Bank A

Active

Post CAS

NOP

CMD_{WRA Bank A}

NOP

Auto Precharge Begins

NOP

Completion of the Burst Write

DQS/DQS

DQs

> = WR

WL =RL - 1 = 4

> = t_RP

DIN A₀

DIN A₁

DIN A₂

DIN A₃

> = t_RC

Rev. 1.5/ Mar. 2008

44

1HY5PS121621CFP

2.8 Refresh Commands

DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of

two ways: by an explicit Auto-Refresh command, or by an internally timed event in SELF REFRESH mode.

Dividing the number of device rows into the rolling 64ms interval, tREFI, which is a guideline to controllers for

distributed refresh timing. For example, a 512Mb DDR2 SDRAM has 8192 rows resulting in a tREFI of 7.8㎲.

To avoid excessive interruptions to the memory controller, higher density DDR2 SDRAMS maintain 7.8㎲

average refresh time and perform multiple internal refresh bursts. In these cases, the refresh recovery times,

tRFC an tXSNR are extended to accomodate these internal operations.

2.8.1 Auto Refresh Command

AUTO REFRESH is used during normal operation of the DDR2 SDRAM. This command is nonpersistent, so

it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command.

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the

Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Pre-

charge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the

device, supplies the bank address during the refresh cycle. No control of the external address bus is required

once this cycle has started.

When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A

delay between the Refresh command (REF) and the next Activate command or subsequent Refresh com-

mand must be greater than or equal to the Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute

refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2

SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh

command is 9 * tREFI.

T0

T1

T2

T3

Tm

Tn

Tn + 1

CK/CK

High

> = t

RFC

CKE

RFC

RP

Precharge

NOP

REF

NOP

ANY

NOP

CMD

2.8.2 Self Refresh Operation

The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mod, the DDR2 SDRAM retains data without external clocking.

The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh

Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.

ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS

command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode.

The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon existing Self

Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are

“don’t care”. The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once

it enters Self Refresh mode.The clock is internally disabled during Self Refresh Operation to save power. The

minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the

external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however,

the clock must be restarted and stable before the device can exit Self Refresh operation.

Rev. 1.5/ Mar. 2008

45

1HY5PS121621CFP

The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable

prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than

the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must

remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh,

the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires.NOP or deselect commands

must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be

turned off during tXSRD.

The Use of Self Refresh mode introduce the possibility that an internally timed refresh event can be missed

when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires

a minimum of one extra auto refresh command before it is put back into Self Refresh mode.

T3

T4

T5

T6

T0

T1

T2

Tm

Tn

tCK

tCH tCL

CK

> = tXSNR

> = tXSRD

tRP*

CKE

ODT

tIS

tAOFD

tIS

tIH

tIS

Self

Refresh

Valid

NOP

CMD

- Device must be in the “All banks idle” state prior to entering Self Refresh mode.

- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again

when tXSRD timing is satisfied.

- tXSRD is applied for a Read or a Read with autoprecharge command

- tXSNR is applied for any command except a Read or a Read with autoprecharge command.

Rev. 1.5/ Mar. 2008

46

1HY5PS121621CFP

2.9 Power-Down

Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE

is not allowed to go low while mode register or extended mode register command time, or read or write operation

is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-

precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those opera-

tions. Timing diagrams are shown in the following pages with details for entry into power down.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting

power-down mode for proper read operation.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon

entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit

active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of

the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must

be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect com-

mand). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied

with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined

at AC spec table of this data sheet.

Basic Power Down Entry and Exit timing diagram

CK/CK

t_IH

t_IS

t_IH

t_IS

t_IH

t_ISt_IH

t_IS

CKE

VALID

t_CKE

NOP

VALID

NOP

Command

t_XP,t_XARD,

t_XARDS

t_CKE

Enter Power-Down mode

Don’t Care

Exit Power-Down mode

Rev. 1.5/ Mar. 2008

47

1HY5PS121621CFP

Read to power down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CK

Read operation starts with a read command and

CKE should be kept high until the end of burst operation.

CMD

CKE

DQ

RD

BL=4

AL + CL

Q

DQS

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CMD

CKE

RD

BL=8

CKE should be kept high until the end of burst operation.

AL + CL

DQ

Q

DQS

Read with Autoprecharge to power down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

CK

CMD

RDA

PRE

BL=4

AL + BL/2

with tRTP = 7.5ns

& tRAS min satisfied

CKE should be kept high

until the end of burst operation.

CKE

DQ

AL + CL

Q

DQS

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6 Tx+7

Tx+8

Tx+9

Start internal precharge

CMD

RDA

PRE

AL + BL/2

BL=8

with tRTP = 7.5ns

CKE should be kept high

& tRAS min satisfied

until the end of burst operation.

CKE

DQ

AL + CL

Q

DQS

Rev. 1.5/ Mar. 2008

48

1HY5PS121621CFP

Write to power down entry

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tx

Tx+1

Tx+2

Ty

Ty+1

Ty+2

Ty+3

CK

CMD

WR

BL=4

CKE

WL

D

DQ

DQS

tWTR

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx

Tx+1 Tx+2

Tx+3

Tx+4

CMD

CKE

DQ

WR

BL=8

WL

D

tWTR

DQS

Write with Autoprecharge to power down entry

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tx

Tx+1

Tx+2

Tx+3 Tx+4

Tx+5

Tx+6

CK

CMD

WRA

PRE

BL=4

CKE

DQ

WL

D

WR*1

DQS

T0

T1

Tm

Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx

Tx+1 Tx+2

Tx+3

Tx+4

CK

CMD

WRA

PRE

BL=8

CKE

DQ

WL

D

WR*1

DQS

* 1: WR is programmed through MRS

Rev. 1.5/ Mar. 2008

49

1HY5PS121621CFP

Refresh command to power down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

CMD

REF

CKE can go to low one clock after an Auto-refresh command

CKE

Active command to power down entry

CMD

CKE

ACT

CKE can go to low one clock after an Active command

Precharge/Precharge all command to power down entry

PR or

PRA

CMD

CKE can go to low one clock after a Precharge or Precharge all command

CKE

MRS/EMRS command to power down entry

MRS or

EMRS

CMD

CKE

tMRD

Rev. 1.5/ Mar. 2008

50

1HY5PS121621CFP

2.10 Asynchronous CKE Low Event

DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asyn-

chronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array. If

this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks.

Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initial-

ized (steps 4 thru 13) as described in initializaliation sequence. DRAM is ready for normal operation after the ini-

tialization sequence. See AC timing parametric table for tDelay specification

Stable clocks

tCK

CK#

CK

tDelay

CKE

CKE asynchronously drops low

Clocks can be turned

off after this point

Rev. 1.5/ Mar. 2008

51

1HY5PS121621CFP

Input Clock Frequency Change during Precharge Power Down

DDR2 SDRAM input clock frequency can be changed under following condition:

DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level.

A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input

clock frequency is allowed to change only within minimum and maximum operating frequency specified for the

particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels.

Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power

down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new

clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During

DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock

frequency.

Clock Frequency Change in Precharge Power Down Mode

T0

T1

T2

T4

Tx

Tx+1

Ty

Ty+1

Ty+2 Ty+3 Ty+4

Tz

CK

DLL

RESET

NOP

Valid

CMD

CKE

Frequency Change

Occurs here

200 Clocks

ODT

tRP

tAOFD

tXP

ODT is off during

DLL RESET

Stable new clock

before power down exit

Minmum 2 clocks

required before

changing frequency

Rev. 1.5/ Mar. 2008

52

1HY5PS121621CFP

2.11 No Operation Command

The No Operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state.

The purpose of the No Operation command (NOP) is to prevent the DDR2 SDRAM from registering any

unwanted commands between operations. A No Operation command is registered when CS is low with

RAS, CAS, and WE held high at the rising edge of the clock. A No Operation command will not terminate a

previous operation that is still executing, such as a burst read or write cycle.

2.12 Deselect Command

The Deselect command performs the same function as a No Operation command. Deselect command

occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become

don’t cares.

Rev. 1.5/ Mar. 2008

53

1HY5PS121621CFP

3. Truth Tables

3.1 Command truth table.

CKE

BA0

Function

CS

RAS

CAS

WE BA1 A15-A11 A10 A9 - A0 Notes

BA2

Current

Cycle

(Extended) Mode Register Set

Refresh (REF)

H

L

H

L

H

L

H

L

H

X

H

L

BA

X

OP Code

1,2

1

X

Self Refresh Entry

L

X

1

X

H

L

X

H

L

Self Refresh Exit

L

H

X

1,7

Single Bank Precharge

Precharge all Banks

Bank Activate

H

X

BA

X

L

H

X

1,2

1

L

H

L

BA

Row Address

1,2

Write

H

X

H

X

H

BA Column

L

H

L

Column 1,2,3,

Column 1,2,3

Write with Auto Precharge

Read

L

H

X

H

X

H

Read with Auto-Precharge

No Operation

L

H

X

H

X

H

X

H

X

1

Device Deselect

Power Down Entry

Power Down Exit

H

L

X

1,4

H

1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.

2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode

Register.

3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-

rupted by a Write" in section 2.2.4 for details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements outlined in section 2.2.7.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See

section 2.2.2.4.

6. “X” means “H or L (but a defined logic level)”.

7. Self refresh exit is asynchronous.

Rev. 1.5/ Mar. 2008

54

1HY5PS121621CFP

3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions

CKE

Command (N) ³

Current State ²

Action (N) ³

Notes

Previous Cycle ¹Current Cycle ¹

RAS, CAS, WE, CS

(N-1)

(N)

L

X

Maintain Power-Down

Power Down Exit

11, 13, 15

4, 8, 11,13

11, 15

Power Down

L

H

L

DESELECT or NOP

X

Maintain Self Refresh

Self Refresh Exit

Self Refresh

Bank(s) Active

All Banks Idle

L

H

L

DESELECT or NOP

REFRESH

4, 5,9

H

Active Power Down Entry

Precharge Power Down Entry

Self Refresh Entry

4,8,10,11,13

4, 8, 10,11,13

6, 9, 11,13

7

L

H

Refer to the Command Truth Table

Notes:

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.

3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).

4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t_XSNRperiod.

Read commands may be issued only after t_XSRD(200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or

Precharge operations are in progress. See section 2.2.9 "Power Down" and 2.2.8 "Self Refresh Command" for a detailed list of

restrictions.

11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See

section 2.2.2.4.

13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh

requirements outlined in section 2.2.7.

14. CKE must be maintained high while the SDRAM is in OCD calibration mode .

15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or

low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).

3.3 DM Truth Table

Name (Functional)

Write enable

Write inhibit

DM

L

DQs

Note

1

Valid

H

X

1

1. Used to mask write data, provided coinsident with the corresponding data

Rev. 1.5/ Mar. 2008

55

1HY5PS121621CFP

4. Operating Conditions

4.1 Absolute Maximum DC Ratings

Symbol

VDD

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Units

V

Notes

1

- 1.0 V ~ 2.3 V

VDDQ

VDDL

- 0.5 V ~ 2.3 V

-55 to +100

V

1

V_INV_OUT

,

V

T_STG

°C

Input Leakage Current; any input 0V <=Vin<=VDD

(All other balls not under test = 0V

IL

-2 to2

uA

Output Leakage Current; 0V <= Vout <= VDDQ

(DQ and ODT disable)

IOZ

-5 to 5

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case temperture on the center/top side of the DRAM. For the Measurement Condition, please refer to

JESD51-2 standard.

4.2 Operating Temperature Condition

Symbol

Toper

Parameter

Operating Temperature

Rating

0 to 85

Units

Notes

1,2

°C

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,

please refer to JESD51-2 standard.

2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature

rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During

operation, the DRAM case temperature must be maintained between 0 ~ 85°C under all other specification parameters. However,

in some applications, it is desirable to operate the DRAM up to 95°C case temperature. Therefore 2 spec options may exist.

1) Supporting 0 - 85°C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature options.

2) Supporting 0 - 85°C and being able to extend to 95°C with doubling auto-refresh commands in frequency to a 32 ms

period(tRFI=3.9us).

Note; Self-refresh period within the above DRAM is hard coded at 64ms(tREFI= 7.8us). Therfore, it is imperative that the system ensures

the DRAM is at or below 85°C case temperature before initiating self-refresh operation.

Rev. 1.5/ Mar. 2008

56

HY5PS121621CFP

4.3 Thermal Characteristics

PARAMETER

Description

Value

115.0

117.4

71.9

UNIT

℃

NOTES

TC

TJ

Case Temperature

7

Junction Temperature

Thermal resistance junction to ambient

℃

Theta_JA

1,2,3,4,5,7

℃/W

Theta_JC

Thermal resistance junction to case

3.9

1,2,6,7

Note:

1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD-51 standared.

2. Theta_JA and Theta_JC must be measured with the high effective thermal conductivity test board defined in JESD51-7

3. Airflow information must be deocumented for Theta_JA.

4. Theta_JA should only be used for comparing the thermal performance of signle packages and not for system related junction.

5. Theta_JA is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure

as described in JESD-51. The environment is sometimes referred to as “still-air” although natural convection causes the air to move.

6. Theta_JC case surface is defined as the “outside surface of the package (case) closest to the chip mounting area when that same

surface is properly hear sunk” so as to minimize temperature variation across that surface.

7. Test condition : Voltage 2.1V(Maximum voltage) / Frequency : 500Mhz

Rev 1.5/ Mar. 2008

57

1HY5PS121621CFP

5. AC & DC Operating Conditons

5.1 DC Operation Conditions

5.1.1 Recommended DC Operating Conditions (SSTL_1.8)

Rating

Symbol

Parameter

Units

Notes

Min.

Typ.

Max.

VDD

VDDL

VDDQ

VDD

1.7

1.8

1.9

V

5

Supply Voltage

1.7

1.8

1.9

4, 5

6

Supply Voltage for DLL

Supply Voltage for Output

Supply Voltage

V

1.9

2.0

2.1

V

VDDL

VDDQ

VREF

VTT

1.9

2.0

2.1

V

4, 6

1, 2

3

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.9

2.0

2.1

V

0.49*VDDQ

VREF-0.04

0.50*VDDQ

VREF

0.51*VDDQ

VREF+0.04

mV

V

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must

be less than or equal to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together

5. 400/350/300Mhz support

6. 500/450Mhz support

5.1.2 ODT DC electrical characteristics

PARAMETER/CONDITION

SYMBOL

Rtt1(eff)

Rtt2(eff)

Rtt3(eff)

delta VM

MIN

NOM

MAX

UNITS NOTES

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm

Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm

Deviation of VM with respect to VDDQ/2

60

75

90

ohm

1

120 150

40

-6

180 ohm

60

6

50

ohm

%

Note 1: Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply V_IH(ac) and V_IL(ac) to test pin separately, then measure current I(V_IH

(ac)) and I( V_IL(ac)) respectively. V_IH(ac), V_IL(ac), and VDDQ values defined in SSTL_18

Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.

V_IH(ac) - V_IL(ac)

Rtt(eff) =

I(V_IH(ac)) - I(V_IL(ac))

2 x Vm

- 1

x 100%

delta VM =

VDDQ

Rev. 1.5/ Mar. 2008

58

1HY5PS121621CFP

5.2 DC & AC Logic Input Levels

5.2.1 Input DC Logic Level

Symbol

Parameter

Min.

Max.

Units

Notes

V_IH(dc)

VREF + 0.125

VDDQ + 0.3

V

dc input logic high

dc input logic low

V_IL(dc)

- 0.3

VREF - 0.125

V

5.2.2 Input AC Logic Level

Symbol

_IH(ac)

V_IL(ac)

Parameter

Min.

Max.

Units

V

VREF + 0.25

-

V

ac input logic high

ac input logic low

VREF - 0.25

V

5.2.3 AC Input Test Conditions

Symbol

V_REF

Condition

Input reference voltage

Value

Units

Notes

0.5 * V_DDQ

1.0

V

1

V_SWING(MAX)

SLEW

Input signal maximum peak to peak swing

Input signal minimum slew rate

1

1.0

V/ns

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V_REFlevel applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V_REFto V_IH(ac)min for rising edges and the range

from V_REFto V_IL(ac)max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

V

DDQ

IH(ac)

IH(dc)

REF

min

V

SWING(MAX)

max

IL(dc)

IL(ac)

SS

delta TF

delta TR

Rising Slew =

V

min - V

REF

V

-

V

max

IL(ac)

IH(ac)

REF

Falling Slew =

delta TR

delta TF

< Figure : AC Input Test Signal Waveform >

Rev. 1.5/ Mar. 2008

59

1HY5PS121621CFP

5.2.4 Differential Input AC logic Level

Symbol

Parameter

Min.

0.5

Max.

Units

V

Notes

1

V_ID(ac)

VDDQ + 0.6

ac differential input voltage

ac differential cross point voltage

V_IX(ac)

0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175

V

2

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and

UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS

or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V

IL(DC).

V

DDQ

V

TR

Crossing point

V

ID

V

IX or OX

V

CP

V

SSQ

< Differential signal levels >

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,

LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)

- V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in

VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.

5.2.5 Differential AC output parameters

Symbol

Parameter

Min.

Max.

Units

V

Notes

1

V_OX(ac)

0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125

ac differential cross point voltage

Notes:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations

in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Rev. 1.5/ Mar. 2008

60

1HY5PS121621CFP

5.2.6 Overshoot/Undershoot Specification

AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE,

CKE, ODT

Specification

Parameter

Maximum peak amplitude allowed for overshoot area (See Figure 1):

Maximum peak amplitude allowed for undershoot area (See Figure 1):

Maximum overshoot area above VDD (See Figure1).

0.9V

0.45 V-ns

Maximum undershoot area below VSS (See Figure 1).

Maximum Amplitude

Overshoot Area

VDD

Volts

(V)

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 1: AC Overshoot and Undershoot Definition for Address and Control Pins

AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK

Parameter

Specification

0.9V

Maximum peak amplitude allowed for overshoot area (See Figure 2):

Maximum peak amplitude allowed for undershoot area (See Figure 2):

Maximum overshoot area above VDDQ (See Figure 2).

Maximum undershoot area below VSSQ (See Figure 2).

0.9V

0.23 V-ns

Maximum Amplitude

Overshoot Area

VDDQ

Volts

(V)

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 2: AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins

Rev. 1.5/ Mar. 2008

61

1HY5PS121621CFP

Power and ground clamps are required on the following input only pins:

1. BA0-BA2

2. A0-A15

3. RAS

4. CAS

5. WE

6. CS

7. ODT

8. CKE

V-I Characteristics table for input only pins with clamps

Minimum Ground

Clamp Current (mA)

0

Voltage across

clamp(V)

Minimum Power

Clamp Current (mA)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

0

0.1

1.0

2.5

4.7

6.8

9.1

11.0

13.5

16.0

18.2

21.0

0.1

1.0

2.5

4.7

6.8

9.1

11.0

13.5

16.0

18.2

21.0

Rev. 1.5/ Mar. 2008

62

1HY5PS121621CFP

5.3 Output Buffer Levels

5.3.1 Output AC Test Conditions

Symbol

V_OH

Parameter

SSTL_18 Class II

V_TT+ 0.603

V_TT- 0.603

Units

V

Notes

Minimum Required Output Pull-up under AC Test Load

Maximum Required Output Pull-down under AC Test Load

Output Timing Measurement Reference Level

V_OL

V

V_OTR

0.5 * V_DDQ

V

1

1. The VDDQ of the device under test is referenced.

5.3.2 Output DC Current Drive

Symbol

I_OH(dc)

I_OL(dc)

Parameter

Output Minimum Source DC Current

Output Minimum Sink DC Current

SSTl_18 Class II

- 13.4

Units

mA

Notes

1, 3, 4

2, 3, 4

13.4

mA

1.

2.

V

_DDQ= 1.7 V; V_OUT= 1420 mV. (V_OUT- V_DDQ)/I_OHmust be less than 21 ohm for values of V_OUTbetween V_DDQand V_DDQ- 280

mV.

_DDQ= 1.7 V; V_OUT= 280 mV. V_OUT/I_OLmust be less than 21 ohm for values of V_OUTbetween 0 V and 280 mV.

V

3. The dc value of V_REFapplied to the receiving device is set to V_TT

4. The values of I_OH(dc)and I_OL(dc)are based on the conditions given in Notes 1 and 2. They are used to test device drive current

capability to ensure V_IHmin plus a noise margin and V_ILmax minus a noise margin are delivered to an SSTL_18 receiver. The

actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define

a convenient driver current for measurement.

5.3.3 OCD defalut characteristics

Description

Parameter

Min

Nom

-

Max

4

Unit

Notes

Pull-up and pull-

down mismatch

0

ohms 1,2,3

Output slew rate

Sout

1.5

5

V/ns 1,4,5,6,7

Note

1: Absolute Specifications (0°C ≤ T_CASE≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT-

Impedance measure-

must be less than 23.4 ohms for

VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.

ment condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol

values of VOUT between 0V and 280mV.

3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and

4: Slew rate measured from vil(ac) to vih(ac).

voltage.

5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew

rate as measured from AC to AC. This is guaranteed by design and characterization.

6: DRAM output slew rate specification Table.

Rev. 1.5/ Mar. 2008

63

1HY5PS121621CFP

5.4 Input/Output Capacitance

300Mhz / 400Mhz

Units

Parameter

Symbol

Min

1.0

x

Max

Input capacitance, CK and CK

CCK

2.0

pF

Input capacitance delta, CK and CK

CDCK

CI

0.25

2.0

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS, DQS

Input/output capacitance delta, DQ, DM, DQS, DQS

1.0

x

CDI

0.25

3.5

CIO

CDIO

2.5

x

0.5

Rev. 1.5/ Mar. 2008

64

1HY5PS121621CFP

6. IDD Specifications & Measurement Conditions

6.1 IDD Specifications

Symbol

IDD0

2

22

140

160

10

25

120

130

8

28

110

120

8

33

100

110

8

Units

mA

160

175

12

IDD1

IDD2P

IDD2N

80

60

50

40

50

F

55

45

35

30

IDD3P

S

20

18

13

IDD3N

120

400

320

240

8

100

380

300

160

8

60

50

W

240

200

165

8

200

170

160

8

170

150

8

IDD4

R

IDD5

IDD6

IDD7

450

420

340

320

Rev. 1.5/ Mar. 2008

65

1HY5PS121621CFP

6.2 IDD Measurement Conditions

Symbol

Conditions

Units

t

Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-

min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus

inputs are SWITCHING

mA

IDD0

IDD1

Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

t

CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W

mA

t

Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address

mA

IDD2P

IDD2N

bus inputs are STABLE; Data bus inputs are FLOATING

t

Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

t

mA

Active power-down current; All banks open; CK = CK(IDD); CKE is

LOW; Other control and address bus inputs are STABLE; Data bus inputs

are FLOATING

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

IDD3P

IDD3N

IDD4W

IDD4R

t

Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data

bus inputs are SWITCHING

mA

t

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK =

t

CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

t

AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid

commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W

t

Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD5B

IDD6

mA

Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL

t

= RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is

HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-

tern is same as IDD4R; - Refer to the following page for detailed timing conditions

mA

IDD7

Note:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combina-

tions of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin ≤ VILAC(max)

HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and

inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.

Rev. 1.5/ Mar. 2008

66

1HY5PS121621CFP

For purposes of IDD testing, the following parameters are to be utilized

Parameter

2

6

22

6

25

6

28

6

33

5

Units

CL(IDD)

tCK

t

16

15.4

15

16.8

16.5

RCD(IDD)

ns

t

60

61.6

60

61.6

59.4

RC(IDD)

t

ns

RRD(IDD)-x16

10

2

11

10

11.2

2.8

9.9

3.3

t

2.2

2.5

CK(IDD)

ns

t

46.2

70K

16

46.2

70K

15.4

105

45

70K

15

44.8

70K

16.8

105

46.2

70K

16.5

105

RASmin(IDD)

t

ns

RASmax(IDD)

t

RP(IDD)

RFC(IDD)-512Mb

t

105

Detailed IDD7

The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

t

All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and address bus

inputs are STABLE during DESELECTs. IOUT = 0mA

Rev. 1.5/ Mar. 2008

67

1HY5PS121621CFP

7. AC Timing Specifications

7.1 Timing Parameters by Speed Grade

2

22

25

28

33

Symbol

Unit Note

Parameter

min

max

min

max

min

max

min

max

min

max

DQ output access time

from CK/CK

tAC

-450

+450

-450

+450

-500

+500

-550 +550 -600

+600 ps

DQS output access time

from CK/CK

tDQSCK

-450

+450

-450

+450

-500

+500

CK high-level width

CK low-level width

tCH

tCL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55 tCK

min(tCL,

tCH)

min(tCL,

tCH)

min(tCL,

tCH)

min(tCL,

tCH)

min(tCL,

tCH)

CK half period

tHP

-

ps 19,20

CL=6 tCK

CL=5 tCK

2

-

8

-

2.2

-

8

-

2.5

-

8

-

2.8

-

8

-

ns

23

Clock cycle time

3.3

8

DQ and DM input hold

time

14,15

,16

tDH

125

50

-

125

50

-

125

50

-

175

50

-

175

50

-

ps

DQ and DM input setup

time

14,15

,16

tDS

Control & Address input

pulse width for each input

tIPW

tDIPW

tHZ

0.6

0.35

-

0.6

0.35

-

0.6

0.35

-

0.6

0.35

-

0.6

0.35

-

tCK

ps

DQ and DM input pulse

width for each input

Data-out high-impedance

time from CK/CK

tAC

max

DQS low-impedance time tLZ

tAC

min

tAC

min

tAC

min

tAC

min

tAC

min

tAC

ps

from CK/CK

(DQS)

max

DQ low-impedance time tLZ

2*tAC

min

tAC

2*tAC

min

tAC

2*tAC

min

tAC

2*tAC tAC 2*tAC

tAC

ps

from CK/CK

(DQ)

max

min

max

250

350

-

min

max

DQS-DQ skew for DQS

tDQSQ

tQHS

tQH

-

200

300

-

200

300

-

200

300

-

300

400

-

ps

21

20

and associated DQ signals

DQ hold skew factor

DQ/DQS output hold time

from DQS

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

Write command to first

DQS latching transition

WL -

0.25

WL + WL -

WL + WL - WL + WL -

WL +

0.25

tDQSS

tDQSH

tCK

0.25

0.35

0.2

0.25

0.35

0.2

0.25

0.35

0.2

0.25

0.35

0.2

DQS input high pulse

width

0.35

0.2

-

tCK

DQS input low pulse width tDQSL

DQS falling edge to CK

tDSS

setup time

Mode register set

tMRD

2

-

2

-

2

-

2

-

2

-

tCK

command cycle time

Rev. 1.5/ Mar. 2008

68

1HY5PS121621CFP

2

22

25

28

33

Symbol

Unit Note

Parameter

min

max

min

max

min

max

min

max

min

max

DQS falling edge hold time

from CK

tDSH

0.2

-

0.2

-

0.2

-

0.2

-

0.2

-

tCK

Write postamble

Write preamble

tWPST

tWPRE

0.4

0.6

-

0.4

0.6

-

0.4

0.6

-

0.4

0.6

-

0.4

0.6 tCK 18

0.35

-

tCK

Address and control input

hold time

13,15

,17

tIH

tIS

300

-

350

-

400

-

450

-

500

-

ps

Address and control input

setup time

13,15

,17

-

ps

Read preamble

Read postamble

tRPRE

tRPST

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

0.9

0.4

1.1 tCK

0.6 tCK

Active to precharge

command

tRAS

tRCD

tRFC

45

70K

45

70K

45

70K

45

70K

45

70K

ns

11

Active to Read or Write

(with and without Auto-

Precharge) delay

16

-

15.4

-

15

-

16.8

-

16.5

-

ns

Auto-Refresh to Active/Auto-

Refresh command period

105

16

-

105

15.4

61.6

-

105

15

-

105

16.8

61.6

-

105

16.5

59.4

-

ns

Precharge Command Period tRP

Active to Active/Auto-Refresh

tRC

60

command period

Active to active command

period for 2KB page

size(x16)

tRRD

10

-

11

-

10

-

11.2

-

9.9

-

ns

12

CAS to CAS command delay tCCD

2

tCK

ns

Write recovery time

tWR

12

-

12

-

15

-

15

-

15

-

Auto precharge write

tWR+

tRP

tWR+

tRP

tWR+

tRP

tWR+

tRP

tWR+

tRP

tDAL

ns

22

11

recovery + precharge time

Internal write to read

command delay

tWTR

tRTP

7.5

-

7.5

-

7.5

-

7.5

-

7.5

-

Internal read to precharge

command delay

ns

Exit self refresh to a non-read

command

tRFC +

10

tRFC +

10

tRFC +

10

tRFC +

10

tRFC +

10

tXSNR

tXSRD

tXP

ns

Exit self refresh to a read

command

200

2

-

200

2

-

200

2

-

200

2

-

200

2

-

tCK

Exit precharge power down

to any non-read command

Exit active power down to

read command

tXARD

2

9

Exit active power down to

read command

tXARD

S

8 - AL

3

8 - AL

3

8 - AL

3

7 - AL

3

6 - AL

3

tCK 9,10

tCK

(Slow exit, Lower power)

CKE minimum pulse width

(high and low pulse width)

^tCKE

Rev. 1.5/ Mar. 2008

69

1HY5PS121621CFP

2

22

25

28

33

Symbol

Unit Note

Parameter

min

max

min

max

min

max

min

max

min

max

Average periodic

Refresh Interval

tREFI

7.8

us

^tAOND

ODT turn-on delay

2

tCK

tAC

(max)

+0.7

tAC

(max)

+0.7

tAC

(min)

tAC

(min)

tAC

^tAON

ODT turn-on

tAC(min) (max) tAC(min) (max)

ns 24

(min) (max)+1

+0.7

ODT turn-on

(Power-Down

mode)

2tCK+

tAC

(max)+1

2tCK+

tAC

(max)+1

2tCK+

tAC

(max)+1

2tCK+

tAC

(max)+1

2tCK+

tAC

(min)+2

tAC

(min)+2

tAC

(min)+2

tAC

(min)+2

^tAONPD

tAC

ns

(min)+2

(max)+1

^tAOFD

^tAOF

ODT turn-off delay

ODT turn-off

2.5

tCK

tAC

(min)

tAC(max)

+0.6

tAC

(min)

tAC(max) tAC tAC(max) tAC tAC(max) tAC tAC(max)

+0.6

ns 25

(min)

+0.6

(min)

+0.6

(min)

+0.6

ODT turn-off

(Power-Down

mode)

4.5tCK

+tAC

(max)+1

4.5tCK

+tAC

(max)+1

3.5tCK

+tAC

(max)+1

3.5tCK

+tAC

(max)+1

3.5tCK

+tAC

(max)+1

tAC(min)

+2

tAC(min)

+2

tAC

(min)+2

tAC

(min)+2

tAC

(min)+2

^tAOFPD

ns

ODT to power

down entry latency

tANPD

tAXPD

tOIT

3

8

0

3

8

0

3

8

0

3

8

0

3

8

0

tCK

ns

ODT power down

exit latency

OCD drive mode

output delay

12

Minimum time

clocks remains ON

after CKE

asynchronously

drops LOW

tIS+tCK+

tIH

tIS+tCK+

tIH

tIS+tCK

+tIH

tIS+tCK

+tIH

tIS+tCK

+tIH

tDelay

ns 23

Rev. 1.5/ Mar. 2008

70

1HY5PS121621CFP

Note)

1~8 : General notes, Which may apply for all AC parameters.

9~25 : Specific Notes for dedicated AC parameters.

1. Slew Rate Measurement Levels

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for

single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between

DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not

necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to

VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to

CK - CK = +500 mV

(250mV to -500 mV for falling egdes).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or

between DQS and DQS for differential strobe.

2. DDR2 SDRAM AC timing reference load

The following fiture represents the timing reference load used in defining the relevant timing parameters of

the part. It is not intended to be either a precise representation of the typical system environment nor a depic-

tion of the actual load presented by a production tester. System designers will use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their pro-

duction test conditions (generally a coaxial transmission line terminated at the tester electronics).

VDDQ

DQ

DQS

Output

DUT

V_TT= V_DDQ/2

RDQS

Timing

reference

point

25Ω

AC Timing Reference Load

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-

ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement

(e.g. DQS) signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown below.

VDDQ

DUT

DQ

Output

DQS, DQS

V_TT= V_DDQ/2

RDQS, RDQS

25Ω

Test point

Slew Rate Test Load

Rev. 1.5/ Mar. 2008

71

1HY5PS121621CFP

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on

the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in sys-

tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In sin-

gle VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS

and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.

Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must

be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.

t

DQSL

DQSH

DQS

DQS/

DQS

t

WPST

WPRE

DQ

DM

D

t

DH

DS

t

DS

DMin

Figure -- Data input (write) timing

t

CL

CH

CK

CK/CK

DQS

DQS/DQS

DQ

t

RPRE

RPST

Q

t

DQSQmax

t

DQSQmax

t

QH

Figure -- Data output (read) timing

5. AC timings are for linear signal transitions. See System Derating for other signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They

may be guaranteed by device design or tester correlation.

7. All voltages referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-

ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full

voltage range specified.

Rev. 1.5/ Mar. 2008

72

1HY5PS121621CFP

9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be

used for fast active power down exit timing. tXARDS is expected to be used for slow active power down

exit timing where a lower power value is defined by each vendor data sheet.

10. AL = Additive Latency

11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and

tRAS(min) have been satisfied.

12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for

other slew rate values.

14. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of

1.0 V/ns. See System Derating for other slew rate values.

15. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS

signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single

ended mode. See System Derating for other slew rate values.

16. tDS and tDH (data setup and hold) derating

tbd

17. tIS and tIH (input setup and hold) derating

tbd

18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value

for this parameter, but system performance (bus turnaround) will degrade accordingly.

19. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as pro-

vided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).

For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock

source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.

20. t QH = t HP – t QHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH,

tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the

next transition, both of which are, separately, due to data pin skew and output pattern effects, and

p-channel to n-channel variation of the output drivers.

21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of

the output drivers for any given cycle.

22. t DAL = (nWR) + ( tRP/tCK):

For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the

application clock period. nWR refers to the t WR parameter stored in the MRS.

Rev. 1.5/ Mar. 2008

73

1HY5PS121621CFP

23. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode.

In case of clock frequency change during precharge power-down, a specific procedure is required as

described in section 2.9.

24. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn

on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

25. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

Rev. 1.5/ Mar. 2008

74

1HY5PS121621CFP

8. Package Dimensions(x16)

84Ball Fine Pitch Ball Grid Array Outline

10.50 +/- 0.10

A1 Ball Mark

1.20 Max.

0.34 +/- 0.05

A1 Ball Mark

1

2

3

7

8

9

84 - φ 0.50

0.80

0.80 x 8 = 6.40

note: all dimension units are Millimeters.

Rev. 1.5/ Mar. 2008

75


型号：	HY5PS121621CFP-25
厂家：	HYNIX SEMICONDUCTOR
描述：	DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, LEAD FREE, FBGA-84 时钟动态存储器双倍数据速率内存集成电路
文件：	总75页 (文件大小：970K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY5PS121621CFP-25 [HYNIX]

相关型号：

HY5PS121621CFP-28

HY5PS121621CFP-C4

HY5PS121621CFP-C4I

HY5PS121621CFP-CFP4

HY5PS121621CFP-E3

HY5PS121621CFP-E3I

HY5PS121621CFP-S5

HY5PS121621CFP-S5I

HY5PS121621CFP-S6

HY5PS121621CFP-S6I

HY5PS121621CFP-Y4

HY5PS121621CFP-Y4I