HY62KF16403E-SD70I [HYNIX]
Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
| 型号： | HY62KF16403E-SD70I |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62KF16403E Series
256Kx16bit full CMOS SRAM
Document Title
256K x 16bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
Revision History
Revision No History
Draft Date
Remark
00
Initial Draft
Dec.26.2001
Preliminary
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.00 / Dec.01
Hynix Semiconductor
HY62KF16403E Series
DESCRIPTION
FEATURES
The HY62KF16403E is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62KF16403E uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
·
-. 44pin 400mil TSOP-II (Forward)
Standby
Temperature
Current(uA)
Voltage
Operation
Current/Icc(mA)
Product No.
Speed (ns)
55/70
(V)
(°C)
SL
6
LL
15
HY62KF16403E-I 2.7~3.6
4
-40~85
Note 1. I : Industrial
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
ROW
DECODER
A4
A3
A2
A1
A0
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
I/O1
I/O8
I/O9
I/O16
/OE
/UB
/LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
/CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
/WE
A17
A16
A15
A14
A13
MEMORY ARRAY
256K x 16
A17
/CS
A8
A9
A10
A11
A12
/OE
/LB
/UB
TSOPII
(Forward)
/WE
PIN DESCRIPTION
Pin Name
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control (I/O1~I/O8)
Pin Name
I/O1~I/O16
A0~A17
Vcc
Pin Function
Data Inputs/Outputs
Address Inputs
Power (2.7~3.6V)
Ground
/CS
/WE
/OE
/LB
Vss
/UB
Upper Byte Control (I/O9~I/O16) NC
No Connection
Rev.00 / Dec.01
2
HY62KF16403E Series
ORDERING INFORMATION
Part No.
HY62KF16403E-SD(I)
HY62KF16403E-DD(I)
Speed
55/70
55/70
Power
SL-part
LL-part
Temp.
Package
TSOP-II
TSOP-II
I
I
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Rating
Unit
V
V
°C
°C
Remark
-0.3 to VCC+0.3V
-0.3 to 4.6
-40 to 85
-55 to 150
1.0
HY62KF16403E-I
PD
W
TSOLDER
Ball Soldering Temperature & Time
260 · 10
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O Pin
/CS
H
/WE
/OE /LB /UB
Mode
Power
Standby
Active
I/O1~I/O8
I/O9~I/O16
X
H
X
X
H
X
X
X
H
L
H
L
X
X
H
H
L
Deselected
High-Z
High-Z
L
Output Disabled
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
DOUT
DOUT
High-Z
DIN
L
L
H
L
L
Read
Write
Active
Active
L
L
H
L
H
L
L
X
DIN
Note:
1. H=VIH, L=VIL, X=don't care (VIL or VIH)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.00 / Dec.01
2
HY62KF16403E Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
Typ
3.0 or 3.3
Max.
3.6
0
Vcc+0.3
0.6
Unit
V
V
V
V
0
-
-
2.2
-0.31.
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C
Sym
ILI
Parameter
Input Leakage Current
Test Condition
Vss < VIN < Vcc
Min Typ1.
Max
1
Unit
uA
-1
-
Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL
/CS = VIL,
ILO
Icc
Output Leakage Current
-1
-
1
4
uA
Operating Power Supply Current
mA
VIN = VIH or VIL, II/O = 0mA
/CS = VIL,
VIN = VIH or VIL, Cycle
Time = Min,
3.0~ 55ns
3.6V
2.7~ 55ns
25
20
20
15
mA
mA
mA
mA
70ns
100% Duty, II/O = 0mA
3.3V
70ns
ICC1
Average Operating Current
/CS < 0.2V,
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
100% Duty, II/O = 0mA
/CS = VIH
3
mA
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
300
uA
VIN = VIH or VIL
/CS > Vcc - 0.2V,
SL
LL
SL
LL
0.2
0.2
0.2
0.2
-
6
15
6
12
0.4
-
uA
uA
uA
uA
V
3.0~
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
3.6V
2.7~
3.3V
ISB1
VOL
VOH
Output Low
Output High
IOL = 2.1mA
IOH = -1.0mA
-
2.4
-
V
Note
1. Typical values are at Vcc = 3.0V TA = 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance (Add, /CS, /WE, /OE)
Output Capacitance (I/O)
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.00 / Dec.01
3
HY62KF16403E Series
AC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
55ns
70ns
#
Symbol
Parameter
Unit
Min. Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tBA
tCLZ
tOLZ
tBLZ
tCHZ
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
/LB, /UB Access Time
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
-
10
5
10
0
0
0
-
70
-
-
-
-
10
5
10
0
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
30
55
-
-
-
20
20
20
-
70
70
35
70
-
-
-
25
25
25
-
10 tOHZ
11 tBHZ
12 tOH
10
10
WRITE CYCLE
13 tWC
14 tCW
15 tAW
16 tBW
17 tAS
18 tWP
19 tWR
20 tWHZ
21 tDW
22 tDH
23 tOW
Write Cycle Time
55
50
50
50
0
45
0
0
-
-
-
-
-
-
-
20
-
-
70
60
60
60
0
50
0
0
-
-
-
-
-
-
-
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
25
0
5
30
0
5
-
-
AC TEST CONDITIONS
TA = -40°C to 85°C, unless otherwise specified
Parameter
Value
Input Pulse Level
Input Rise and Fall Time
0.4V to 2.2V
5ns
Input and Output Timing Reference Level
Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW
Others
1.5V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note 1. Including jig and scope capacitance
Rev.00 / Dec.01
4
HY62KF16403E Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
tRC
ADDR
/CS
tAA
tACS
tOH
tCHZ(3)
tBA
/UB ,/ LB
/OE
tBHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tOHZ(3)
tCLZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2 (Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Previous Data
Out
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and /UB and/or /LB .
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.00 / Dec.01
5
HY62KF16403E Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tAS
tDW
Data Valid
tDH
Data In
High-Z
tWHZ(3,7)
(5)
(6)
tOW
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tAS
tWR(2)
tCW
/CS
tAW
tBW
/UB,/LB
/WE
tWP
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.00 / Dec.01
6
HY62KF16403E Series
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS and a low /UB and/or /LB .
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
/CS > Vcc - 0.2V,
Min
Typ1. Max
Unit
VDR
Vcc for Data Retention
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Vcc=1.5V,
/CS > Vcc - 0.2V or
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
1.2
-
3.6
V
SL
LL
-
-
0.1
0.1
3
uA
uA
Iccdr
Data Retention Current
10
Chip Deselect to Data
Retention Time
Operating Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
tRC
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
VIH
VDR
/CS >VCC-0.2V
/CS
VSS
Rev.00 / Dec.01
7
HY62KF16403E Series
PACKAGE INFORMATION
44pin 400mil Thin Small Outline Package Forward (D)
#44
#23
Max.
UNIT : INCH(mm)
Min.
0.470(11.938)
0.462(11.735)
#1
#22
0.729(18.517)
0.721(18.313)
0.404(10.262)
0.396(10.058)
0.047(1.194)
0.039(0.991)
0.0083(0.21)
0.0047(0.120)
0.10MAX
0.004MAX
0.0235(0.597)
0~5
0.0160(0.406)
0.016(0.4)
0.012(0.3)
0.0059(0.150)
0.002(0.050)
0.0315(0.800)
BSC
Rev.00 / Dec.01
8
HY62KF16403E Series
MARKING INFORMATION
Package
Marking Example
h
H
K
y
Y
O
n
6
i
x
y
y
c
w
s
w
s
p
t
TSOP-II
(Forward)
2
E
K
A
F
6
4
0
3
E
R
Index
• hynix
: hynix Logo
• yy
: Year ( ex : 02 = year 2002, 03 = year 2002 )
: Work Week ( ex : 12 = ww12 )
: Process Code
• ww
• p
• HY62KF6403E
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
ss
•
: Speed
- 55
- 70
: 55ns
: 70ns
t
•
•
: Temperature
- I
°
: Industrial ( -40 ~ 85 C )
KOREA
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item (Except hynix)
Rev.00 / Dec.01
9
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