HY62UF16804A-DM55C [HYNIX]
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, MICRO, BGA-48;
| 型号： | HY62UF16804A-DM55C |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, MICRO, BGA-48 静态存储器 |
| 文件： | 总10页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62UF16804A Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History
Draft Date
Remark
04
Initial Revision History Insert
Revised
Jul.02.2000
Preliminary
- Reliability Spec Deleted
05
Change AC Characteristics
Oct.23.2000 Preliminary
Nov.13.2000 Preliminary
- tBLZ : 5/5/5
---> 10/10/10
06
Part Number is changed
- HY62UF16803A --> HY62UF16804A
07
08
Marking Instruction is inserted
Dec.5.2000
Preliminary
Test Condition Changed
- ILO / ISB / ISB1 / VDR / ICCDR
Marking Istruction Inserted
Dec.16.2000 Preliminary
09
10
Change Logo
- Hyundai à Hynix
Apr.28.2001
Jan.28.2002
Change DC Parameter
- Isb1(LL) : 40uA à 25uA
- Isb1(Typ) : 8uA à 1uA
- Icc
: 5mA à 4mA
- Icc1(1us) : 8mA à 4mA
- Icc1(Min) : 50mA à 40mA
Change Data Retention
- IccDR(LL) : 25uA à 15uA
Change AC Parameter
- tOE
: 35ns à 25ns@55ns
: 40ns à 35ns@70ns
- tCW
- tAW
- tBW
- tWP
- tCHZ
- tOHZ
- tBHZ
: 50ns à 45ns@55ns
: 50ns à 45ns@55ns
: 50ns à 45ns@55ns
: 45ns à 40ns@55ns
: 30ns à 20ns@55ns , 30ns à 25ns@70ns
: 30ns à 20ns@55ns , 30ns à 25ns@70ns
: 30ns à 20ns@55ns , 30ns à 25ns@70ns
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.10 /Jan2002
Hynix Semiconductor
HY62UF16804A
DESCRIPTION
FEATURES
The HY62UF16804A is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62UF16804A
uses high performance full CMOS process
technology and is designed for high speed and
low power circuit technology. It is particularly well-
suited for the high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 1.2V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.2V(min) data retention
Standard pin configuration
- 48-uBGA
·
Product
No.
HY62UF16804A-C
HY62UF16804A-I
Voltage
(V)
2.7~3.3 55/70/85
2.7~3.3 55/70/85
Speed
(ns)
Operation
Current/Icc(mA)
Standby Current(uA)
Temperature
LL
25
25
SL
8
8
(°C)
0~70
-40~85
4
4
Note 1. C : Commercial, I : Industrial
2. Current value is max.
PIN CONNECTION ( Top View )
BLOCK DIAGRAM
A1,A2
A4,A6~A7
A9
ROW
DECODER
I/O1
I/O8
I/O9
I/O16
/LB /OE A0 A1 A2 NC
IO9 /UB A3 A4 /CS IO1
IO10 IO11 A5 A6 IO2 IO3
Vss IO12 A17 A7 IO4 Vcc
Vcc IO13 Vss A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 NC A12 A13 /WE IO8
A18 A8 A9 A10 A11 NC
A12
A15~A18
A8
A10
A13
A14
MEMORY ARRAY
512K x 16
A0
A3
A5
A11
/CS
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Pin Name
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.7V~3.3V)
Ground
I/O1~I/O16
A0~A18
Vcc
Vss
/UB
Upper Byte Control(I/O9~I/O16) NC
No Connection
Rev.10/Jan. 2002
2
HY62UF16804A
ORDERING INFORMATION
Part No.
Speed
Power
LL-part
SL-part
LL-part
SL-part
Package Temp.
HY62UF16804A-DMC
HY62UF16804A-SMC
HY62UF16804A-DMI
HY62UF16804A-SMI
55/70/85
55/70/85
55/70/85
55/70/85
uBGA
uBGA
uBGA
uBGA
C
C
I
I
Note 1. C : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
Parameter
Input/Output Voltage
Power Supply
Rating
Unit
V
V
°C
°C
Remark
-0.3 to Vcc+0.3V
-0.3 to 3.6
0 to 70
-40 to 85
-55 to 150
1.0
HY62UF16804A-C
HY62UF16804A-I
TA
Operating Temperature
TSTG
PD
Storage Temperature
Power Dissipation
°C
W
TSOLDER
Ball Soldering Temperature & Time
260 · 10
°C · sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O
/CS
/WE
/OE /LB /UB
Mode
Power
I/O1~I/O8 I/O9~I/O16
H
X
L
L
L
X
X
H
H
H
X
X
H
H
L
X
H
L
X
L
H
L
L
X
H
X
L
H
L
L
H
L
Deselected
Deselected
Output Disabled
Output Disabled
Read
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
Standby
Standby
Active
Active
Active
L
L
X
Write
Active
H
L
High-Z
DIN
L
DIN
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.10/Jan. 2002
2
HY62UF16804A
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Min.
2.7
0
2.2
-0.3(1)
Typ.
3.0
0
-
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C
Sym
ILI
Parameter
Input Leakage Current
Test Condition
Vss < VIN < Vcc
Min.
-1
Typ. Max.
Unit
uA
-
1
Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL,
/UB = /LB = VIH
ILO
Icc
Output Leakage Current
-1
-
1
uA
Operating Power Supply
Current
/CS = VIL, VIN = VIH or VIL, II/O = 0mA
-
-
-
-
-
-
-
-
4
40
4
mA
mA
mA
mA
uA
Cycle Time=Min,100% duty,
II/O = 0mA, /CS = VIL,VIN = VIH or VIL
Cycle time = 1us, 100% duty,
II/O = 0mA, /CS < 0.2V, VIN<0.2V
/CS = VIH or /UB=/LB= VIH,
VIN = VIH or VIL
Average Operating
Current
Icc1
-
TTL Standby Current
(TTL Input)
ISB
-
0.5
8
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
SL
-
Standby Current
(CMOS Input)
ISB1
VIN > Vcc-0.2V or
VIN < Vss+0.2V
LL
1
25
uA
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1mA
IOH = -1.0mA
-
-
-
0.4
-
V
V
2.4
Note : Typical values are at Vcc = 3.0V, TA = 25°C
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
CIN
COUT
Parameter
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Input Capacitance(Add, /CS, /LB, /UB /WE, /OE)
Output Capacitance(I/O)
Note : These parameters are sampled and not 100% tested
Rev.10/Jan. 2002
3
HY62UF16804A
AC CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C unless otherwise specified
-55
-70
Max. Min
-85
#
Symbol
Parameter
Unit
Min.
Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tBA
tCLZ
tOLZ
tBLZ
tCHZ
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
/LB, /UB Access Time
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
-
10
5
10
0
0
0
-
70
-
-
-
-
10
5
10
0
0
0
-
85
-
-
-
-
10
5
10
0
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
25
55
-
-
-
20
20
20
-
70
70
35
70
-
-
-
25
25
25
-
85
85
45
85
-
-
-
30
30
30
-
10 tOHZ
11 tBHZ
12 tOH
10
10
10
WRITE CYCLE
13 tWC
14 tCW
15 tAW
16 tBW
17 tAS
18 tWP
19 tWR
20 tWHZ
21 tDW
22 tDH
23 tOW
Write Cycle Time
55
45
45
45
0
40
0
0
-
-
-
-
-
-
-
20
-
-
70
60
60
60
0
50
0
0
-
-
-
-
-
-
-
25
-
-
85
70
70
70
0
55
0
0
-
-
-
-
-
-
-
30
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
25
0
5
30
0
5
35
0
5
-
-
-
AC TEST CONDITIONS
TA = 0°C to 70°C / -40°C to 85°C, unless otherwise specified
PARAMETER
Value
Input Pulse Level
Input Rise and Fall Time
0.4V to 2.2V
5ns
Input and Output Timing Reference Level
1.5V
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
Output Load
Other
AC TEST LOADS
VTM
= 2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note
1. Including jig and scope capacitance
Rev.10/Jan. 2002
4
HY62UF16804A
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
/CS
tAA
tACS
tOH
tCHZ(3)
tBA
/UB ,/ LB
/OE
tBHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOHZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Previous Data
Out
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tCHZ(3)
Data
Out
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and /or /LB
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.10/Jan. 2002
5
HY62UF16804A
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tAS
tDW
Data Valid
tDH
Data In
High-Z
tWHZ(3,7)
(5)
(6)
tOW
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tCW
tAS
tWR(2)
/CS
tAW
tBW
/UB,/LB
/WE
tWP
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.10/Jan. 2002
6
HY62UF16804A
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and /or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C / -40°C to 85°C
Symbol
Parameter
Test Condition
/CS > Vcc - 0.2V or
Min
Typ
Max
Unit
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VDR
Vcc for Data Retention
1.2
-
3.3
V
VIN < Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
LL
-
-
-
-
15
8
uA
uA
ICCDR
Data Retention Current
SL
VIN < Vss+0.2V
Chip Deselect to Data
Retention Time
Operating Recovery Time
TCDR
TR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
tRC(2)
Notes:
1. Typical values are under the condition of TA = 25°C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
VIH
VDR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
/CS or
/UB & /LB
Vss
Rev.10/Jan. 2002
7
HY62UF16804A
PACKAGE INFORMATION
48ball Micro Ball Grid Array Package(M)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
3.0 X 5.0 MIN
FLAT AREA
F
G
H
C1/2
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
A
r
3
D(DIAMETER)
Note
Symbol
Min.
-
-
-
-
Typ.
0.75
3.75
7.4
5.25
8.5
0.35
0.9
0.65
0.25
-
Max.
-
-
-
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
A
B
B1
C
C1
D
E
E1
E2
r
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
-
-
0.3
0.85
0.6
0.2
-
0.4
0.95
0.7
0.3
0.08
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
Rev.10/Jan. 2002
8
HY62UF16804A
MARKING INSTRUCTION
Package
Marking Example
H
Y
U
F
6
8
y
0
4
A
c
x
s
x
s
x
t
w
K
w
O
p
uBGA
x
x
R
Index
• HYUF6804A
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
• ss
: Speed
- 55
: 55ns
: 70ns
: 85ns
- 70
- 85
• t
: Temperature
- C
- I
: Commercial ( -0 ~ 70 °C )
: Industrial ( -40 ~ 85 °C )
• y
: Year (ex : 0 = year 2000, 1= year 2001)
: Work Week ( ex : 12 = work week 12 )
: Process Code
• ww
• p
• xxxxx
• KOR
: Lot No.
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.10/Jan. 2002
9
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