HYMD132G725B4-H_技术文档

32Mx72 bits

Registered DDR SDRAM DIMM

HYMD132G725B(L)4-M/K/H/L

DESCRIPTION

Hynix HYMD132G725B(L)4-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132G725B(L)4-M/

K/H/L series consists of eighteen 32Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.

Hynix HYMD132G725B(L)4-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of

industry standard. It is suitable for easy interchange and addition.

Hynix HYMD132G725B(L)4-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control

inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high

bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable

latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD132G725B(L)4-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

256MB (32M x 72) Registered DDR DIMM based on

32Mx4 DDR SDRAM

•

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

•

JEDEC Standard 184-pin dual in-line memory module

(DIMM)

•

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Error Check Correction (ECC) Capability

Registered inputs with one-clock delay

•

tRAS Lock-out function supported

Phase-lock loop (PLL) clock driver to reduce loading

2.5V +/- 0.2V VDD and VDDQ Power supply

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

4096 refresh cycles / 64ms

All inputs and outputs are compatible with SSTL_2

interface

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD132G725B(L)4-M

HYMD132G725B(L)4-K

HYMD132G725B(L)4-H

HYMD132G725B(L)4-L

133MHz (*DDR266:2-2-2)

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

VDD=2.5V

VDDQ=2.5V

184pin Registered DIMM

5.25 x 1.7 x 0.15 inch

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3/May. 02

1

HYMD132G725B(L)4-M/K/H/L

PIN DESCRIPTION

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Pin Description

DQs Power Supply

Ground

CK0, /CK0

CS0

VDDQ

VSS

CKE0

VREF

Reference Power Supply

Power Supply for SPD

/RAS, /CAS, /WE

A0 ~ A11

VDDSPD

SA0~SA2

2

E PROM Address Inputs

2

BA0, BA1

Bank Address

SCL

E PROM Clock

2

DQ0~DQ63

Data Inputs/Outputs

SDA

E PROM Data I/O

CB0~CB7

DQS0~DQS17

DM0~8

Data Strobe Inputs/Outputs

Data-In Mask

WP

Write Protect Flag

VDD Identification Flag

Do not Use

VDDID

DU

VDD

Power Supply

NC

No Connection

FET Enable

/RESET

Reset Enable

FETEN

PIN ASSIGNMENT

1

Name

VREF

DQ0

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Name

A5

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Name

VDDQ

/WE

93

Name

VSS

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Name

VSS

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Name

/RAS

2

DQ24

VSS

DQ25

DQS3

A4

94

DQ4

A6

DQ45

VDDQ

/CS0

3

DQ41

/CAS

VSS

95

DQ5

DQ28

DQ29

VDDQ

DQS12

A3

4

DQ1

DQS0

DQ2

VDD

DQ3

NC

96

VDDQ

DQS9

DQ6

5

97

/CS1*

DM5

6

DQS5

DQ42

DQ43

VDD

98

7

VDD

DQ26

DQ27

A2

99

DQ7

VSS

8

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

VSS

DQ30

VSS

DQ46

DQ47

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

/RESET

VSS

NC

DQ31

CB4

Vss

DQ48

DQ49

VSS

A13*

VDDQ

DQ12

DQ13

DQS10

VDD

VDDQ

DQ52

DQ53

NC, FETEN*

VDD

DQ8

DQ9

DQS1

VDDQ

DU

A1

CB5

CB0

CB1

VDD

DQS8

A0

VDDQ

CK0

DU

/CK0

VSS

VDDQ

DQS6

DQ50

DQ51

VSS

DM6

DU

DQ14

DQ15

CKE1*

VDDQ

BA2*

DQ20

A12*

VSS

DQS17

A10

DQ54

DQ55

VDDQ

NC

VSS

CB2

VSS

CB3

BA1

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

CB6

VDDQ

CB7

VDDID

DQ56

DQ57

VDD

DQ60

DQ61

VSS

Key

key

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

145

146

147

148

149

150

151

152

153

VSS

DQ36

DQ37

VDD

DM7

DQS7

DQ58

DQ59

VSS

DQ21

A11

DQ62

DQ63

VDDQ

SA0

A9

DQS11

VDD

DQS13

DQ38

DQ39

VSS

DQ18

A7

BA0

WP

DQ22

A8

SA1

VDDQ

DQ19

DQ35

DQ40

SDA

SA2

SCL

DQ23

DQ44

VDDSPD

* These are not used on this module but may be used for other module in 184pin DIMM family

Rev. 0.3/May. 02

2

HYMD132G725B(L)4-M/K/H/L

FUNCTIONAL BLOCK DIAGRAM

VSS

/RCS0

DQS9

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DM

DQS

/CS

DM

DQS

/CS

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

D9

D0

DQS10

DQS11

DQS12

DQS13

DQS14

DQS

/CS

DQS

/CS

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

D10

D1

DQS

/CS

DQS

/CS

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

DQ8

I/O 0

I/O 1

I/O 2

I/O 3

DQ9

D11

D2

DQ10

DQ11

DQS

/CS

DQS

/CS

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

D12

D3

DQS

/CS

DQS

/CS

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

D13

D4

DQS

/CS

DQS

/CS

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

D14

D5

DQS15

DQS16

DQS17

DQS6

DQS7

DQS8

DM

DQS

/CS

DM

DQS

/CS

Serial PD

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

SCL

WP

D15

D6

SDA

A0

A1

A2

SA0 SA1 SA2

DQS

/CS

DQS

/CS

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D16

D7

VDDSPD

.

SPD

=

DQS

/CS

.

D0 - D17

DQS

/CS

VDDQ

VDD

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

D17

D8

= =

.

VREF

=

. . . .

.

VSS

D0 - D17

..

VDDID

Strap:see Note 4

Notes:

/RCS0 -->/CS0 : SDRAMs D0-D17

/CS0

1. DQ-to-I/O wiring may be changed within a byte

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

BA0-BA1

A0-A11

/RAS

RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D17

RA0 -R A11 -->A0 - A11 : SDRAMs D0 - D17

/RRAS --> /RAS : SDRAMs D0 - D17

/RCAS --> /CAS : SDRAMs D0 - D17

RCKE0 --> CKE : SDRAMs D0 - D17

/RWE --> /WE : SDRAMs D0 - D17

R

E

G

3. DQ/DQS resistors should be 18 Ohms.

4. VDDID strap connections(for memory device VDD, VDDQ);

Strap out :(open) : VDD=VDDQ

/CAS

CKE0

/WE

Strap In (Vss) : VDD=VDDQ

5. Address and control resistors should be 22 Ohms

PCK

/RESET

/PCK

CK0, /CK0 --------- PLL*

* Wire per clock loading table/wiring diagrams

Rev. 0.3/May. 02

3

HYMD132G725B(L)4-M/K/H/L

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

-55 ~ 125

-0.5 ~ 3.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Output Short Circuit Current

Power Dissipation

VIN, VOUT

VDD

V

VDDQ

IOS

V

mA

W

PD

18

^oC / Sec

Soldering Temperature / Time

TSOLDER

260 / 10

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS=0V)

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

Termination Voltage

Reference Voltage

Note :

VDD

2.3

2.5

2.7

V

VDDQ

VIH

2.5

2.7

1

2

3

VREF + 0.15

-0.3

-

VDDQ + 0.3

VREF - 0.15

VREF + 0.04

0.51*VDDQ

VIL

VTT

VREF - 0.04

0.49*VDDQ

VREF

0.5*VDDQ

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of VREF is approximately equal to 0.5VDDQ.

AC OPERATING CONDITIONS (TA=0 to 70^oC, Voltage referenced to VS=0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

Input Differential Voltage, CK and /CK inputs

Input Crossing Point Voltage, CK and /CK inputs

Note :

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

VREF + 0.31

V

VREF - 0.31

VDDQ + 0.6

0.7

1

2

0.5*VDDQ-0.2

0.5*VDDQ+0.2

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

Rev. 0.3/May. 02

4

HYMD132G725B(L)4-M/K/H/L

AC OPERATING TEST CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS=0V)

Parameter

Value

Unit

Reference Voltage

Termination Voltage

VDDQ x 0.5

V

VDDQ x 0.5

AC Input High Level Voltage (VIH, min)

AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level Voltage

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

VREF + 0.31

V

VREF - 0.31

V

VREF

VTT

1.5

1

V

Input minimum Signal Slew Rate

V/ns

Ω

Termination Resistor (RT)

50

Series Resistor (RS)

25

Ω

Output Load Capacitance for Access Time Measurement (CL)

30

pF

Rev. 0.3/May. 02

5

HYMD132G725B(L)4-M/K/H/L

CAPACITANCE (TA=25^oC, f=100MHz )

Parameter

Symbol

Min

Max

Unit

Input Capacitance

A0 ~ A11, BA0, BA1

CIN1

CIN2

CIN3

CIN4

CIN5

CIO1

CIO2

5

8

12

11

pF

Input Capacitance

/RAS, /CAS, /WE

CKE0

Input Capacitance

CS0

Input Capacitance

CK0, /CK0

Data Input / Output Capacitance

DQ0 ~ DQ63, DQS0 ~ DQS17

CB0 ~ CB7

Note :

1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

VTT

Ω

RT=50

Output

Ω

Zo=50

VREF

CL=30pF

Rev. 0.3/May. 02

6

HYMD132G725B(L)4-M/K/H/L

DC CHARACTERISTICS I (TA=0 to 70^oC, Voltage referenced to VSS=0V)

Parameter

Symbol

Min.

Max

Unit

Note

Add, CMD, /CS, /CKE

CK, /CK

-2

2

Input Leakage

Current

ILI

uA

1

-4

4

Output Leakage Current

Output High Voltage

Output Low Voltage

ILO

VOH

VOL

-5

5

uA

V

2

VTT + 0.76

-

IOH = -15.2mA

IOL = +15.2mA

VTT - 0.76

V

Note :

1. VIN=0 to 3.6V, All other pins are not tested under VIN=0V

2. DOUT is disabled, VOUT=0 to 2.7V

Rev. 0.3/May. 02

7

HYMD132G725B(L)4-M/K/H/L

DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS=0V)

Speed

-M -K -H

Parameter

Symbol

Test Condition

Unit Note

-L

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing

twice per clock cycle; address and control inputs

changing once per clock cycle

Operating Current

IDD0

2270 2090 2090 2090 mA

2630 2450 2450 2090 mA

One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min);

address and control inputs changing once per

clock cycle

Operating Current

IDD1

IDD2P

IDD2F

IDD3P

Precharge Power Down

Standby Current

All banks idle; Power down mode ; CKE=Low,

tCK=tCK(min)

920

1280

1010

mA

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing

once per clock cycle.

Idle Standby Current

VIN=VREF for DQ, DQS and DM

Active Power Down

Standby Current

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

/CS=HIGH; CKE=HIGH; One bank; Active-

Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,

Active Standby Current

IDD3N DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing

once per clock cycle

1370

mA

Burst=2; Reads; Continuous burst; One bank

Operating Current

IDD4R active; Address and control inputs changing once 4070 4070 4070 3350 mA

per clock cycle; tCK=tCK(min); IOUT=0mA

Burst=2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle

IDD4W

IDD5

4070 4070 4070 3350 mA

3050 3050 3050 2870 mA

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz;

distributed refresh

Auto Refresh Current

Self Refresh Current

Normal

386

368

mA

CKE=<0.2V; External clock on;

tCK=tCK(min)

IDD6

IDD7

Low Power

Operating Current - Four

Bank Operation

Four bank interleaving with BL=4, Refer to the

following page for detailed test condition

5330 5330 5330 4610 mA

Rev. 0.3/May. 02

8

HYMD132G725B(L)4-M/K/H/L

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

DDR266(2-2-2)

DDR266A

DDR266B

DDR200

Min Max

Parameter

Symbol

Unit Note

Min

60

Max

Min

65

Max

Min

65

Max

Row Cycle Time

tRC

tRFC

tRAS

-

70

80

50

-

ns

Auto Refresh Row Cycle Time

Row Active Time

75

45

120K

45

120K

45

120K

120k ns

Active to Read with Auto

Precharge Delay

tRAP

15

-

20

-

20

-

20

-

ns

16

Row Address to Column

Address Delay

tRCD

tRRD

tCCD

15

1

-

20

15

1

-

20

15

1

-

20

15

1

-

ns

CK

Row Active to Row Active Delay

Column Address to Column

Address Delay

Row Precharge Time

tRP

tWR

tWTR

15

1

-

20

15

1

-

20

15

1

-

20

15

1

-

ns

CK

Write Recovery Time

Write to Read Command Delay

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

Auto Precharge Write Recovery

+ Precharge Time

tDAL

tCK

-

CK

15

(tRP/tCK)

CL = 2.5

7.5

12

7.5

12

7.5

10

12

8.0

10

12

ns

System Clock

Cycle Time

CL = 2

Clock High Level Width

Clock Low Level Width

tCH

tCL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55 CK

Data-Out edge to Clock edge

Skew

tAC

tDQSCK

tDQSQ

tQH

-0.75

-

0.75

0.5

-

-0.75

-

0.75

0.5

-

-0.75

-

0.75

0.5

-

-0.8

-

0.8

0.6

-

ns

DQS-Out edge to Clock edge

Skew

DQS-Out edge to Data-Out

edge Skew

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Data-Out hold time from DQS

Clock Half Period

1, 10

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

tHP

-

1,9

10

Data Hold Skew Factor

tQHS

tDV

-

0.75

-

0.75

-

0.75

-

0.75

ns

Valid Data Output Window

tQH-tDQSQ

Data-out high-impedance

window from CK,/CK

tHZ

tLZ

-0.75

0.75

-0.75

0.75

-0.75

0.75

-0.8

0.8

ns

17

Data-out low-impedance

window from CK,/CK

Rev. 0.3/May. 02

9

HYMD132G725B(L)4-M/K/H/L

-Continued -

DDR266(2-2-2)

DDR266A

DDR266B

DDR200

Min Max

1.1

Parameter

Symbol

Unit

Note

Min

0.9

Max

Min

0.9

Max

Min

0.9

Max

Input Setup Time (fast slew rate)

Input Hold Time (fast slew rate)

tIS

tIH

-

ns

2,3,5,6

0.9

1.1

-

Input Setup Time

(slow slew rate)

tIS

1.0

-

1.0

-

1.0

-

ns

2,4,5,6

Input Hold Time (slow slew rate)

Input Pulse Width

tIH

1.0

2.2

1.0

2.2

1.0

2.2

1.1

2.5

-

ns

2,4,5,6

6

tIPW

Write DQS High Level Width

Write DQS Low Level Width

tDQSH

tDQSL

0.35

-

0.35

-

0.35

-

0.35

CK

Clock to First Rising edge of

DQS-In

tDQSS

tDS

0.72

0.5

1.28

0.75

0.5

1.25

0.75

0.5

1.25

0.75

0.6

1.25

CK

ns

Data-In Setup Time to DQS-In

(DQ & DM)

-

6,7,

11~13

Data-in Hold Time to DQS-In

(DQ & DM)

tDH

0.5

0.6

DQ & DM Input Pulse Width

Read DQS Preamble Time

Read DQS Postamble Time

tDIPW

tRPRE

tRPST

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

2

0.9

0.4

0

-

1.1

0.6

-

ns

CK

Write DQS Preamble Setup Time tWPRES

Write DQS Preamble Hold Time

Write DQS Postamble Time

Mode Register Set Delay

tWPREH

tWPST

tMRD

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.6

-

0.6

-

0.6

-

0.6

-

Exit Self Refresh to Any Execute

Command

tXSC

200

-

200

-

200

-

200

-

CK

us

8

Average Periodic Refresh Interval

tREFI

15.6

Rev. 0.3/May. 02

1 0

HYMD132G725B(L)4-M/K/H/L

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tIS

ps

Delta tIH

V/ns

0.5

ps

0

0.4

+50

0

0.3

+100

0

5. CK, /CK slew rates are >=1.0V/ns

6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to

n-channel variation of the output drivers.

¹¹.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

0.5

ps

0

ps

0

0.4

+75

+150

+75

+150

0.3

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

I/O Input Level

mV

Delta tDS

ps

Delta tDH

ps

+280

+50

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS

slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns

and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

0

ps

0

ps

0

+/-0.25

+/- 0.5

+50

+100

+50

+100

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

Rev. 0.3/May. 02

1 1

HYMD132G725B(L)4-M/K/H/L

15. tDAL = (tWR / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.

tCK is equal to the actual system clock cycle time.

Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,

tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be

tRAS - BL/2 x tCK.

17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced

to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

Rev. 0.3/May. 02

1 2

HYMD132G725B(L)4-M/K/H/L

SIMPLIFIED COMMAND TRUTH TABLE

A10/

AP

ADDR

Command

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

BA

Note

Extended Mode Register Set

Mode Register Set

Device Deselect

No Operation

H

X

L

OP code

1,2

H

L

X

H

L

X

H

X

H

X

1

Bank Active

L

RA

V

1

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

1,3

1

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Read Burst Stop

Auto Refresh

H

L

1,4

1,5

1

X

V

H

L

H

X

H

L

H

L

H

L

H

X

H

X

H

X

H

X

V

X

1

Entry

L

1

Self Refresh

Exit

H

L

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

L

H

L

H

L

1

H

L

1

Entry

Precharge Power

Down Mode

H

L

Exit

H

L

Entry

H

L

Active Power

Down Mode

Exit

H

X

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. DM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

Rev. 0.3/May. 02

1 3

HYMD132G725B(L)4-M/K/H/L

PACKAGE DIMENSIONS

Front

133.35

5.25

131.35

5.171

128.95

5.077

43.18

1.7

Register

PLL

Register

(2) 0

2.5

0.098

Back

Side

3.99

.157max

(Front)

1.27+/-0.10

0.05+/-0.004

Rev. 0.3/May. 02

1 4

SERIAL PRESENCE DETECT

SPD SPECIFICATION

(32Mx72 Registered DDR DIMM)

Rev. 0.3/May. 02

15

HYMD132G725B(L)4-M/K/H/L

SERIAL PRESENCE DETECT

Bin Sort :M(DDR266(2-2-2),K(DDR266A@CL=2)

H(DDR266B@CL=2.5),L(DDR200@CL=2)

Function Supported

Hexa Value

Byte#

Function Description

Note

M

K

H

L

M

K

H

L

Number of Bytes written into serial memory at module man-

ufacturer

0

128 Bytes

80h

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Total number of Bytes in SPD device

Fundamental memory type

Number of row address on this assembly

Number of column address on this assembly

Number of physical banks on DIMM

Module data width

256 Bytes

DDR SDRAM

08h

07h

0Ch

0Bh

01h

48h

00h

04h

12

11

1Bank

72 Bits

-

1

Module data width (continued)

Module voltage Interface levels(VDDQ)

DDR SDRAM cycle time at CAS Latency =2.5(tCK)

DDR SDRAM access time from clock at CL=2.5 (tAC)

Module configuration type

Refresh rate and type

Primary DDR SDRAM width

SSTL 2.5V

7.5ns 7.5ns 7.5ns

+/-0.75ns

8.0ns

+/-0.8ns 75h

75h

80h

2

ECC

02h

80h

04h

15.6us & Self refresh

x4

Error checking DDR SDRAM data width

Minimum clock delay for back-to-back random column

15

1 CLK

01h

address(tCCD)

16

17

18

19

20

Burst lengths supported

Number of banks on each DDR SDRAM

CAS latency supported

CS latency

2,4,8

4 Banks

2, 2.5

0

0Eh

04h

0Ch

01h

02h

WE latency

1

Registered Address and

21

DDR SDRAM module attributes

26h

control input PLL

+/-0.2Voltage tolerance,

Concurrent Auto Precharge

tRAS Lock Out

22

DDR SDRAM device attributes : General

C0h

23

24

25

26

27

28

29

30

31

DDR SDRAM cycle time at CL=2.0(tCK)

DDR SDRAM access time from clock at CL=2.0(tAC)

DDR SDRAM cycle time at CL=1.5(tCK)

DDR SDRAM access time from clock at CL=1.5(tAC)

Minimum row precharge time(tRP)

Minimum row activate to row active delay(tRRD)

Minimum RAS to CAS delay(tRCD)

Minimum active to precharge time(tRAS)

Module row density

7.5ns 7.5ns

+/-0.75ns

10ns

+/-0.8ns 75h

75h

A0h

75h

A0h

80h

2

-

00h

15ns

45ns

20ns

15ns

20ns

45ns

20ns

15ns

20ns

45ns

20ns

15ns

20ns

50ns

3Ch

2Dh

50h

3Ch

50h

2Dh

50h

3Ch

50h

32h

3Ch

50h

2Dh

256MB

40h

32

33

34

35

36~40

41

Command and address signal input setup time(tIS)

Command and address signal input hold time(tIH)

Data signal input setup time(tDS)

Data signal input hold time(tDH)

Reserved for VCSDRAM

0.9ns 0.9ns 0.9ns

0.5ns 0.5ns 0.5ns

Undefined

1.1ns

0.6ns

90h

50h

90h

50h

90h

50h

B0h

60h

00h

Minimum active / auto-refresh Time (tRC)

60ns

75ns

12ns

65ns

75ns

12ns

65ns

75ns

12ns

70ns

80ns

3Ch

4Bh

41h

4Bh

41h

4Bh

46h

50h

Minimum auto-refresh to active / auto-refresh command

42

period(tRFC)

43

44

45

46~61

62

63

Maximum cycle time (tCK max)

Maximum DQS-DQ skew time (tDQSQ)

Maximum read data hold skew factor (tQHS)

Superset Information (may be used in future)

SPD Revision code

12ns

0.6ns

30h

32h

75h

30h

32h

75h

30h

32h

75h

30h

3Ch

75h

0.5ns 0.5ns 0.5ns

0.75ns 0.75ns 0.75ns 0.75ns

Undefined

Initial release

-

00h

Checksum for Bytes 0~62

98h

C5h

F0h

8Ah

Rev. 0.3/May. 02

1 6

HYMD132G725B(L)4-M/K/H/L

SERIAL PRESENCE DETECT(continued)

Function Supported

Hexa Value

Byte#

Function Description

Manufacturer JEDEC ID Code

Note

M

K

H

L

M

K

H

L

64

65~71

Hynix JEDEC ID

-

ADh

00h

------ Manufacturer JEDEC ID Code

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

0*h

1*h

2*h

3*h

4*h

5*h

72

Manufacturing location

6

Asia Area

73

74

75

76

77

78

79

80

81

82

83

84

85

Manufacture part number(Hynix Memory Module)

----- Manufacture part number (Hynix Memory Module)

Manufacture part number (DDR SDRAM)

Manufacture part number (Memory density)

Manufacture part number(Module Depth)

------- Manufacture part number (Module Depth)

Manufacture part number(Module type)

Manufacture part number(Data width)

-------Manufacture part number (Data width)

Manufacture part number(Refresh, # of Bank.)

Manufacture part number(Component Generation)

Manufacture part number(Component Configuration)

Manufacture part number(Hyphen)

H

Y

M

D

1

3

2

G

48h

59h

4Dh

44h

31h

33h

32h

47h

37h

32h

35h

42h

34h

2Dh

7

2

5(4K refresh,4Bank)

B

4

‘-’

86

87

88~90

91

92

93

Manufacture part number(Minimum cycle time)

Manufacture part number(T.B.D)

Manufacture revision code (for Component)

Manufacture revision code (for PCB)

M

K

H

L

4Dh

4Bh

48h

4Ch

-

20h

30h

-

Blank

0

-

Manufacturing date(Year)

3

4

5

94

95~98

Manufacturing date(Week)

Module serial number

-

99~127 Manufacturer specific data (may be used in future)

128~255 Open for customer use

Undefined

00h

Note :

1. The bank address is excluded

2. These value is based on the component specification

3. These bytes are programmed by code of date week & date year

4. These bytes apply to Hynix’s own Module Serial Number system

5. These bytes undefined and coded as ‘00h’

6. Refer to Hynix web site

Byte 85~86, Low power part

Function Supported

Hexa Value

Byte#

Function Description

Note

M

K

H

L

M

K

H

L

85

86

Manufacture part number(Low power part)

Manufacture part number(Component Configuration)

L

4

4Ch

34h

Rev. 0.3/May. 02

1 7


型号：	HYMD132G725B4-H
厂家：	HYNIX SEMICONDUCTOR
描述：	Registered DDR SDRAM DIMM 注册DDR SDRAM DIMM 存储内存集成电路动态存储器双倍数据速率时钟
文件：	总17页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYMD132G725B4-H [HYNIX]

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