HYMD564646BP8-H [HYNIX]
1184pin Unbufferd DDR SDRAM DIMMs; 1184pin Unbufferd的DDR SDRAM DIMM
| 型号： | HYMD564646BP8-H |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 1184pin Unbufferd DDR SDRAM DIMMs |
| 文件： | 总30页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
184pin Unbuffered DDR SDRAM DIMMs based on 512Mb B ver.
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered DIMM series provide
a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange
and addition.
FEATURES
•
•
•
•
•
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
•
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Two ranks 128M x 72, 128M x 64 and One rank 64M
x 72, 64M x 64, 32M x 64 organization
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
2.6V ± 0.1V VDD and VDDQ Power supply for
DDR400, 2.5V ± 0.2V for DDR333 and below
All inputs and outputs are compatible with SSTL_2
interface
Serial Presence Detect (SPD) with EEPROM
Built with 512Mb DDR SDRAMs in 400 mil TSOP II
packages
Fully differential clock operations (CK & /CK) with
133/166/200MHz
•
Lead-free product listed for each configuration
(RoHS compliant)
•
•
DLL aligns DQ and DQS transition with CK transition
Programmable CAS Latency: DDR266(2, 2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
ADDRESS TABLE
# of
DRAMs
Refresh
# of row/bank/column Address
Method
Organization
Ranks
SDRAMs
256MB
512MB
512MB
1GB
32M x 64
64M x 64
64M x 72
128M x 64
128M x 72
1
1
1
2
2
32Mb x 16
64Mb x 8
64Mb x 8
128Mb x 8
128Mb x 8
4
8
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
9
16
18
1GB
PERFORMANCE RANGE
-D431
Part-Number Suffix
Speed Bin
-J
DDR333
2.5-3-3
-
-H
DDR266B
2.5-3-3
-
Unit
-
DDR400B
3-3-3
200
CL - tRCD- tRP
CL=3
CK
MHz
MHz
MHz
Max Clock
CL=2.5
166
166
133
Frequency
CL=2
133
133
133
Note:
1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / May. 2005
1
1184pin Unbufferd DDR SDRAM DIMMs
ORDERING INFORMATION
# of
DRAMs
ECC
Support
Part Number
Density Organization
Material
DIMM Dimension
133.35 x 31.75 x 3.18 [mm3]
HYMD532646B6-H
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
32Mb x 16
32Mb x 16
32Mb x 16
32Mb x 16
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
4
4
Normal
None
None
None
None
None
None
None
None
ECC
Lead-free1
Normal
↑
HYMD532646BP6-H
HYMD532646B6J-D43/J
HYMD532646BP6J-D43/J
HYMD564646B8-H
4
↑
Lead-free1
Normal
↑
4
8
↑
Lead-free1
Normal
↑
HYMD564646BP8-H
8
HYMD564646B8J-D43/J
HYMD564646BP8J-D43/J
HYMD564726B8-H
8
↑
Lead-free1
Normal
↑
8
9
↑
Lead-free1
Normal
↑
HYMD564726BP8-H
9
ECC
HYMD564726B8J-D43/J
HYMD564726BP8J-D43/J
HYMD512646B8-H
9
ECC
↑
Lead-free1
Normal
↑
9
ECC
133.35 x 31.75 x 4 [mm3]
16
16
16
16
18
18
18
18
None
None
None
None
ECC
Lead-free1
Normal
↑
↑
↑
↑
↑
↑
↑
HYMD512646BP8-H
1GB
HYMD512646B8J-D43/J
HYMD512646BP8J-D43/J
HYMD512726B8-H
1GB
Lead-free1
Normal
1GB
1GB
Lead-free1
Normal
HYMD512726BP8-H
1GB
ECC
HYMD512726B8J-D43/J
HYMD512726BP8J-D43/J
1GB
ECC
Lead-free1
1GB
ECC
Note:
1. The “Lead-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.
* These products are built with HY5DU124(8,16)22BT[P], the Hynix DDR SDRAM component.
Rev. 1.1 / May. 2005
2
1184pin Unbufferd DDR SDRAM DIMMs
PIN DESCRIPTION
Pin
Pin Description
Differential Clock Inputs
Chip Select Inputs
Clock Enable Inputs
Commend Sets Inputs
Address Inputs
Address Input/Autoprecharge
Bank Address
Data Inputs/Outputs
Data Check bits
Pin
Pin Description
Power Supply for Core and I/O
Power Supply for DQs
Ground
Input/Output Reference
Power Supply for SPD
VDD, VDDQ Level Detection
SPD Address Inputs
SPD Clock Input
CK0~2, /CK0~2
/CS0, /CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A13
VDD
VDDQ
VSS
VREF
VDDSPD
VDDID
A10/AP
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~8
SA0~SA2
SCL
SDA
DU
NC
SPD Data Input/Output
Do not Use
No Connect
Data Strobes
Data-in Masks
TEST
Reserved for test equipment use
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
A5
DQ24
VSS
DQ25
DQS3
A4
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC,/CS2
DQ48
DQ49
VSS
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Name
Pin
124
125
126
127
128
Name
VSS
A6
DQ28
DQ29
VDDQ
Pin
154
155
156
157
158
Name
/RAS
DQ45
VDDQ
/CS0
VSS
DQ4
DQ5
VDDQ
DM0,DQS9
DQ6
/CS1
DM5,DQS14
VSS
129 DM3,DQS12 159
VDD
DQ7
VSS
NC
130
131
132
133
134
135
136
137
A3
DQ30
VSS
DQ31
CB4,NC
CB5,NC
VDDQ
CK0
160
161
162
163
164
165
166
167
168
169
DQ26
DQ27
A2
VSS
A1
CB0,NC
CB1,NC
VDD
NC,DQS8
A0
CB2,NC
VSS
CB3,NC
BA1
DQ46
DQ47
NC,/CS3
VDDQ
DQ52
DQ53
NC,A13
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
VSS
NC,TEST
NC,FETEN
VDDQ
DQ12
DQ13
DQ8
DQ9
DQS1
VDDQ
CK1
/CK2
CK2
107 DM1,DQS10 138
/CK0
VSS
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
108
109
110
111
112
113
114
115
116
117
118
VDD
DQ14
DQ15
CKE1
VDDQ
BA2
DQ20
A12
VSS
139
DM6
/CK1
VSS
140 DM8,DQS17 170
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
141
142
143
144
A10
171
172
173
174
175
176
177
178
179
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
CB6,NC
VDDQ
CB7,NC
Key
Key
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
VSS
DQ36
DQ37
VDD
DM7,DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
DQ21
A11
119 DM2,DQS11 149 DM4,DQS13 180
120
121
122
123
VDD
DQ22
A8
150
151
152
153
DQ38
DQ39
VSS
181
182
183
184
NC
SDA
SCL
DQ23
DQ44
note:
1. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are reserved for x72 variants of this module and are not used on the x64 versions.
2. Pins 111, 158 are not used for single rank module.
3. Pin 167 is “NC” for 256MB, 512MB and 1GB or “A13” for 2GB module.
4. Pins 9, 10, 71, 82, 90, 101, 102, 103, 113, 163, 167, 173 are not used on this module.
Rev. 1.1 / May. 2005
3
1184pin Unbufferd DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB, 32M x 64 Unbuffered DIMM: HYMD532646B[P]6[J]
/CS0
DQS1
DM1/DQS10
DQS5
/CS
/CS
LDQS
LDM
I/O0
I/O1
I/O2
LDQS
LDM
I/O0
I/O1
I/O2
DM5/DQS14
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O3
I/O4
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
DQ45
DQ46
DQ47
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
D0
D2
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ32
I/O9
I/O10
I/O9
I/O10
DQ1
DQ33
DQ34
DQ35
DQ36
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O11
I/O12
I/O11
I/O12
I/O13
I/O14
I/O15
I/O13
I/O14
I/O15
DQ37
DQ38
DQ39
DQS3
DM3/DQS12
DQS7
DM7/DQS16
DQ56
/CS
/CS
LDQS
LDM
I/O0
I/O1
I/O2
LDQS
LDM
I/O0
I/O1
I/O2
DQ24
DQ25
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ26
DQ27
DQ28
I/O3
I/O4
I/O3
I/O4
DQ29
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
DQ30
DQ31
D3
D1
DQS2
DM2/DQS11
DQS6
DM6/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
I/O9
I/O10
I/O9
I/O10
DQ49
DQ50
I/O11
I/O12
I/O11
I/O12
DQ51
DQ52
DQ53
DQ54
DQ55
I/O13
I/O14
I/O15
I/O13
I/O14
I/O15
Serial PD
VDD SPD
SPD
*Clock Wiring
SDA
VDD /VDDQ
VREF
DO-D3
DO-D3
DO-D3
SCL
Clock Input
SDRAMs
W
P
NC
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
A0 A1 A2
2 SDRAMs
2 SDRAMs
SA0 SA1 SA2
VSS
*Wire per Clock Loading
Table/Wiring Diagrams
VDDID
Strap:see Note 4
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
BA0-BA1
A0-A13
BA0-BA1 : SDRAMs D0-D3
A0-A13 : SDRAMs D0-D3
/RAS : SDRAMs D0-D3
/CAS : SDRAMs D0-D3
CKE : SDRAMs D0-D3
/WE : SDRAMs D0-D3
/RAS
/CAS
CKE0
/WE
STRAP IN (VSS) : VDD ≠ V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms +- 5%
Rev. 1.1 / May. 2005
4
1184pin Unbufferd DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64M x 64 Unbuffered DIMM: HYMD564646B[P]8[J]
/CS0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
I/O7
/CS
DQS
DQS
DQS
DQS
DM
I/O7
/CS
DQS
DQS
DQS
DQS
DQ0
DQ32
I/O6
I/O1
I/O6
I/O1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O0
I/O5
I/O0
I/O5
D0
D4
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS1
DM1/DQS10
DQS5
DM5/DQS14
DM
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ8
DQ40
DQ9
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O0
I/O5
I/O0
I/O5
D1
D5
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS2
DM2/DQS11
DQS6
DM6/DQS15
DM
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O0
I/O5
I/O0
I/O5
D2
D6
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS3
DM3/DQS12
DQS7
DM7/DQS16
DM
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O0
I/O5
I/O0
I/O5
D3
D7
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
VDD SPD
SPD
*Clock Wiring
Serial PD
VDD /VDDQ
VREF
DO-D8
DO-D8
Clock Input
SDRAMs
SDA
SCL
W
P
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
A0
A1
A2
VSS
DO-D8
Strap:see Note 4
SA0 SA1 SA2
VDDID
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
BA0-BA1
A0-A13
/RAS
BA0-BA1 : SDRAMs D0-D7
A0-A13 : SDRAMs D0-D7
/RAS : SDRAMs D0-D7
/CAS : SDRAMs D0-D7
CKE : SDRAMs D0-D7
/WE : SDRAMs D0-D7
1. DQ-to-I/O wiring is shown as recommended but
may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ V DDQ
/CAS
CKE0
/WE
5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5%
Rev. 1.1 / May. 2005
5
1184pin Unbufferd DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64M x 72 ECC Unbuffered DIMM : HYMD564726B[P]8[J]
/CS0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
DM
DM
DM
DM
/CS
DQS
DQS
DQS
DQS
DQS
DM
I/O7
/CS
DQS
DQS
DQS
DQS
I/O7
I/O6
I/O1
DQ0
DQ32
I/O6
I/O1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O0
I/O5
I/O0
I/O5
D0
D4
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS1
DM1/DQS10
DQS5
DM5/DQS14
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ8
DQ40
DQ9
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O0
I/O5
I/O0
I/O5
D1
D5
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS2
DM2/DQS11
DQS6
DM6/DQS15
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O0
I/O5
I/O0
I/O5
D2
D6
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQS3
DM3/DQS12
DQS7
DM7/DQS16
/CS
DM
/CS
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O0
I/O5
I/O0
I/O5
D3
D7
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
VDD SPD
VDD /VDDQ
VREF
SPD
DQS3
DM3/DQS12
*Clock Wiring
DO-D8
DO-D8
Clock Input
SDRAMs
/CS
I/O7
I/O6
I/O1
CB0
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
3 SDRAMs
3 SDRAMs
3 SDRAMs
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VSS
DO-D8
Strap:see Note 4
I/O0
I/O5
VDDID
D8
*Wire per Clock Loading
Table/Wiring Diagrams
Serial PD
I/O4
I/O3
I/O2
SDA
SCL
W
P
A0
A1
A2
SA0 SA1 SA2
Notes :
BA0-BA1
A0-A13
/RAS
BA0-BA1 : SDRAMs D0-D8
A0-A13 : SDRAMs D0-D8
/RAS : SDRAMs D0-D8
/CAS : SDRAMs D0-D8
CKE : SDRAMs D0-D8
/WE : SDRAMs D0-D8
1. DQ-to-I/O wiring is shown as recommended but
may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5%
/CAS
CKE0
/WE
Rev. 1.1 / May. 2005
6
1184pin Unbufferd DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB, 128M x 64 Unbuffered DIMM : HYMD512646B[P]8[J]
/S1
/S0
DQS4
DM4
DQS0
DM0
DM
I/O0
I/O1
I/O6
/S
DQS
DQS
DQS
DM
I/O0
I/O1
I/O6
/S
DQS
DQS
DQS
DM
I/O7
I/O6
I/O1
/S
DQS
DQS
DQS
DM
I/O7
I/O6
I/O1
/S
DQS
DQS
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
I/O0
I/O5
I/O7
I/O2
I/O0
I/O5
D12
I/O7
I/O2
D0
D8
D4
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
DQ7
DQ39
DQS5
DM5
DQS1
DM1
DM
/S
DM
/S
DM
/S
DM
/S
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
I/O0
I/O1
I/O6
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
I/O0
I/O1
I/O6
DQ10
DQ11
DQ12
DQ13
DQ14
I/O7
I/O2
I/O0
I/O5
D1
D9
I/O0 D5
D13
I/O7
I/O2
I/O5
I/O3
I/O4
I/O5
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
DQ15
DQ47
DQS2
DM2
DQS6
DM6
DM
/S
DM
/S
DM
/S
DM
I/O7
I/O6
I/O1
/S
I/O0
I/O1
I/O6
I/O0
I/O1
I/O6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
I/O7
I/O6
I/O1
I/O7
I/O2
I/O7
I/O2
I/O0
I/O5
I/O0
I/O5
D14
D2
D10
D6
I/O3
I/O4
I/O5
I/O3
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
I/O4
I/O5
DQ55
DQ23
DQS3
DM3
DQS7
DM7
DM
/S
DQS
DM
/S
DQS
DM
/S
DM
/S
DQS
I/O7
I/O6
I/O1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
I/O0
I/O1
I/O6
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
I/O0
I/O1
I/O6
I/O7
I/O6
I/O1
I/O0
I/O5
I/O7
I/O2
I/O7
I/O2
I/O0
I/O5
D3
D11
D7
D15
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
I/O3
I/O4
I/O5
I/O4
I/O3
I/O2
DQ31
DQ63
VDDSPD
SPD
* Clock Wiring
Serial PD
DO-D15
DO-D15
DO-D15
VDD/VDDQ
VREF
Clock Input
SDRAMs
SCL
SDA
*CK0,/CK0
*CK1,/CK1
*CK2,/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
WP
A0
A1 A2
VSS
SA0 SA1SA2
* Wire per Clock Loading
Table/Wiring Diagrams
Strap:see Note 4
VDDID
Note :
BA0-BA1-> : SDRAMs D0-D15
A0-A13-> : SDRAMs D0-D15
CKE : SDRAMs D8-D15
BA0-BA1
A0-A13
CKE1
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ,DQS,DM/DQS resistors : 22 Ohms ? 5%
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
/RAS : SDRAMs D0-D15
/RAS
/CAS
/CAS : SDRAMs D0-D15
CKE : SDRAMs D0-D7
/WE : SDRAMs D0-D15
CKE0
STRAP IN (VSS) : VDD ≠ VDDQ
5. BAx, Ax, /RAS, /CAS, /WE resistors : 3 Ohms ? 5%
/WE
Rev. 1.1 / May. 2005
7
1184pin Unbufferd DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB, 128M x 72 ECC Unbuffered DIMM : HYMD512726B[P]8[J]
/S1
/S0
DQS4
DM4
DQS0
DM0
DM
I/O0
I/O1
I/O6
/S
DQS
DQS
DQS
DM
I/O0
I/O1
I/O6
/S
DQS
DQS
DQS
DM
I/O7
I/O6
I/O1
/S
DQS
DQS
DQS
DQS
DQS
DM
I/O7
I/O6
I/O1
/S
DQS
DQS
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
I/O0
I/O5
I/O0
I/O5
D12
I/O7
I/O2
I/O7
I/O2
D0
D8
D4
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
I/O3
I/O4
I/O5
DQ7
DQ39
DQS5
DM5
DQS1
DM1
DM
/S
DM
/S
DM
/S
DM
/S
DQ8
DQ9
I/O7
I/O6
I/O1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
I/O7
I/O6
I/O1
I/O0
I/O1
I/O6
I/O0
I/O1
I/O6
DQ10
DQ11
DQ12
DQ13
DQ14
I/O0
I/O5
D1
D9
I/O0 D5
D13
I/O7
I/O2
I/O7
I/O2
I/O5
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
I/O3
I/O4
I/O5
DQ15
DQ47
DQS2
DM2
DQS6
DM6
DM
/S
DM
/S
DM
/S
DM
I/O7
I/O6
I/O1
/S
I/O0
I/O1
I/O6
I/O0
I/O1
I/O6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
I/O7
I/O6
I/O1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
I/O7
I/O2
I/O7
I/O2
I/O0
I/O5
I/O0
I/O5
D14
D2
D10
D6
I/O3
I/O3
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
I/O4
I/O5
I/O4
I/O5
DQ55
DQ23
DQS3
DM3
DQS7
DM7
DM
/S
DM
/S
DQS
DM
/S
DM
/S
DQS
I/O0
I/O1
I/O6
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
I/O0
I/O1
I/O6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
I/O7
I/O6
I/O1
I/O7
I/O6
I/O1
I/O7
I/O2
I/O7
I/O2
I/O0
I/O5
I/O0
I/O5
D3
D11
D7
D15
I/O3
I/O4
I/O5
I/O3
I/O4
I/O5
I/O4
I/O3
I/O2
I/O4
I/O3
I/O2
DQ63
DQ31
DQS8
DM8
Serial PD
* Clock Wiring
Clock Input
SDRAMs
SCL
SDA
DM
/S
DM
/S
DQS
*CK0,/CK0
*CK1,/CK1
*CK2,/CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
WP
A0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
I/O7
I/O6
I/O1
I/O0
I/O1
I/O6
A1 A2
I/O0
I/O5
I/O7
I/O2
D8
D17
SA0 SA1 SA2
* Wire per Clock Loading
Table/Wiring Diagrams
I/O4
I/O3
I/O2
I/O3
I/O4
I/O5
Note :
CB7
1. DQ-to-I/O wiring is shown as
recommended
but may be changed.
VDDSPD
SPD
2. DQ/DQS/DM/CKE/S relationships
must be maintained as shown.
3. DQ,DQS,DM/DQS resistors
: 22 Ohms ? 5%
4. VDDID strap connections
(for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. BAx, Ax, /RAS, /CAS, /WE
resistors : 3 Ohms ? 5%
BA0-BA1-> : SDRAMs D0-D17
A0-A13-> : SDRAMs D0-D17
CKE : SDRAMs D8-D17
BA0-BA1
A0-A13
CKE1
/RAS
VDD/
VDDQ
DO-D15
DO-D15
/RAS : SDRAMs D0-D17
VREF
/CAS
CKE0
/WE
/CAS : SDRAMs D0-D17
CKE : SDRAMs D0-D8
/WE : SDRAMs D0-D17
DO-D15
VSS
Strap:see Note 4
VDDID
Rev. 1.1 / May. 2005
8
1184pin Unbufferd DDR SDRAM DIMMs
1
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
oC
Operating Temperature (Ambient)
TA
0 ~ 70
oC
V
Storage Temperature
TSTG
VDD
-55 ~ 150
-1.0 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
-0.5 ~3.6
50
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Voltage on inputs relative to Vss
Voltage on I/O pins relative to Vss
Output Short Circuit Current
Soldering Temperature ⋅ Time
VDDQ
VINPUT
VIO
V
V
V
IOS
mA
oC ⋅ Sec
TSOLDER
260 ⋅ 10
Note:
1. Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Power Supply Voltage (DDR 200, 266, 333)
Power Supply Voltage (DDR 400)
Power Supply Voltage (DDR 200, 266, 333)
Power Supply Voltage (DDR 400)
Input High Voltage
Symbol
VDD
Min
2.3
Typ.
2.5
2.6
2.5
2.6
-
Max
2.7
Unit
V
Note
VDD
2.5
2.7
V
2
1
VDDQ
VDDQ
VIH
2.3
2.7
V
2.5
2.7
V
1,2
VREF + 0.15
-0.3
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
VDDQ+0.3
VDDQ+0.6
1.4
V
Input Low Voltage
VIL
-
V
3
4
Termination Voltage
VTT
VREF - 0.04
VREF
V
Reference Voltage
VREF
VIN(DC)
VID(DC)
VI(RATIO)
ILI
0.49*VDDQ 0.5*VDDQ
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input Leakage Current
-0.3
0.36
0.71
-2
-
-
-
-
-
V
V
5
6
7
8
-
2
uA
uA
Output Leakage Current
ILO
-5
5
Normal Strength
Output Driver
Output High Current
(min VDDQ, min VREF, min VTT)
IOH
IOL
IOH
IOL
-16.8
16.8
-13.6
13.6
-
-
-
-
-
-
-
-
mA
mA
mA
mA
(VOUT=VTT±0.84)
Output Low Current
(min VDDQ, max VREF, max VTT)
Half Strength Out- Output High Current
put Driver
(VOUT=VTT ± 0.68)
(min VDDQ, min VREF, min VTT)
Output Low Current
(min VDDQ, max VREF, max VTT)
Note:
1. VDDQ must not exceed the level of VDD.
2. For DDR400, VDD=2.6V ± 0.1V, VDDQ=2.6V ± 0.1V
3. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to
peak noise on VREF may not exceed ± 2% of the DC value.
5. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-
ture and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum differ-
ence between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum
pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
7. VIN=0 to VDD, All other pins are not tested under VIN =0V.
8. DQs are disabled, VOUT=0 to VDDQ.
Rev. 1.1 / May. 2005
9
1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
256MB, 32M x 64 Unbuffered DIMM: HYMD532646B[P]6[J]
Speed
Symbol
Test Condition
Unit
Note
DDR400B
DDR333
DDR266B
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
600
560
480
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
800
40
720
40
600
40
mA
mA
mA
mA
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
140
48
140
48
140
48
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
IDD3N
200
180
160
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
IDD4R
IDD4W
IDD5
1120
1320
1200
1000
1120
1120
840
1000
1040
mA
mA
mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
Normal
20
10
20
10
20
10
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
2160
1840
1520
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
10
1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64M x 64 Unbuffered DIMM: HYMD564646B[P]8[J]
Speed
Symbol
Test Condition
Unit
Note
DDR400B
DDR333
DDR266B
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
1200
1120
960
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
1600
80
1440
80
1200
80
mA
mA
mA
mA
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
280
96
280
96
280
96
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
IDD3N
400
360
320
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
IDD4R
IDD4W
IDD5
2240
2240
2400
2000
2000
2240
1680
1680
2080
mA
mA
mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
Normal
40
20
40
20
40
20
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
4320
3680
3040
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
11
1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726B[P]8[J]
Speed
Symbol
Test Condition
Unit
Note
DDR400B
DDR333
DDR266B
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
1350
1260
1080
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
1800
90
1620
90
1350
90
mA
mA
mA
mA
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
315
108
315
108
315
108
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
IDD3N
450
105
360
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
IDD4R
IDD4W
IDD5
2520
2520
2700
2250
2250
2520
1890
1890
2340
mA
mA
mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
Normal
45
23
45
23
45
23
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
4860
4140
3420
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
12
1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
1GB, 128M x 64 Unbuffered DIMM: HYMD512646B[P]8[J]
Speed
Symbol
Test Condition
Unit
Note
DDR400B
DDR333
DDR266B
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
1600
1480
1280
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
2000
160
560
192
1800
160
560
192
1520
160
560
192
mA
mA
mA
mA
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
IDD3N
800
720
640
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
IDD4R
IDD4W
IDD5
2640
2640
2800
2360
2360
2600
2000
2000
2400
mA
mA
mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
Normal
80
40
80
40
80
40
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
4720
4040
3360
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
13
1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
1GB, 128M x 72 ECC Unbuffered DIMM: HYMD512726B[P]8[J]
Speed
Symbol
Test Condition
Unit
Note
DDR400B
DDR333
DDR266B
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
IDD0
1800
1665
1440
mA
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
IDD1
IDD2P
IDD2F
IDD3P
2250
180
630
216
2025
180
630
216
1710
180
630
216
mA
mA
mA
mA
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
IDD3N
900
810
720
mA
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
IDD4R
IDD4W
IDD5
2970
2970
3150
2655
2655
2925
2250
2250
2700
mA
mA
mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
Normal
90
45
90
45
90
45
mA
mA
CKE=<0.2V; External clock on;
tCK =tCK(min)
IDD6
IDD7
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
5310
4545
3780
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
14
1184pin Unbufferd DDR SDRAM DIMMs
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Max
-
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VREF + 0.31
-
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
0.7
V
1
2
0.5*VDDQ-0.2
V
Note:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
V
Reference Voltage
VDDQ x 0.5
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
VREF + 0.31
V
VREF - 0.31
V
VREF
VTT
1.5
1
V
V
V
Input minimum Signal Slew Rate
V/ns
Ω
Termination Resistor (RT)
50
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
OUTPUT LOAD CIRCUIT
VTT
Ω
RT=50
Output
Ω
Zo=50
VREF
CL=30pF
Rev. 1.1 / May. 2005
15
1184pin Unbufferd DDR SDRAM DIMMs
CAPACITANCE (TA=25oC, f=100MHz)
256MB: HYMD532646B[P]6[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
40
40
40
40
22
7
52
52
52
52
32
12
12
pF
pF
pF
pF
pF
pF
pF
/CS
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
7
512MB: HYMD564646B[P]8[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
58
58
58
58
25
7
71
71
72
72
40
12
12
pF
pF
pF
pF
pF
pF
pF
/CS
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
7
512MB (with ECC): HYMD564726B[P]8[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
CIO2
60
60
60
60
27
7
75
75
75
75
45
12
12
12
pF
pF
pF
pF
pF
pF
pF
pF
/CS
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
CB0 ~ CB7
7
7
Rev. 1.1 / May. 2005
16
1184pin Unbufferd DDR SDRAM DIMMs
CAPACITANCE (TA=25oC, f=100MHz)
1GB: HYMD512646B[P]8[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
90
90
58
58
30
12
12
104
104
72
pF
pF
pF
pF
pF
pF
pF
CKE0, CKE1
/CS0, /CS1
72
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
45
18
DQ0 ~ DQ63, DQS0 ~ DQS7
18
1GB (with ECC): HYMD512726B[P]8[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
CIO2
95
95
60
60
32
12
12
12
110
110
80
pF
pF
pF
pF
pF
pF
pF
pF
/CS0,/CS1
80
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
45
18
DQ0 ~ DQ63, DQS0 ~ DQS7
CB0 ~ CB7
18
18
Rev. 1.1 / May. 2005
17
1184pin Unbufferd DDR SDRAM DIMMs
AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)
DDR400B
DDR333
DDR266A
DDR266B
DDR200
Min Max
Parameter
Symbol
UNIT
Min
Max
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
55
-
-
60
-
-
65
-
65
-
70
80
50
-
ns
ns
ns
ns
Auto Refresh Row
Cycle Time
tRFC
tRAS
tRAP
70
40
72
42
75
45
-
120K
-
75
45
-
120K
-
-
120K
-
Row Active Time
70K
-
70K
-
Active to Read with
tRCD or
tRASmin
tRCD or
tRASmin
tRCD or
tRASmin
tRCD or
tRASmin
tRCD or
tRASmin
Auto Precharge Delay
Row Address to
Column Address Delay
tRCD
tRRD
tCCD
15
10
1
-
-
-
18
12
1
-
-
-
20
15
1
-
-
-
20
15
1
-
-
-
20
15
1
-
-
-
ns
ns
Row Active to Row
Active Delay
Column Address to
Column Address Delay
tCK
Row Precharge Time
Write Recovery Time
tRP
15
15
-
-
18
15
-
-
20
15
-
-
20
15
-
-
20
15
-
-
ns
ns
tWR
Internal Write to Read
Command Delay
tWTR
2
-
1
-
1
-
1
-
1
-
tCK
(tWR/
tCK)
+
(tWR/
tCK)
+
(tWR/
tCK)
+
(tWR/
tCK)
+
(tWR/
tCK)
+
Auto Precharge Write
Recovery + Precharge
Time22
tDAL
-
-
-
-
-
tCK
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
CL = 3
System
5
-
10
-
-
-
-
-
-
-
-
-
Clock Cycle
Time24
CL = 2.5
tCK
6
12
7.5
12
7.5
12
8.0
10
12
12
ns
ns
CL = 2
-
-
7.5
0.45
0.45
12
7.5
12
10
12
Clock High Level Width
Clock Low Level Width
tCH
tCL
0.45
0.45
0.55
0.55
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55 tCK
0.55 tCK
Data-Out edge to Clock
edge Skew
tAC
-0.7
-0.55
-
0.7
0.55
0.4
-0.7
-0.6
-
0.7
0.6
-0.75
-0.75
-
0.75
0.75
0.5
-0.75
-0.75
-
0.75
0.75
0.5
-0.75
-0.75
-
0.75
0.75
0.6
ns
ns
ns
DQS-Out edge to Clock
edge Skew
tDQSCK
tDQSQ
DQS-Out edge to Data-
Out edge Skew21
0.45
Data-Out hold time
from DQS20
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tQH
tHP
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
min
(tCL,tCH)
min
(tCL,tCH)
min
(tCL,tCH)
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period19,20
Data Hold Skew
Factor20
tQHS
tDV
-
0.5
-
0.55
-
0.75
-
0.75
-
0.75
Valid Data Output
Window
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
Rev. 1.1 / May. 2005
18
1184pin Unbufferd DDR SDRAM DIMMs
- Continue
DDR400B
DDR333
DDR266A
Min Max
DDR266B
DDR200
Parameter
Symbol
UNIT
Min Max
Min Max
Min
Max
Min
Max
Data-out high-impedance window
from CK,/CK10
tHZ
tLZ
tIS
tIH
tIS
-0.7
-0.7
0.6
0.6
0.7
0.7
-0.7
-0.7
0.75
0.75
0.8
0.7
-0.75 0.75
-0.75 0.75
-0.75
0.75
-0.8
-0.8
1.1
1.1
1.1
1.1
0.8
ns
ns
ns
ns
ns
ns
Data-out low-impedance window
from CK, /CK10
0.7
0.7
-0.75
0.9
0.75
0.8
Input Setup Time (fast slew
rate)14,16-18
-
-
-
-
-
-
-
-
0.9
0.9
1.0
1.0
-
-
-
-
-
-
-
-
-
-
-
-
Input Hold Time (fast slew
rate)14,16-18
0.9
Input Setup Time (slow slew
rate)15-18
1.0
Input Hold Time (slow slew
rate)15-18
tIH
0.7
2.2
0.8
1.0
Input Pulse Width17
tIPW
-
-
-
2.2
-
-
-
2.2
-
-
-
2.2
-
-
-
2.5
-
-
-
ns
Write DQS High Level Width
Write DQS Low Level Width
tDQSH 0.35
tDQSL 0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
tCK
tCK
Clock to First Rising edge of DQS-
In
tDQSS 0.72
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tCK
tCK
tCK
DQS falling edge to CK setup time
tDSS
tDSH
0.2
0.2
-
-
-
-
-
-
-
-
-
-
DQS falling edge hold time from
CK
0.2
0.2
0.2
0.2
DQ & DM input setup time25
DQ & DM input hold time25
tDS
tDH
0.4
0.4
-
-
0.45
0.45
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.6
0.6
-
-
ns
ns
DQ & DM Input Pulse Width17
Read DQS Preamble Time
Read DQS Postamble Time
tDIPW 1.75
-
1.1
0.6
-
1.75
0.9
0.4
0
-
1.1
0.6
-
1.75
0.9
0.4
0
-
1.1
0.6
-
1.75
0.9
0.4
0
-
1.1
0.6
-
2
0.9
0.4
0
-
1.1
0.6
-
ns
tRPRE
tRPST
0.9
0.4
0
tCK
tCK
ns
Write DQS Preamble Setup Time12
Write DQS Preamble Hold Time
tWPRES
tWPREH 0.25
-
0.25
0.4
2
-
0.25
0.4
2
-
0.25
0.4
2
-
0.25
0.4
2
-
tCK
tCK
tCK
Write DQS Postamble Time11
Mode Register Set Delay
tWPST
tMRD
0.4
2
0.6
-
0.6
-
0.6
-
0.6
-
0.6
-
Exit Self Refresh to non-Read
command23
tXSNR
tXSRD
tREFI
75
200
-
-
-
75
200
-
-
-
75
200
-
-
-
75
200
-
-
-
80
200
-
-
-
ns
tCK
us
Exit Self Refresh to Read
command
Average Periodic Refresh
Interval13,25
7.8
7.8
7.8
7.8
7.8
Rev. 1.1 / May. 2005
19
1184pin Unbufferd DDR SDRAM DIMMs
Note:
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to
be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics).
VDDQ
50 Ω
Output
(VOUT)
30 pF
Figure: Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under
normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the
dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is
recognized as LOW.
7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference
level for signals other than CK, /CK is VREF.
8. The output timing reference voltage level is VTT.
9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previ-
ously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
14. For command/address input slew rate ≥ 1.0 V/ns.
15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns
16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended)
17. These parameters guarantee device timing, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
18. Slew Rate is measured between VOH(ac) and VOL(ac).
19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half
period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
Rev. 1.1 / May. 2005
20
1184pin Unbufferd DDR SDRAM DIMMs
20.tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the
worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,
and p-channel to n-channel variation of the output drivers.
21. tDQSQ:
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
22. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For DDR266B at CL=2.5 and tCK=7.5 ns
tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks
= ((2) + (3)) clocks
= 5 clocks
23. In all circumstances, tXSNR can be satisfied using
tXSNR = tRFCmin + 1*tCK
24. The only time that the clock frequency is allowed to change is during self-refresh mode.
25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid
READ can be executed.
Rev. 1.1 / May. 2005
21
1184pin Unbufferd DDR SDRAM DIMMs
SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS
The following tables are described specification parameters that required in systems using DDR devices to ensure
proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.
Input Slew Rate for DQ/DM/DQS (Table a.)
AC CHARACTERISTICS
PARAMETER
DDR400
DDR333
DDR266
DDR200
UNIT Note
Symbol
min
max
min
max
min
max
min
max
DQ/DM/DQS input slew rate
measured between VIH(DC),
VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
0.5
4.0
0.5
4.0
0.5
4.0
V/ns
1,12
Address & Control Input Setup & Hold Time Derating (Table b.)
Input Slew Rate
0.5 V/ns
Delta tIS
0
Delta tIH
UNIT
Note
0
0
0
ps
ps
ps
9
9
9
0.4 V/ns
+50
0.3 V/ns
+100
DQ & DM Input Setup & Hold Time Derating (Table c.)
Input Slew Rate
0.5 V/ns
Delta tDS
0
Delta tDH
UNIT
ps
Note
11
0
0
0
0.4 V/ns
+75
ps
11
0.3 V/ns
+150
ps
11
DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate (Table d.)
Input Slew Rate
Delta tDS
0
Delta tDH
UNIT
ps
Note
10
0
± 0.0 ns/V
+50
+50
+100
ps
10
± 0.25 ns/V
± 0.5 ns/V
+100
ps
10
Output Slew Rate Characteristics (for x4, x8 Devices) (Table e.)
Typical Range (V/
Slew Rate Characteristic
Minimum (V/ns)
Maximum (V/ns)
Note
ns)
Pullup Slew Rate
1.2 - 2.5
1.2 - 2.5
1.0
1.0
4.5
4.5
1,3,4,6,7,8
2,3,4,6,7,8
Pulldown Slew Rate
Output Slew Rate Characteristics (for x16 Device) (Table f.)
Typical Range (V/
Slew Rate Characteristic
Minimum (V/ns)
Maximum (V/ns)
Note
ns)
Pullup Slew Rate
1.2 - 2.5
1.2 - 2.5
1.0
1.0
4.5
4.5
1,3,4,6,7,8
2,3,4,6,7,8
Pulldown Slew Rate
Output Slew Rate Matching Ratio Characteristics (Table g.)
Slew Rate Characteristic
Parameter
DDR266A
DDR266B
DDR200
Note
min
max
min
max
min
max
Output Slew Rate Matching Ratio
(Pullup to Pulldown)
-
-
-
-
0.71
1.4
5,12
Rev. 1.1 / May. 2005
22
1184pin Unbufferd DDR SDRAM DIMMs
Note:
1. Pullup slew rate is characterized under the test conditions as shown in below Figure.
Test Point
Output
(VOUT)
Ω
50
VSSQ
Figure: Pullup Slew rate
2. Pulldown slew rate is measured under the test conditions shown in below Figure.
VDDQ
Ω
50
Output
(VOUT)
Test Point
Figure: Pulldown Slew rate
3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV)
Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example: For typical slew, DQ0 is switching
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
4. Evaluation conditions
Typical: 25 oC (Ambient), VDDQ = nominal, typical process
Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process
Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process
5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process
variation.
6. Verified under typical conditions for qualification purposes.
7. TSOP-II package devices only.
8. Only intended for operation up to 256 Mbps per pin.
9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.
The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), sim-
ilarly for rising transitions.
10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c
& d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on
the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The
delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(slew Rate2)}
For example:
If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would
result in the need for an increase in tDS and tDH of 100ps.
11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by
either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.
12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-
sitions through the DC region must be monotonic.
Rev. 1.1 / May. 2005
23
1184pin Unbufferd DDR SDRAM DIMMs
SIMPLIFIED COMMAND TRUTH TABLE
ADDR
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
A10/AP
BA
Note
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
H
H
X
X
L
L
L
L
L
L
L
L
OP code
OP code
1,2
1,2
H
L
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active
L
RA
V
V
1
1
Read
L
H
L
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
1,3
1
H
H
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
H
H
L
1,4
1,5
1
X
V
H
L
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
L
L
L
1
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry
Precharge Power
Down Mode
H
L
Exit
H
H
L
Entry
Exit
H
L
L
Active Power Down
Mode
H
X
Note :
1. DM( Hst=aLteosgiacrHeiDghonL’et vCeal,reL.=RLeofgeirctLoobwelLoewveWl,rXite=DMoans’kt CTraurteh, VTa=bVlea.lid Data Input, OP Code=Operand Code, NOP=No Operation )
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
WRITE MASK TRUTH TABLE
Function
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
DM
L
ADDR A10/AP
BA
Note
Data Write
H
H
X
X
X
X
X
X
1
1
Data-In Mask
H
Note:
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
Rev. 1.1 / May. 2005
24
1184pin Unbufferd DDR SDRAM DIMMs
PACKAGE DIMENSIONS
256MB, 32M x 64 Unbuffered DIMM: HYMD532646B[P]6[J]
Millimeters
Inches
Un it :
Front
133.35
5.25
131.35
5.171
128.95
5.077
31.75
1.250
(2) 0
2.5
0.098
Side
Back
3.18
.125MAX
(Front)
1.27+/-0.10
.050+/-.004
Rev. 1.1 / May. 2005
25
1184pin Unbufferd DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64M x 64 Unbuffered DIMM: HYMD564646B[P]8[J]
Millimeters
Inches
Unit :
Front
133.35
5.25
131.35
5.171
128.95
5.077
31.75
1.250
(2) 0
2.5
0.098
Back
Side
3.18
0.125MAX
(Front)
1.27+/-0.10
0.050+/-0.004
Rev. 1.1 / May. 2005
26
1184pin Unbufferd DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726B[P]8[J]
Millimeters
Inches
Un it :
Front
133.35
5.25
131.35
5.171
128.95
5.077
31.75
1.250
(2) 0
2.5
0.098
Back
Side
3.18
0.125MAX
(Front)
1.27+/-0.10
0.050+/-0.004
Rev. 1.1 / May. 2005
27
1184pin Unbufferd DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128M x 64 Unbuffered DIMM : HYMD564646B[P]8[J]
Millimeters
Inches
Front
Un it :
133.35
5.25
131.35
5.171
128.95
5.077
31.75
1.250
(2) 0
2.5
0.098
Back
Side
4.00
0.157MAX
(Front)
1.27+/-0.10
0.050+/-0.004
Rev. 1.1 / May. 2005
28
1184pin Unbufferd DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128M x 72 ECC Unbuffered DIMM: HYMD512726B[P]8[J]
Millimeters
Inches
Un it :
Front
133.35
5.25
131.35
5.171
128.95
5.077
31.75
1.250
(2) 0
2.5
0.098
Back
Side
4.00
0.157MAX
(Front)
1.27+/-0.10
0.050+/-0.004
Rev. 1.1 / May. 2005
29
1184pin Unbufferd DDR SDRAM DIMMs
REVISION HISTORY
Revision
History
Date
Remark
First Version Release - Datasheet coverage is changed from an individual module part to a
component based module family
1.0
1.1
Feb. 2005
May. 2005
Corrected PIN DESCRIPTION and PIN ASSIGNMENT Tables
Rev. 1.1 / May. 2005
30
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明