HYMD564726A8-K_技术文档

64Mx72 bits

Unbuffered DDR SDRAM DIMM

HYMD564726A(L)8-M/K/H/L

Preliminary

DESCRIPTION

Hynix HYMD564726A(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD564726A(L)8-M/

K/H/L series consists of nine 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.

Hynix HYMD564726A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of

industry standard. It is suitable for easy interchange and addition.

Hynix HYMD564726A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs

are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-

ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD564726A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

512MB (64M x 72) Unbuffered DDR DIMM based on

64Mx8 DDR SDRAM

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

•

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

Data inputs on DQS centers when write (centered

DQ)

•

Error Check Correction (ECC) Capability

2.5V +/- 0.2V VDD and VDDQ Power supply

Data strobes synchronized with output data for read

and input data for write

•

Programmable CAS Latency 2 / 2.5 supported

All inputs and outputs are compatible with SSTL_2

interface

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Fully differential clock operations (CK & /CK) with

100MHz / 133MHz

•

tRAS Lock-out function supported

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD564726A(L)8-M

HYMD564726A(L)8-K

HYMD564726A(L)8-H

HYMD564726A(L)8-L

133MHz (DDR266 2-2-2)

133MHz (DDR266A)

133MHz (DDR266B)

100MHz (DDR200)

VDD=2.5V

VDDQ=2.5V

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

SSTL_2

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Feb. 2003

1

HYMD564726A(L)8-M/K/H/L

PIN DESCRIPTION

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Pin Description

DQs Power Supply

Ground

CK0,/CK0,CK1,/CK1,CK2,/CK2

VDDQ

VSS

CS0

CKE0

VREF

Reference Power Supply

Power Supply for SPD

/RAS, /CAS, /WE

A0 ~ A12

VDDSPD

SA0~SA2

2

E PROM Address Inputs

2

BA0, BA1

Bank Address

SCL

SDA

E PROM Clock

2

DQ0~DQ63

Data Inputs/Outputs

E PROM Data I/O

CB0~CB7

DQS0~DQS8

DM0~DM8

VDD

Check Bit

WP

Write Protect Flag

VDD Identification Flag

Do not Use

Data Strobe Inputs/Outputs

Data-in Mask

VDDID

DU

Power Supply

NC

No Connection

PIN ASSIGNMENT

Name

VREF

DQ0

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Name

A5

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Name

VDDQ

/WE

93

Name

VSS

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Name

VSS

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Name

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

1

2

DQ24

VSS

DQ25

DQS3

A4

94

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

A6

3

DQ41

/CAS

VSS

95

DQ28

DQ29

VDDQ

DM3

A3

4

DQ1

DQS0

DQ2

VDD

DQ3

NC

96

5

97

6

DQS5

DQ42

DQ43

VDD

98

7

VDD

DQ26

DQ27

A2

99

VSS

8

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

DQ30

VSS

DQ46

DQ47

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

NC

DQ31

CB4

VSS

Vss

DQ48

DQ49

VSS

A13

VDDQ

DQ52

DQ53

NC

DQ8

DQ9

DQS1

VDDQ

CK1

A1

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

BA2*

DQ20

A12

CB5

CB0

CB1

VDD

DQS8

A0

VDDQ

CK0

/CK2

CK2

/CK0

VSS

VDD

VDDQ

DQS6

DQ50

DQ51

VSS

DM6

/CK1

VSS

DM8

A10

DQ54

DQ55

VDDQ

NC

CB2

VSS

CB3

BA1

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

CB6

VDDQ

CB7

VDDID

DQ56

DQ57

VDD

DQ60

DQ61

VSS

Key

key

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

145

146

147

148

149

150

151

152

153

VSS

DQ36

DQ37

VDD

VSS

DM7

DQS7

DQ58

DQ59

VSS

DQ21

A11

DQ62

DQ63

VDDQ

SA0

A9

DM2

VDD

DQ22

A8

DM4

DQ18

A7

DQ38

DQ39

VSS

BA0

WP

SA1

VDDQ

DQ19

DQ35

DQ40

SDA

SA2

SCL

DQ23

DQ44

VDDSPD

* These are not used on this module but may be used for other module in 184pin DIMM family

Rev. 0.1/Feb. 2003

2

HYMD564726A(L)8-M/K/H/L

FUNCTIONAL BLOCK DIAGRAM

/CS0

DQS0

DM0

DQS4

DM4

DQS

DM

/CS

DM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D0

D4

DQS1

DM1

DQS5

DM5

DM

/CS

DQS

DM

/CS

DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ9

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DQS

DM

/CS

DM

/CS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D2

D6

DQS3

DM3

DQS7

DM7

DQS

DM

/CS

DM

/CS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D3

D7

DQS8

DM8

*Clock Wiring

SDRAMs

DQS

DM

/CS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

Clock Input

D8

*CK0,/CK0

*CK1,/CK1

*CK2,/CK2

3 SDRAMs

* W ire per clock loading table/wiring diagrams

Serial PD

.

SPD

VDDSPD

SCL

W P

.

VDD/VDDQ

D0 - D8

SDA

= =

.

VREF

VSS

A0

A1

A2

=

. . . .

D0 - D8

SA0

SA1

SA2

. .

VDDID

Strap:see Note 4

Notes:

BA0-BA1

A0 - A12

/RAS

BA0-BA1 : SDRAMs D0 - D8

A0 - A12 : SDRAMs D0 - D8

/RAS : SDRAMs D0 - D8

/CAS : SDRAMs D0 - D8

CKE : SDRAMs D0 - D8

/W E : SDRAMs D0 - D8

1. DQ-to-I/O wiring is shown as recommended

but may be changed

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown

/CAS

CKE0

/W E

3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5%

4. VDDID strap connections

(for memory device VDD, VDDQ) :

Strap out :(open) : VDD=VDDQ

Strap In (Vss) : VDD= VDDQ

Rev. 0.1/Feb. 2003

3

HYMD564726A(L)8-M/K/H/L

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

0 ~ 70

^oC

V

Storage Temperature

TSTG

-55 ~ 125

-0.5 ~ 3.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Output Short Circuit Current

Power Dissipation

VIN, VOUT

VDD

V

VDDQ

IOS

V

mA

W

PD

9

^oC / Sec

Soldering Temperature Þ Time

TSOLDER

260 / 10

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS= 0V)

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

VDD

2.3

2.5

2.7

V

VDDQ

VIH

2.5

2.7

1

2

3

VREF + 0.15

-0.3

-

VDDQ + 0.3

VREF - 0.15

VREF + 0.04

0.51*VDDQ

VIL

Termination Voltage

Reference Voltage

VTT

VREF - 0.04

0.49*VDDQ

VREF

0.5*VDDQ

VREF

Note :

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of VREF is approximately equal to 0.5VDDQ.

AC OPERATING CONDITIONS (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

Input Differential Voltage, CK and /CK inputs

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

VREF + 0.31

V

VREF - 0.31

VDDQ + 0.6

0.7

1

2

Input Crossing Point Voltage, CK and /CK inputs

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

Rev. 0.1/Feb. 2003

4

HYMD564726A(L)8-M/K/H/L

AC OPERATING TEST CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Value

Unit

Reference Voltage

Termination Voltage

VDDQ x 0.5

V

VDDQ x 0.5

AC Input High Level Voltage (VIH, min)

AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level Voltage

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

VREF + 0.31

V

VREF - 0.31

V

VREF

VTT

1.5

1

V

Input minimum Signal Slew Rate

V/ns

W

pF

Termination Resistor (RT)

50

Series Resistor (RS)

25

Output Load Capacitance for Access Time Measurement (CL)

30

Rev. 0.1/Feb. 2003

5

HYMD564726A(L)8-M/K/H/L

CAPACITANCE (TA=25^oC, f=100MHz )

Parameter

Symbol

Min

Max

Unit

Input Capacitance

A0 ~ A12, BA0, BA1

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIO1

CIO2

TBD

pF

Input Capacitance

/RAS, /CAS, /WE

CKE0

Input Capacitance

CS0

Input Capacitance

CK0, /CK0, CK1, /CK1, CK2,/CK2

DM0 ~ DM8

Input Capacitance

Data Input / Output Capacitance

DQ0 ~ DQ63, DQS0 ~ DQS8

CB0 ~ CB7

Note :

1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

VTT

Ω

RT=50

Output

Ω

Zo=50

VREF

CL=30pF

Rev. 0.1/Feb. 2003

6

HYMD564726A(L)8-M/K/H/L

DC CHARACTERISTICS I (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min.

Max

Unit

Note

Add, CMD, /CS, /CKE

CK, /CK

-18

18

Input Leakage

Current

ILI

uA

1

-12

12

Output Leakage Current

Output High Voltage

Output Low Voltage

ILO

VOH

VOL

-5

5

uA

V

2

VTT + 0.76

-

IOH = -15.2mA

IOL = +15.2mA

VTT - 0.76

V

Note :

1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 2.7V

3. These values are device characteristics.

Rev. 0.1/Feb. 2003

7

HYMD564726A(L)8-M/K/H/L

DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)

Speed

-K -H

Parameter

Symbol

Test Condition

Unit Note

-M

-L

One bank; Active - Precharge ; tRC=tRC(min);

tCK= tCK(min) ; DQ,DM and DQS inputs changing

twice per clock cycle ; address and control inputs

changing once per clock cycle

IDD0

TBD

mA

Operating Current

One bank ; Active - Read - Precharge ; Burst

Length = 2 ; tRC=tRC(min); tCK= tCK(min) ;

address and control inputs changing once per clock

cycle

Operating Current

IDD1

TBD

mA

Precharge Power

Down Standby

Current

All banks idle ; Power down mode ; CKE= Low,

tCK= tCK(min)

IDD2P

IDD2N

IDD2F

TBD

mA

Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and

DM

Idle Standby Current

/CS = High, All banks idle ; tCK= tCK(min) ; CKE =

High ; address and control inputs changing once

per clock cycle. VIN = VREF for DQ, DQS and DM

/CS>=Vih(min); All banks idle; CKE>=Vih(min);

Addresses and other control inputs stable, Vin=Vref

for DQ, DQS and DM

Idle Quiet Standby

Current

IDD2Q

IDD3P

TBD

mA

Active Power Down

Standby Current

One bank active ; Power down mode ; CKE= Low,

tCK= tCK(min)

/CS= HIGH; CKE = HIGH; One bank; Active-

Precharge; tRC = tRAS(max); tCK = t CK (max);

DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing

once per clock cycle

Active Standby

Current

IDD3N

TBD

mA

Burst = 2 ; Reads; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK= tCK (min); IOUT = 0mA

Operating Current

IDD4R

IDD4W

IDD5

TBD

Burst = 2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK = tCK (min); DQ, DM, and DQS

inputs changing twice per clock cycle

mA

tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz;

distributed refresh

Auto Refresh Current

Self Refresh Current

Normal

TBD

mA

CKE =< 0.2V; External clock on;

IDD6

IDD7

tCK = tCK(min)

Low Power

Operating Current -

Four Bank Operation

Four bank interleaving with BL=4 Refer to the

following page for detailed test condition

TBD

mA

4banks active read with activate every 20ns,

AP(Auto Precharge) read every 20ns, BL=4,

tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS

inputs changing twice per clock cycle; 100%

addresses changing once per clock cycle

Random Read

Current

IDD7A

TBD

mA

Rev. 0.1/Feb. 2003

8

HYMD564726A(L)8-M/K/H/L

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

DDR266(2-2-2)

DDR266A

DDR266B

DDR200

Min Max

Parameter

Row Cycle Time

Symbol

Unit Note

Min

60

Max

Min

65

Max

Min

65

Max

tRC

-

70

80

50

-

ns

Auto Refresh Row Cycle Time

Row Active Time

tRFC

tRAS

75

45

120K

45

120K

45

120K

120K ns

Active to Read with Auto

Precharge Delay

tRAP

15

-

20

-

20

-

20

-

ns

16

Row Address to Column

Address Delay

tRCD

tRRD

tCCD

15

1

-

20

15

1

-

20

15

1

-

20

15

1

-

ns

Row Active to Row Active Delay

Column Address to Column

Address Delay

CK

Row Precharge Time

tRP

tWR

15

1

-

20

15

1

-

20

15

1

-

20

15

1

-

ns

Write Recovery Time

Write to Read Command Delay

tWTR

CK

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

Auto Precharge Write Recovery

+ Precharge Time

tDAL

tCK

-

CK

15

(tRP/tCK)

CL = 2.5

7.5

12

7.5

12

7.5

10

12

8.0

10

12

ns

System Clock

Cycle Time

CL = 2

Clock High Level Width

Clock Low Level Width

tCH

tCL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55 CK

Data-Out edge to Clock edge

Skew

tAC

tDQSCK

tDQSQ

tQH

-0.75

-

0.75

0.5

-

-0.75

-

0.75

0.5

-

-0.75

-

0.75

0.5

-

-0.8

-

0.8

0.6

-

ns

DQS-Out edge to Clock edge

Skew

DQS-Out edge to Data-Out edge

Skew

tHP

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

Data-Out hold time from DQS

Clock Half Period

ns 1, 10

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

tHP

-

ns

1,9

10

Data Hold Skew Factor

tQHS

tDV

-

0.75

-

0.75

-

0.75

-

0.75 ns

Valid Data Output Window

tQH-tDQSQ

ns

Data-out high-impedance

window from CK, /CK

tHZ

tLZ

-0.75

0.75

-0.75

0.75

-0.75

0.75

-0.8

0.8

17

Data-out low-impedance window

from CK, /CK

ns

Rev. 0.1/Feb. 2003

9

HYMD564726A(L)8-M/K/H/L

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

- continued -

DDR266(2-2-2)

DDR266A

Min Max

DDR266B

Min Max

DDR200

Min Max

Parameter

Symbol

Unit Note

Min

0.9

Max

Input Setup Time (fast slew rate)

Input Hold Time (fast slew rate)

Input Setup Time (slow slew rate)

Input Hold Time (slow slew rate)

Input Pulse Width

tIS

tIH

-

0.9

-

0.9

-

1.1

-

ns 2,3,5,6

ns 2,4,5,6

0.9

tIS

1.0

1.1

tIH

1.0

1.1

tIPW

tDQSH

tDQSL

2.2

2.5

ns

CK

6

Write DQS High Level Width

Write DQS Low Level Width

0.35

-

0.35

-

0.35

-

0.35

-

Clock to First Rising edge of

DQS-In

tDQSS

tDS

0.72

0.5

1.28

0.75

0.5

1.25

0.75

0.5

1.25

0.75

0.6

1.25

CK

ns

Data-In Setup Time to DQS-In

(DQ & DM)

6,7,

11~13

-

Data-in Hold Time to DQS-In (DQ

& DM)

6,7,

11~13

tDH

0.5

0.6

ns

DQ & DM Input Pulse Width

Read DQS Preamble Time

Read DQS Postamble Time

tDIPW

tRPRE

tRPST

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

1.75

0.9

0.4

0

-

1.1

0.6

-

2

0.9

0.4

0

-

1.1

0.6

-

ns

CK

Write DQS Preamble Setup Time tWPRES

Write DQS Preamble Hold Time

Write DQS Postamble Time

Mode Register Set Delay

tWPREH

tWPST

tMRD

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.25

0.4

2

-

0.6

-

0.6

-

0.6

-

0.6

-

Exit Self Refresh to Any Execute

Command

tXSC

tREFI

200

-

200

-

200

-

200

-

CK

us

8

Average Periodic Refresh Interval

7.8

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tIS

ps

Delta tIH

V/ns

0.5

ps

0

0.4

+50

0

0.3

+100

0

Rev. 0.1/Feb. 2003

10

HYMD564726A(L)8-M/K/H/L

5. CK, /CK slew rates are >=1.0V/ns

6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by

design or tester correlation.

7.

8.

Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9.

Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device

(i.e. this value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel

to n-channel variation of the output drivers.

¹¹.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

0.5

ps

0

ps

0

0.4

+75

+150

+75

+150

0.3

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

I/O Input Level

Delta tDS

Delta tDH

mV

ps

+280

+50

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS

slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns

and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

0

ps

0

ps

0

+/-0.25

+/- 0.5

+50

+100

+50

+100

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK

is equal to the actual system clock cycle time.

Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,

tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be

tRAS - BL/2 x tCK.

Rev. 0.1/Feb. 2003

11

HYMD564726A(L)8-M/K/H/L

SIMPLIFIED COMMAND TRUTH TABLE

A10/

ADDR

Command

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

BA

Note

AP

Extended Mode Register Set

Mode Register Set

Device Deselect

No Operation

H

X

L

H

L

OP code

1,2

X

H

L

X

H

X

H

X

1

Bank Active

RA

V

1

Read

L

H

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

1,3

1

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Read Burst Stop

Auto Refresh

H

L

1,4

1,5

1

X

V

H

X

H

L

H

L

H

L

H

X

H

X

H

X

H

X

V

X

1

Entry

L

1

Self Refresh

Exit

H

L

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

L

H

L

H

L

1

H

L

1

Entry

Precharge

Power Down

H

L

Mode

Exit

H

L

Entry

H

L

Active Power

Down Mode

Exit

H

X

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. DM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

Rev. 0.1/Feb. 2003

12

HYMD564726A(L)8-M/K/H/L

PACKAGE DIMENSIONS

Front

133.35

5.25

131.35

5.171

Side

128.95

5.077

3.18

0 .125MAX

31.75

1.250

(Front)

1.27+/-0.10

0.050+/-.004

(2) 0

2.5

0.098

Rev. 0.1/Feb. 2003

13

SERIAL PRESENCE DETECT

SPD SPECIFICATION

(64Mx72 Unbuffered DDR DIMM)

Rev. 0.1/Feb. 2003

14

HYMD564726A(L)8-M/K/H/L

SERIAL PRESENCE DETECT

Bin Sort :M(DDR266(2-2-2),K(DDR266A@CL=2)

H(DDR266B@CL=2.5),L(DDR200@CL=2)

Function Supported

Hexa Value

Byte#

Function Description

Note

M

K

H

L

M

K

H

L

Number of Bytes written into serial memory at module

manufacturer

0

128 Bytes

80h

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Total number of Bytes in SPD device

Fundamental memory type

Number of row address on this assembly

Number of column address on this assembly

Number of physical banks on DIMM

Module data width

256 Bytes

DDR SDRAM

08h

07h

0Dh

0Bh

01h

48h

00h

04h

13

11

1Bank

72 Bits

-

1

Module data width (continued)

Module voltage Interface levels(VDDQ)

DDR SDRAM cycle time at CAS Latency=2.5(tCK)

DDR SDRAM access time from clock at CL=2.5 (tAC)

Module configuration type

Refresh rate and type

Primary DDR SDRAM width

SSTL 2.5V

7.5ns

8.0ns

+/-0.8ns

75h

80h

2

+/-0.75ns

ECC

02h

82h

08h

7.8us & Self refresh

x8

Error checking DDR SDRAM data width

Minimum clock delay for back-to-back random column

15

1 CLK

01h

address(tCCD)

16

17

18

19

20

21

Burst lengths supported

Number of banks on each DDR SDRAM

CAS latency supported

CS latency

WE latency

DDR SDRAM module attributes

2,4,8

4 Banks

2, 2.5

0

0Eh

04h

0Ch

01h

02h

20h

1

Differential Clock Input

+/-0.2Voltage tolerance,

22

DDR SDRAM device attributes : General

Concurrent Auto Precharge

C0h

tRAS Lock Out

23

24

25

26

27

28

29

30

31

32

33

34

35

DDR SDRAM cycle time at CL=2.0(tCK)

DDR SDRAM access time from clock at CL=2.0(tAC)

DDR SDRAM cycle time at CL=1.5(tCK)

DDR SDRAM access time from clock at CL=1.5(tAC)

Minimum row precharge time(tRP)

Minimum row activate to row active delay(tRRD)

Minimum RAS to CAS delay(tRCD)

Minimum active to precharge time(tRAS)

Module row density

7.5ns

+/-0.75ns

10ns

+/-0.8ns

75h

A0h

75h

A0h

80h

2

-

00h

15ns

45ns

20ns

15ns

20ns

45ns

512MB

0.9ns

0.5ns

20ns

15ns

20ns

45ns

20ns

15ns

20ns

50ns

3Ch

2Dh

50h

3Ch

50h

2Dh

50h

3Ch

50h

2Dh

50h

3Ch

50h

32h

80h

00h

Command and address signal input setup time(tIS)

Command and address signal input hold time(tIH)

Data signal input setup time(tDS)

0.9ns

0.5ns

0.9ns

0.5ns

1.1ns

0.6ns

90h

50h

90h

50h

90h

50h

B0h

60h

Data signal input hold time(tDH)

36~40 Reserved for VCSDRAM

Undefined

41

Minimum active / auto-refresh time ( tRC)

60ns

75ns

65ns

70ns

80ns

3Ch

4Bh

41h

4Bh

41h

4Bh

46h

50h

Minimum auto-refresh to active/auto-refresh

42

75ns

command period(tRFC)

43

44

45

Maximum cycle time (tCK max)

Maximim DQS-DQ skew time(tDQSQ)

Maximum read data hold skew factor(tQHS)

12ns

0.5ns

12ns

0.5ns

12ns

0.5ns

12ns

0.6ns

30h

32h

75h

30h

32h

75h

30h

32h

75h

30h

3Ch

75h

0.75ns 0.75ns 0.75ns 0.75ns

46~61 Superset information(may be used in future)

Undefined

Initial release

-

00h

62

63

SPD Revision code

Checksum for Bytes 0~62

DDh

0Ah

35h

CFh

Rev. 0.1/Feb. 2003

15

HYMD564726A(L)8-M/K/H/L

SERIAL PRESENCE DETECT

- continued -

Function Supported

Hexa Value

Byte #

Function Description

Manufacturer JEDEC ID Code

Note

M

K

H

L

M

K

H

L

64

Hynix JEDEC ID

-

ADh

00h

65~71 --------- Manufacturer JEDEC ID Code

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

0*h

1*h

2*h

3*h

4*h

5*h

72

Manufacturing location

6

Asia Area

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

Manufacture part number(Hynix Memory Module)

-------- Manufacture part number(Hynix Memory Module)

Manufacture part number (DDR SDRAM)

Manufacture part number(Memory density)

Manufacture part number(Module Depth)

------- Manufacture part number(Module Depth)

Manufacture part number(Module type)

Manufacture part number(Data width)

-------Manufacture part number(Data width)

Manufacture part number(Refresh, # of Bank.)

Manufacture part number(Component Generation)

Manufacture part number(Component configuration)

Manufacture part number(Hyphen)

H

Y

M

D

5

6

4

Blank

7

2

48h

59h

4Dh

44h

35h

36h

34h

20h

37h

32h

36h

41h

38h

2Dh

6(8K refresh,4Bank)

A

8

‘-’

Manufacture part number(Minimum cycle time)

M

K

H

L

4Dh

4Bh

48h

4Ch

88~90 Manufacture part number(T.B.D)

-

20h

-

91

92

93

94

Manufacture revision code(for Component)

Manufacture revision code (for PCB)

Manufacturing date(Year)

3

4

5

Manufacturing date(Week)

95~98 Module serial number

-

99~127 Manufacturer specific data (may be used in future)

128~255 Open for customer use

Undefined

00h

Note :

1. The bank address is excluded

2. These value is based on the component specification

3. These bytes are programmed by code of date week & date year

4. These bytes apply to Hynix’s own Module Serial Number system

5. These bytes undefined and coded as ‘00h’

6. Refer to Hynix web site

Byte 85~86, Low power part

Function Supported

Hexa Value

Byte #

Function Description

Note

M

K

H

L

M

K

H

L

85

86

Manufacture part number(Low power part)

Manufacture part number(Component configuration)

L

8

4Ch

38h

Rev. 0.1/Feb. 2003

16


型号：	HYMD564726A8-K
厂家：	HYNIX SEMICONDUCTOR
描述：	Unbuffered DDR SDRAM DIMM 无缓冲DDR SDRAM DIMM 存储内存集成电路动态存储器双倍数据速率时钟
文件：	总16页 (文件大小：265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYMD564726A8-K [HYNIX]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E