HYMP112U728-C4 [HYNIX]
DDR DRAM Module, 128MX72, 0.5ns, CMOS, DIMM-240;
| 型号： | HYMP112U728-C4 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 128MX72, 0.5ns, CMOS, DIMM-240 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总22页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb 1st ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball
Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based DDR2 Unbuffered DIMM
series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
•
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
•
•
•
8 Bank architecture
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68ball FBGA
133.35 x 30.00 mm form factor
Posted CAS
Programmable CAS Latency 3, 4, 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Lead-free products are RoHS compliant
ORDERING INFORMATION
# of
DRAMs
# of
ranks
Part Name
Density
Organization
Materials
ECC
HYMP112U648-E3/C4
HYMP112U728-E3/C4
HYMP125U648-E3/C4
HYMP125U728-E3/C4
HYMP112U64P8-E3/C4
HYMP112U72P8-E3/C4
HYMP125U64P8-E3/C4
HYMP125U72P8-E3/C4
1GB
1GB
2GB
2GB
1GB
1GB
2GB
2GB
128Mx64
128Mx72
256Mx64
256Mx72
128Mx64
128Mx72
256Mx64
256Mx72
8
9
1
1
2
2
1
1
2
2
Leaded
Leaded
None
ECC
16
18
8
Leaded
None
ECC
Leaded
Lead free
Lead free
Lead free
Lead free
None
ECC
9
16
18
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
1
1240pin DDR2 SDRAM Unbuffered DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
C4 (DDR2-533)
Unit
Speed @CL3
Speed @CL4
Speed @CL5
CL-tRCD-tRP
400
400
-
400
533
-
Mbps
Mbps
Mbps
tCK
3-3-3
4-4-4
ADDRESS TABLE
# of
DRAMs
Refresh
Method
Density Organization Ranks
SDRAMs
# of row/bank/column Address
1GB
1GB
2GB
2GB
128M x 64
128M x 72
256M x 64
256M x 72
1
1
2
2
128Mb x 8
128Mb x 8
128Mb x 8
128Mb x 8
8
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
16
18
Rev. 1.0 / Apr. 2005
2
1240pin DDR2 SDRAM Unbuffered DIMMs
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are
sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read)
data is reference to the crossing of CK and /CK (Both directions of crossing)
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new com-
mands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1
is selected by S1
Differential
Crossing
CK[2:0], CK[2:0]
SSTL
CKE[1:0]
S[1:0]
SSTL
SSTL
Active High
Active Low
RAS, CAS, WE
ODT[1:0]
Vref
SSTL
Active Low
Active High
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
SSTL
Supply
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu-
nity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power
VDDQ
Supply
SSTL
plane as VDD pins.
BA[2:0]
-
-
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input difines the row
address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column address
when sampled at the cross point of the rising edge of CK and falling edge of CK. In
addition to the column address, AP is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During
a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state
of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.
A[9:0], A10/AP,
A[15:11]
SSTL
DQ[63:0], CB[7:0] SSTL
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled
High coincident with that input data during a write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
DM[8:0]
VDD,VSS
SSTL
Active High
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ
Supply
pins are tied to VDD/VDDQ planes on these modules.
Data strobe for input and output data. For Rawcards using x16 organized DRAMs,
DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin
of the DRAM
Differential
crossing
DQS[8:0], DQS[8:0] SSTL
These signals are tied at the system planar to either VSS or VDD to configure the serial
SA[2:0]
SDA
-
-
-
SPD EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to VDD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 1.7V to 3.6V.
SCL
VDDSPD
Supply
Rev. 1.0 / Apr. 2005
3
1240pin DDR2 SDRAM Unbuffered DIMMs
PIN CONFIGURATION
Front Side
1 pin
64 pin 65 pin
120 pin
184 pin
240 pin
185 pin
121 pin
Back Side
PIN ASSIGNMENT
Pin
1
Name
VREF
VSS
Pin
41
42
43
44
Name
VSS
Pin
81
82
83
84
Name
DQ33
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
Name
VSS
Pin
Name
Pin
Name
VSS
161 NC(CB4)* 201
162 NC(CB5)* 202
2
NC(CB0)*
NC(CB1)*
VSS
VSS
DQS4
DQS4
VSS
DQ4
DQ5
VSS
DM4
NC
3
DQ0
DQ1
VSS
163
VSS
203
4
164 NC(DM8)* 204
VSS
5
45 NC(DQS8)* 85
46 NC(DQS8)* 86
DM0
NC
165
166
NC
205
206
DQ38
DQ39
VSS
6
DQS0
DQS0
VSS
DQ34
DQ35
VSS
VSS
7
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
VSS
NC(CB2)*
NC(CB3)*
VSS
87
88
VSS
167 NC(CB6)* 207
168 NC(CB7)* 208
8
DQ6
DQ7
VSS
DQ44
DQ45
VSS
9
DQ2
DQ3
VSS
89
DQ40
DQ41
VSS
169
170
171
172
173
174
175
176
177
178
179
180
181
182
VSS
VDDQ
CKE1
VDD
A15
A14
VDDQ
A12
A9
209
210
211
212
213
214
215
216
217
218
219
220
221
222
10
11
12
13
14
15
16
17
18
19
20
21
22
90
VDDQ
CKE0
VDD
91
DQ12
DQ13
VSS
DM5
NC
DQ8
DQ9
VSS
92
DQS5
DQS5
VSS
93
VSS
BA2
94
DM1
NC
DQ46
DQ47
VSS
DQS1
DQS1
VSS
NC
95
DQ42
DQ43
VSS
VDDQ
A11
96
VSS
97
CK1
DQ52
DQ53
VSS
NC
A7
98
DQ48
DQ49
VSS
CK1
VDD
A8
NC
VDD
99
VSS
VSS
A5
100
101
102
DQ14
DQ15
VSS
A6
CK2
DQ10
DQ11
A4
SA2
VDDQ
A3
CK2
NC,TEST1
VDDQ
VSS
* The pin names in parenthesises are applied to DIMM with ECC only.
Rev. 1.0 / Apr. 2005
4
1240pin DDR2 SDRAM Unbuffered DIMMs
- Continued -
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
VSS
Pin
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
A2
Pin
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
VSS
Pin
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
DQ20
DQ21
VSS
Pin
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Name
A1
Pin
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
DM6
NC
DQ16
DQ17
VSS
VDD
VSS
DQS6
DQS6
VSS
VDD
CK0
VSS
VSS
DM2
NC
CK0
DQ54
DQ55
VSS
DQS2
DQS2
VSS
VDD
NC
DQ50
DQ51
VSS
VDD
A0
VSS
VDD
A10/AP
BA0
DQ22
DQ23
VSS
VDD
BA1
DQ60
DQ61
VSS
DQ18
DQ19
VSS
DQ56
DQ57
VSS
VDDQ
RAS
VDDQ
WE
DQ28
DQ29
VSS
DM7
NC
DQ24
DQ25
VSS
DQS7
DQS7
VSS
S0
CAS
VDDQ
ODT0
A13
VSS
VDDQ
S1
DM3
NC
DQ62
DQ63
VSS
DQS3
DQS3
VSS
DQ58
DQ59
VSS
ODT1
VDDQ
VSS
VSS
VDD
VSS
DQ30
DQ31
VSS
VDDSPD
SA0
DQ26
DQ27
SDA
DQ36
DQ37
DQ32
SCL
SA1
*NC=No connect
Notes :
1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs).
2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 1.0 / Apr. 2005
5
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) : HYMP112U64[P]8
/S0
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
DM
DM
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
D0
D4
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
I/O 6
I/O 7
I/O 6
I/O 7
/DQS1
/DQS5
DQS1
DM1
DQS5
DM5
DM
DM
DM
DM
DM
DM
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ8
DQ40
DQ9
DQ10
DQ11
DQ41
DQ42
DQ43
D1
D5
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
I/O 6
I/O 7
I/O 6
I/O 7
/DQS2
/DQS6
DQS2
DM2
DQS6
DM6
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
D6
I/O 6
I/O 7
I/O 6
I/O 7
/DQS3
/DQS7
DQS3
DM3
DQS7
DM7
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
I/O 6
I/O 7
I/O 6
I/O 7
Clock Signal Loads
SCL
SCL
WP
SDA
Clock Input
CK0, /CK0
CK1, /CK1
CK2, /CK2
SDRAMs
Serial PD
2
3
3
A0
SA0
A1
SA1 SA2
A1
BA0-BA2
A0-A13
/RAS
SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7
Serial
PD
VDD SPD
VDD/VDDQ
VREF
Notes:
/CAS
DO-D7
DO-D7
DO-D7
1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.
2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %.
CKE0
/WE
SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7
ODT0
VSS
Rev. 1.0 / Apr. 2005
6
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) - HYMP112U72[P]8
/S0
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
DM
DM
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
D0
D4
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
I/O 6
I/O 7
I/O 6
I/O 7
/DQS1
/DQS5
DQS1
DM1
DQS5
DM5
DM
DM
DM
DM
DM
DM
DM
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ8
DQ40
DQ9
DQ10
DQ11
DQ41
DQ42
DQ43
D1
D5
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
I/O 6
I/O 7
I/O 6
I/O 7
/DQS2
/DQS6
DQS2
DM2
DQS6
DM6
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
D6
I/O 6
I/O 7
I/O 6
I/O 7
/DQS3
/DQS7
DQS3
DM3
DQS7
DM7
/CS DQS /DQS
/CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
I/O 6
I/O 7
I/O 6
I/O 7
/DQS8
DQS8
DM8
Clock Signal Loads
/CS DQS /DQS
Clock Input
CK0, /CK0
CK1, /CK1
CK2, /CK2
SDRAMs
SCL
SCL
WP
SDA
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
CB0
Serial PD
3
3
3
CB1
CB2
CB3
CB4
CB5
CB6
CB7
A0
SA0
A1
SA2
A1
A1
D8
SA1
I/O 6
I/O 7
Serial
PD
VDD SPD
VDD/VDDQ
VREF
BA0-BA2
A0-A13
SDRAMS D0-7,D8
SDRAMS D0-7,D8
SDRAMS D0-7,D8
Notes:
1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.
2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %.
DO-D8
DO-D8
DO-D8
/RAS
/CAS
SDRAMS D0-7,D8
CKE0
/WE
SDRAMS D0-7,D8
SDRAMS D0-7,D8
SDRAMS D0-7,D8
VSS
ODT0
Rev. 1.0 / Apr. 2005
7
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx64) - HYMP125U64[P]8
/S1
/S0
/ DQS0
DQS0
DM0
/ DQS4
DQS4
DM4
DM
DM
I/ O 0
DM
I/ O0
/CS
DQS /D
/
QS
/CS
DQS /DQS
/CS
DQS /DQS
DM
/CS
DQS /DQS
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
D0
D8
D4
D12
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
I/ O6
I/ O 7
I/ O 6
I/ O 7
I/ O6
I/ O7
I/ O 6
I/ O7
/ DQS1
/ DQS5
DQS1
DM1
DQS5
DM5
DM
/CS
DQS /DQS
DM
DM
DM
DQS /DQS
DQS /DQS
DQS /DQS
/CS
/CS
/CS
/CS
/CS
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
DQ8
DQ40
DQ9
DQ10
DQ11
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
D9
D5
D13
DQ12
DQ13
DQ14
DQ15
I/ O6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O7
I/ O6
I/ O7
/ DQS2
/ DQS6
DQS2
DM2
DQS6
DM6
DM
DM
DM
/CS
DQS /DQS
/CS
DQS /DQS
/CS
DQS /DQS
DM
DQS /DQS
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
D6
D10
D14
I/ O6
I/ O 7
I/ O 6
I/ O 7
I/ O6
I/ O 7
I/ O6
I/ O7
/ DQS3
/ DQS7
DQS3
DM3
DQS7
DM7
DM
DM
DQS /DQS
DQS /DQS
/CS
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O0
I/ O1
I/ O2
I/ O3
I/ O4
I/ O5
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D11
D7
D15
I/ O6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O7
I/ O6
I/ O7
BA0-BA2
SDRAMS D0-D15
SDRAMS D0-D15
SDRAMS D0-D7
SDRAMS D8-D15
SDRAMS D0-D15
SDRAMS D0-D15
SDRAMS D0-D15
SCL
WP
SCL
A0-A15
CKE0
SDA
Clock Signal Loads
Serial PD
Clock Input
CK0, /CK0
CK1, /CK1
CK2, /CK2
SDRAMs
CKE1
/CAS
/RAS
A0
SA0
A1
A1
SA2
4
6
6
SA1
/WE
ODT0
ODT1
Serial
PD
VDD SPD
VDD/VDDQ
VREF
SDRAMS D0-D7
SDRAMS D8-D15
DO-D15
DO-D15
DO-D15
Notes:
1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.
2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 Ω +/- 5 %.
VSS
Rev. 1.0 / Apr. 2005
8
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) - HYMP125U72[P]8
/S1
/S0
/ DQS0
DQS0
DM0
/ DQS4
DQS4
DM4
DM
DM
DM
DM
/
CS
DQS / DQS
/
CS
DQS / DQS
/
CS
DQS / DQS
/
CS
DQS / DQS
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D9
D4
D13
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS1
/ DQS5
DQS1
DM1
DQS5
DM5
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
/
/
/
/
CS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
/
/
/
CS
DQS / DQS
DQS / DQS
DQS / DQS
DQS / DQS
/
CS
DQS / DQS
DQS / DQS
DQS / DQS
/
/
/
CS
DQS / DQS
DQS / DQS
DQS / DQS
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ8
DQ40
DQ9
DQ10
DQ11
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
D10
D5
D14
DQ12
DQ13
DQ14
DQ15
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS2
/ DQS6
DQS2
DM2
DQS6
DM6
CS
CS
/
CS
CS
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
D6
D11
D15
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS3
/ DQS7
DQS3
DM3
DQS7
DM7
DM
CS
CS
CS
/
CS
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D12
D7
D16
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS8
DQS8
DM8
Serial
Clock Signal Loads
VDD SPD
VDD/VDDQ
VREF
PD
DM
CS
/
CS
Clock Input
CK0, /CK0
CK1, /CK1
CK2, /CK2
SDRAMs
DO-D17
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
CB0
6
6
6
DO-D17
DO-D17
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VSS
D8
D17
SCL
WP
SCL
SDA
I/ O 6
I/ O 7
I/ O 6
I/ O 7
Serial PD
A0
SA0
A1
A1
SA2
BA0-BA2
SDRAMS D0-D17
SDRAMS D0-D17
SDRAMS D0-D8
SDRAMS D9-D17
SDRAMS D0-D17
SDRAMS D0-D17
SA1
A0-A13
CKE0
Notes:
CKE1
/CAS
/RAS
1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.
2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 Ω +/- 5 %.
/WE
ODT0
ODT1
SDRAMS D0-D17
SDRAMS D0-D8
SDRAMS D9-D17
Rev. 1.0 / Apr. 2005
9
1240pin DDR2 SDRAM Unbuffered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDD
Value
Unit
Note
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
V
V
V
V
1
1
Voltage on VDD pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on VDDQ pin relative to Vss
VDDL
VDDQ
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-50 ~ +100
5 to 95
1
1
1
1
V
IN, VOUT
TSTG
Voltage on any pin relative to Vss
Storage Temperature
oC
HSTG
Storage Humidity(without condensation)
%
Notes:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
Notes
oC
TOPR
0 ~ +55
DIMM Operating temperature(ambient)
PBAR
DIMM Barometric Pressure(operating & storage)
105 to 69
0 ~+95
K Pascal
1
2
DRAM Component Case Temperature Range
oC
TCASE
Notes:
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
1.7
Max
1.9
Unit
V
Note
VDDL
1.7
1.9
V
Power Supply Voltage
VDDQ
VREF
1.7
1.9
V
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
V
VDDSPD
VTT
V
V
REF+0.04
V
3
VREF-0.04
Termination Voltage
Notes:
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 1.0 / Apr. 2005
10
1240pin DDR2 SDRAM Unbuffered DIMMs
INPUT DC LOGIC LEVEL
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.30
Max
Unit
V
Note
VDDQ + 0.3
VREF - 0.125
V
INPUT AC LOGIC LEVEL
Parameter
AC Input logic High
AC Input logic Low
Symbol
VIH(AC)
VIL(AC)
Min
Max
Unit
V
Note
V
REF + 0.250
-
V
-
V
REF - 0.250
AC INPUT TEST CONDITIONS
Symbol
VREF
Condition
Input reference voltage
Value
Units
Notes
0.5 * VDDQ
V
1
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
delta TR
Rising Slew =
V
min - V
REF
V
-
V
max
IL(ac)
IH(ac)
REF
Falling Slew =
delta TF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Apr. 2005
11
1240pin DDR2 SDRAM Unbuffered DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID (ac)
0.5
VDDQ + 0.6
V
1
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.
The minimum value is equal to VIH(DC) - VIL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 1.0 / Apr. 2005
12
1240pin DDR2 SDRAM Unbuffered DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18
Units
Notes
- 13.4
13.4
mA
mA
1, 3, 4
2, 3, 4
Notes:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
DDQ - 280 mV.
V
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 1.0 / Apr. 2005
13
1240pin DDR2 SDRAM Unbuffered DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
1GB : HYMP112U64[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
22
62
42
6
30
84
64
9
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
1GB : HYMP112U72[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
22
63
43
6
30
85
66
9
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB : HYMP125U64[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
22
64
50
8
35
87
88
13
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB : HYMP125U72[P]8
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
CI1
CI2
CIO
23
65
52
9
35
89
92
13
pF
pF
pF
pF
CKE, ODT,CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
Notes:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 1.0 / Apr. 2005
14
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD SPECIFICATIONS (T
: 0 to 95℃)
CASE
1GB, 128M x 64 U-DIMM : HYMP112U64[P]8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
800
880
48
880
960
48
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
320
360
200
56
400
440
240
64
480
1040
1120
2160
64
560
1360
1440
2160
64
1
IDD7
1920
2400
1GB, 128M x 72 ECC U-DIMM : HYMP112U72[P]8
Symbol
IDD0
E3(DDR2 400@CL3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
900
990
54
990
1080
54
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
360
405
225
63
450
495
270
72
540
1170
1260
2430
72
630
1530
1620
2430
72
1
IDD7
2160
2700
Notes:
1. IDD6 current values are guaranted up to Tcase of 85℃ max.
Rev. 1.0 / Apr. 2005
15
1240pin DDR2 SDRAM Unbuffered DIMMs
2GB, 256M x 64 U - DIMM : HYMP125U64[P]8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
1280
1360
96
1440
1520
96
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
640
800
720
880
400
480
112
128
960
1120
1920
2000
2720
128
1520
1600
2640
128
1
IDD7
2400
2960
2GB, 256M x 72 ECC U-DIMM : HYMP125U72[P]8
Symbol
IDD0
E3(DDR2 400@CL 3)
C4(DDR2 533@CL 4)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
1440
1530
108
1620
1710
108
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
720
900
810
990
450
540
126
144
1080
1710
1800
2970
144
1260
2160
2250
3060
144
1
IDD7
2700
3330
Notes:
1. IDD6 current values are guaranted up to Tcase of 85℃ max.
Rev. 1.0 / Apr. 2005
16
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD MEASUREMENT CONDITIONS
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
IDD0
IDD1
mA
t
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; CK =
t
t
t
t
t
t
t
CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH between valid
commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address
IDD2P
IDD2Q
IDD2N
mA
mA
mA
bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
mA
mA
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK
t
t
t
t
t
= CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6
current values are guaranted up to Tcase of 85℃ max.
Normal
Low Power
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
t
t
t
t
AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig-
nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not
including masks or strobes.
Rev. 1.0 / Apr. 2005
17
1240pin DDR2 SDRAM Unbuffered DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-533 (C4)
DDR2-400 (E3)
Unit
4-4-4
min
4
3-3-3
min
3
tCK
ns
15
15
tRP
15
15
ns
tRC
60
55
ns
tRAS
45
40
ns
AC Timing Parameters by Speed Grade
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
-600
-500
0.45
0.45
Max
600
Min
-500
-450
0.45
0.45
Max
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
500
450
ps
ns
500
0.55
0.55
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
System Clock Cycle Time
tCK
tDS
5000
150
275
25
8000
3750
100
225
-25
8000
ps
DQ and DM input setup time
-
-
-
-
-
-
-
-
-
-
ps
ps
1
1
1
1
DQ and DM input hold time
tDH
DQ and DM input setup time(single-ended strobe)
DQ and DM input hold time(single-ended strobe)
Control & Address input Pulse Width for each input
tDS1
tDH1
tIPW
ps
25
-25
ps
0.6
0.6
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
tHZ
0.35
-
0.35
-
tCK
Data-out high-impedance window from CK, /CK
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC max
tAC max
350
tAC min
tAC max
tAC max
300
ps
ps
ps
ps
ps
2*tAC min
2*tAC min
-
-
-
450
-
400
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
tQH
tHP - tQHS
-
tHP - tQHS
-
tDQSS
-0.25
+0.25
-0.25
+0.25
tCK
DQS input high pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
-
0.35
0.35
0.2
0.2
2
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
-
-
tDSH
-
-
tMRD
tWPST
tWPRE
-
-
0.4
0.35
0.6
-
0.4
0.35
0.6
-
Write preamble
Rev. 1.0 / Apr. 2005
18
1240pin DDR2 SDRAM Unbuffered DIMMs
- Continued -
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Address and control input setup time
Address and control input hold time
Read preamble
tIS
350
475
0.9
0.4
-
250
375
0.9
0.4
-
ps
ps
tIH
-
-
tRPRE
tRPST
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
105
-
105
-
ns
Row Active to Row Active Delay for 1KB page size
tRRD
tRRD
tFAW
tFAW
7.5
10
-
-
-
-
7.5
10
-
-
-
-
ns
ns
ns
ns
Row Active to Row Active Delay for 2KB page size
Four Activate Window for 1KB page size
Four Activate Window for 2KB page size
37.5
50
37.5
50
CAS to CAS command delay
tCCD
tWR
tDAL
2
15
tWR+tRP
2
15
tWR+tRP
tCK
ns
tCK
Write recovery time
Auto Precharge Write Recovery + Precharge Time
-
-
-
-
Write to Read Command Delay
tWTR
10
-
ns
7.5
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
tRTP
tXSNR
tXSRD
7.5
tRFC + 10
200
7.5
tRFC + 10
200
ns
ns
-
-
-
-
tCK
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
Exit active power down to read command
tXARD
tXARDS
6 - AL
6 - AL
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
tAOND
tAON
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
2
2
tAC(max)+
1
tAC(max)+
1
ODT turn-on
tAC(min)
tAC(min)
2tCK+tAC(
max)+1
2.5
tAC(max)+
0.6
2tCK+tAC(
max)+1
2.5
tAC(max)+
0.6
tAONPD
tAOFD
tAOF
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+tAC
(max)+1
2.5tCK+tAC
(max)+1
tAOFPD
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Notes:
1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS12[8/16]21(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 1.0 / Apr. 2005
19
1240pin DDR2 SDRAM Unbuffered DIMMs
PACKAGE OUTLINE
128Mx[64/72] - HYMP112U[64/72][P]8-E3/C4
Front
133.35
Side
2.7 max
ECC(x72) only.
(Front)
4.0±0.1
30.0
Detail-A
Detail-B
5.175
1.27 ± 0.10
5.175
63.0
55.0
5.0
Back
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
±
0.05
0.8
±
0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
20
1240pin DDR2 SDRAM Unbuffered DIMMs
PACKAGE OUTLINE
256Mx[64/72] - HYMP125U[64/72][P]8-E3/C4
Front
133.35
Side
4.00 max.
ECC(x72) only.
4.0±0.1
30.0
Detail-A
Detail-B
5.175
5.175
1.27 ± 0.10
63.0
55.0
5.0
Back
ECC(x72) only.
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
±
0.05
0.8
±
0.10
1.50
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
21
1240pin DDR2 SDRAM Unbuffered DIMMs
REVISION HISTORY
Revision
History
Date
Remark
First Version Release - Data sheet coverage is changed from an individual
module part to a component based module family.
Feb. 2005
Apr. 2005
1.0
Added VDDL spec, corrected tDS & tDH spec values.
Rev. 1.0 / Apr. 2005
22
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