HYMP112U72L8-E4 [HYNIX]
DDR DRAM Module, 128MX72, 0.6ns, CMOS, PDMA240;
| 型号： | HYMP112U72L8-E4 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR DRAM Module, 128MX72, 0.6ns, CMOS, PDMA240 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128Mx64 / 128Mx72 bits
Unbuffered DDR2 SDRAM DIMM
HYMP112U648/HYMP112U728
Revision History
No.
History
Draft Date
Remark
0.1
Defined target spec.
May. 2004
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/ May. 2004
1
128Mx64 / 128Mx72 bits
Unbuffered DDR2 SDRAM DIMM
HYMP112U648/HYMP112U728
Preliminary
DESCRIPTION
Hynix HYMP112U64(72)8 series is unbuffered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 128Mx64(72) high-speed memory arrays. Hynix HYMP112U64(72)8 series
consists of eignt(nine) 128Mx8 DDR2 SDRAM in 68-ball FBGA packages. Hynix HYMP112U64(72)8 series provide a
high performance 8-byte interface in 133.35mm width form factor of industry standard. It is suitable for easy inter-
change and addition.
Hynix HYMP112U64(72)8 series is designed for high speed and offers fully synchronous operations referenced to both
rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising
edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 4-bit prefetched to achieve very high bandwidth. All input and output volt-
age levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow
variety of device operation in high performance memory system.
Hynix HYMP112U64(72)8 series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
1GB Unbuffered DDR2 DIMM based on 128Mx8
DDR2 SDRAM
•
•
•
Fully differential clock operations (CK & /CK)
Programmable CAS Latency 3 / 4 /5 supported
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
•
•
•
All inputs and outputs SSTL_1.8 compatible
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
All inputs and outputs are compatible with SSTL_1.8
interface
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
ORDERING INFORMATION
Type
Part No.
Description
CL-tRCD-tRP
Form Factor
HYMP112U64(L)8-E4
HYMP112U64(L)8-E3
HYMP112U64(L)8-C5
HYMP112U64(L)8-C4
HYMP112U72(L)8-E4
HYMP112U72(L)8-E3
HYMP112U72(L)8-C5
HYMP112U72(L)8-C4
4-4-4
3-3-3
5-5-5
4-4-4
4-4-4
3-3-3
5-5-5
4-4-4
PC2-3200 (DDR2-400)
one rank 1GB
(128M x 64)
Unbuffered DIMM
(None ECC)
PC2-4300 (DDR2-533)
PC2-3200 (DDR2-400)
PC2-4300 (DDR2-533)
240pin Unbuffered
DIMM
133.35 mm x 30,00 mm
(MO-237)
one rank 1GB
(128M x 72)
Unbuffered DIMM
(ECC)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/ May. 2004
2
HYMP112U648/HYMP112U728
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs
are sampled on the crossing of positive edge of CK and negative edge of /CK.
Output(read) data is reference to the crossing of CK and /CK (Both directions of
crossing)
CK0~CK2
/CK0~/CK2
Differential
Crossing
SSTL
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down mode
or the Self Refresh mode.
CKE0~CKE1
SSTL
SSTL
Active High
Active Low
Enables the associated DDR2 SDRAM command decoder when low and dis-
ables the command decoder when high. When the command decoder is dis-
abled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1
/S0~/S1
/RAS, /CAS, /WE
ODT0~ODT1
Vref
SSTL
SSTL
Supply
Active Low
Active High
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the
DDR2 SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise
immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the
VDDQ
Supply
SSTL
same power plane as VDD pins.
BA0~BA2
-
-
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input difines the row
address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column
address when sampled at the cross point of the rising edge of CK and falling
edge of CK. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high., auto-
precharge is selected and BA0-BAn defines the bank to be precharged. If AP is
low, autoprecharge is disabled. During a Precharge command cycle., AP is used
in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high,
all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is
low, then BA0-BAn are used to define which bank to precharge.
A0~A13
SSTL
DQ0~DQ63,
CB0~CB7
SSTL
SSTL
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when
DM is sampled High coincident with that input data during a write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
DM0~DM8
VDD,VSS
Active High
Power and ground for the DDR2 SDRAM input buffers, and core logic.
VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
Supply
SSTL
Data strobe for input and output data. For Rawcards using x16 orga-
nized DRAMs, DQ0~7 connect to the LDQS pin of the DRAMs and
DQ8~15 connect to the UDQS pin of the DRAM
DQS0~DQS8,
/DQS0~/DQS8
Differential
crossing
These signals are tied at the system planar to either VSS or VDD to con-
figure the serial SPD EEPROM.
SA0~SA2
SDA
-
-
This is a bidirectional pin used to transfer data into or out of the SPD
EEPROM. A resister must be connected to VDD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A
resistor may be connected from SCL to VDD to act as a pull up on the
SCL
-
system board.
Power supply for SPD EEPROM. This supply is separate from the
VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to
3.6V.
VDDSPD
Supply
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
PIN CONFIGURATION
Front Side
1 pin
64 pin 65 pin
120 pin
184 pin
240 pin
185 pin
121 pin
Back Side
Pin Assignment
Pin
1
Name
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
NC
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Name
VSS
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
Name
DQ33
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Name
VSS
DQ4
DQ5
VSS
DM0
NC
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
Name
Pin
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
Name
VSS
NC(CB4)*
NC(CB5)*
VSS
2
NC(CB0)*
NC(CB1)*
VSS
VSS
DQS4
DQS4
VSS
DM4
NC
3
4
NC(DM8)*
NC
VSS
5
NC(DQS8)*
DQS8
VSS
DQ38
DQ39
VSS
6
DQ34
DQ35
VSS
VSS
7
VSS
DQ6
DQ9
VSS
DQ12
DQ13
VSS
DM1
NC
NC(CB6)*
NC(CB7)*
VSS
8
NC(CB2)*
NC(CB3)*
VSS
DQ44
DQ45
VSS
9
DQ40
DQ41
VSS
10
11
12
13
14
15
16
17
18
19
20
21
VDDQ
CKE1
VDD
VDDQ
CKE0
VDD
DM5
NC
DQS5
DQS5
VSS
A15
VSS
BA2
A14
DQ46
DQ47
VSS
NC
DQ42
VDQ43
VSS
VDDQ
A12
VDDQ
A11
VSS
NC
A9
DQS2
DQ53
VSS
A7
DQ48
DQ49
VSS
NC
VDD
NC
VDD
VSS
DQ14
DQ15
A8
VSS
DQ10
A5
A6
CK2
A4
SA2
VDDQ
CK2
22
DQ11
62
VDDQ
102
NC,TEST1
142
VSS
182
A3
222
VSS
* The pin names in parenthesises are applied to DIMM with ECC only. only.
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
Pin Assignment(Continued)
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
VSS
Pin
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
A2
Pin
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
VSS
Pin
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
DQ20
DQ21
VSS
Pin
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Name
A1
Pin
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
DM6
NC
DQ16
DQ17
VSS
VDD
VSS
DQS6
DQS6
VSS
VDD
CK0
CK0
VDD
A0
VSS
VSS
DM2
NC
DQ54
DQ55
VSS
DQS2
DQS2
VSS
VDD
NC
DQ50
DQ51
VSS
VSS
VDD
A10/AP
BA0
DQ22
DQ23
VSS
VDD
BA1
DQ60
DQ61
VSS
DQ18
DQ19
VSS
DQ56
DQ57
VSS
VDDQ
RAS
S0
VDDQ
WE
DQ28
DQ29
VSS
DM7
NC
DQ24
DQ25
VSS
DQS7
DQS7
VSS
CAS
VDDQ
S1
VDDQ
ODT0
A13
VSS
DM3
NC
DQ62
DQ63
VSS
DQS3
DQS3
VSS
DQ58
DQ59
VSS
ODT1
VDDQ
VSS
VSS
VDD
VSS
DQ36
DQ37
DQ30
DQ31
VSS
VDDSPD
SA0
DQ26
DQ27
SDA
DQ32
SCL
SA1
*NC=No connect; RFU=Reserved Future Use
Note :
1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs).
2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 0.1/ May. 2004
5
HYMP112U648/HYMP112U728
FUNCTIONAL BLOCK DIAGRAM
/S0
/DQS0
DQS0
DM0
/DQS4
DQS4
DM 4
DM
DM
/CS
DQS /DQS
/CS
DQS /DQS
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
D0
D4
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
I/O
I/O
6
7
I/O
I/O
6
7
/DQS1
/DQS5
DQS1
DM1
DQS5
DM 5
DM
DM
DM
DM
DM
DM
DM
/CS
DQS /DQS
DQS /DQS
DQS /DQS
DQS /DQS
/CS
DQS /DQS
DQS /DQS
DQS /DQS
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
DQ8
DQ40
DQ9
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
I/O
I/O
6
7
I/O
I/O
6
7
/DQS2
/DQS6
DQS2
DM2
DQS6
DM6
/CS
/CS
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
DQ16
DQ48
DQ17
DQ18
DQ19
DQ49
DQ50
DQ51
D2
D6
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
DQ54
DQ55
I/O
I/O
6
7
I/O
I/O
6
7
/DQS3
/DQS7
DQS3
DM3
DQS7
DM 7
/CS
/CS
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
I/O
I/O
6
7
I/O
I/O
6
7
/DQS8
DQS8
DM8
SCL
SCL
W P
SDA
/CS
Serial PD
Serial
PD
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
CB0
VDD SPD
A0
SA0
A1
A1
CB1
CB2
CB3
SA1
SA2
VDD/VDDQ
VREF
DO-D8
DO-D8
DO-D8
D8
CB4
CB5
CB6
CB7
VSS
I/O
I/O
6
7
D8 for ECC modules only
Notes :
BA0-BA2
A0-A13
SDRAMS D0-7,D8
SDRAMS D0-7,D8
SDRAMS D 0-7,D8
SDRAMS D 0-7,D8
1. DQ-to-I/O wiring shown as recommanded but may be changed.
2. DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be maintained as
shown.
3. DQ,DM,DQS,/DQS resistors;Refer to associated topology diagram.
4. BAx,Ax,/RAS,/CAS,/WE resistors: Refer to associate topology diagram
5. Refer to the appropriate clock wiring topology under the DIMM wiring
details section of this document.
/RAS
/CAS
CKE0
/W E
SDRAMS D 0-7,D8
SDRAMS D0-7,D8
SDRAMS D 0-7,D8
ODT0
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
TOPR
Value
0 ~ +55
Note
Unit
oC
Operating temperature(ambient)
DRAM Component Case Temperature Range
Operating Humidity(relative)
1
2
1
1
1
oC
%
TCASE
HOPR
0 ~+95
10 to 90
-50 ~ +100
5 to 95
oC
oC
Storage Temperature
TSTG
HSTG
Storage Humidity(without condensation)
Barometric Pressure(operating & storage)
PBAR
105 to 69
1,3
K Pascal
Note :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9㎲. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
3. Up to 9850 ft.
Operating Condtions(AC&DC)
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
Max
Unit
Note
1.7
1.7
1.9
1.9
V
V
V
V
V
Power Supply Voltage
VDDQ
VREF
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
VDDSPD
VTT
VREF+0.04
3
VREF-0.04
Termination Voltage
Note :
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Input DC Logic Level
Parameter
Input High Voltage
Symbol
Min
Max
Unit
Note
VIH(DC)
VIL(DC)
VREF + 0.125
-0.30
VDDQ + 0.3
V
V
Input Low Voltage
VREF - 0.125
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
Input AC Logic Level
Parameter
Symbol
Min
Max
Unit
Note
AC Input logic High
AC Input logic Low
VIH(AC)
VIL(AC)
VREF + 0.250
-
-
V
V
VREF - 0.250
AC Input Test Conditions
Symbol
VREF
Condition
Input reference voltage
Value
Units
Notes
0.5 * VDDQ
1.0
V
1
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
V
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising
edges and the range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and
VIH(ac) to VIL(ac) on the negative transitions.
Start of Rising Edge Input Timing
Start of Falling Edge Input Timing
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
V
delta TR
Rising Slew =
V
min - V
max
min -
V
max
IL(ac)
IH(ac)
IL(dc)
IH(dc)
Falling Slew =
delta TR
delta TF
< Figure : AC Input Test Signal Waveform >
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
Differential Input AC logic Level
Note
Symbol
Parameter
ac differential input voltage
ac differential cross point voltage
Min.
Max.
Units
1
VID (ac)
0.5
VDDQ + 0.6
V
2
VIX (ac)
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
V
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The
minimum value is equal to VIH(DC) - V IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Differential AC output parameters
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected
to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.1/ May. 2004
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HYMP112U648/HYMP112U728
Output Buffer Levels
Output AC Test Conditions
Symbol
VOH
Parameter
SSTL_18 Class II
VTT + 0.603
VTT - 0.603
Units Notes
Minimum Required Output Pull-up under AC Test Load
Maximum Required Output Pull-down under AC Test Load
Output Timing Measurement Reference Level
V
V
VOL
VOTR
0.5 * VDDQ
V
1
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18 Class II
Units
mA
Notes
1, 3, 4
2, 3, 4
- 13.4
13.4
mA
1.
V
DDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ
and VDDQ - 280 mV.
DDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
2.
V
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section
3.3) along a 21 ohm load line to define a convenient driver current for measurement.
OCD defalut characteristics
Description
Parameter
Min
12.6
0
Nom
Max
23.4
4
Unit
ohms
ohms
V/ns
Notes
1,2
Output impedance
18
Pull-up and pull-down mismatch
Output slew rate
1,2,3
Sout
1.5
-
5
1,4,5,6
Note:
1. Absolute Specifications (0°C ≤ TCASE ≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh
must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condi-
tion for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of
VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured
from AC to AC.
6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Rev. 0.1/ May. 2004
10
HYMP112U648/HYMP112U728
PIN CAPACITANCE (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
Non-ECC
ECC
Parameter
Pin
Symbol
Unit
Min
Max
Min
Max
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
CK0, /CK0
CKE0, /CS
CCK
CI1
23
66
46
6
32
87
68
9
23
67
47
6
32
90
70
9
pF
pF
pF
pF
Address, /RAS, /CAS, /WE
DQ,DM,DQS, /DQS
CI2
CIO
Note :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
IDD Specifications(max.)
128Mx64
128Mx72
Parameter
Symbol
Unit
PC2 3200 PC2 4300 PC2 5300 PC2 3200 PC2 4300 PC2 5300
Operating one bank
active-precharge current
IDD0
IDD1
800
880
40
880
960
48
960
1040
56
900
990
45
990
1080
54
1080
1170
63
mA
mA
mA
mA
Operating one bank active-
read-precharge current
Precharge power-down
current
IDD2P
IDD2Q
Precharge quiet standby
current
320
400
480
360
450
540
Precharge standby current
Active power-down current
Active Standby Current
IDD2N
IDD3P(F)
IDD3P(S)
IDD3N
360
200
56
440
240
64
520
280
72
405
225
63
495
270
72
585
315
81
mA
mA
mA
mA
480
560
640
540
630
720
Operating burst read
current
IDD4R
1040
1360
1840
1170
1530
2070
mA
Operating Current
IDD4W
IDD5B
IDD6
1120
2160
56
1440
2160
56
1920
2160
56
1260
2430
63
1620
2430
63
2160
2430
63
mA
mA
mA
mA
Burst auto refresh current
Self Refresh Current
IDD6(L)
40
40
40
45
45
45
Operating bank interleave
read current
IDD7
1920
2400
2640
2160
2700
2970
mA
Rev. 0.1/ May. 2004
11
HYMP112U648/HYMP112U728
IDD Meauarement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
ING;Data bus inputs are SWITCHING
IDD0
IDD1
mA
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is
mA
HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as
IDD4W
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control
IDD2P
IDD2Q
IDD2N
mA
mA
and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
mA
t
t
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
IDD3P
IDD3N
IDD4W
Slow PDN Exit MRS(12) = 1
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
= CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
IDD4R
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL =
t
t
t
t
t
t
t
t
CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
IDD7
t
t
mA
RCD = 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig-
nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not
including masks or strobes.
Rev. 0.1/ May. 2004
12
HYMP112U648/HYMP112U728
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-533(C4)
DDR2-533(C5)
DDR2-400(C3)
DDR2-400(C4)
Unit
4-4-4
min
4
5-5-5
min
3-3-3
min
3
4-4-4
min
4
5
ns
ns
ns
ns
ns
15
18.75
18.75
63.75
45
15
20
tRP
15
15
20
tRC
60
55
65
tRAS
45
40
45
AC Timing Parameters by Speed Grade
DDR2-400
DDR2-533
Parameter
Symbol
Unit
Note
Min
-600
-500
0.45
0.45
Max
600
Min
-500
-500
0.45
0.45
min
(tCL,tCH)
3750
350
Max
500
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
ps
ns
500
450
0.55
0.55
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
System Clock Cycle Time
tCK
tDH
tDS
5000
400
400
0.6
8000
8000
ps
ps
DQ and DM input hold time
-
-
-
-
-
-
1
1
DQ and DM input setup time
350
ps
Control & Address input Pulse Width for each input
tIPW
0.6
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
Data-out high-impedance window from CK, /CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC max
tAC min
tAC max
ps
ps
2*tAC min
tAC max
2*tAC min
tAC max
-
350
-
300
ps
-
tHP - tQHS
WL - 0.25
0.35
450
-
tHP - tQHS
WL - 0.25
0.35
400
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tQH
-
-
ps
tDQSS
tDQSH
tDQSL
tDSS
WL + 0.25
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
DQS input low pulse width
0.35
-
0.35
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
0.2
-
0.2
-
tDSH
0.2
-
-
0.2
-
-
tMRD
2
2
tWPST
tWPRE
0.4
0.6
-
0.4
0.6
-
Write preamble
0.25
0.25
Rev. 0.1/ May. 2004
13
HYMP112U648/HYMP112U728
- continued -
DDR2 400
DDR2 533
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Address and control input hold time
Address and control input setup time
Read preamble
tIH
tIS
600
600
0.9
0.4
-
500
500
0.9
0.4
-
ps
ps
-
-
tRPRE
tRPST
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
tRRD
127.5
7.5
-
-
127.5
7.5
-
-
ns
ns
Active to active command period
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
2
tCK
ns
15
-
-
15
-
-
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Auto Precharge Write Recovery + Precharge Time
Write to Read Command Delay
tDAL
tCK
ns
tWTR
10
-
7.5
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tRTP
tXSNR
tXSRD
7.5
tRFC + 10
200
7.5
tRFC + 10
200
ns
ns
-
-
-
-
tCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
CKE minimum pulse width
(high and low pulse width)
t
3
3
tCK
CKE
t
ODT turn-on delay
ODT turn-on
2
2
2
2
tCK
ns
AOND
t
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
AON
2tCK+tAC(ma
x)+1
2tCK+tAC(ma
x)+1
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
AONPD
t
2.5
2.5
AOFD
tAC(max)+
0.6
tAC(max)+
0.6
t
ODT turn-off
tAC(min)
tAC(min)
AOF
2.5tCK+tAC
(max)+1
2.5tCK+tAC
(max)+1
tAOFPD
ns
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tCK
tCK
ns
tANPD
tAXPD
tOIT
3
8
0
3
8
0
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
ns
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
us
us
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G831(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.1/ May. 2004
14
HYMP112U648/HYMP112U728
PACKAGE OUTLINE
Frontside View
133.35
Side
2.7 max
ECC(x72) only.
(Front)
4.0±0.1
30.0
Detail-A
Detail-B
1.27 ± 0.10
5.175
63.0
55.0
5.175
5.0
Backside View
3.0
3.0
Detail of Contacts A
Detail of Contacts B
2.50
1.0
0.8
± 0.05
1.50
± 0.10
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 0.1/ May. 2004
15
SERIAL PRESENCE DETECT
SPD SPECIFICATION
128Mx64(72) Unbuffered DDR2 DIMM
Rev. 0.1/ May. 2004
16
HYMP112U648/HYMP112U728
Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4),
C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)
SERIAL PRESENCE DETECT
Function Supported
Hexa Value
Speed
Grade
Byte#
Function Description
Note
128Mx64
128Mx72 128Mx64 128Mx72
0
1
2
3
4
5
6
7
8
Number of bytes utilized by module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
all
all
128 Bytes
80
08
08
0E
0A
60
40
00
05
50
3D
60
50
00
82
08
08
00
0C
04
38
00
02
00
01
50
3D
60
50
50
00
00
←
←
←
←
←
←
←
←
48
256 Bytes
all
DDR2 SDRAM
←
Number of row address on this assembly
Number of column address on this assembly
Number of DIMM ranks
all
14
1
1
←
all
10
←
all
1 rank
←
Module data width
all
72 Bits
64 Bits
Module data width (continued)
all
-
←
←
←
←
←
←
←
←
02
Voltage Interface level of this assembly
all
SSTL 1.8V
E3,E4
C4,C5
E3,E4
C4,C5
all
5.0 ns
2
2
←
9
DDR SDRAM cycle time at CL=5
3.75 ns
←
+/-0.6ns
←
10
DDR SDRAM access time from clock (tAC)
+/-0.5ns
←
ECC
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type
Refresh Rate and Type
None
all
7.8us & Self refresh
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Primary DDR SDRAM width
Error Checking DDR SDRAM data width
Reserved
all
x8
all
x8
-
Burst Lengths Supported
Number of banks on each SDRAM Device
CAS latency supported
all
all
all
4,8
4
3, 4, 5
Reserved
-
DIMM Type
all
all
Regular UDIMM
Normal
DDR SDRAM module attributes
DDR SDRAM device attributes : General
all
Supports weak driver
5.0ns
E3,E4,C5
C4
23
24
25
26
DDR SDRAM cycle time at CL=4(tCK)
2
2
2
2
3.75ns
E3,E4,C5
C4
+/-0.6ns
+/-0.5ns
5.0ns
DDR SDRAM access time from clock at CL=4(tAC)
DDR SDRAM cycle time at CL=3(tCK)
E3,C4
E4,C5
E3,C4
E4,C5
E3, C4
E4
Undefined
-
DDR SDRAM access time from clock at CL=3(tAC)
15ns
3C
50
4B
1E
3C
50
4B
28
2D
01
60
50
60
50
40
35
40
35
3C
28
1E
1E
00
06
56
37
3C
41
3F
27
28
29
Minimum Row Precharge Time(tRP)
20ns
C5
18.75ns
Minimum Row Activate to Row Active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
all
7.5ns
E3, C4
E4
15ns
20ns
C5
18.75ns
E3
40ns
30
31
32
Minimum active to precharge time(tRAS)
Module rank density
E4,C4,C5
all
45ns
1GB
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
all
0.6ns
Address and command input setup time before clock (tIS)
0.5ns
0.6ns
33
34
Address and command input hold time after clock (tIH)
Data input setup time before clock (tDS)
0.5ns
0.40ns
0.35ns
0.40ns
35
36
37
Data input hold time after clock (tDH)
Write recovery time(tWR)
0.35ns
15ns
E3, E4
C4, C5
all
10ns
Internal write to read command delay(tWTR)
7.5ns
38
39
Internal read to precharge command delay(tRTP)
Memory analysis probe characteristics
7.5ns
Undefined
E3,E4,C4
C5
Extension of Byte #42
Extension of Byte #41&42
55ns
40
Extension of byte 41 tRC and byte 42 tRFC
E3
C4
60ns
41
Minimum active / auto-refresh time ( tRC)
E4
65ns
C5
63.75ns
Rev. 0.1/ May. 2004
17
HYMP112U648/HYMP112U728
- continued -
Function Supported
Hexa Value
Speed
Grade
Byte#
Function Description
Note
128Mx64
128Mx72 128Mx64 128Mx72
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
42
43
44
all
127.5ns
7F
←
←
Maximum cycle time (tCK max)
all
8.0ns
80
23
1E
2D
28
00
00
10
53
DA
CD
B1
AD
00
←
←
←
←
←
←
←
←
←
←
←
←
E3, E4
C4, C5
E3, E4
C4, C5
0.35ns
Maximim DQS-DQ skew time(tDQSQ)
0.30ns
0.45ns
45
46
Maximum read data hold skew factor(tQHS)
PLL Relock time
0.40ns
No PLL
Undefined
47~61 Superset information(may be used in future)
←
←
-
←
←
65
EC
DF
C3
62
63
64
SPD Revision code
1.0
E3
E4
C4
C5
-
-
-
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
-
-
-
-
Hynix JEDEC ID
-
←
-
←
←
65~71 --------- Manufacturer JEDEC ID Code
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
0*
1*
2*
3*
4*
5*
72
Manufacturing location
6
←
←
Asia Area
73
74
75
76
77
78
79
80
81
82
83
84
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR2 SDRAM)
---------Manufacture part number(Memory density)
Manufacture part number(Module Depth)
H
Y
48
59
4D
50
31
31
32
55
36
34
38
2D
45
43
33
34
35
20
←
←
←
←
←
←
←
←
7
←
←
←
←
←
←
←
←
37
32
M
P
1
1
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
2
U
6
Manufacture part number(Data width)
-------Manufacture part number(Data width)
Manufacture part number(Component configuration)
Manufacture part number(Hyphen)
4
2
8
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
‘-’
E
E3, E4
C4, C5
E3
85
Manufacture part number(Minimum cycle time)
C
3
86
-------Manufacture part number(Minimum cycle time)
E4,C4
C5
4
5
87~90 Manufacture part number(T.B.D)
Blank
91
92
93
94
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
Manufacturing date(Year)
3
3
4
5
Manufacturing date(Week)
95~98 Module serial number
99~127 Manufacturer specific data (may be used in future)
Undefined
Undefined
00
00
←
←
←
←
128~25
Open for customer use
5
5
Note :
1. The bank address is excluded
2. This value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number System
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix Web Site
Byte 83~84, Low Power Part
Speed
Grade
Hexa
Value
Byte #
Function Description
Function Supported
Note
83
84
Manufacture part number(Low power part)
L
8
4C
38
Manufacture part number(Component Configuration)
Rev. 0.1/ May. 2004
18
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