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HYMP125F72CP8D5-Y5 [HYNIX]

240pin Fully Buffered DDR2 SDRAM DIMMs; 240PIN全缓冲DDR2 SDRAM DIMM内存模块
HYMP125F72CP8D5-Y5
型号： HYMP125F72CP8D5-Y5
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

240pin Fully Buffered DDR2 SDRAM DIMMs
240PIN全缓冲DDR2 SDRAM DIMM内存模块

动态存储器 双倍数据速率
文件： 总32页 (文件大小：1179K)
中文：  中文翻译
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240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb C-ver.  
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow  
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that  
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of  
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the  
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host  
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point  
Link Interface at 1.5V power.  
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control  
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,  
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for  
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other  
FBDIMMs on the memory channel.  
FEATURES  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module  
JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply  
All inputs and outputs are compatible with SSTL_1.8 interface  
Built with 1Gb DDR2 SDRAMs in 60ball FBGA  
Host interface and AMB component industry standard compliant  
MBIST, IBIST test functions  
8 Bank architecture  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
Fully differential clock operations (CK & CK)  
Programmable Burst Length 4 / 8 with both sequential and interleave mode  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
Serial presence detect with EEPROM  
133.35 x 30.35 mm form factor  
RoHS compliant  
Full DIMM Heat Spreader  
This document is a general product description and is subject to change without notice. Hynix Electronics does not  
assume any responsibility for use of circuits described. No patent licenses are implied.  
Rev 1.01 /Sep. 2008  
1
1240pin Fully Buffered DDR2 SDRAM DIMMs  
ORDERING INFORMATION  
AMB  
# of  
DRAMs ranks  
# of  
Part Name  
Density  
Org.  
H. S type Height  
Vendor Version  
HYMP112F72CP8N3-C4/Y5  
HYMP112F72CP8D3-C4/Y5/S5/S6  
HYMP112F72CP8D5-C4/Y5/S5/S6  
HYMP125F72CP8N3-C4/Y5  
Intel  
IDT  
D1  
C1  
1GB  
2GB  
4GB  
128Mx72  
9
1
2
2
AMB+  
D1  
Intel  
IDT  
HYMP125F72CP8D3-C4/Y5/S5/S6  
HYMP125F72CP8D5-C4/Y5/S5/S6  
HYMP151F72CP4N3-C4/Y5  
256Mx72  
512Mx72  
18  
36  
C1  
Full  
AMB+  
D1  
30.35mm  
Module  
Intel  
IDT  
HYMP151F72CP4D3-C4/Y5/S5/S6  
HYMP151F72CP4D5-C4/Y5/S5/S6  
HYMP151F72CP8D5-Y5/S5/S6  
HYMP31GF72CMP4D5-Y5/S5/S6  
C1  
AMB+  
AMB+  
AMB+  
4GB  
8GB  
512Mx72  
1Gx72  
36  
72  
4
4
IDT  
IDT  
Note  
*: The 14th and 15th digits stand for AMB vendor and revision.  
**: ‘P’ of Part Number;12th digit, stands for lead free products.  
SPEED GRADE & KEY PARAMETERS  
Speed Grade  
C4  
Y5  
S5/6  
Unit  
DDR2 DRAM Speed Grade  
FB-DIMM Speed Grade  
DDR2 533 4-4-4  
DDR2 667 5-5-5  
DDR2 800 5-5-5 / 6-6-6  
PC2 4200  
6.4  
PC2 5300  
8.0  
PC2 6400  
9.6  
FB-DIMM Peak Channel Throughput  
FB-DIMM Link Transfer Rate  
GByte/S  
GT/s  
3.2  
4.0  
4.8  
ADDRESS TABLE  
# of  
DRAMs  
Refresh  
Method  
Density Organization Ranks SDRAMs  
# of row/bank/column Address  
1GB  
2GB  
4GB  
4GB  
8GB  
128M x 72  
256M x 72  
512M x 72  
512M x 72  
1G x 72  
1
2
2
4
4
128Mbx8  
128Mbx8  
256Mbx4  
128Mbx8  
256Mbx4  
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)  
14(A0~A13)/3(BA0~BA2)/10(A0~A9)  
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
18  
36  
36  
72  
Rev 1.01 / Sep. 2008  
2
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Input/Output Functional Description  
Pin Name  
SCK  
type  
Input  
Polarity  
Positive  
Negative  
Positive  
Negative  
Positive  
Negative  
Positive  
Negative  
Positive  
Negative  
-
Function Description  
Count  
1
System clock input  
SCK  
Input  
System clock input  
1
PN[13:0]  
PN[13:0]  
PS[9:0]  
PS[9:0]  
SN[13:0]  
SN[13:0]  
SS[9:0]  
SS[9:0]  
SCL  
Output  
Output  
Input  
Primary Northbound Data  
Primary Northbound Data  
14  
14  
10  
10  
14  
14  
10  
10  
1
Primary Southbound Data  
Input  
Primary Southbound Data  
Output  
Output  
Input  
Secondary Northbound Data  
Secondary Northbound Data  
Secondary Southbound Data  
Input  
Secondary Southbound Data  
Input  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input / Output  
SDA  
Input / Output  
Input  
-
1
SA[2:0]  
-
SPD Address inputs, also used to select the DIMM number in the AMB  
3
Voltage ID: These pins must be unconnected for DDR2-based Fully buff-  
ered DIMMs  
2
VID[1:0]  
Input  
-
RESET  
RFU  
Input  
-
Active Low  
-
AMB reset signal  
1
16  
8
Reserved for Future Use  
VCC  
Supply  
Supply  
Supply  
Supply  
Supply  
+1.5V  
+1.8V  
+0.9V  
+3.3V  
AMB Core Power and AMB channel Interface Power(1.5volt)  
DRAM Power and AMB DRAM I/O Power  
DRAM Address/Command/Clock Termination Power(VDD/2)  
SPD Power  
VDD  
24  
4
VTT  
VDDSPD  
VSS  
1
Ground  
80  
1
The DNU/M_Test pin provides an external connection on R/Cs A-D for  
testing the margin of Vref which is produced by a voltage divider on the  
module. It is not intended to be used in normal system operation and  
must not be connected(DNU) in a system. This test pin may have other  
features on future card designs and if it does, will be included in this  
specification at that time.  
DNU/M_Test  
- / Analog  
- / 0.9V  
Total  
240  
Rev 1.01 / Sep. 2008  
3
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PIN ASSIGNMENT  
Pin  
1
Name  
VDD  
VDD  
VDD  
VSS  
VDD  
VDD  
VDD  
VSS  
VCC  
VCC  
VSS  
VTT  
Pin  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
Name  
PN13  
VSS  
VSS  
RFU*  
RFU*  
VSS  
VSS  
PN12  
PN12  
VSS  
PN6  
Pin  
81  
Name  
VSS  
PS4  
PS4  
VSS  
VSS  
RFU*  
RFU*  
VSS  
VSS  
PS9  
PS9  
VSS  
PS5  
PS5  
VSS  
PS6  
PS6  
VSS  
PS7  
PS7  
VSS  
PS8  
PS8  
VSS  
RFU**  
RFU**  
VSS  
VDD  
VDD  
VSS  
VDD  
VDD  
VDD  
VSS  
VDD  
VDD  
VTT  
SA2  
SDA  
SCL  
Pin  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
Name  
VDD  
VDD  
VDD  
VSS  
Pin  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
Name  
SN13  
VSS  
VSS  
RFU*  
RFU*  
VSS  
VSS  
SN12  
SN12  
VSS  
SN6  
Pin  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
Name  
VSS  
SS4  
2
82  
3
83  
SS4  
4
84  
VSS  
VSS  
RFU*  
RFU*  
VSS  
VSS  
SS9  
5
85  
VDD  
VDD  
VDD  
VSS  
6
86  
7
87  
8
88  
9
89  
VCC  
VCC  
VSS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
90  
91  
SS9  
PN6  
92  
VCC  
VCC  
VSS  
SN6  
VSS  
SS5  
VCC  
VSS  
VTT  
VSS  
PN7  
93  
VSS  
SN7  
94  
SS5  
PN7  
95  
VTT  
SN7  
VSS  
SS6  
VID1  
RESET  
VSS  
RFU**  
RFU**  
VSS  
PN0  
PN0  
VSS  
PN1  
PN1  
VSS  
PN2  
PN2  
VSS  
PN3  
PN3  
VSS  
PN4  
PN4  
VSS  
PN5  
PN5  
VSS  
PN13  
VSS  
PN8  
96  
VID0  
DNU/M_Test  
VSS  
VSS  
SN8  
97  
SS6  
PN8  
98  
SN8  
VSS  
SS7  
VSS  
PN9  
99  
RFU**  
RFU**  
VSS  
VSS  
SN9  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
SS7  
PN9  
SN9  
VSS  
SS8  
VSS  
PN10  
PN10  
VSS  
PN11  
PN11  
VSS  
SN0  
VSS  
SN10  
SN10  
VSS  
SN11  
SN11  
VSS  
SN0  
SS8  
VSS  
VSS  
RFU*  
RFU*  
VSS  
SCK  
SCK  
VSS  
VDD  
VDD  
VDD  
VSS  
VDD  
VDD  
VTT  
SN1  
SN1  
VSS  
SN2  
Key  
SN2  
Key  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
VSS  
PS0  
PS0  
VSS  
PS1  
PS1  
VSS  
PS2  
PS2  
VSS  
PS3  
PS3  
VSS  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
VSS  
SS0  
SS0  
VSS  
SS1  
SS1  
VSS  
SS2  
SS2  
VSS  
SS3  
SS3  
SN3  
SN3  
VSS  
SN4  
SN4  
VSS  
SN5  
SN5  
VDDSPD  
SA0  
VSS  
SN13  
SA1  
NC= No Connect, RFU= Reserved for Future Use.  
Note:  
*: These pin positions are reserved for forwarded clocks to be used in future module implementations  
**: These pin positions are reserved for future architecture flexibility  
1) The following signals are CRC bits and thus appear out of the normal sequence:  
PN12/ PN12, SN12 / SN12, PN13 / PN13, SN13 / SN13,PS9 / PS9, SS9 / SS9  
Rev 1.01 / Sep. 2008  
4
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
1GB(128Mbx72) ECC FB-DIMM  
/S0  
DQS4  
/DQS4  
DQS13  
DQS0  
/DQS0  
DQS9  
DM  
NU  
/CS  
DQS /DQS  
DQS /DQS  
DQS /DQS  
DM  
RDQS /RDQS  
I/O 0  
NU  
/CS  
DQS /DQS  
RDQS /RDQS  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O  
I/O  
I/O  
0
1
2
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
D4  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
D0  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS5  
/DQS5  
DQS14  
DQS1  
/DQS1  
DQS10  
DM  
NU  
DM  
RDQS /RDQS  
I/O 0  
NU  
/CS  
/CS  
DQS /DQS  
RDQS /RDQS  
I/O  
I/O  
I/O  
0
1
2
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 1  
I/O 2  
D5  
D1  
I/O  
I/O  
I/O  
3
4
5
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O  
I/O  
6
7
DQS6  
/DQS6  
DQS15  
DQS2  
/DQS2  
DQS11  
DM  
NU  
/CS  
DM  
RDQS /RDQS  
I/O 0  
NU  
/CS  
DQS /DQS  
RDQS /RDQS  
I/O 0  
I/O 1  
I/O 2  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
D6  
D2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS3  
DQS7  
/DQS7  
DQS16  
/DQS3  
DQS12  
DM  
RDQS /RDQS  
I/O 0  
NU  
DM  
RDQS /RDQS  
I/O 0  
NU  
/CS  
DQS /DQS  
/CS  
DQS /DQS  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
D3  
D7  
I/O 3  
I/O 4  
I/O 5  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 6  
I/O 7  
DQS8  
/DQS8  
DQS17  
All address/command/control/clock  
VTT  
DM  
RDQS /RDQS  
I/O 0  
NU  
/CS  
DQS /DQS  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O 1  
I/O 2  
D8  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
SN0-SN13  
/SN0-/SN13  
SS0-SS9  
PN0-PN13  
Serial PD  
U0  
/PN0-/PN13  
PS0-PS9  
SDA  
A2  
SCL  
SCL  
WP  
SDA  
VTT  
VCC  
Terminators  
AMB  
/SS0-/SS9  
/PS0-/PS9  
A
M
B
A0  
A1  
/S0-/CS(all SDRAMs)  
CKE0 -> CKE  
DQ0-DQ63  
CB0-CB7  
DQS0-DQS17  
/DQS0-/DQS8  
VDD SPD  
Serial PD,AMB  
SA0 SA1 SA2  
VDD  
VREF  
VSS  
DO-D8, AMB  
DO-D8  
ODT -> ODT  
BA0-BA2  
SCL  
SDA  
SA0-SA2  
A0-A15  
/RAS  
DO-D8,SPD, AMB  
/CAS  
/RESET  
/WE  
CK/ /CK  
SCK/ /SCK  
Notes :  
1. DQ-to-I/O wiring may be changed within a byte.  
2. There are two physical copies of each address/command/control/clock.  
Rev 1.01 / Sep. 2008  
5
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
2GB(256Mbx72) ECC FB-DIMM  
/S1  
/S 0  
D Q S  
/D Q S  
D Q S 9  
D Q S 5  
/D Q S5  
D Q S14  
D M  
NU  
/R DQ S  
DM  
DQ S /D Q S  
NU  
DQ S /DQ S  
D M  
N U  
DM  
NU  
/CS  
/CS  
/CS  
/RDQ S  
DQ S /DQ S  
DQ S /DQ S  
DQ S /DQ S  
D Q S /DQ S  
DQ S /DQ S  
DQ S /DQ S  
DQ S /DQ S  
DQ S /DQ S  
/CS  
RDQ S  
RDQ S  
RDQ S /RDQ S  
RDQ S /RDQ S  
D Q 40  
D Q 41  
D Q 42  
D Q 43  
D Q 44  
D Q 45  
D Q 46  
D Q 47  
I/O  
I/O  
I/O  
0
1
2
I/O  
I/O  
I/O  
0
1
2
D Q 0  
D Q 1  
D Q 2  
D Q 3  
D Q 4  
D Q 5  
D Q 6  
D Q 7  
I/O  
I/O  
I/O  
0
1
2
I/O  
I/O  
I/O  
0
1
2
D0  
D9  
D 5  
D 14  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
D Q S1  
/D Q S 1  
D Q S 10  
D Q S6  
/D Q S 6  
D Q S15  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
RDQ S  
I/O  
I/O  
I/O  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
DQ S /DQ S  
NU  
/CS  
/RDQ S  
DQ S /DQ S  
NU /CS  
/R DQ S  
NU /CS  
/RDQ S  
NU /CS  
RDQ S  
/RDQ S  
D Q48  
D Q49  
D Q50  
D Q51  
D Q52  
D Q53  
D Q54  
D Q 55  
D Q 8  
D Q 9  
0
1
2
0
1
2
0
1
2
I/O  
I/O  
I/O  
0
1
2
D Q10  
D Q11  
D Q12  
D Q13  
D Q14  
D Q 15  
D1  
D 6  
D 15  
D10  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
D Q S7  
/D Q S7  
D Q S16  
D Q S2  
/D Q S 2  
D Q S11  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
DQ S /DQ S  
NU  
DQ S /DQ S  
NU /CS  
/RDQ S  
NU /CS  
RDQ S  
/RDQ S  
/CS  
NU  
/RDQ S  
/CS  
RDQ S  
/RDQ S  
D Q16  
D Q17  
D Q18  
D Q19  
D Q20  
D Q21  
D Q22  
D Q 23  
D Q 56  
D Q 57  
D Q 58  
D Q 59  
D Q 60  
D Q 61  
D Q 62  
D Q 63  
0
1
2
0
1
2
I/O  
I/O  
I/O  
0
1
2
I/O  
I/O  
I/O  
0
1
2
D 7  
D 16  
D2  
D11  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
D Q S 8  
/D Q S 8  
D Q S17  
D Q S 3  
/D Q S3  
D Q S12  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
RDQ S  
I/O  
I/O  
I/O  
D M  
RDQ S  
I/O  
I/O  
I/O  
DM  
RDQ S  
I/O  
I/O  
I/O  
DQ S /D Q S  
NU  
/RDQ S  
DQ S /DQ S  
NU  
/RDQ S  
NU  
/CS  
/RDQ S  
/CS  
NU  
/RDQ S  
/CS  
/CS  
D Q24  
D Q25  
D Q26  
D Q27  
D Q28  
D Q29  
D Q30  
D Q 31  
C B0  
C B1  
C B2  
C B3  
C B4  
C B5  
C B6  
C B7  
0
1
2
0
1
2
0
1
2
0
1
2
D3  
D12  
D 8  
D 17  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
D Q S4  
/D Q S4  
D Q S 13  
D M  
RDQ S  
DM  
NU  
DQ S /D Q S  
NU  
/RDQ S  
DQ S /DQ S  
/CS  
/RDQ S  
/CS  
RDQ S  
D Q32  
D Q33  
D Q34  
D Q35  
D Q36  
D Q37  
D Q38  
D Q 39  
I/O  
I/O  
I/O  
0
1
2
I/O  
I/O  
I/O  
0
1
2
D 13  
D 4  
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
3
4
5
6
7
SN0-SN13  
PN0-PN13  
/PN0-/PN13  
PS0-PS9  
/SN0-/SN13  
All address/com m and/control/clock  
VTT  
SS0-SS9  
/SS0-/SS9  
/S0-/CS (D0-D8)  
CKE0 -> CKE (D0-D8)  
/S1-/CS (D9-D17)  
CKE1 -> CKE (D9-D17)  
/PS0-/PS9  
A
M
B
DQ0-DQ63  
CB0-CB7  
DQS0-DQS17  
/DQS0-/DQS8  
VTT  
VCC  
Term inators  
AMB  
Serial PD  
U0  
ODT -> ODT (all SDRAMs)  
BA0-BA2 (all SDRAMs)  
A0-A15 (all SDRAMs)  
/RAS (all SDRAMs)  
/CAS (all SDRAMs)  
/W E (all SDRAM s)  
CK, /CK (all SDRAMs)  
SDA  
A2  
SCL  
SCL  
W P  
SDA VDD SPD  
Serial PD,AM B  
SCL  
SDA  
SA0-SA2  
VDD  
DO-D17, AMB  
DO-D17  
A0  
A1  
VREF  
VSS  
/RESET  
SA0 SA1 SA2  
DO-D17,SPD, AMB  
SCK, /SCK  
Notes :  
1. DQ-to-I/O wiring may be changed within a byte.  
2. There are two physical copies of each address/command/control/clock.  
Rev 1.01 / Sep. 2008  
6
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
4GB(512Mbx72) ECC FB-DIMM - 2 Rank  
VSS  
/S1  
/S0  
/DQS9  
DQS9  
/DQS0  
DQS0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQ4  
DQ5  
DQ6  
DQ7  
DQ0  
DQ1  
DQ2  
DQ3  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
D27  
I/O 2  
D9  
D0  
D18  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 3  
/DQS10  
DQS10  
/DQS1  
DQS1  
DM  
DM  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DM  
DM  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQ12  
DQ13  
DQ14  
DQ15  
/DQS11  
DQS11  
DQ 8  
DQ 9  
DQ10  
DQ11  
/DQS2  
DQS2  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
D10  
D28  
D1  
D19  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQ20  
DQ21  
DQ22  
DQ23  
DQ16  
DQ17  
DQ18  
DQ19  
I/O 1  
I/O 1  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
D11  
D29  
D2  
D20  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
/DQS14  
DQS14  
/DQS3  
DQS3  
DM  
DM  
DM  
DM  
DM  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQ28  
DQ29  
DQ30  
DQ31  
/DQS13  
DQS13  
DQ24  
DQ25  
DQ26  
DQ27  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
D21  
I/O 2  
D12  
D30  
D3  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 3  
/DQS4  
DQS4  
DQS/D Q S /CS DM  
I/O 0  
DM  
DM  
DM  
DM  
DQS  
/D Q S  
/CS  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQ36  
DQ37  
DQ38  
DQ39  
DQ 32  
DQ 33  
DQ 34  
DQ 35  
/DQS5  
DQS5  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 1  
I/O 1  
D22  
I/O 2  
D13  
D31  
D4  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
/DQS14  
DQS14  
DM  
DM  
DQS/D Q S /CS  
I/O 0  
I/O 1  
D14  
I/O 2  
DQS/D Q S /CS  
I/O 0  
I/O 1  
D32  
I/O 2  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
I/O 1  
D23  
I/O 2  
DQ44  
DQ45  
DQ46  
DQ47  
/DQS15  
DQS15  
DQ40  
DQ41  
DQ42  
DQ43  
/DQS6  
DQS6  
I/O 1  
I/O 2  
D5  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS/D Q S /CS  
I/O 0  
I/O 1  
D15  
I/O 2  
DQS/D Q S /CS  
I/O 0  
I/O 1  
D33  
I/O 2  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQ52  
DQ53  
DQ54  
DQ55  
/DQS16  
DQS16  
DQ48  
DQ49  
DQ50  
DQ51  
/DQS7  
DQS7  
I/O 1  
I/O 2  
I/O 1  
I/O 2  
D6  
D24  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DM  
DM  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQ60  
DQ61  
DQ62  
DQ63  
DQ56  
DQ57  
DQ58  
DQ59  
I/O 1  
I/O 1  
I/O 1  
D16  
I/O 2  
I/O 3  
I/O 1  
D34  
I/O 2  
I/O 3  
D7  
D25  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
/DQS17  
DQS17  
/DQS8  
DQS8  
DM  
DM  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
DQS/D Q S /CS DM  
I/O 0  
CB4  
CB5  
CB6  
CB7  
CB0  
CB1  
CB2  
CB3  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
D17  
D35  
D8  
D26  
I/O 2  
I/O 3  
I/O 2  
I/O 3  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
All address/command/control/clock  
VTT  
SN0-SN13  
PN0-PN13  
/PN0-/PN13  
PS0-PS9  
/SN0-/SN13  
SS0-SS9  
VTT  
VCC  
Terminators  
/SS0-/SS9  
/PS0-/PS9  
A
M
B
AMB  
/S0-/CS (all SDRAMs)  
CKE0 -> CKE (all SDRAMs)  
DQ0-DQ63  
CB0-CB7  
DQS0-DQS17  
/DQS0-/DQS17  
VDD SPD  
Serial PD  
Serial PD,AMB  
VDD  
SCL  
SCL  
SDA  
SDA  
DO-D35, AMB  
DO-D35  
ODT -> ODT (all SDRAMs)  
BA0-BA2 (all SDRAMs)  
A0-A15 (all SDRAMs)  
/RAS (all SDRAMs)  
/CAS (all SDRAMs)  
/WE (all SDRAMs)  
CK, /CK (all SDRAMs)  
U0  
SCL  
SDA  
SA0-SA2  
VREF  
VSS  
WP A0 A1 A2  
SA0 SA1 SA2  
DO-D35, SPD, AMB  
/RESET  
SCK, /SCK  
Notes:  
1. DQ-to-I/O wiring may be changed within a byte.  
2. There are two physical copies of each address/command/control/clock.  
Rev 1.01 / Sep. 2008  
7
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
4GB(512Mbx72) ECC FB-DIMM - 4 Rank  
DQS0  
DQS0  
DQS9  
S3  
S0  
S1  
S2  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ0  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D0  
D9  
D18  
D27  
DQ7  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS1  
DQS1  
DQS10  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ8  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ9  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
D1  
D10  
D19  
D28  
DQ15  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS2  
DQS2  
DQS11  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ16  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D2  
D11  
D20  
D29  
DQ23  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS3  
DQS3  
DQS12  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ24  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D3  
D12  
D21  
D30  
DQ31  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS4  
DQS4  
DQS13  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ32  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D4  
D13  
D22  
D31  
DQ39  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
Rev 1.01 / Sep. 2008  
8
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
4GB(512Mbx72) ECC FB-DIMM - 4 Rank  
DQS5  
DQS5  
DQS14  
S3  
S0  
S1  
S2  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ40  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D5  
D14  
D23  
D32  
DQ47  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS6  
DQS6  
DQS15  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ48  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D6  
D15  
D24  
D33  
DQ55  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS7  
DQS7  
DQS16  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ56  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D7  
D16  
D25  
D34  
DQ63  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQS8  
DQS8  
DQS17  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DM/ NU/  
RDQS RDQS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQS DQS CS  
DQ24  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
D8  
D17  
D26  
D35  
DQ31  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
SN0-SN13  
Serial PD  
SN0-SN13  
SS0-SS9  
SS0-SS9  
CKE0 -> CKE(D0-D17)  
CKE1 -> CKE(D18-D35)  
ODT0 -> ODT(D0-D17)  
ODT1 -> ODT(D18-D26)  
ODT2 -> ODT(D27-D35)  
BA0-BA2 (all SDRAMs)  
PN0-PN13  
SCL  
SDA  
PN0-PN13  
PS0-PS9  
PS0-PS9  
WP A0 A1 A2  
SA0 SA1 SA2  
A
M
B
VTT  
DQ0-DQ63  
CB0-CB7  
DQS0-DQS17  
Terminators  
VCC  
AMB  
SPD,AMB  
D0–D17,AMB  
D0–D17  
DQS0-DQS8  
VDDSPD  
VDD  
SCL  
SDA  
SA1-SA2  
SA0  
A0,A1-A3-A5-A7-A15(all SDRAMs)  
A2,A6 (D0-D7, D8-D16, D‘8-D25, D27-D34)  
VREF  
A2_ECC, A6_ECC (D8, D17, D26, D35)  
RAS (all SDRAMs)  
VSS  
D0–D17,SPD,AMB  
Note:  
RESET  
CAS (all SDRAMs)  
WE (all SDRAMs)  
CK/CK (all SDRAMs)  
1. DQ-to-I/O wiring may be changed within a byte.  
2. There are two physical copies of each address/command/control/clock excluding  
CKE0/1, ODT1/2, CS  
SCK/SCK  
All address/command/control/clock  
VTT  
Rev 1.01 / Sep. 2008  
9
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
8GB(1Gbx72) ECC FB-DIMM - 4 Rank  
VSS  
S1  
S3  
S0  
S2  
DQS0  
DQS0  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ0  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
DQS9  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D0  
D36  
D18  
D54  
DQS9  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ4  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ5  
DQ6  
DQ7  
DQS1  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D1  
D37  
D19  
D55  
DQS1  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ8  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ9  
DQ10  
DQ11  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D2  
D38  
D20  
D56  
DQS10  
DQS10  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ12  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ13  
DQ14  
DQ15  
DQS2  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D3  
D39  
D21  
D57  
DQS2  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ16  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ17  
DQ18  
DQ19  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D4  
D40  
D22  
D58  
DQS11  
DQS11  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ20  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D5  
D41  
D23  
D59  
DQS3  
DQS3  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ24  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ25  
DQ26  
DQ27  
DQS12  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D6  
D42  
D24  
D60  
DQS12  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ28  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D7  
D43  
D25  
D61  
DQS8  
DQS8  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CB0  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
CB1  
CB2  
CB3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D8  
D44  
D26  
D62  
Rev 1.01 / Sep. 2008  
10  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
8GB(1Gbx72) ECC FB-DIMM - 4 Rank  
VSS  
S1  
S3  
S0  
S2  
DQS4  
DQS4  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ32  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
DQS13  
D9  
D45  
D27  
D63  
DQS13  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ36  
DQ37  
DQ38  
DQ39  
DQS5  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D10  
D46  
D28  
D64  
DQS5  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ40  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ41  
DQ42  
DQ43  
DQS14  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D11  
D47  
D29  
D65  
DQS14  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ44  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ45  
DQ46  
DQ47  
DQS6  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D12  
D48  
D30  
D66  
DQS6  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ48  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ49  
DQ50  
DQ51  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D13  
D49  
D31  
D67  
DQS15  
DQS15  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ52  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ53  
DQ54  
DQ55  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D14  
D50  
D32  
D68  
DQS7  
DQS7  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ56  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
DQ57  
DQ58  
DQ59  
DQS16  
D15  
D51  
D33  
D69  
DQS16  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
DQ60  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ61  
DQ62  
DQ63  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D16  
D52  
D34  
D70  
DQS17  
DQS17  
DM  
DM  
DM  
DM  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
CS DQS DQS  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
CB4  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
CB5  
CB6  
CB7  
D17  
D53  
D35  
D71  
SN0-SN13  
SN0-SN13  
SS0-SS9  
VTT  
Terminators  
All address/command/control/clock  
VTT  
PN0-PN13  
VCC  
AMB  
Serial PD  
PN0-PN13  
PS0-PS9  
PS0-PS9  
SS0-SS9  
SPD,AMB  
D0–D71,AMB  
D0–D71  
S0-CS(D36-D53)  
S1-CS(D54-D71)  
S2-CS(D0-D17)  
S3-CS(D18-D35)  
VDDSPD  
VDD  
SCL  
SDA  
A
M
B
WP A0 A1 A2  
DQ0-DQ63  
CB0-CB7  
DQS0-DQS17  
VREF  
SA0 SA1 SA2  
CKE0 -> CKE(D0-D17, D36-D53)  
CKE2 -> CKE(D18-D35, D54-D71)  
ODT -> ODT0(D36-D71)  
VSS  
D0–D71,SPD,AMB  
Note:  
DQS0-DQS17  
1. DQ-to-I/O wiring may be changed within a byte.  
BA0-BA2 (all SDRAMs)  
A0-A13 (all SDRAMs)  
ECCA2, ECCA6 -> NC  
RAS (all SDRAMs)  
CAS (all SDRAMs)  
WE (all SDRAMs)  
SCL  
SDA  
SA1-SA2  
SA0  
2. There are two physical copies of each address/command/control/clock excluding CS.  
3. There are four physical copies of each clock.  
4. ECCA2 and ECCA6 does not use(NC)  
5. ODT pin(D0-D35) is connected to VSS  
RESET  
SCK/SCK  
CK/CK (all SDRAMs)  
Rev 1.01 / Sep. 2008  
11  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Architecture  
Advanced Memory Buffer Pin Description  
Pin Name  
Pin Description  
FB-DIMM Channel Signals  
System Clock Input, positive line  
Count  
99  
1
SCK  
SCK  
System Clock Input, negative line  
1
PN[13:0]  
PN[13:0]  
PS[9:0]  
Primary Northbound Data, positive lines  
Primary Northbound Data, negative lines  
Primary Southbound Data, positive lines  
Primary Southbound Data, negative lines  
Secondary Northbound Data, positive lines  
Secondary Northbound Data, negative lines  
Secondary Southbound Data, positive lines  
Secondary Southbound Data, negative lines  
To an external precision calibration resistor connected to Vcc  
DDR2 Interface Signals  
14  
14  
10  
10  
14  
14  
10  
10  
1
PS[9:0]  
SN[13:0]  
SN[13:0]  
SS[9:0]  
SS[9:0]  
FBDRES  
175  
9
DQS[8:0]  
DQS[8:0]  
Data Strobes, positive lines  
Data Strobes, negative lines  
9
Data Strobes(x4 DRAM only), positive lines. These signals are driven low to x8  
DRAM on writes.  
DQS[17:9]/DM[8:0]  
9
DQS[17:9]  
Data Strobes(x4 DRAM only), negative lines  
Data  
9
64  
8
DQ[63:0]  
CB[7:0]  
Checkbits  
A[15:0]A,A[15:0]B  
BA[2:0]A,BA[2:0]B  
RASA,RASB  
CASA,CASB  
WEA,WEB  
Addresses. A10 is part of the pre-charge command  
Bank Addresses  
32  
6
Part of command, with CAS, WE and CS[1:0]  
Part of command, with RAS, WE and CS[1:0]  
Part of command, with RAS, WE and CS[1:0]  
On-die Termination Enable  
2
2
2
ODTA,ODTB  
CKE[1:0]A,CKE[1:0]B  
CS[1:0]A,CS[1:0]B  
2
Clock Enable(one per rank)  
4
Chip Select(One per rank)  
4
CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs.  
CLK[3:2] should be output disabled when not in use.  
CLK[3:0]  
4
CLK[3:0]  
Negative lines for CLK[3:0]  
4
1
1
1
1
1
DDRC_C14  
DDRC_B18  
DDRC_C18  
DDRC_B12  
DDRC_C12  
DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18  
DDR Compensation: Resistor connected to common return pin DDRC_C14  
DDR Compensation: Resistor connected to common return pin DDRC_C14  
DDR Compensation: Resistor connected to VSS  
DDR Compensation: Resistor connected to VDD  
Rev 1.01 / Sep. 2008  
12  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Advanced Memory Buffer Pin Description  
Pin Name  
Pin Description  
SPD Bus Interface Signals  
Count  
5
1
SCL  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input / Output  
SDA  
1
SA{2:0]  
SPD Address Inputs, also used to select the DIMM number in the AMB  
Miscellaneous Signals  
3
163  
1
PLLTSTO  
VCCAPLL  
VSSAPLL  
TEST_pin#  
TESTLO_pin#  
BFUNC  
PLL Clock Observability Output  
Analog VCC for the PLL. Tied with low pass filter to VCC.  
Analog VSS for the PLL. Tied to  
1
1
Leave floating on the DIMM  
6
Tie to ground on the DIMM2  
5
Tie to ground to set functionality as “buffer on DIMM.”  
AMB reset signal  
1
RESET  
1
No connect. Many NC are connected to VDD on the DIMM, to lower the  
impedance of the VDD power islands.  
NC  
129  
RFU  
Reserved for Future Use  
Power/Ground Signals  
AMB Core Power(1.5 Volt)  
18  
213  
24  
VCC  
VCCFBD  
VDD  
VDDSPD  
VSS  
AMB Channel I/O Power(1.5 Volt)  
AMB DRAM I/O Power (1.8 Volt)  
SPD Power (3.3 Volt)  
Ground  
8
24  
1
156  
655  
Total  
Note:  
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ CK frequency.  
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on protype DIMMs: each pin should  
have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC.  
These resistors can be replaced on production DIMMs with a direct connection to ground.  
Rev 1.01 / Sep. 2008  
13  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Pin Assignments for the Advanced Memory Buffer(AMB) (Top View)  
655-Ball LFBGA 0.8 mm x 0.8 mm pitch  
Left Side  
1
2
3
4
5
6
7
8
9
10  
11  
12  
VDD  
DDRC  
DDRC  
VSS  
13  
TEST  
TESTLO  
VSS  
14  
VDD VDD  
VDD VSS  
15  
A
B
C
D
E
F
VSS DQ26 DQ12  
VDD DQS3 DQS3 VSS  
VSS DQS2 DQ18 VSS DQ4  
VDD DQS10 DQ13  
VDD DQS1 DQ10  
DQ11 DQS1 VSS  
DQ14 DQS10  
VSS  
DQ15  
DQ7  
VSS  
DQS9  
VSS  
VSS  
DQS9  
DQ6  
DQ9  
VSS  
DQ5  
VSS  
DQ3 DQS0  
DQ1 VSS  
DQ8  
DDRC DQS17  
DQS8 VDD  
DQ19 DQS2 VSS DQ16 DQ24  
DQ21 VSS DQ17 DQ29 VSS  
DQS8  
CB1  
DQ25  
DQ0  
DQ2  
BFUNC  
VSS  
VSS  
CB0  
RFU  
VSS  
VDD  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VSS  
CB2  
CB3  
RFU  
VDD  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VSS DQ20 DQ23 VSS DQ31 DQ27  
VSS TESTLO TEST VSS DQS0  
VDD  
RFU  
G
H
J
DQS11 DQS11 NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
DQS12 DQS12  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQ22 VSS  
VSS CLK2  
CLK2 CLK0  
CLK0 VSS  
ODT0A RFU  
CS1A CS0A  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQ28 DQ30  
VSS  
CKE1A  
RASA  
VSS  
VDD  
VSS  
BA1A  
VSS  
VSS  
WEA  
CKE0A  
VSS  
VDD  
VSS  
K
L
VCC  
A0A  
VCC  
VSS  
VSS  
M
N
P
CASA  
VSS  
BA2A  
A10A  
A3A  
VCC  
BA0A  
A1A  
VCC  
VSS  
VSS  
A6A  
VSS  
VSS  
A8A  
A2A  
VCC  
R
T
U
A11A  
VSS  
VSS  
A5A  
VCC  
VSS  
VSS  
A4A A13A  
A9A  
A7A  
VCC  
PN0  
PN0  
A15A  
A14A  
A12A  
RFU  
VCCFBD  
V
W
Y
PN1  
PN2  
PN3  
VSS  
PN1  
PN2  
PN3  
PN4  
VSS  
VSS  
VSS  
PN4  
SN0  
SN1  
SN2  
VSS  
SN0 VCCFBD VSS VCCFBD VSS  
RFUa RFUa VCCFBD  
VSS  
SN8  
SN8  
VSS  
VSS  
VSS  
SN1  
SN0  
VSS  
SN3  
SN3  
VSS  
SN4  
SN4  
VSS  
SN5  
SN6  
VSS  
SN13 SN12 SN6  
SN13 SN12 SN6  
SN7  
SN7  
VSS  
SN9 SN10  
SN9 SN10  
AA  
VSS  
PN7  
VSS  
PN8  
VSS  
VSS  
VSS  
AB  
AC  
VSS RESET PN5 PN13  
RFUa  
PN12  
PN6  
PN9 VSSAPLL VCCAPLL PN10 PN11  
PN9 FBDRES PLLTSTO PN10 PN11  
VSS  
3
PN5 PN13  
RFUa  
6
PN12  
7
PN6  
8
PN7  
9
PN8  
10  
1
2
4
5
11  
12  
13  
14  
15  
NC= No Connect, RFU= Reserved for Future Use.  
Note:  
a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations  
Rev 1.01 / Sep. 2008  
14  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Right Side  
16  
17  
TEST  
TEST  
VSS  
18  
19  
DQ52 DQS15  
VSS  
20  
21  
22  
DQ49 DQS6  
VSS  
DQ55 DQ51  
23  
24  
25  
26  
27  
28  
29  
A
B
C
D
E
F
VDD  
VDD  
DQS17  
CB6  
VDD  
VDD  
VDD  
DQ48 DQ38  
VDD  
DDRC  
DQS15 DQ53  
VSS  
DQS16 DQ63  
DQS6 DQ50  
VSS DQS7 DQ56  
DQ59 DQS7  
VSS DQ58 DQ39  
VSS DQ37 DQ35  
DQS4 DQS4  
VSS DQS13 DQS13  
VSS  
DDRC DQ54  
VSS  
DQ46 DQS14 VDD  
VSS DQS14 DQ47  
CB7  
VSS  
VSS  
VSS  
DQ36 DQ44  
VSS  
CB5  
DQS16  
VSS  
DQ61  
VSS  
NC  
DQ57  
VSS  
DQ33 DQ45  
VSS  
DQ41  
VSS  
CB4  
VDD  
DQ62 DQ60  
TEST TEST  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
SCL  
DQS5 DQ43  
G
H
J
TESTLO RFU  
RFU  
VSS  
VDD  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
DQ34 DQ32  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
SA0  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
SDA  
DQS5 DQ40  
VSS  
VDD  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VDD  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
NC  
VSS  
VSS  
CLK3  
CLK1  
VSS  
DQ42  
VSS  
NC  
RASB  
VSS  
RFU  
VSS  
K
L
NC  
ODT0B CS1B  
CLK3  
CLK1  
NC  
VSS  
CS0B  
A0B  
CASB  
VSS  
WEB  
BA1B  
VSS  
M
N
P
NC  
NC  
CKE0B VSS  
BA0B BA2B  
VSS CKE1B  
A2B  
A4B  
VSS  
NC  
VSS  
A1B  
R
T
U
NC  
A6B  
A10B  
VSS  
A3B  
A7B  
PS8  
VSS  
A5B  
PS8  
NC  
NC  
A11B  
A8B  
A9B  
A15B  
VSS VCCFBD RFU  
A14B  
V
W
Y
VCCFBD VSS VCCFBD VSS VCCFBD RFUa  
RFUa  
SS9  
SS9  
VSS  
VSS  
SS5  
SS5  
VSS  
A13B  
SS6  
A12B  
SS7  
SA2  
SS8  
SS8  
VSS  
SA1  
VSS  
VSS  
PS9  
PS7  
PS6  
PS5  
PS9  
PS7  
PS6  
PS5  
VSS  
VSS  
VSS  
VSS  
SS0  
SS0  
VSS  
SS1  
SS1  
VSS  
SS2  
SS2  
VSS  
SS3  
SS3  
VSS  
SS4  
SS4  
VSS  
SS6  
SS7  
AA  
VSS  
VSS  
AB  
AC  
VSS  
SN11  
VSS  
SCK TESTLO PS0  
SCK TESTLO PS0  
PS1  
PS2  
PS3  
PS4  
RFUa VDDSPD VSS  
RFU  
SN11  
VSS  
PS1  
PS2  
PS3  
PS4  
RFUa  
VSS  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
NC= No Connect, RFU= Reserved for Future Use.  
Note:  
a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations  
Rev 1.01 / Sep. 2008  
15  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Advanced Memory Buffer(AMB) DRAM Interface Specifications  
Please refer to the AMB Specification for all technical requirements  
The following specifications for the AMB constitute the subset which is critical for proper operation of the  
DDR2 SDRAM interface.  
Note:  
This list is not complete, more information will follow in later revisions of this specification.  
Critical AMB Specifications  
VDDQ =1.8V +/-0.1V  
Symbol  
Parameter  
Type  
Units Notes  
Min.  
Max  
245  
245  
tSU  
tH  
DQ to DQS / DQS setup time (read)  
DQ to DQS / DQS hold time (read)  
AMB Data Valid Before DQS  
AMB Data Valid After DQS  
Input  
Input  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
1
1
1
1
1
1
1
tDVBamb  
tDVAamb  
tCVBamb  
tCVAamb  
tDQSCKamb  
CIN  
Output  
Output  
Output  
Output  
Output  
470  
470  
C/A/CNTL Valid Before Clock  
C/A/CNTL Valid After Clock  
1030  
890  
DQS/DQS-to-CK/CK output skew  
-240  
240  
2.5  
Input Capacitance(DQ/DQS/DQS)  
2.0  
pF  
1
Note 1:  
The timing numbers are for example only. Design should be based on the latest component specifications  
Rev 1.01 / Sep. 2008  
16  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Basic Functionality  
1. Advanced Memory Buffer Overview  
The Advanced Memory Buffer reference design complies with the JEDEC FB-DIMM Architecture and Proto-  
col  
Specification.  
2. Advanced Memory Buffer Functionality  
2.1 Advanced Memory Buffer  
•
Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Archi-  
tecture and Protocol Specification to align the clocks and the frame boundaries verify channel connec-  
tivity and identify AMB DIMM position.  
•
Supports the forwarding of southbound and northbound frames, servicing requests directed to DIMM,  
as defined in the protocol chapter, and merging the return data into the northbound frames.  
If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.  
Detects errors on the channel and reports them to the host memory controller.  
Acts as DRAM memory buffer for all read, write and configuration accesses addressed to the DIMM.  
Provides a read buffer FIFO and a write buffer FIFO.  
Supports an SMBus protocol interface for access to the AMB configuration registers.  
Provides logic to support MEMBIST and IBIST Design for Test functions.  
Provides a register interface for the thermal sensor and status indicator.  
•
•
•
•
•
•
•
•
Functions as a repeater to extend the maximum length of FBD Links.  
2.2 Transparent Mode for DRAM Test Support  
In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through  
the FB-DIMM I/O pins. This allows the tester to send and arbitrary test pattern to the DRAMs. Transparent  
mode only supports a maximum DRAM frequency equivalent to DDR2 400.  
Transparent mode functionality:  
•
Reconfigure FB-DIMM inputs from differential high speed link receivers to two single ended lower  
speed receivers(~200 Mhz)  
•
•
These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs  
Used low speed direct drive FB-DIMM outputs to bypass high speed Parallel/Serial circuitry and provide  
test results back to tester  
2.3 DDR2 SDRAM  
•
•
•
Supports DDR2 at speeds of 533,667 and 800 MT/s  
Supports 512Mb devices in x4 and x8 configurations  
72 bit DDR2 SDRAM memory array  
Rev 1.01 / Sep. 2008  
17  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
3. Advanced Memory Buffer Block Diagram  
10x2  
10x2  
South bound  
Data in  
South bound  
Data out  
Data Merge  
PISO  
Re-Time  
Re-synch  
PLL  
1x2  
Demux  
I0*12  
Ref Clock  
I0*12  
MUX  
Reset#  
Link init SM &  
Control & CSRs  
Reset  
Control  
Init  
patterns  
IBIST - RX  
IBIST - RX  
4
4
DRAMclock  
Command  
Decoder &  
CRC Check  
Failover  
DRAMclock#  
DRAM Cmd  
Cmd  
Out  
DRAM Address  
/CommandCopy1  
LAI Logic  
29  
29  
DDR State  
Controller  
& CSRs  
Thermal  
Sensor  
DRAM Address  
/CommandCopy2  
36 Deep  
Write  
Data  
Data  
Out  
DDR  
Core Control  
& CSRs  
FIFO  
IO’s  
External MEMBIST  
DDR Calibration &  
DDR IOBIST/DFX  
DRAM Address  
Data/Strobe  
72+18X2  
Data In  
Data CRC Gen  
& Read FIFO  
LAI  
Controller  
NB LAI  
Buffer  
Sync & Idle  
Pattern Generator  
IBIST - TX  
IBISt - RX  
MUX  
SMbus  
Link init SM &  
Control & CSRs  
SMbus  
Controller  
Failover  
14*6*2  
14*12  
Demux  
PISO  
Re-synch  
Re-Time  
Data Merge  
Northbound  
DataOut  
Northbound  
DataIn  
14x2  
14x2  
Advanced Memory Buffer Block Diagram  
Rev 1.01 / Sep. 2008  
18  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
4. Interfaces  
Below Figure illustrates the AMB and all of its interfaces.They consists of two FB-DIMM links, one DDR2 channel and  
an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM.  
The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM.  
Memory Interface  
DDR2  
Channel  
SB FBD  
In Link  
SB FBD  
Out Link  
AM B  
NB FBD  
Out Link  
NB FBD  
In Link  
SMBus  
Advanced M em ory Buffer Interfaces  
4.1 FBD High-Speed Differential Point-to-Point Link (at 1.5V) Interfaces  
The Advanced Memory Buffer supports one FBD channel consisting of two bidirectional link interfaces  
using high speed differential point-to-point electrical signaling.  
The southbound input link is 10 lanes wid and carries commands and write data from the host memory  
controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data  
to the next FBD.  
The northbound input link is 13 to 14 lanes wide and carries read return data or status information from  
the next FB-DIMM in the chain back towards the host. The northbound output link forwards this informa-  
tion back towards the host and multiplexes in any read return data or status information that is generated  
internally.  
4.2 DDR2 Channel  
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The  
DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight  
check-bit signals.  
There are two copies of address and command signals to support DIMM routing and electrical require-  
ments.  
Four transfer bursts are driven on the data and check-bit lines at 800 MHz. Propagation delays between  
read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware  
state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single  
core clock. The Advanced Memory Buffer provides four copies of the command clock phase refer-  
ences(CLK[3:0]) and write data/check-bit strobes(DQSs) for each DRAM nibble.  
Rev 1.01 / Sep. 2008  
19  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
4.3 SMBus Slave Interface  
The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration regis-  
ters independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus,  
only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory  
Buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to  
insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus  
address straps located on the DIMM connector are used by the unique ID.  
4.4 FBD Channel Latency  
FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins  
to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory con-  
troller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel  
is always equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in  
a specific configuration with some number of DIMMs installed. As more DIMMs are added to the channel,  
additional latency is required to read from each DIMM on the channel. Because the channel is based on  
the point to point interconnection of buffer components between DIMMs, memory requests are required to  
travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configura-  
tion will have greater idle read latency compared to a 1DIMM channel configuration.The Variable Read  
Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in  
this section are representative of what might be achieved in typical AMB designs. Actual implementations  
with latencies less than the values listed will have higher application performance and vice versa.  
4.5 Peak Theoretical Throughput  
An FB-DIMM channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are  
transferred for every FBD Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a  
single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped  
channels provides a total of 72 bytes of data(64 bytes plus 8 bytes ECC)  
The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the  
DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput  
as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput as a single  
DRAM channel.For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data  
connection is 4.276 GB/sec.  
Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72  
bits of data are transferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte  
data transfer of and ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers from a single  
channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data(64 bytes plus & bytes ECC)  
When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will  
exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533  
DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec.  
The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical through-  
put of the Northbound data connection and the Southbound command and data connection. When the FBD frame rate  
matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM chan-  
nel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a DDR2 533 channel would be  
4.267 GB/sec, while the peak theoretical throughput of and FBD -/+533 channel would be 6.4 GB/sec.  
Rev 1.01 / Sep. 2008  
20  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
5 Hot-add  
The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a  
new DIMM south of the currently active last DIMM. It is assumed the system will be notified through some  
means of the addition of one or more new DIMMs so that specific commands can be sent to the host con-  
troller to initialize the newly added DIMM(s) and perform a Hot-add Reset to bring them into the channel  
timing domain. It should be noted that the power to the DIMM socket must be removed before a “hot-add”  
DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform  
function.  
6 Hot-remove  
In order to accomplish removal of DIMMs the host must perform a Fast Reset sequence targeted at the last  
DIMM that will be retained on the channel. The Fast Reset re-establish the appropriate last DIMM so that  
the Southbound  
Tx outputs of the last DIMM and the Southbound and Northbound outputs of the DIMMs beyond the last  
active DIMM are disabled. Once the appropriate outputs are disabled the system can coordinate the proce-  
dure to remove power in preparation for physical removal of the DIMM if needed.  
It should be noted that the power to the DIMM socket must be removed before a “hot-add” DIMM is  
inserted or removed. Applying or removing the power to a DIMM socket is a system platform function.  
7 Hot-replace  
Hot replace of DIMM is accomplished through combing th Hot-Remove and Hot-Add process.  
Rev 1.01 / Sep. 2008  
21  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Electrical Characteristics  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN, VOUT  
VCC  
Value  
Unit  
V
Note  
- 0.3 V ~ 1.75 V  
- 0.3 V ~ 1.75 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
1
1
1
1
1
Voltage on any pins relative to Vss  
Voltage on VCC relative to Vss  
V
VDD  
V
Voltage on VDD relative to Vss  
Voltage on VTT relative to Vss  
Storage Temperature range  
VTT  
V
- 55 oC ~ 100 oC  
oC  
TSTG  
Note:  
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device  
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
OPERATING TEMPERATURE RANGE  
Parameter  
Symbol  
TCASE  
Rating  
Units  
Notes  
0 ~ + 110  
oC  
AMB Component Case temperature Range  
DRAM Component Case Temperature Range  
0 ~ + 95  
oC  
1,2  
TCASE  
Note:  
1. Within the DRAM component Case Temperature range all DRAM specification will be supported.  
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced from 7.8us of  
tREFI to 3.9us.  
Supply Voltage Levels and DC Operating Conditions.  
Parameter  
AMB Supply Voltage  
DRAM Supply Voltage  
Symbol  
VCC  
Min  
Nom  
Max  
Unit  
V
Note  
1.455  
1.7  
1.5  
1.8  
1.575  
1.9  
VDD  
V
0.48 x VDD  
0.50 x VDD  
0.52 x VDD  
VTT  
V
Termination Voltage  
VDDSPD  
VIH(DC)  
VIL(DC)  
VIH(DC)  
VIL(DC)  
EEPROM Supply Voltage  
3.0  
2.1  
-
3.3  
3.6  
V
VDDSPD  
DC Input Logic High(SPD)  
DC Input Logic Low(SPD)  
DC Input Logic High(RESET)  
-
-
-
V
1
1
2
0.8  
-
V
1.0  
V
DC Input Logic Low(RESET)  
Leakage Current (RESET)  
Leakage Current (Link)  
-
-
-
-
+0.5  
+90  
+5  
V
2
2
3
IL  
IL  
-90  
-5  
uA  
uA  
Note:  
1. Applies for SMB and SPD bus Signals.  
2. Applies for AMB CMOS Signal RESET.  
3. for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications  
Rev 1.01 / Sep. 2008  
22  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Timing Parameters  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Note  
EI Assertion Pass-Thru Timing  
EI Deassertion Pass-Thru Timing  
EI Assertion Duration  
tEI Propagad  
tEID  
-
4
clks  
clks  
-
-
bit lock  
tEI  
100  
clks  
1
1
1
Bit Lock Interval  
tBitLock  
tFrameLock  
119  
154  
frames  
frames  
Frame Lock Interval  
Note:  
1. Defined in FB-DIMM Architecture and Protocol Spec.  
Environmental Parameters  
Symbol  
TOPR  
Parameter  
Operating temperature  
Rating  
Units  
Notes  
1
2
2
2
2
2
See Note  
10 to 90  
-50 to +100  
5 to 95  
HOPR  
TSTG  
Operating humidity(relative)  
Storage temperature  
%
oC  
%
m
HSTG  
PBAR  
Storage humidity(without condensation)  
Barometric pressure(operating)  
Barometric pressure (storage)  
3050  
PBAR  
15240  
m
Note:  
1. The designer must meet the case temperature specifications for individual module components.  
2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and  
device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating  
conditions for extended periods  
Rev 1.01 / Sep. 2008  
23  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
IDD Specification and Conditions  
I
Measurement Conditions  
DD  
Symbol  
Conditions  
Idle Current, single or last DIMML0 state, idle (0 BW)Primary channel enabled, Sec-  
ondary Channel Disabled CKE high. Command and address lines stable. DRAM clock  
active.  
Idle_0  
Idle Current, first DIMML0 state, idle (0 BW)Primary and Secondary channels  
enabled CKE high. Command and address lines stable. DRAM clock active.  
Idle_1  
Idle Current, DRAM power downL0 state, idle (0 BW)Primary and Secondary chan-  
nels enabledCKE low. Command and address lines floated. DRAM clock active, ODT  
and CKE driven low.  
Idle_2  
Active PowerL0 state. 50% DRAM BW, 67% read, 33% write.  
Primary and Secondary channels enabled. DRAM clock active, CKE high.  
Active_1  
Active_2  
Active Power, data pass throughL0 state. 50% DRAM BW to downstream DIMM,  
67% read, 33% write. Primary and Secondary channels enabled CKE high.  
Command and address lines stable. DRAM clock active.  
Channel Standby Average power over 42 frames where the channel enters and exits  
L0sDRAMs Idle (0 BW). CKE low. Command and address lines floated.  
Dram clocks active, ODE and CKE driven low.  
L0s  
Training  
(for AMB spec, not in  
SPD)  
Training Primary and Secondary channels enabled.100% toggle on all channels  
lanes.DRAMs idle (0 BW).CKE high. Command and address lines stable.DRAM clock  
active.  
Rev 1.01 / Sep. 2008  
24  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
IDD Power Supply Currents Specifications.  
SAC Timing Parameters by Speed Grade  
Power Supply  
Icc_Idle_0 @1.5V  
Idd_Idle_0 @1.8V  
Idle_0 Total Power  
Icc_Idle_1 @1.5V  
Idd_Idle_1 @1.8V  
Idle_1 Total Power  
Icc_Idle_2 @1.5V  
Idd_Idle_2 @1.8V  
Idle_2 Total Power  
Icc_Active_1 @1.5V  
Idd_Active_1 @1.8V  
Active_1 Total Power  
Icc_Active_2 @1.5V  
Idd_Active_2 @1.8V  
Active_2 Total Power  
Icc_L0s @1.5V  
Max.  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Unit  
mA  
mA  
W
Note1)  
mA  
mA  
W
mA  
mA  
W
mA  
mA  
W
mA  
mA  
W
mA  
mA  
W
Idd_L0s @1.8V  
L0s Total Power  
Icc_Training @1.5V  
Idd_Training @1.8V  
Training Total Power  
mA  
mA  
W
Note:  
1) Assure that Primary channel Drive strength at 100% with De-emphasis at -6.5dB Secondary channel drive strength  
at 60% with De-emphasis at -3dB when enabled. Address and Data fields are pseudo-random, which provides a 50%  
toggle rate on DRAM data lines and link lanes when data is being transferred.  
Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes  
northbound are enabled and active (12 lanes NB if non-ECC DIMM).  
SPD specific assumption:Number of devices on the specific DIMM assumed.Termination of command, address, and  
control is actual value used on the DIMM. ECC or non-ECC as per the specific DIMM.  
SPD specifies Delta TAMB power spec specific assumptions: Dual rank x8 ECC DIMM assumed (18 DRAM devices  
present on DIMM)  
Modeled with 27 ohm termination for command, address, and clocks, and 47 ohm termination for control.  
ECC DIMM assumed (72 bit data, 14 lanes northbound). AMB specification specifies current for each rail.  
Rev 1.01 / Sep. 2008  
25  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
Termination Current  
Internal signals are terminated on the DIMM through resistors to an external power supply VTT = VDD / 2.  
Modeled with 30 Ohm termination for clocks, 39 ohm for command / address and 47 ohm for control.  
The VTT power supply must be able to source and sink these currents:  
VTT Currents table  
Description  
Symbol  
Typ  
Max  
700  
700  
Unit  
mA  
ITT1  
Idle Current, DRAM Power Down (Conditions TBD)  
Active Power, 50% DRAM BW (conditions TBD)  
-
-
ITT2  
mA  
Rev 1.01 / Sep. 2008  
26  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PACKAGE OUTLINE  
128Mx72, 1GB Module (1 rank of x8 based DDR2 SDRAMs)  
HYMP112F72CP8(N3,D3,D5)  
FRONT VIEW  
133.35 ±0.15  
30.35  
AMB  
67.00  
51.00  
5.00  
BACK VIEW  
Chekbit  
FRONT VIEW WITH HEAT SPREADER  
Side  
8.20 max  
5.20 max  
BACK VIEW WITH HEAT SPREADER  
3.0 max  
1.27±0.10  
Note 1: All dimensions are typical millimeter scale unless otherwise stated.  
Rev 1.01 / Sep. 2008  
27  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PACKAGE OUTLINE  
256Mx72, 2GB Module (2 ranks of x8 based DDR2 SDRAMs)  
HYMP125F72CP8(N3,D3,D5)  
FRONT VIEW  
133.35 ±0.15  
AMB  
67.00  
51.00  
5.00  
BACK VIEW  
Chekbit  
Chekbit  
FRONT VIEW WITH HEAT SPREADER  
Side  
8.20 max  
5.20 max  
BACK VIEW WITH HEAT SPREADER  
3.0 max  
1.27±0.10  
Note 1: All dimensions are typical millimeter scale unless otherwise stated.  
Rev 1.01 / Sep. 2008  
28  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PACKAGE OUTLINE  
512Mx72, 4GB Module (2 ranks of x4 based DDR2 SDRAMs)  
HYMP151F72CP4(N3,D3,D5)  
FRONT VIEW  
133.35 ±0.15  
67.00  
51.00  
5.00  
BACK VIEW  
FRONT VIEW WITH HEAT SPREADER  
Side  
8.20 max  
5.20 max  
BACK VIEW WITH HEAT SPREADER  
3.0 max  
1.27±0.10  
Note 1: All dimensions are typical millimeter scale unless otherwise stated.  
Rev 1.01 / Sep. 2008  
29  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PACKAGE OUTLINE  
512Mx72, 4GB Module (4 ranks of x8 based DDR2 SDRAMs)  
HYMP151F72CP8D5  
FRONT VIEW  
133.35 ±0.15  
67.00  
51.00  
5.00  
BACK VIEW  
FRONT VIEW WITH HEAT SPREADER  
Side  
8.20 max  
5.20 max  
BACK VIEW WITH HEAT SPREADER  
3.0 max  
1.27±0.10  
Note 1: All dimensions are typical millimeter scale unless otherwise stated.  
Rev 1.01 / Sep. 2008  
30  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
PACKAGE OUTLINE  
1Gx72, 8GB Module (4 ranks of x4 based DDR2 SDRAMs)  
HYMP31GF72CMP4D5  
FRONT VIEW  
133.35 ±0.15  
67.00  
51.00  
5.00  
BACK VIEW  
FRONT VIEW WITH HEAT SPREADER  
Side  
8.20 max  
5.20 max  
BACK VIEW WITH HEAT SPREADER  
3.0 max  
1.27±0.10  
Note 1: All dimensions are typical millimeter scale unless otherwise stated.  
Rev 1.01 / Sep. 2008  
31  
1240pin Fully Buffered DDR2 SDRAM DIMMs  
REVISION HISTORY  
Revision  
History  
Date  
Remark  
0.1  
1.0  
First Version Release  
July. 2007  
July. 2008  
Sep. 2008  
AMB Revision Added & Datasheet Version changed  
Typo corrected  
1.01  
Rev 1.01 / Sep. 2008  
32  

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