HYMP351P72CMP4L-Y5 [HYNIX]
240pin DDR2 VLP Registered DIMMs; 240PIN DDR2 VLP Registered DIMM内存模组
| 型号： | HYMP351P72CMP4L-Y5 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 240pin DDR2 VLP Registered DIMMs |
| 文件： | 总27页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C ver-
sion DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C ver-
sion based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of
industry standard. It is suitable for easy interchange and addition.
ORDERING INFORMATION
Parity
Support
Part Name
Density
Org.
Component Configuration
Ranks
HYMP112P72CP8L-C4/Y5/S6
HYMP125P72CP4L-C4/Y5/S6
HYMP351P72CMP4L-C4/Y5/S6
HYMP41GP72CNP4L-C4/Y5
1GB
2GB
4GB
8GB
128Mbx72
128Mbx8(HY5PS1G821CFP)*9
1
1
2
4
O
O
O
O
256Mbx72 256Mbx4(HY5PS1G421CFP)*18
512Mbx72 512Mbx4(HY5PS2G421CMP)*18
1Gbx72
1Gbx4(HY5PS4G421CNP)*18
Note:
1. “P” of part number[12th digit] stands for Lead free products.
SPEED GRADE & KEY PARAMETERS
C4 (DDR2-533)
Y5 (DDR2-667)
S6 (DDR2-800)
Unit
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
533
-
400
533
667
-
-
Mbps
Mbps
Mbps
Mbps
tCK
400
533
800
6-6-6
-
4-4-4
5-5-5
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / May. 2008
1
1240pin DDR2 VLP Registered DIMMs
FEATURES
•
•
JEDEC standard 1.8V +/- 0.1V Power Supply
VDDQ : 1.8V +/- 0.1V
•
•
•
•
•
•
•
•
•
All inputs and outputs are compatible with SSTL_1.8 interface
4 Bank architecture
Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequential and interleave mode
Average Auto Refresh Period 7.8us under TCASE 85℃, 3.9us at 85℃ < TCASE ≤ 95 ℃
•
•
•
•
•
•
•
High Temperature Self-Refresh Entry enablble features
PASR(Partial Array Self- Refresh)
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA
133.35 x 18.29 mm form factor
Lead-free Products are RoHS compliant
ADDRESS TABLE
# of
DRAMs
Refresh
Method
Density Organization Ranks
SDRAMs
# of row/bank/column Address
1GB
2GB
4GB
8GB
128Mb x 72
256Mb x 72
512Mb x 72
1Gb x 72
1
1
2
4
128Mb x 8
256Mb x 4
256Mb x 4
256Mb x 4
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
18
36
72
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
Input/Output Functional Description
Symbol
Type Polarity
Pin Description
Positive
Edge
CK0
IN
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative
Edge
CK0
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
CKE[1:0]
IN
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
Active
Low
S[1:0]
IN
Active
High
ODT[1:0]
IN
On-Die Termination signals.
Active
Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define
the command being entered.
RAS, CAS, WE
Vref
IN
Supply
Supply
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
VDDQ
BA[1:0]
IN
IN
-
-
Selects which DDR2 SDRAM internal bank of four is activated.
During a Bank Activate command cycle, Address input defines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sam-
pled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
A[9:0],
A10/AP
A[13:11]
DQ[63:0],
CB[7:0]
IN
IN
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coin-
cident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Active
High
DM[8:0]
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are
tied to VDD/VDDQ planes on these modules.
V
DD,VSS
Supply
Positive
Edge
DQS[17:0]
DQS[17:0]
SA[2:0]
I/O
I/O
IN
Positive line of the differential data strobe for input and output data
Negative line of the differential data strobe for input and output data
Negative
Edge
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
-
-
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SDA
I/O
IN
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to VDDSPD to act as a pull up on the system board.
SCL
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
VDDSPD
Supply
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
RESET
IN
Par_In
Err_Out
TEST
IN
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
OUT
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PIN DESCRIPTION
Pin
CK0
CK0
Pin Description
Pin
ODT[1:0] On Die Termination Inputs
VDDQ DQs Power Supply
Pin Description
Clock Input,positive line
Clock input,negative line
CKE0~CKE1 Clock Enable Input
DQ0~DQ63 Data Input/Output
CB0~CB7 Data check bits Input/Output
DQS(0~8) Data strobes
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
DQS(0~8) Data strobes,negative line
DM(0~8),
S0,S1
Chip Select Input
Address input
Data Maskes/Data strobes
DQS(9~17)
A0~A9,
A11~A13
DQS(9~17) Data strobes,negative line
A10/AP
Address input/Autoprecharge
SDRAM Bank Address
RFU
NC
Reserved for Future Use
No Connect
BA0,BA1
Memory bus test tool
(Not Connected and Not Usable on DIMMs)
SCL
Serial Presence Detect(SPD) Clock Input
TEST
SDA
SA0~SA2
Par_In
SPD Data Input/Output
VDD
VDDQ
VSS
Core Power
E2PROM Address Inputs
I/O Power
Parity bit for the Address and Control bus
Parity error found on the Address
Reset Enable
Ground
Err_Out
RESET
VREF
Input/Output Reference
SPD Power
VDDSPD
CB0~CB7 Data Check bit Inputs/Outputs
PIN LOCATION
Front Side
1 pin
120 pin
64 pin
65 pin
Banck Side
121 pin
185 pin
184 pin
240 pin
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PIN ASSIGNMENT
Pin
1
Name
VREF
VSS
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VSS
Pin
81
Name
DQ33
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
Name
VSS
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
CB4
Pin
201
202
203
Name
VSS
2
CB0
82
DQ4
CB5
DM4/DQS13
DQS13
VSS
3
DQ0
CB1
83
DQS4
DQS4
VSS
DQ5
VSS
4
DQ1
VSS
84
VSS
DM8,DQS17 204
5
VSS
DQS8
DQS8
VSS
85
DM0/DQS9
DQS9
VSS
DQS17
VSS
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DQ38
DQ39
VSS
6
DQS0
DQS0
VSS
86
DQ34
DQ35
VSS
7
87
CB6
8
CB2
88
DQ6
CB7
DQ44
DQ45
VSS
9
DQ2
CB3
89
DQ40
DQ41
VSS
DQ7
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ3
VSS
90
VSS
VDDQ
NC,CKE1
VDD
A15,NC
A14,NC
VDDQ
A12
VSS
VDDQ
CKE0
VDD
BA2,NC
NC,Err_Out
VDDQ
A11
91
DQ12
DQ13
VSS
DM5/DQS14
DQS14
VSS
DQ8
92
DQS5
DQS5
VSS
DQ9
93
VSS
94
134 DM1/DQS10
DQ46
DQ47
VSS
DQS1
DQS1
VSS
95
DQ42
DQ43
VSS
135
136
137
138
139
140
141
142
143
144
145
DQS10
VSS
96
97
RFU
A9
DQ52
DQ53
VSS
RESET
NC
A7
98
DQ48
DQ49
VSS
RFU
VDD
A8
VDD
A5
99
VSS
VSS
100
101
102
103
104
105
106
107
108
DQ14
DQ15
VSS
A6
RFU
DQ10
DQ11
VSS
A4
SA2
VDDQ
A3
RFU
VDDQ
A2
NC(TEST)
VSS
VSS
DQ20
DQ21
VSS
A1
DM6/DQS15
NC,DQS15
VSS
DQ16
DQ17
VSS
VDD
Key
DQS6
DQS6
VSS
VDD
Key
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
146 DM2/DQS11
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
CK0
CK0
DQ54
DQ55
VSS
DQS2
DQS2
VSS
VSS
DQ50
DQ51
VSS
147
148
149
150
151
152
153
154
DQS11
VSS
VDD
VDD
A0
NC,Err_Out 109
DQ22
DQ23
VSS
DQ60
DQ61
VSS
DQ18
DQ19
VSS
VDD
A10/AP
BA0
110
111
112
113
114
115
116
117
118
119
120
DQ56
DQ57
VSS
VDD
BA1
DQ28
DQ29
VSS
VDDQ
RAS
DM7/DQS16
NC,DQS16
VSS
DQ24
DQ25
VSS
VDDQ
WE
DQS7
DQS7
VSS
S0
CAS
155 DM3/DQS12
VDDQ
ODT0
A13,NC
VDD
VSS
DQ62
DQ63
VSS
DQS3
DQS3
VSS
VDDQ
NC, S1
NC, ODT1
VDDQ
VSS
DQ58
DQ59
VSS
156
157
158
159
160
DQS12
VSS
DQ30
DQ31
VSS
VDDSPD
SA0
DQ26
DQ27
SDA
SCL
DQ36
DQ37
SA1
DQ32
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) : HYMP112P72CP8L
RS0
DQS0
DQS4
DQS0
DQS4
DM0,DQS9
DQS9
DM4,DQS13
DQS13
NU/ /CS
RDQS RDQS
I/O 0
NU/ /CS
DM/
DQS /DQS
DM/
DQS /DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
I/O 0
I/O 1
I/O 1
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
D2
D3
D4
DQS1
DQS5
DQS5
DM5,DQS14
DQS14
DQS1
DM1,DQS10
DQS10
NU/ /CS
RDQS RDQS
I/O 0
NU/ /CS
DM/
DQS /DQS
DM/
RDQS RDQS
I/O 0
DQS /DQS
DQ8
DQ9
DQ40
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D5
VDD SPD
DD/VDDQ
Serial PD
D0-D8
DQS2
DQS6
DQS6
DM6,DQS15
DQS15
V
DQS2
DM2,DQS11
DQS11
D0–D8
D0–D8
V
REF
NU/ /CS
RDQS RDQS
I/O 0
NU/ /CS
RDQS RDQS
I/O 0
DM/
DQS /DQS
DM/
DQS /DQS
DQ16
DQ48
VSS
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
Serial PD
DQS3
DQS7
/DQS7
DM7,DQS16
DQS16
SCL
SDA
DQS3
DM3,DQS12
DQS12
WP A0 A1 A2
SA0SA1SA2
NU/ /CS
RDQS RDQS
I/O 0
NU/ /CS
RDQS RDQS
I/O 0
DM/
DQS /DQS
DM/
DQS /DQS
DQ24
DQ56
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 6
I/O 7
DQS8
Note:
DQS8
1.DQ-to-I/O wiring may be changed within a byte.
DM8,DQS17
DQS17
2.Unless otherwise noted, resistor values are 22 Ohms +/-5%.
NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
DM/
DQS /DQS
CB0
Signals for Address and Command Parity Function (Raw Card F, F and AC)
Register
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Vss
C0
D8
I/O 3
I/O 4
I/O 5
Vss
PAR_IN
100K ohms
C1
I/O 6
I/O 7
PAR_IN
PRO
QERR
Err_Out
S0*
/RS0 to /CS-> /CS: SRAMSs D0-D8
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section:
1:1
R
E
G
I
S
T
E
R
BA0- BA2**
RBA0 to RBA2->BA0-BA2: SDRAMs D0-D8***
/RA0-RA15->A0-A15: SDRAMs D0- D8***
“Register Options for unused Address inputs”
A0- A15**
RAS
PCK0-PCK6, PCK8, PKC9
PCK0-PCK6, PCK8, PCK9
→
→
CK: SDRAMs D0-D8
CK: SDRAMs D0-D8
CK0
/RRAS-> /RAS: SDRAMs D0-D8
/RCAS ->/CAS: SDRAMs D0-D8
/RWE ->/WE : SDRAMs D0-D8
RCKE0-> CKE0: SDRAMs D0-D8
RODT0-> ODT0: SDRAMs D0-D8
P
L
L
CK0
CAS
WE
PCK7
PCK7
→
→
CK: Register
CK: Resgister
RESET
CKE0
OE
ODT0
/RESET
* S0 connects to DCS and VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC
** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
*** For Rqw Card R and A Co, post register A14, A15 and BA2 are not connected to the SDRAMs.
And for Raw Card AC1, post register A14 and A15 are not connected to the SDRAMs.
RST
PCK7
/PCK7
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) : HYMP125P72CP4L
VSS
RS0
DQS0
DQS0
Serial PD
DQS9
DQS9
SCL
SCL
SDA
SDA
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
WP A0 A1 A2
SA0SA1SA2
D0
D9
DQS10
DQS10
DQS1
DQS1
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
VDD SPD
Serial PD
D0–D17
D0–D17
D0–D17
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
V
DD/VDDQ
REF
SS
D1
D10
DQS2
DQS2
DQS11
DQS11
V
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
V
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D2
D11
PCK0 - PCK6, PCK8, PKC9
PCK0 - PCK6, PCK8, PCK9
→
→
CK: SDRAMs D0-D17
CK: SDRAMs D0-D17
CK0
CK0
P
L
L
DQS3
DQS3
DQS12
DQS12
PCK7
PCK7
→
→
CK: Register
CK: Resgister
DM /CS DQS /DQS
I/O 0
DM /CS DQS /DQS
I/O 0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RESET
Note:
OE
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D3
D12
DQS4
DQS4
DQS13
DQS13
1.DQ-to-I/O wiring may be changed within a byte.
2.Unless otherwise noted, resistor values are 22 Ohms +/-5%.
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
* S0 connects to DCS or Register A and CSR of Register B.
CSR of Register A and DCS of Register B connects to VDD.
D4
D13
DQS5
DQS5
DQS14
DQS14
** RESET, PCK7 and PCK7 connects to both Registers.
Other signals connects to one of two Registers.
Raw Card V has only one register.
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D5
D14
*** A13-A15, BA2 have the optional pull down resistors
(100K ohms), which is not indicated here.
DQS15
DQS15
DQS6
DQS6
**** For /raw /card U0 and V, post register A14, A15 and BA2
are not connected to the SDRAMs.
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
And for Raw Care U1, post register A14 and A15 are not
connected to the SDRAMs.
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D6
D15
DQS7
DQS7
DQS16
DQS16
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out
refer to the section:
“Register Options for unused Address inputs”
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D7
D16
DQS8
DQS8
DQS17
DQS17
DM CS DQS DQS
I/O 0
DM CS DQS DQS
I/O 0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D8
D17
S0*
RS0 -> CS: SRAMSs D0-D17
1:2
BA0-BA2***
Signals for Address and Command Parity Function (Raw Card H, U)
RBA0-RBA2->BA0-BA2: SDRAMs D0-D17****
RA0- RA15->A0-A15: SDRAMs D0-D17****
RRAS-> RAS: SDRAMs D0-D177
R
E
G
I
S
T
E
R
A0-A15***
RAS
Register A
Register B
Vss
V
DD
C0
C1
C0
C1
VDD
VDD
CAS
WE
RCAS ->CAS: SDRAMs D0-D17
PRO
QERR
PAR_IN
100K ohms
PAR_IN
PRO
QERR
PAR_IN
RWE-> WE: SDRAMs D0-D17
ROKE0-> CKE: SDRAMs D0-D17
RODT0-> ODT0: SDRAMs D0-D17
Err_Out
CKE0
ODT0
For R/C U, 0 ohm resistor is placed at the end of Err_Out just before the edge connector and is
not populated for the non-parity card.
RESET**
PCK7**
PCK7**
RST
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(256Mbx72) : HYMP351P72CMP4L
VSS
RS0
RS1
DQS0
DQS0
DQS9
DQS9
CS
DQS
CS
DQS
CS
CS
DQS
CS
CS
DQS
DQS
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
Serial PD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 0
I/O 1
D18
D27
D0
D9
SCL
SCL
SDA
SDA
I/O 2
I/O 3
I/O 2
I/O 3
DQS1
DQS1
DQS10
DQS10
WP A0 A1 A2
SA0 SA1 SA2
CS
DQS
CS
DQS
DQS DQS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D19
D28
D1
D10
VDD SPD
DD/VDDQ
Serial PD
D0–D35
D0–D35
D0–D35
DQS2
DQS2
DQS11
DQS11
V
CS
CS
CS
DQS
CS
CS
CS
DQS
CS
CS
CS
DQS
CS
CS
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
V
REF
SS
D20
D29
D2
D11
V
DQS3
DQS3
DQS12
DQS12
DQS
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D21
D30
D3
D12
PCK0 to PCK6, PCK8, PKC9
CK: SDRAMs D0-D35
PCK0 to PCK6, PCK8, PCK9
CK: SDRAMs D0-D35
CK0
CK0
P
L
L
→
→
DQS8
DQS8
DQS17
DQS17
PCK7
→
CK: Register
DQS
DQS
DQS DQS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
PCK7
→
CK: Resgister
OE
RESET
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D26
D35
D8
D17
RS0
RS1
DQS4
DQS4
DQS13
DQS13
CS
CS
CS
CS
DQS
CS
CS
CS
CS
DQS
CS
CS
CS
CS
CS
CS
CS
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
DQ33
DQ34
DQ35
D22
D31
D4
D13
DQS5
DQS5
DQS14
DQS14
DQS
DQS
DQS DQS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ44
DQ45
DQ46
DQ47
DQ41
DQ42
DQ43
D23
D32
D5
D14
DQS6
DQS6
DQS15
DQS15
DQS
DQS
DQS DQS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ52
DQ53
DQ54
DQ55
DQ49
DQ50
DQ51
D24
D33
D6
D15
DQS7
DQS7
DQS16
DQS16
DQS
DQS
DQS DQS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
The resistors on Par_In, A13, A14, A15, BA2
and signal line of Err_Out refer to the section:
“Register Options for Unused Address inputs”
DQ56
DQ60
DQ61
DQ62
DQ63
DQ57
DQ58
DQ59
D25
D34
D7
D16
Signals for Address and Command Parity Function
S0*
S1*
BA0-BA2***
RS0 -> CS: SRAMSs D0-D17
RS1 -> CS: SRAMSs D18-D35
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35
RA0-RA15 -> A0-A15: SDRAMs D0-D35****
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
1:2
Register 1
Register 2
R
E
G
I
S
T
E
R
Vss
V
DD
C1
C2
C1
C2
VSS
VDD
0 ohm
A0-A15***
RAS
CAS
WE
CKE0
CKE
ODT0
PARIN1
PARIN2
PRO1
PRO2
PARIN1
PARIN2
PTYERR1
PTYERR2
Err_Out
PAR_IN
100K ohms
Register 1 share a part of Addr/Cmd input signal set.
Register 2 share the other part of Addr/Cmd input signal set.
0 Ohm resistor on Err_Out is not populated for non-parity card.
Notes:
RODT0 -> ODT0: SDRAMs D0-D17
RODT1 -> ODT1: SDRAMs D18-D35
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 22 ohms +/-5%.
3. RS0 and RS1 altemate between the bottom and surface sides of the DIMM.
ODT1
RESET**
RST
PCK7**
PCK7**
* S0 connects to DCS and S1 connects to CSR on Register1. S1 connects to DCS and S0 connects to CSR on Register 2.
** RESET, PCK7 and PCK7 connect to both Registers. Other signals connect to one of two Registers.
*** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
**** For Raw Card AJ, post register A14, A15 are not connected to the SDRAMs.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
8GB(256Mbx72) : HYMP41GP72CNP4L
VSS
RS0
RS1
RS2
RS3
Serial PD
DQS0
DQS0
DQS9
DQS9
SCL
SCL
SDA
SDA
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WP A0 A1 A2
SA0 SA1 SA2
I/O 2
I/O 3
I/O 2
I/O 3
D0
D9
DQS10
DQS10
DQS1
DQS1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDD SPD
DD/VDDQ
Serial PD
D0–D35
D0–D35
D0–D35
I/O 2
I/O 3
I/O 2
I/O 3
D1
D10
V
DQS2
DQS2
DQS11
DQS11
VREF
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
I/O 2
I/O 3
I/O 2
I/O 3
D2
D11
DQS3
DQS3
DQS12
DQS12
PCK to PCK6, PCK8, PKC9-> CK: SDRAMs D0-D35
PCK0 - PCK6, PCK8, PCK9-> CK: SDRAMs D0-D35
CK0
CK0
P
L
L
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
PCK7 ->CK: Register
PCK7->CK: Resgister
I/O 2
I/O 3
I/O 2
I/O 3
D3
D12
OE
RESET
DQS8
DQS8
DQS17
DQS17
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Signals for Address and Command Parity Function
Register
I/O 2
I/O 3
I/O 2
I/O 3
D4
D13
PARIN
PTYERR
0 ohm
DQS4
DQS4
DQS13
DQS13
PAR_IN
100K ohms
ERR_OUT
Register
PARIN
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
PTYERR
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 2
I/O 3
I/O 2
I/O 3
D5
D14
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of
Err_Out refer to the section:
DQS14
DQS14
DQS5
DQS5
“Register Options for Unused Address inputs”
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 2
I/O 3
I/O 2
I/O 3
D6
D15
DQS6
DQS6
DQS15
DQS15
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 2
I/O 3
I/O 2
I/O 3
D7
D16
DQS7
DQS7
DQS16
DQS16
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DM DQS DQS CS0 CS1 CS2 CS3
I/O 0
I/O 1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 2
I/O 3
I/O 2
I/O 3
D8
D17
S0,1*
RS0,1->CS0,1: SRAMSs D0-D17
RS2,3-> CS2,3: SRAMSs D0-D17
RBA0-RBA2->BA0-BA2: SDRAMs D0-D17
RA0- RA15->A0-A15: SDRAMs D0-D17****
RRAS-> RAS: SDRAMs D0-D177
RCAS ->CAS: SDRAMs D0-D17
RWE->WE: SDRAMs D0-D17
ROKE0-> CKE: SDRAMs D0-D17
ROKE1->CKE: SDRAMs D0-D17
RODT0-> ODT0: SDRAMs D0-D17
RODT1->ODT1: SDRAMs D0-D17
Note:
S2,3*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
1.DQ-to-I/O wiring may be changed within a nibble.
2.Unless otherwise noted, resistor values are 22 Ohms +/-5%.
3.RS0,1,2,3 alternate between the bottom and surface sides of the DIMM.
R
E
G
I
S
T
E
R
* S0 connects to DCS0, S1 to DCS1 on first Register and S2 connects to DCS0, S3 connects to DCS1
on second Registers
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connects to two Registers.
*** A13-A15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
**** For Raw Card AG, post register A14, A15 are not connected to the SDRAMs.
RESET**
PCK7**
RST
/PCK7**
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
VDD
VDDL
- 1.0 V ~ 2.3 V
-0.5V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-50 ~ +100
V
V
V
V
1
1
1
1
1
1
Voltage on VDD pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on VDDQ pin relative to Vss
VDDQ
VIN, VOUT
TSTG
Voltage on any pin relative to Vss
Storage Temperature
oC
%
HSTG
Storage Humidity(without condensation)
5 to 95
Note :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
Notes
oC
TOPR
0 ~ +55
DIMM Operating temperature(ambient)
PBAR
DIMM Barometric Pressure(operating & storage)
105 to 69
0 ~+95
K Pascal
1
2
DRAM Component Case Temperature Range
oC
TCASE
Note :
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
VDD
Min
1.7
Max
1.9
Unit
V
Note
VDDL
1.7
1.9
V
Power Supply Voltage
VDDQ
VREF
1.7
1.9
V
1
2
Input Reference Voltage
EEPROM Supply Voltage
0.49 x VDDQ
1.7
0.51 x VDDQ
3.6
V
VDDSPD
VTT
V
V
REF+0.04
V
3
VREF-0.04
Termination Voltage
Note :
1. VDDQ must be less than or equal to VDD
.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
INPUT DC LOGIC LEVEL
Parameter
Input High Voltage
Input Low Voltage
Symbol
Min
VREF + 0.125
-0.30
Max
Unit
V
Notes
VIH(DC)
VIL(DC)
VDDQ + 0.3
VREF - 0.125
V
INPUT AC LOGIC LEVEL
DDR2 400/533
DDR2 667/800
Notes
Parameter
Symbol
Unit
Min
Max
Min
Max
AC Input logic High
AC Input logic Low
VIH(AC)
VIL(AC)
V
V
VREF + 0.250
-
-
VREF + 0.200
-
-
VREF - 0.250
VREF - 0.200
AC INPUT TEST CONDITIONS
Symbol
VREF
Condition
Input reference voltage
Value
Units
Notes
0.5 * VDDQ
V
1
VSWING(MAX)
SLEW
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
delta TR
Rising Slew =
V
min - V
REF
V
-
V
max
IL(ac)
IH(ac)
REF
Falling Slew =
delta TF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID (ac)
0.5
VDDQ + 0.6
V
1
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The mini-
mum value is equal to VIH(DC) - VIL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
ac differential cross point voltage
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc)
IOL(dc)
Parameter
SSTl_18
Units
Notes
Output Minimum Source DC Current
Output Minimum Sink DC Current
- 13.4
13.4
mA
mA
1, 3, 4
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
1GB : HYMP112P72CP8L
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
CI3
CIO
7
8
8
8
6
11
12
12
12
9
CKE, ODT
CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB : HYMP125P72CP4L
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
7
8
11
12
15
12
9
CKE, ODT
CS
10
8
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CI3
CIO
6
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
4GB : HYMP351P72CMP4L
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
CI3
CIO
9.5
10.5
10.5
10.5
17
10.4
16
CKE, ODT
CS
16
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
16
21
8GB : HYMP41GP72CNP4L
Pin
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
CK0, CK0
CCK
CI1
CI2
7
8
11
12
12
15
22
CKE, ODT
CS
8
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
CI3
10
18
CIO
Note :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
o
IDD SPECIFICATIONS (T
: 0 to 95 C)
CASE
1GB, 128M x 72 VLP Registered DIMM : HYMP112P72CP8L
Symbol
IDD0
C4 (533@CL4)
Y5 (667@CL5)
S6 (800@CL6)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1235
1325
740
1280
1370
740
1325
1415
740
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
893
920
938
965
1010
875
1055
875
830
758
758
758
1055
1775
1775
2135
540
1100
2000
2000
2225
540
1145
2180
2180
2225
540
1
IDD6
IDD7
2225
2270
2315
2GB, 256M x 72 VLP Registered DIMM : HYMP125P72CP4L
Symbol
IDD0
C4 (533@CL4)
1820
Y5 (667@CL5)
1910
S6 (800@CL6)
2000
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD1
2000
2090
2180
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
830
830
830
1136
1190
1226
1280
1370
1460
1010
1100
1100
866
866
866
1460
1550
1640
2900
3350
3710
2900
3350
3710
3620
3800
3600
1
IDD6
630
630
630
IDD7
3800
3890
3980
Notes :
1. IDD6 current values are guaranteed up to Tcase of 85oC max.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
4GB, 256M x 72 VLP Registered DIMM : HYMP351P72CMP4L
Symbol
IDD0
C4 (533@CL4)
2630
Y5 (667@CL5)
2810
S6 (800@CL6)
2990
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD1
2810
2990
3170
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
1010
1010
1010
1622
1730
1802
1910
2090
2270
1370
1550
1550
1082
1082
1082
2270
2450
2630
3710
4250
4700
3710
4250
4700
4430
4700
4790
1
IDD6
810
810
810
IDD7
4610
4790
4970
8GB, 256M x 72 VLP Registered DIMM : HYMP41GP72CNP4L
Symbol
IDD0
C4 (533@CL4)
Y5 (667@CL5)
Unit
Notes
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
1
IDD6
IDD7
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
IDD Measurement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
IDD0
IDD1
mA
t
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; CK =
t
t
t
t
t
t
t
CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is HIGH between valid
commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and address
IDD2P
IDD2Q
IDD2N
mA
mA
mA
bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD); CKE is LOW;
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
IDD3P
IDD3N
IDD4W
IDD4R
Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-
ING
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
mA
mA
t
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK
t
t
t
t
t
= CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5B
IDD6
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃max.
mA
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
t
t
t
t
t
t
t
t
t
t
AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
DDR2-533 (C4)
DDR2-400 (E3)
Unit
DDR2-800(S6)
DDR2-667(Y5)
4-4-4
min
4
3-3-3
min
3
6-6-6
min
6
5-5-5
min
5
ns
ns
ns
ns
ns
15
15
15
15
tRP
15
15
15
15
tRC
60
55
60
60
tRAS
45
40
45
45
AC Timing Parameters by Speed Grade
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
600
Min
-500
-500
0.45
0.45
Max
500
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
tAC
tDQSCK
tCH
-600
-500
0.45
0.45
ps
ns
500
450
0.55
0.55
0.55
0.55
CK
CK
Clock Low Level Width
tCL
min
(tCL,tCH)
min
(tCL,tCH)
Clock Half Period
tHP
-
-
ns
ps
System Clock Cycle Time
tCK
tDS
5000
150
275
0.6
8000
3750
100
225
0.6
8000
DQ and DM input setup time
-
-
-
-
-
-
ps
ps
1
1
DQ and DM input hold time
tDH
tIPW
Control & Address input Pulse Width for each input
tCK
DQ and DM input pulse witdth for each input pulse width
for each input
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
Data-out high-impedance window from CK, /CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC max
tAC min
tAC max
ps
ps
2*tAC min
tAC max
2*tAC min
tAC max
-
350
-
300
ps
-
tHP - tQHS
WL - 0.25
0.35
450
-
tHP - tQHS
WL - 0.25
0.35
400
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tQH
-
-
ps
tDQSS
tDQSH
tDQSL
tDSS
WL + 0.25
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
-
-
DQS input low pulse width
0.35
-
0.35
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
0.2
-
0.2
-
tDSH
0.2
-
-
0.2
-
-
tMRD
2
2
tWPRE
tWPST
0.35
-
0.35
-
Write postamble
0.4
0.6
0.4
0.6
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
- continued -
DDR2-400
DDR2-533
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Address and control input setup time
Address and control input hold time
Read preamble
tIS
tIH
350
475
0.9
-
-
250
375
0.9
-
-
ps
ps
tRPRE
tRPST
tRFC
1.1
0.6
-
1.1
0.6
-
tCK
tCK
ns
Read postamble
0.4
0.4
Auto-Refresh to Active/Auto-Refresh command period
127.5
7.5
127.5
7.5
tRRD
tRRD
tFAW
tFAW
-
-
ns
Row Active to Row Active Delay for 1KB page size
Row Active to Row Active Delay for 2KB page size
Four Activate Window for 1KB page size
10
37.5
50
-
-
-
10
37.5
50
-
-
-
ns
ns
ns
Four Activate Window for 2KB page size
CAS to CAS command delay
tCCD
tWR
2
2
15
tCK
ns
Write recovery time
15
-
-
-
-
Auto Precharge Write Recovery + Precharge Time
tDAL
tWR+tRP
tCK
tWR+tRP
10
Write to Read Command Delay
tWTR
-
ns
7.5
-
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
ns
ns
tRFC + 10
tRFC + 10
200
2
-
-
200
2
-
-
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
2
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
tCKE
6 - AL
3
6 - AL
3
tCK
tCK
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
2
2
tCK
ns
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
2tCK+tAC(m
ax)+1
2tCK+tAC(m
ax)+1
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
2.5
2.5
tAC(max)+
0.6
tAC(max)+
0.6
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+tA
C(max)+1
2.5tCK+tA
C(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
tCK
tCK
ns
3
8
0
3
8
0
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[4,8]31CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
DDR2-667
DDR2-800
Symbol
Unit Note
Parameter
min
max
+450
+400
0.55
min
max
+400
+350
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
-400
-350
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
0.55
0.55
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
tCK
tDS
-
8000
-
-
ps
ps
Clock cycle time, CL=x
3000
2500
DQ and DM input setup time
(differential strobe)
100
50
-
-
-
ps
ps
1
1
DQ and DM input hold time
(differential strobe)
tDH
175
0.6
-
-
125
0.6
Control & Address input pulse width for each
input
tIPW
tCK
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tLZ(DQS)
tLZ(DQ)
tAC min
2*tAC min
tAC min
2*tAC min
ps
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
240
-
200
ps
DQ hold skew factor
tQHS
tQH
-
340
-
-
300
-
ps
ps
DQ/DQS output hold time from DQS
tHP - tQHS
tHP - tQHS
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
-
0.35
0.35
0.2
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
-
-
-
-
tDSH
tMRD
tWPRE
tWPST
tIS
0.2
0.2
2
-
2
-
0.35
0.4
-
0.35
0.4
-
Write postamble
0.6
-
0.6
-
Address and control input setup time
Address and control input hold time
Read preamble
200
275
0.9
175
250
0.9
tIH
-
-
ps
tRPRE
tRPST
tRFC
1.1
0.6
-
1.1
0.6
-
tCK
tCK
ns
Read postamble
0.4
0.4
Auto-Refresh to Active/Auto-Refresh command period
127.5
127.5
Active to active command period for 1KB page
size products
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
Active to active command period for 2KB page
size products
Four Active Window for 1KB page size products tFAW
Four Active Window for 2KB page size products tFAW
37.5
50
-
-
35
45
-
-
ns
ns
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
- continued -
DDR2-667
DDR2-800
Symbol
Unit Note
Parameter
min
max
min
max
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
15
2
15
tCK
ns
-
-
-
-
-
-
Auto precharge write recovery + precharge time tDAL
WR+tRP
7.5
WR+tRP
7.5
tCK
ns
Internal write to read command delay
tWTR
tRTP
Internal read to precharge command delay
7.5
7.5
ns
tRFC +
10
Exit self refresh to a non-read command
tXSNR
tXSRD
tXP
tRFC + 10
ns
Exit self refresh to a read command
200
2
-
-
200
-
-
tCK
tCK
tCK
tCK
Exit precharge power down to any non-read
command
2
Exit active power down to read command
Exit active power down to read command
tXARD
tXARDS
2
2
7 - AL
8 - AL
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tCKE
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
tAOND
tAON
2
2
tAC(max)
+0.7
tAC(max)
+0.7
ODT turn-on
tAC(min)
tAC(min)
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min)+2
2.5
ns
tCK
ns
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)
+0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tDelay
tIS+tCK+tIH
ns
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
Average periodic Refresh Interval
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[4,8]31CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HYMP112P72CP8L
Front
133.35
4.0
± 0.1
Detail A
Detail B
55.0
63.0
5.175
5.175
5.0
Back
Detail of Contacts A
Side
4.00 max
Detail of Contacts B
0.8
± 0.05
2.50
1.00
1.50
± 0.10
1.27 ± 0.10
max
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
256Mx72 (1 rank) - HYMP125P72CP4L
Front
133.35
4.0
± 0.1
Detail A
Detail B
55.0
63.0
5.175
5.175
5.0
Back
Detail of Contacts A
Detail of Contacts B
Side
4.00 max
0.8
± 0.05
2.50
1.00
1.50
± 0.10
1.27 ± 0.10
max
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
256Mx72 (2 rank) - HYMP351P72CMP4L
Front
133.35
4.0
± 0.1
Detail A
Detail B
55.0
63.0
5.175
5.175
5.0
Back
Side
7.55 max
Detail of Contacts A
Detail of Contacts B
0.8
± 0.05
2.50
1.00
1.50
± 0.10
1.27 ± 0.10
max
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
256Mx72 (4 rank) - HYMP41GP72CNP4L
Front
133.35
Side
4.0
± 0.1
7.55 max
Detail A
Detail B
55.0
63.0
5.175
5.175
5.0
Back
1.27 ±
max
0.10
Front
133.35
Side
10.55 max
126.80
Back
2.4 max
1.27 ± 0.10
max
Detail of Contacts A
Detail of Contacts B
0.8
± 0.05
2.50
1.00
1.50
± 0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.2 / May. 2008
1240pin DDR2 VLP Registered DIMMs
REVISION HISTORY
Revision
History
Date
Remark
0.1
0.2
Initial Release
Aug. 2007
May. 2008
8GB added, IDD updated
Rev. 0.2 / May. 2008
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