IBM0118165PT3-6R [IBM]
EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44;
| 型号： | IBM0118165PT3-6R |
| 厂家： | 
IBM |
| 描述： | EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总31页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
.
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Features
• Low Power Dissipation
• 1,048,576 word by 16 bit organization
- Active (max) - 185 mA / 165 mA / 140 mA
- Standby: TTL Inputs (max) - 1.0 mA
- Standby: CMOS Inputs (max)
- 1.0 mA (SP version)
• Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply
• Standard Power (SP) and Low Power (LP)
- 0.2 mA (LP version)
- Self Refresh (LP version only)
- 200µA (3.3 Volt)
• 1024 Refresh Cycles
- 16 ms Refresh Rate (SP version)
- 128 ms Refresh Rate (LP version)
- 300µA (5.0 Volt)
• High Performance:
• Extended Data Out (Hyper Page) Mode
• Dual CAS Byte Read/Write
• Read-Modify-Write
-50 -60 -6R -70 Units
tRAC
tCAC
tAA
RAS Access Time
CAS Access Time
50 60 60 70
13 15 17 20
ns
ns
ns
• RAS Only and CAS before RAS Refresh
• Hidden Refresh
Column Address Access Time 25 30 30 35
tRC
Cycle Time
84 104 104 124 ns
20 25 25 30 ns
EDO (Hyper Page) Mode
Cycle Time
• Package: TSOP-II 50/44 (400milx825mil)
SOJ 42/42 (400mil)
tHPC
Description
vide high performance, low power dissipation, and
high reliability. The devices operate with a single
3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 20
addresses required to access any bit of data are
multiplexed (10 are strobed with RAS, 10 are
strobed with CAS).
The IBM0118165 is a dynamic RAM organized
1,048,576 words by 16 bits, which has a very low
“sleep mode” power consumption option. These
devices are fabricated in IBM’s advanced 0.5µm
CMOS silicon gate process technology. The circuit
and process have been carefully designed to pro-
Pin Assignments (Top View)
Pin Description
RAS
LCAS / UCAS
WE
Row Address Strobe
L/U Column Address Strobe
Read/Write Input
Address Inputs
50/44 TSOP
42/42 SOJ
VCC
IO0
IO1
IO2
IO3
VCC
IO4
IO5
IO6
IO7
NC
1
50
VSS
VCC
IO0
IO1
IO2
IO3
VCC
IO4
IO5
IO6
IO7
1
2
3
4
5
6
7
8
42
VSS
2
3
4
5
49 IO15
48 IO14
47 IO13
46 IO12
41 IO15
40 IO14
39 IO13
38 IO12
A0 - A9
OE
Output Enable
6
7
8
9
10
11
45
VSS
37
VSS
44 IO11
43 IO10
42 IO9
41 IO8
40 NC
36 IO11
35 IO10
34 IO9
I/O0 - I/O15
VCC
Data Input/Output
Power (+3.3V or +5.0V)
Ground
9
33
32 NC
IO8
10
11
VSS
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
A1
A2
25 A6
24 A5
A3
VCC
20
21
23 A4
24
25
22
VSS
26
VSS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-04
Revised 11/96
Page 1 of 30
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Ordering Information
Power
Supply
Part Number
SP / LP
Self Refresh
Speed
Package
Notes
IBM0118165T3 -50
IBM0118165T3 -60
IBM0118165T3 -6R
IBM0118165T3 -70
IBM0118165BT3 -50
IBM0118165BT3 -60
IBM0118165BT3 -6R
IBM0118165BT3 -70
IBM0118165J3 -50
IBM0118165J3 -60
IBM0118165J3 -6R
IBM0118165J3 -70
IBM0118165BJ3 -50
IBM0118165BJ3 -60
IBM0118165BJ3 -70
IBM0118165MT3 -50
IBM0118165MT3 -60
IBM0118165MT3 -70
IBM0118165PT3 -50
IBM0118165PT3 -60
IBM0118165PT3 -6R
IBM0118165PT3 -70
IBM0118165MJ3 -50
IBM0118165MJ3 -60
IBM0118165MJ3 -70
IBM0118165PJ3 -50
IBM0118165PJ3 -60
IBM0118165PJ3 -70
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
No
No
5.0V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
3.3V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
50ns
60ns
60ns
70ns
50ns
60ns
60ns
70ns
50ns
60ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil SOJ 42/42
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
400mil SOJ 42/42
No
400mil SOJ 42/42
No
400mil SOJ 42/42
No
400mil SOJ 42/42
No
400mil SOJ 42/42
No
400mil SOJ 42/42
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil TSOP-II 50/44
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
400mil SOJ 42/42
1. SP = Standard Power version (IBM0118165 and IBM0118165B); LP = Low Power version (IBM0118165M and IBM00118165P)
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 2 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Block Diagram
I/O0
I/O15
Vss
Vcc
(5.0 Volt version)
(to OCDs)
16
16
Regulator
OE
V
(internal)
Data In Buffer
Data Out Buffer
DD
WE
&
16
16
UCAS
LCAS
CAS Clock
Generator
OR
Column Address
Buffer (10)
16
Column Decoder and I/O Gate
Sense Amplifiers
10
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
1024 x 16
Controller
Refresh Counter
(10)
Memory Array
1024 x 1024 x 16
10
10
1024
Row Address
Buffer (10)
10
RAS Clock
Generator
RAS
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 3 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Truth Table
Row
Address Address
Column
Function
RAS
LCAS UCAS
WE
OE
I/O0 - I/O15
H→X H→X
Standby
H
L
X
H
X
L
X
X
High Impedance
Data Out
Read: Word
L
L
L
Row
Col
Lower Byte: Data Out
Upper Byte: High-Z
Read: Lower Byte
Read: Upper Byte
L
L
L
L
L
H
H
H
L
L
L
Row
Row
Row
Row
Row
Col
Col
Col
Col
Col
Lower Byte: High-Z
Upper Byte: Data Out
H
L
L
L
Write: Word
Early-Write
X
X
X
Data In
Write: Lower Byte
Early-Write
Lower Byte: Data In
Upper Byte: High-Z
L
H
L
L
Write: Upper Byte
Early-Write
Lower Byte: High-Z
Upper Byte: Data In
H
L
H→L
H
L→H
Read-Modify-Write
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
H
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Col
Col
Col
Col
Col
Col
Col
N/A
N/A
Col
Data Out, Data In
Data Out
1st Cycle
L
L
L
EDO (Hyper Page) Mode
Read
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L
H
Data Out
L
L
X
Data In
EDO (Hyper Page) Mode
Write
L
L
X
Data In
H→L
H→L
X
L→H
L→H
X
L
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
Data Out
EDO (Hyper Page) Mode
Read-Modify-Write
L
L
RAS-Only Refresh
H→L
L→H→L
CAS-Before-RAS Refresh
L
L
H
X
Read
Write
L
L
H
L
Row
Hidden Refresh
L
L
H
X
Row
X
Col
X
Data In
L→H→L
H→L
Self Refresh (LP version only)
L
L
H
X
High Impedance
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 4 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Absolute Maximum Ratings
Rating
Symbol
Parameter
Units Notes
3.3 Volt Device
-0.5 to +4.6
5.0 Volt Device
VCC
VIN
Power Supply Voltage
Input Voltage
-1.0 to +7.0
V
V
1
1
1
1
1
1
1
-0.5 to min (VCC+0.5, 4.6)
-0.5 to min (VCC+0.5, 4.6)
0 to +70
-0.5 to min (VCC+0.5, 7.0)
VOUT
TOPR
TSTG
PD
-0.5 to min (VCC+0.5, 7.0)
Output Voltage
V
°C
°C
W
mA
Operating Temperature
Storage Temperature
Power Dissipation
0 to +70
-55 to +150
1.0
-55 to +150
1.0
IOUT
Short Circuit Output Current
50
50
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Recommended DC Operating Conditions (T = 0 to 70˚C)
A
3.3 Volt Device
5.0 Volt Device
Symbol
Parameter
Units
Notes
Min.
3.0
Typ.
3.3
—
Max.
3.6
Min.
4.5
Typ.
5.0
—
Max.
5.5
VCC
VIH
VIL
Supply Voltage
V
V
V
1
V
CC + 0.5
0.8
VCC + 0.5
0.8
Input High Voltage
Input Low Voltage
2.0
2.4
1, 2
1, 2
-0.5
—
-0.5
—
1. All voltages referenced to VSS
.
2. VIH may overshoot to VCC + 1.2V for pulse widths of ≤ 4.0ns with 3.3 Volt, or VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V
for ≤ 8.0ns) with 5.0 Volt. Additionally, VIL may undershoot to -2.0V for pulse widths ≤ 4.0ns with 3.3 Volt, or to -2.0V for pulse
widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns) with 5.0 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC ref-
erence.
Capacitance (T = 25°C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
Symbol
CI1
Parameter
Input Capacitance (A0 - A9)
Min.
—
Max.
Units
pF
Notes
5
7
7
1
1
1
CI2
Input Capacitance (RAS, LCAS, UCAS, WE, OE)
Output Capacitance (I/O0 - I/O15)
—
pF
CO
—
pF
1. Input capacitance measurements made with rise time shift method with CAS & RAS = VIH to disable output.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 5 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
DC Electrical Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
Symbol
Parameter
Min.
—
Max.
185
165
140
Units
mA
Notes
1, 2, 3
-50
-60 / -6R
-70
Operating Current
ICC1
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min.)
—
—
Standby Current (TTL)
Power Supply Standby Current
(RAS = CAS = VIH)
ICC2
—
2
mA
mA
-50
-60 / -6R
-70
—
—
—
—
—
—
—
185
165
140
100
90
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS = VIH: tRC = tRC min)
ICC3
1, 3
-50
EDO (Hyper Page) Mode Current
Average Power Supply Current
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
ICC4
ICC5
ICC6
-60 / -6R
-70
mA
mA
mA
1, 2, 3
80
Standby Current (CMOS)
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
SP version
1
LP version
—
0.2
-50
-60 / -6R
-70
—
—
—
—
185
165
140
200
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
1, 3
Self Refresh Current, LP version only
3.3V
Average Power Supply Current during Self Refresh
CBR cycle with RAS ≥ tRASS (min); CAS held low;
WE = VCC - 0.2V; Addresses and DIN = VCC - 0.2V or 0.2V.
ICC7
µA
5.0V
—
300
Input Leakage Current
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC + 0.3V)), All Other Pins Not Under Test = 0V
II(L)
IO(L)
VOH
µA
µA
V
-10
-10
2.4
+10
+10
VCC
Output Leakage Current
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC
)
Output Level (TTL)
Output “H” Level Voltage
(IOUT = -2.0mA for 3.3V, or IOUT = -5mA for 5.0V)
Output Level (TTL)
Output “L” Level Voltage
VOL
0.0
0.4
V
(IOUT = +2.0mA for 3.3V, or IOUT = +4.2mA for 5.0V)
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 6 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
1. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only
refresh cycles is required.
2. AC measurements assume tT=2ns.
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH
and VIL.
4. Valid column addresses are A0 through A9.
5. When both LCAS and UCAS go low at the same time, all 16 bits of data are read/written into the device. LCAS and UCAS cannot be
staggered within the same Read/Write cycle.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
-50
-60
-6R
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
89
35
8
—
—
104
40
10
60
10
0
—
—
104
40
10
60
10
0
—
—
124
50
10
70
12
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCP
CAS Precharge Time
—
—
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
RAS Pulse Width
50
8
10K
10K
—
10K
10K
—
10K
10K
—
10K
10K
—
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
0
10
0
—
10
0
—
10
0
—
10
0
—
—
—
—
—
8
_
10
14
12
10
50
5
—
10
14
12
10
50
5
—
10
14
12
12
55
5
—
14
12
8
37
25
—
45
30
—
43
30
—
50
35
—
1
2
CAS Hold Time
45
5
—
—
—
—
CAS to RAS Precharge Time
OE to DIN Delay Time
—
—
—
—
13
0
—
15
0
—
15
0
—
15
0
—
3
4
4
5
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
—
—
—
—
0
—
0
—
0
—
0
—
2
30
2
30
2
30
2
30
1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC
2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is
.
greater than the specified tRAD(max.) limit, then access time is controlled by tAA
.
3. Either tCDD or tOED must be satisfied.
4. Either tDZC or tDZO must be satisfied.
5. AC measurements assume tT=2ns.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 7 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Write Cycle
-50
Max.
-60 / -6R
-70
Max.
Symbol
Parameter
Units
Notes
1
Min.
0
Min.
Max.
—
Min.
0
tWCS
tWCH
tWP
Write Command Set Up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Setup Time
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
7
10
10
10
10
0
—
12
12
12
12
0
7
—
tRWL
tCWL
tDS
7
—
7
—
0
—
2
2
tDH
DIN Hold Time
7
10
—
12
1. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics
only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a Read-Modify-Write cycle and the data out
will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at
access time) is indeterminate.
2. These parameters are referenced to LCAS or UCAS leading edge in early write cycles and to WE leading edge in Read-Modify-
Write cycles.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 8 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Read Cycle
-50
-60
-6R
-70
Symbol
Parameter
Access Time from RAS
Units
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
tRAC
tCAC
tAA
—
—
—
—
0
50
13
25
13
—
—
—
—
—
13
—
13
—
—
—
—
—
—
0
60
15
30
15
—
—
—
—
—
15
—
15
—
—
—
—
—
—
0
60
17
30
17
—
—
—
—
—
15
—
15
—
—
—
—
—
—
0
70
20
35
20
—
—
—
—
—
15
—
15
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 3
2, 3
3
Access Time from CAS
Access Time from Address
tOEA
tRCS
tRCH
tRRH
tRAL
tCLZ
tOFF
tCDD
tOEZ
tOES
tORD
Access Time from OE
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
CAS to Output in Low-Z
0
0
0
0
4
4
0
0
0
0
25
0
30
0
30
0
35
0
3
5, 6
7
Output Buffer Turn-Off Delay
CAS to DIN Delay Time
—
13
—
5
—
15
—
5
—
15
—
5
—
15
—
5
Output Buffer Turn-Off Delay from OE
OE Setup Time Prior to CAS
OE Setup Time Prior to RAS (Hidden Refresh)
5
0
0
0
0
1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC
2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD
is greater than the specified tRAD(max.) limit, then access time is controlled by tAA
.
.
3. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V.
4. Either tRCH or tRRH must be satisfied for a read cycle.
5. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced to output
voltage levels.
6. tOFF is referenced from the rising edge of RAS or CAS, which ever is last.
7. Either tCDD or tOED must be satisfied.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 9 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Read-Modify-Write Cycle
-50
-60
-6R
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
tRWC
tRWD
tCWD
tAWD
tOEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
115
67
30
42
7
—
—
—
—
—
135
79
34
49
10
—
—
—
—
—
135
79
36
49
10
—
—
—
—
—
162
94
44
59
12
—
—
—
—
—
ns
ns
ns
ns
ns
1
1
1
CAS to WE Delay Time
Column Address to WE Delay Time
OE Command Hold Time
1. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics
only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a Read-Modify-Write cycle and the data out
will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at
access time) is indeterminate.
Extended Data Out (Hyper Page) Mode Cycle
-50
Max.
-60 / -6R
-70
Max.
Symbol
Parameter
Units
Notes
Min.
8
Min.
Max.
10K
—
Min.
12
tHCAS
tHPC
EDO (Hyper Page) Mode CAS Pulse Width
10K
—
10
25
10K
—
ns
ns
EDO (Hyper Page) Mode Cycle Time (Read/Write) 20
30
EDO (Hyper Page) Mode Read Modify Write Cycle
Time
tHPRWC
51
—
60
—
72
—
ns
tDOH
tWHZ
tWPZ
tCPRH
tCPA
Data-out Hold Time from CAS
5
—
10
5
—
10
5
—
15
ns
ns
ns
ns
ns
ns
ns
ns
Output buffer Turn-Off Delay from WE
WE Pulse Width to Output Disable at CAS High
RAS Hold Time from CAS Precharge
Access Time from CAS Precharge
EDO (Hyper Page) Mode RAS Pulse Width
OE High Pulse Width
0
0
0
7
—
10
35
—
60
10
10
—
10
40
—
70
10
10
—
30
—
50
10
10
—
—
—
30
35
40
1
tRASP
tOEP
125K
—
125K
—
125K
—
tOEHC
OE High Hold Time from CAS High
—
—
—
1. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 10 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Refresh Cycle
-50
-60 / -6R
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max.
CAS Setup Time
(CAS before RAS Refresh Cycle)
tCSR
tCHR
tWRP
5
—
—
—
5
—
—
—
5
—
—
—
ns
ns
ns
CAS Hold Time
(CAS before RAS Refresh Cycle)
10
10
10
10
10
10
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Cycle)
tWRH
tRPC
10
5
—
—
10
5
—
—
10
5
—
—
ns
ns
RAS Precharge to CAS Hold Time
Self Refresh Cycle - Low Power version only
-50
-60
-70
Symbol
Parameter
Units
Notes
Min.
100
Max.
—
Min. Max. Min. Max.
RAS Pulse Width
tRASS
tRPS
tCHS
tCHD
µs
ns
ns
µs
100
104
-50
—
—
—
—
100
124
-50
—
—
—
—
1
During Self Refresh Cycle
RAS Precharge Time
During Self Refresh Cycle
89
-50
350
—
—
—
1
CAS Hold Time From RAS Rising
During Self Refresh Cycle
1, 2
1, 2
CAS Hold Time From RAS Falling
During Self Refresh Cycle
350
350
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:
If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles,
then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a
full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
2. If tRASS > tCHD (min) then tCHD applies. If tRASS ≤ tCHD (min) then tCHS applies.
Refresh
-50
Max.
-60 / -6R
Min. Max.
-70
Max.
SYMBOL
Parameter
Units
ms
Notes
1
Min.
—
Min.
—
SP version
LP version
16
—
—
16
16
tREF
Refresh Period
—
128
128
—
128
1. 1024 cycles.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 11 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
UCAS
LCAS
tCAS
VIL
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
Address
Row
Column
VIL
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
VIL
NOTE 1
WE
OE
tAA
tOES
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tOED
VIH
VIL
DIN
Hi-Z
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Hi-Z
Valid Data Out
Hi-Z
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H”: or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 12 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
UCAS
tCAS
LCAS
VIL
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRH
tWRP
tWCS
tWCH
VIH
VIL
tWP
WE
OE
NOTE 1
VIH
VIL
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 13 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Write Cycle (Delayed Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
UCAS
LCAS
tCAS
VIL
tRAD
tASR
tASC
tRAH
tCAH
VIH
Address
Row
tWRP
Column
VIL
tWRH
tRCS
tCWL
VIH
VIL
tWP
NOTE 1
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tOED
tDZO
tDS
tWRP
tDZC
VIH
VIL
DIN
Hi-Z
Valid Data In
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
tOEH greater than or equal to tCWL
: “H” or “L”
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 14 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
tCAS
UCAS
LCAS
tRAD
VIL
tASR
tASC
tRAH
tCAH
VIH
Address
Row
Column
VIL
tCWD
tRWL
tCWL
tAWD
tWRH
tWRP
tRWD
tWP
VIH
VIL
NOTE 1
tAA
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
VIH
VIL
DIN
Hi-Z
tCAC
DIN
tOED
tCLZ
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
*
tRAC
t
OEH greater than or equal to tCWL
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 15 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Read Cycle
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
UCAS
LCAS
VIL
tCSH
tRAL
tCAH
tASR tRAH
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tWP
tCAC
tCAC
tCPA
tCPA
tOFF
tOES
tOEA
tAA
tAA
VIH
VIL
OE
tOEZ
tRAC
tAA
tDOH
tDOH
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 16 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Read Cycle (OE Control)
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
VIL
UCAS
LCAS
tCSH
tASC
tRAL
tCAH
tASR tRAH
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tCAC
tCAC
tCPA
tOFF
tCPA
tOES
tOEA
tAA
tAA
tOES
tOEHC
tOEP
tOES
tOEHC
tOEP
VIH
VIL
OE
tOEZ
tRAC
tAA
tOEA
tOEA
tCAC
tCLZ
tOEZ
tOEZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 17 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Read Cycle (WE Control)
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tRSH
tCP
tHCAS
tHCAS
tHCAS
VIH
UCAS
LCAS
VIL
tCSH
tRAL
tASR tRAH
tASC
tASC
tCAH
tASC
tCAH
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tAA
tAA
tRAD
tRCH
tRRH
tRCH
tRCS tRCH
tRCS
tWRH
tWRP
tRCS
tWPZ
tWPZ
VIH
VIL
WE
NOTE 1
tCAC
tOFF
tCAC
tCPA
tCPA
tOES
tOEA
VIH
VIL
OE
tOEZ
tRAC
tAA
tWHZ
tWHZ
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 18 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Early Write Cycle
tRP
tRASP
VIH
RAS
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
UCAS
LCAS
VIL
tRAD
tCSH
tASC
tRAL
tCAH
tCAH
tASR tRAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tRWL
tWCH
tWCH
tWRH
tWRP
tWCS
tWP
tWCS
tWP
tWCH
tWCS
VIH
VIL
tWP
WE
NOTE 1
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DIN
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
OE = Don’t care
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 19 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Late Write Cycle
tRP
tRASP
VIH
RAS
VIL
tHPC
tCRP
tRCD
tCP
tCP
tRSH
tHCAS
VIH
VIL
UCAS
LCAS
tHCAS
tHCAS
tRAD
tASR tRAH
tCSH
tASC
tRAL
tCAH
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tCWL
tCWL
tWRH
tWRP
tRCS
tRCS
tRWL
tWP
tRCS
tWP
tWP
VIH
VIL
WE
NOTE 1
tOEH
tOEH
tOEH
VIH
VIL
OE
tOED
tDS
tDH
tOED
tDS
tDH
tOED
tDS
tDH
VIH
VIL
DIN
Hi-Z
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 20 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Read Modify Write Cycle
tRP
tRASP
VIH
VIL
RAS
tHPRWC
tCRP
tCP
tCP
tRCD
VIH
VIL
UCAS
LCAS
tCAS
tCAS
tCAS
tCSH
tASC
tASC
tRAD
tRAH
tRAL
tASR
tASC
tCAH
tCAH
tCAH
VIH
VIL
Address
Column 1
Column 2
Column N
Row
tCWL
tRWL
tCPA
tAA
tCPA
tAA
tCWL
tRWD
tAWD
tCWD
tWRP
tWRH
tAWD
tCWD
tAWD
tCWD
tRCS
tRCS
tRCS
tWP
tWP
tWP
VIH
VIL
WE
OE
NOTE 1
tCAC
tRAC
tAA
tCAC
tCAC
tOEH
tOEH
tOEA
tOEH
tOEA
VIH
VIL
tOEA
tOED
tOED
tOED
tCLZ
tOEZ
DOUT
tDS
tOEZ
DOUT
tDS
tOEZ
tCLZ
tCLZ
VOH
VOL
DOUT
Hi-Z
Hi-Z
DOUT
tDS
tDH
DIN
tDH
DIN
tDH
DIN
VIH
VIL
DIN
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 21 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
EDO (Hyper Page) Mode Read and Write Cycle
tRP
tRASP
VIH
RAS
VIL
tCRP
tHPC
tHCAS
tRSH
tHCAS
tCP
tRCD
tCP
tHCAS
VIH
VIL
UCAS
LCAS
tRAD
tASR tRAH
tCSH
tASC
Column 1
tRAL
tCAH
tCAH
tASC
tASC
tCAH
VIH
VIL
Address
Row
Column 2
Column N
tWRP
tWRH
tRCS
tRCH
tWCS
VIH
VIL
tWCH
WE
tWP
NOTE 1
tCPA
tAA
tOEA
VIH
VIL
tCAC
OE
tOEZ
tRAC
tAA
tCAC
tDOH
Data Out
tWHZ
Data Out
tCLZ
VOH
VOL
DOUT
Hi-Z
tDS
tDH
VIH
VIL
DIN
Hi-Z
Data In
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 22 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCRP
tRPC
VIH
UCAS
LCAS
VIL
tASR
tRAH
VIH
Address
Row
VIL
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: WE, OE and DIN are “H” or “L”
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 23 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
CAS Before RAS Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tRPC
tCSR
tCSR
tCP
tCHR
VIH
VIL
UCAS
LCAS
tWRH
tWRH
tWRP
tWRP
VIH
VIL
WE
VIH
VIL
OE
tODD
tCDD
VOH
VOL
DIN
Hi-Z
tOEZ
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address is “H” or “L”
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 24 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
VIL
UCAS
LCAS
tRAL
tWRH
tWRP
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
OE
tORD
tAA
VIH
VIL
tOEA
tDZC
tCDD
tOED
tDZO
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
: “H” or “L”
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 25 of 32
IBM0118165M IBM0118165
IBM0118165P IBM0118165B
1M x 16 10/10 EDO DRAM
Hidden Refresh Cycle (Write)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRSH
tCRP
tRCD
tCHR
VIH
VIL
UCAS
LCAS
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tWCS
tWCH
VIH
VIL
tWP
WE
OE
VIH
VIL
tDH
tDS
VIH
VIL
DIN
Valid Data
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 26 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Self Refresh Cycle (Sleep Mode) - Low Power version only
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCHS
tCSR
tCRP
tCP
tCHD
VIH
VIL
UCAS
LCAS
tWRH
tWRP
VIH
VIL
WE
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTES:
1. Address and OE are “H” or “L”
2. Once RAS (min) is provided and RAS remains low, the DRAM
will be in Self Refresh, commonly known as “Sleep Mode.”
3. If tRASS > tCHD (min) then tCHD applies.
If tRASS ≤ tCHD (min) then tCHS applies.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 27 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
PACKAGE DIMENSIONS (400mil; 50/44 lead; Thin Small Outline Package)
20.95 ± 0.10
Detail A
+0.075
-0.005
0.125
Lead #1
Seating Plane
0.10
+ 0.10
- 0.05
0.35
0.80 Basic
0.875 REF
Detail A
0.25 Basic
1.00 ± 0.05
Gage Plane
+0.10
-0.00
0.5 ± 0.1
0.05
NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 28 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
PACKAGE DIMENSIONS (400mil; 42/42 lead; Small Outline J-Lead)
27.305 ± 0.127
3.505 ± 0.254
2.083 min
0.76 min
+0.097
0.203
-0.025
Lead #1 I.D.
Lead #1
Seating Plane
0.10
+0.088
0.42
-0.039
+0.123
-0.03
1.27 Basic
0.69
NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 29 of 32
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Revision Log
Revision
Contents Of Modification
11/15/95
Initial Release
1. The Low Power and Standard Power Specifications were combined. ES# 28H4722 and ES# 28H4723 were
combined into ES# 28H4723.
2. Added Die Rev E part numbers.
3. A -6R speed sort was added, with the following differences over the -60 speed sort:
-
-
-
-
tCAC was increased from 15ns to 17ns for the -6R speed sort
tRCD (max) was decreased from 45ns to 43ns for the -6R speed sort.
tCWD was increased from 34ns to 36ns for the -6R speed sort.
tOEA was increased from 15ns to 17ns for the -6R speed sort.
12/10/95
4. tCHD was added to the Self Refresh Cycle with a value of 350µs for all speed sorts.
5. The Self Refresh timing diagram was changed to allow CAS to go high tCHD (350µs) after RAS falls entering a
Self Refresh.
6. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
7. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 30 of 32
International Business Machines Corp.1996
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
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