IBM11D1320B-70 [IBM]
Fast Page DRAM Module, 1MX32, 70ns, CMOS, PSMA72;
| 型号： | IBM11D1320B-70 |
| 厂家： | 
IBM |
| 描述： | Fast Page DRAM Module, 1MX32, 70ns, CMOS, PSMA72 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IBM11D1320B1M
x 3210/10, 5.0V, Sn/PbMMDS16DSU-001021720. IBM11D2320B2M x 3210/10, 5.0V, Sn/PbMMDS16DSU-001021720.
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Features
• 72-Pin JEDEC Standard Single-In-Line
Memory Module
• Performance:
• High Performance CMOS process
• Single 5V, ± 0.5V Power Supply
• Low active current dissipation
• All inputs & outputs are fully TTL & CMOS
compatible
-60
-70
• Fast Page Mode access cycle
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
• 1024 refresh cycles distributed across 16ms
• 10/10 Addressing (Row/Column)
• Optimized for use in byte-write non-parity appli-
cations.
tRAC
tCAC
tAA
RAS Access Time
CAS Access Time
60ns 70ns
15ns 18ns
Access Time From Address 30ns 35ns
tRC
Cycle Time
110ns 130ns
• Available in tin/lead tabs.
• DRAMs in SOJ Package
tPC
Fast Page Mode Cycle Time 40ns 40ns
Description
The IBM11D2320B is an 8MB industry standard
72-pin 4-byte single in-line memory module (SIMM).
The module is organized as a 2Mx32 high speed
memory array, and is configured as two 1Mx32
banks -each independently selectable via unique
RAS inputs. The assembly is intended for use in 16,
32 and 64 bit applications. It is manufactured with
sixteen 1Mx4 devices, each in a 300mil package,
and is compatible with the JEDEC 72-Pin SIMM
standard.
The IBM11D1320B is a 4MB half populated version,
manufactured with eight 1Mx4 devices.
The IBM 72-Pin SIMMs provide a high performance,
flexible 4-byte interface in a 4.25” long footprint.
Related products include the 2Mx36 parity SIMM,
IBM11D2360B, as well as other density offerings
and ECC-optimized SIMMs.
Card Outline
1
36
37
72
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 1 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Pin Description
Pinout
RAS0, RAS2
RAS0 - RAS3
CAS0 - CAS3
WE
Row Address Strobe (4MB)
Pin # Name
Pin # Name
Pin # Name
Row Address Strobe (8MB)
Column Address Strobe
Read/write Input
VSS
1
2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQ24
DQ7
DQ25
A7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ9
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
VCC
3
A0 - A9
Address Inputs
4
DQ0-7, 9-16, 18-25,
27-34
Data Input/output
5
NC
VCC
6
VCC
VSS
Power (+5V)
Ground
7
A8
NC
No Connect
Presence Detects
8
A9
PD1 - PD4
9
RAS3*
RAS2
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
A0
NC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
A1
NC
A2
NC
VSS
A3
A4
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1*
NC
A5
A6
NC
PD1
DQ4
DQ22
DQ5
DQ23
DQ6
PD2
PD3
PD4
WE
NC
VSS
NC
1. DQ numbering is compatible with parity (x36) version.
2. * RAS1 and RAS3 are “NC” on 4MB SIMM.
Ordering Information
Part Number
Organization
Addr.
10/10
Speed
60ns
Leads
Sn/Pb
Dimensions
Notes
IBM11D1320B-60
IBM11D1320B-70
IBM11D1320B-60J
IBM11D1320B-70J
IBM11D2320B-60
70ns
60ns
70ns
1M x 32
2M x 32
4.25” x .9” x .205”
1
1
60ns
70ns
60ns
70ns
IBM11D2320B-70
IBM11D2320B-60J
IBM11D2320B-70J
4.25” x 1” x .360”
1
1
1. DRAM package designator appended to speed portion of part number on assemblies beginning with die rev G.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 2 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Block Diagram
Applies to both 4MB and 8MB SIMMs
DQ0
DQ7
DQ9
DQ16
DQ1-4
WE
DQ1-4
WE
DQ1-4
WE
DQ1-4
WE
CAS
U4
RAS
OE
WE
CAS0
RAS0
CAS
RAS
OE
CAS
RAS
OE
CAS
RAS
OE
U1
U2
U3
A0-A9
A0-A9
A0-A9
A0-A9
10
10
10
10
CAS1
DQ18
DQ25
DQ27
DQ34
DQ1-4
DQ1-4
WE
DQ1-4
WE
DQ1-4
WE
WE
CAS2
RAS2
CAS
RAS
OE
CAS
RAS
OE
CAS
RAS
OE
CAS
U8
RAS
OE
U5
U7
U6
A0-A9
A0-A9
A0-A9
A0-A9
10
10
10
10
CAS3
A0-A9
Applies to 8MB SIMM only
DQ7
DQ0
DQ9
DQ16
DQ1-4
DQ1-4
WE
DQ1-4
DQ1-4
WE
WE
CAS0
RAS1
WE
WE
CAS
RAS
OE
CAS
U16
RAS
OE
CAS
RAS
OE
CAS
U12
RAS
OE
U15
U11
A0-A9
A0-A9
A0-A9
A0-A9
10
10
10
10
CAS1
DQ18
DQ25
DQ27
DQ34
DQ1-4
DQ1-4
WE
DQ1-4
WE
DQ1-4
WE
WE
CAS2
RAS3
CAS
RAS
OE
CAS
U14
RAS
OE
CAS
RAS
OE
CAS
RAS
OE
U13
U9
U10
A0-A9
A0-A9
A0-A9
A0-A9
10
10
10
10
CAS3
A0-A9
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 3 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Truth Table
Row
Address
Column
Address
Function
RAS
CAS
WE
All DQ, PQ bits
Standby
Read
H
L
L
H→X
X
H
L
X
X
High Impedance
Valid Data Out
Valid Data In
L
L
Row
Row
Col
Col
Early-Write
Fast Page Mode - Read:
1st Cycle
L
L
L
H→L
H→L
H→L
H
H
L
Row
N/A
Col
Col
Col
Valid Data Out
Valid Data Out
Valid Data In
Subsequent Cycles
Fast Page Mode - Write:
1st Cycle
Row
Subsequent Cycles
RAS-Only Refresh
L
H→L
L
X
H
H
L
N/A
Row
X
Col
N/A
X
Valid Data In
High Impedance
High Impedance
Data Out
L
H
L
L
L
CAS-Before-RAS Refresh
H→L
Read
Write
L→H→L
L→H→L
Row
Row
Col
Col
Hidden Refresh
Data In
Presence Detect
1M x 32
2M x 32
Pin
-60
-70
-60
-70
VSS
VSS
NC
NC
VSS
VSS
VSS
NC
NC
NC
NC
NC
PD1
PD2
PD3
PD4
NC
NC
VSS
NC
1. NC= OPEN, V = GND
ss
Absolute Maximum Ratings
Symbol
VCC
Parameter
Rating
Units
V
Notes
1
1
Power Supply Voltage
Input Voltage
-0.5 to + 6.0
-0.5 to + 6.0
-0.5 to + 6.0
0 to +70
VIN
V
1
VOUT
TOPR
TSTG
PD
Output Voltage
V
1
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
1
-55 to +125
1, 2
1
3.75 (4MB) 7.5 (8MB)
50
IOUT
Short Circuit Output Current
mA
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect reliability.
2. Maximum power occurs when all banks are active (refresh cycle).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 4 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Recommended DC Operating Conditions (TA = 0 to 70°C)
Symbol
VCC
Parameter
Min
4.5
Typ
5.0
Max
5.5
Units
V
Notes
1
Supply Voltage
1, 2
1, 2
VIH
VIL
Input High Voltage
Input Low Voltage
2.4
—
—
VCC + 0.5
0.8
V
V
-0.5
1. All voltages referenced to VSS
.
2. VIH may overshoot to VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V for ≤ 8.0ns). Additionally, VIL may undershoot to -2.0V
for pulse widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC refer-
ence.
Capacitance (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
1M x 32
Max
2M x 32
Max
Symbol
Parameter
Units
CI1
CI2
CI3
CI4
CI5
CI/O
Input Capacitance (A0-A9)
60
35
35
67
21
13
100
40
pF
pF
pF
pF
pF
pF
Input Capacitance (4MB: RAS0, 8MB: RAS0, 1)
Input Capacitance (4MB: RAS2, 8MB: RAS2, 3)
Input Capacitance (WE)
40
127
40
Input Capacitance (CAS)
Output Capacitance (DQ0-DQ34)
25
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 5 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
DC Electrical Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
Symbol
ICC1
Parameter
1M x 32
2M x 32
Units Notes
Operating Current
-60
-70
—
680
560
—
696
576
1, 2, 3
mA
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
—
—
—
—
Standby Current (TTL)
Power Supply Standby Current
(RAS = CAS ≥ VIH)
ICC2
16
32
mA
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS ≥ VIH: tRC = tRC min)
-60
-70
-60
-70
—
—
—
—
680
560
480
400
—
—
—
—
696
576
496
416
1, 3, 4
mA
ICC3
ICC4
ICC5
ICC6
Fast Page Mode Current
Average Power Supply Current, Fast Page Mode
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
1, 2, 3
mA
Standby Current (CMOS)
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
—
8
—
16
mA
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
-60
-70
—
—
680
560
—
—
696
576
1, 3, 4
mA
RAS
CAS
-40
-20
-80
+40
+20
+80
-40
-40
+40
+40
Input Leakage Current
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC < 6.0V))
µA
µA
II(L)
All Other Pins Not Under Test = 0V
All others
-160
+160
Output Leakage Current
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC
IO(L)
VOH
VOL
-10
2.4
—
+10
VCC
0.4
-20
2.4
—
+20
VCC
0.4
)
Output High Level
Output "H" Level Voltage (IOUT = -5mA @ 2.4V)
V
V
Output Low Level
Output "L" Level Voltage (IOUT = +4.2mA @ 0.4V)
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open.
3. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH
4. Refresh current is specified for 1 bank active and 1 bank standby.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 6 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
AC Characteristics (TA = 0 to +70°C, VCC = 5.0V ± 0.5V)
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL.
2. An initial pause of 100µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. AC measurements assume tT = 5ns.
Read, Write, and Refresh Cycles (Common Parameters)
-60
-70
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
tRC
tRP
tCP
Random Read or Write Cycle Time
RAS Precharge Time
110
40
—
—
—
130
50
—
—
—
ns
ns
ns
CAS Precharge Time
10
10
tRAS
RAS Pulse Width
60
10K
70
10K
ns
tCAS
tASR
tRAH
tASC
CAS Pulse Width
15
0
100K
—
18
0
100K
—
ns
ns
ns
ns
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
10
0
—
10
0
—
—
—
tCAH
tRCD
Column Address Hold Time
RAS to CAS Delay Time
10
20
—
10
20
—
ns
ns
45
52
1
2
tRAD
tRSH
tCSH
tCRP
tDZC
tT
RAS to Column Address Delay Time
RAS Hold Time
13
15
60
5
30
—
—
—
—
50
—
15
18
70
5
35
—
—
—
—
50
—
ns
ns
ns
ns
ns
ns
ns
CAS Hold Time
CAS to RAS Precharge Time
CAS Delay Time from DIN
0
0
Transition Time (Rise and Fall)
Column Address Hold Time Referenced to RAS
3
3
tAR
—
—
3
1. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled by tCAC
2. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD
is greater than the specified tRAD (max) limit, then access time is controlled by tAA
3. This timing parameter is not applicable to this product, but applies to a related product in this family.
.
.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 7 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Write Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min
0
Max
—
Min
0
Max
—
tWCS
tWCH
tWP
Write Command Set Up Time
Write Command Hold Time
Write Command Pulse Width
ns
ns
ns
10
10
—
15
15
—
—
—
tRWL
Write Command to RAS Lead Time
15
—
18
—
ns
1
tCWL
tWCR
tDHR
tDS
Write Command to CAS Lead Time
Write Command Hold Time Referenced to RAS
Data Hold Time Referenced to RAS
DIN Setup Time
15
—
—
0
—
—
—
—
18
—
—
0
—
—
—
—
ns
ns
ns
ns
1
1
1
tDH
DIN Hold Time
12
—
15
—
ns
1. This timing parameter is not applicable to this product, but applies to a related product in this family.
Read Cycle
-60
-70
Symbol
Parameter
Access Time from RAS
Units
Notes
Min
—
—
—
0
Max
60
15
30
—
Min
—
—
—
0
Max
70
18
35
—
tRAC
tCAC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
1, 2
1, 2
Access Time from CAS
Access Time from Address
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
0
—
0
—
3
3
0
—
0
—
30
—
0
—
35
—
0
—
—
—
4
—
—
Output Data Hold Time
0
—
0
—
tCDD
tOFF
CAS to DIN Delay Time
15
—
—
20
—
—
ns
ns
4
5
Output Buffer Turn-off Delay
15
15
1. Measured with the specified current load and 100pF.
2. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA
3. Either tRCH or tRRH must be satisfied for a read cycle.
.
4. This timing parameter is not applicable to this product, but applies to a related product in this family.
5. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 8 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Fast Page Mode Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min
40
60
35
—
Max
—
Min
40
70
40
—
Max
—
tPC
Fast Page Mode Cycle Time
ns
ns
ns
ns
tRASP
tCPRH
tCPA
Fast Page Mode RAS Pulse Width
RAS Hold Time from CAS Precharge
Access Time from CAS Precharge
100K
—
100K
—
35
40
1, 2
1. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA
2. Access time assumes a load of 100pF.
.
Refresh Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min
10
Max
—
Min
10
Max
—
CAS Hold Time
(CAS before RAS Refresh Cycle)
tCHR
tCSR
tWRP
tWRH
ns
ns
ns
ns
CAS Setup Time
(CAS before RAS Refresh Cycle)
—
—
—
—
—
—
5
5
WE Setup Time
(CAS before RAS Refresh Cycle)
10
10
10
10
WE Hold Time
(CAS before RAS Refresh Cycle)
tRPC
tREF
RAS Precharge to CAS Hold Time
Refresh Period
0
—
0
—
ns
—
16
—
16
ms
1
1. 1024 refreshes are required every 16ms.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 9 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
CAS
VIL
tCAS
tRAL
tRAD
tCAL
tASR
tASC
tAR
tRAH
tCAH
VIH
Address
Row
Column
VIL
tRCH
tRCS
tRRH
VIH
VIL
WE
tAA
tDZC
tCDD
VIH
VIL
Hi-Z
DIN
tCAC
tOFF
tCLZ
VOH
VOL
Hi-Z
Hi-Z
DOUT
Valid Data Out
tOH
tRAC
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 10 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
tCAS
CAS
VIL
tAR
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWCS
tWCH
VIH
VIL
tWP
WE
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 11 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Fast Page Mode Read Cycle
tRASP
tRP
tCPRH
VIH
tAR
RAS
CAS
VIL
tPC
tCRP
tRSH
tCP
tRCD
tCP
VIH
VIL
tCAS
tCAS
tCAS
tCAL
tCSH
tRAL
tRAH
tASR
tASC tCAH
tCAH
tASC
tASC tCAH
Column N
VIH
VIL
Address
Column 1
Column 2
Row
tRAD
tRCS
tRCS
t
tRCH
RCS
tRCH
tRCH
VIH
VIL
WE
tRRH
tAA
tAA
tAA
tCPA
tCPA
tOH
tOH
tOH
t
t
DZC
tDZC
t
DZC
CDD
VIH
VIL
DIN
tCAC
tCAC
tCAC
tOFF
tOFF
tOFF
tRAC
tCLZ
tCLZ
tCLZ
VOH
VOL
DOUT
1
DOUT
2
DOUT N
DOUT
: “H” or “L”
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Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 12 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Fast Page Mode Write Cycle
tRASP
tRP
VIH
tAR
RAS
CAS
VIL
tPC
tCRP
tRSH
tRCD
tCP
tCP
VIH
VIL
tCAS
tCAS
tCAS
tCSH
tCAH
tRAH
tASC tCAH
tASR
tASC tCAH
tASC
VIH
VIL
Address
Column 1
Column 2
Column N
tCWL
Row
tRAD
tWCR
tCWL
tCWL
tRWL
tWCH
tWCH
tWCH
tWCS
tWCS
tWCS
tWP
tWP
tWP
VIH
VIL
WE
tDHR
tDS
tDS tDH
tDS tDH
tDH
VIH
VIL
DIN
DIN
1
DIN
2
DIN N
VOH
VOL
DOUT
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 13 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCRP
tRPC
VIH
VIL
tASR
tRAH
VIH
Address
Row
VIL
VOH
Hi-Z
DOUT
VOL
: “H” or “L”
Note: WE, DIN are “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 14 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
CAS Before RAS Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tRPC
tCSR
tCSR
tCP
tCHR
VIH
VIL
CAS
tWRH
tWRH
tWRP
tWRP
VIH
VIL
WE
tCDD
VOH
VOL
DIN
Hi-Z
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address is “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 15 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
CAS
VIL
tRAL
tWRH
tWRP
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
tAA
tDZC
tCDD
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
tOH
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 16 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Hidden Refresh Cycle (Write)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRSH
tCRP
tRCD
tCHR
VIH
CAS
VIL
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tWCS
tWCH
VIH
VIL
tWP
WE
tDH
tDS
VIH
VIL
DIN
Valid Data
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 17 of 20
IBM11D2320B IBM11D1320B
1M/2M x 32 DRAM Module
Layout Drawing: IBM11D/E1320B (4MB) & IBM11D2320B (8MB)
107.95
4.25
101.190
3.983
Front
(2X) 0
3.1877
.1255
6.35
.250
2.03
.08
1.27 PITCH
.050
44.45
1.75
1.00 WIDTH
.039
95.25
3.75 REF.
Side (4MB)
Side (8MB)
9.14
5.20
.360 MAX.
.205 MAX.
.1016
.1016
+
_
+
_
1.27
.050
1.27
.050
.0762
.0762
.004
+
_
.004
+
_
.003
.003
Millimeters
Inches
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 18 of 20
IBM11D1320B IBM11D2320B
1M/2M x 32 DRAM Module
Revision Log
Rev
Contents of Modification
Initial release of combined datasheet for 1M x 32, 2M x 32
12/95
3/96
Previously released as publications SA14-4306 (03H7139) and SA14-4307 (03H7140)
tCAC changed from 15ns to 10ns for the -70 speed
tDH changed from 15ns to 12ns for the -60 speed
CBR timing diagram changed to allow CAS to remain low for back-to-back CBR cycles
Updated ordering information
6/96
Added package descriptor to speed designation
Removed gold tab versions
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7976
SA14-4333-02
Revised 6/96
Page 19 of 20
International Business Machines Corp.1996
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.
SA14-4333-02
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