IBM11M32735BBC-60Y [IBM]
EDO DRAM Module, 32MX72, 60ns, CMOS, DIMM-168;
| 型号： | IBM11M32735BBC-60Y |
| 厂家： | 
IBM |
| 描述： | EDO DRAM Module, 32MX72, 60ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M1730BB1M
x 72 E10/10, 3.3V, Au.
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Features
• Au contacts
• 168 Pin JEDEC Standard, 8 Byte Dual In-line
Memory Module
• Optimized for ECC applications
• System Performance Benefits:
- Buffered inputs (except RAS, Data)
• 2Mx72 Fast Page Mode DIMM
• Performance:
- Reduced noise (32 V /V pins)
- Buffered PDs
SS CC
-60
-70
tRAC
tCAC
tAA
RAS Access Time
60ns
20ns
35ns
70ns
25ns
40ns
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
CAS Access Time
Access Time From Address
Cycle Time
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
tRC
104ns 124ns
25ns 30ns
tHPC
EDO Page Mode Cycle Time
• 2048 refresh cycles distributed across 32ms
• 11/10 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.157"
• DRAMS in TSOP Package
• All inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
• Single 3.3V ± 0.3V or 5.0V ± 0.5V Power Supply
Description
IBM11M2735H is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) which is
organized as a 2Mx72 high speed memory array
designed with EDO DRAMs for ECC applications.
The DIMM uses 9 2Mx8 DRAMs in TSOP packages.
The use of EDO DRAMs allows for a reduction in
Page Mode Cycle time from 40ns (Fast Page) to
25ns for 60ns DRAM modules.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, the system
will determine that ECC DIMMs are installed if PD8
is low (0). ID0 need not be sensed since both x72
and x80 ECC DIMMs will function in a x72 bank.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and RAS signals are not
buffered, which preserves the DRAM access specifi-
cations of 60ns and 70ns.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x64 and x72 par-
ity (5V) DIMMs and ECC DIMMs (5V and 3.3V).
Card Outline 3.3V
Detail A
(Front)
(Back)
1
85
10 11
94 95
84
168
40 41
124 125
See Detail A
for 5.0V Version
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Pin Description
VCC
VSS
RAS0, RAS2
Row Address Strobe
Power (3.3V or 5.0V)
CAS0, CAS4
WE0, WE2
OE0, OE2
Column Address Strobe (Buffered)
Read/write Input (Buffered)
Output Enable (Buffered)
Address Inputs (Buffered)
Data Input/Output
Ground
NC
No Connect
PD1 - PD8
PDE
Presence Detects (Buffered)
Presence Detect Enable
ID Bits
A0, B0, A1 - A10
DQx
ID0 - ID1
Pinout
Front
Side
Back
Front
Side
Back
Side
Front
Side
Back
Front
Side
Back
Side
Pin#
Pin#
Pin#
22
Pin#
106
Pin#
Pin#
Pin#
64
Pin#
148
Side
Side
DQ17
VSS
DQ53
VSS
NC
NC
VSS
VSS
VSS
VSS
1
2
3
4
5
85
86
87
88
89
43
44
45
46
47
127
128
129
130
131
DQ0
DQ1
DQ2
DQ3
VCC
DQ36
DQ37
DQ38
DQ39
VCC
23
24
25
26
107
108
109
110
OE2
RAS2
CAS4
NC
NC
NC
NC
NC
65
66
67
68
DQ25
DQ26
DQ27
VSS
149
150
151
152
DQ61
DQ62
DQ63
VSS
NC
NC
VCC
NC
NC
VCC
6
90
27
WE0
111
NC
48
WE2
VCC
132
PDE
VCC
69
DQ28
153
DQ64
7
8
9
DQ4
DQ5
DQ6
DQ7
91
92
93
94
DQ40
DQ41
DQ42
DQ43
28
29
30
31
CAS0
NC
RAS0
OE0
VSS
112
113
114
115
NC
NC
NC
NC
VSS
49
50
51
52
133
134
135
136
70
71
72
73
DQ29
DQ30
DQ31
VCC
154
155
156
157
DQ65
DQ66
DQ67
VCC
NC
NC
DQ18
NC
NC
DQ54
10
11
DQ8
VSS
95
DQ44
VSS
32
116
53
DQ19
VSS
137
DQ55
VSS
74
DQ32
158
DQ68
12
13
14
15
16
17
96
97
98
99
100
101
33
34
35
36
37
38
A0
A2
A4
A6
A8
117
118
119
120
121
122
A1
A3
A5
A7
A9
NC
54
55
56
57
58
59
138
139
140
141
142
143
75
76
77
78
79
80
DQ33
DQ34
DQ35
VSS
159
160
161
162
163
164
DQ69
DQ70
DQ71
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ20
DQ21
DQ22
DQ23
VCC
DQ56
DQ57
DQ58
DQ59
VCC
PD1
PD3
PD2
PD4
A10
39
40
41
42
NC
VCC
NC
NC
123
124
125
126
NC
VCC
NC
B0
81
82
83
84
PD5
PD7
ID0
165
166
167
168
PD6
PD8
ID1
18
19
20
21
102
103
104
105
60
61
62
63
DQ24
NC
144
145
146
147
DQ60
NC
DQ14
DQ15
DQ16
DQ50
DQ51
DQ52
NC
NC
VCC
VCC
NC
NC
Note: All pin assignments are consistent for all 8 Byte versions.
Ordering Information
Part Number
IBM11M2735H-60
Organization
Addr.
Dimension
Power
5.0V
Notes
Speed
60ns
Leads
IBM11M2735H-70
IBM11M2735H-60T
IBM11M2735H-70T
IBM11M2735HB-60
IBM11M2735HB-70
IBM11M2735HB-60T
IBM11M2735HB-70T
70ns
60ns
70ns
60ns
70ns
60ns
70ns
1
1
2Mx72
11/10
5.25”x1.0”x 0.157”
Au
3.3V
1
1
1. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev E.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Block Diagram
OE0
OE2
WE0
RAS0
CAS0
WE2
RAS2
CAS4
CAS RAS WE OE
CAS RAS WE OE
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D5
CAS RAS WE OE
I/O 7
CAS RAS WE OE
I/O 0
DQ8
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ9
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CAS RAS WE OE
I/O 4
CAS RAS WE OE
I/O 0
DQ16
DQ17
DQ18
DQ19
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 5
I/O 2
I/O 3
I/O 6
I/O 7
I/O 0
I/O 1
I/O 1
I/O 2
I/O 3
I/O 7
I/O 6
I/O 5
I/O 4
D2
D7
CAS RAS WE OE
I/O 7
CAS RAS WE OE
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
I/O 6
I/O 5
I/O 4
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 1
I/O 2
I/O 3
I/O 7
I/O 6
I/O 5
I/O 4
D8
CAS RAS WE OE
I/O 7
V
PD1 - 8
SS
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
PDE
(when=0, 1=NC)
I/O 6
I/O 5
I/O 4
I/O 0
I/O 1
I/O 2
I/O 3
D4
A1 - AN
A0
A1-AN: DRAMS D0 - D8
A0: DRAMS D0 - D4
B0
A0: DRAMS D5 - D8
Note: DRAM IO assignments are scrambled to minimize DQ capacitance.
V
D0 - D8
D0 - D8
CC
V
SS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Truth Table
Row
Column
Function
RAS
CAS
WE
OE
PDE
DQx
Address Address
Standby
Read
H
L
L
L
H→X
X
H
X
L
X
X
X
X
X
X
High Impedance
Valid Data Out
Valid Data In
L
L
L
Row
Row
Row
Col
Col
Col
Early-Write
Late-Write
L
X
H
H→L
Valid Data In
Valid Data Out,
Valid Data In
H→L
L→H
RMW
L
L
Row
Col
X
EDO Page Mode - Read
1st Cycle
H→L
H→L
H→L
H→L
H→L
L
L
L
L
L
H
H
L
L
Row
N/A
Col
Col
Col
Col
Col
X
X
X
X
X
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Subsequent Cycles
EDO Page Mode - Write
1st Cycle
L
X
Row
N/A
Subsequent Cycles
L
X
EDO Page Mode - RMW
1st Cycle
Valid Data Out,
Valid Data In
H→L
L→H
Row
Valid Data Out,
Valid Data In
H→L
H→L
L→H
Subsequent Cycles
L
N/A
Col
X
L
H
L
L
L
X
H
H
H
X
X
L
Row
X
N/A
X
X
X
X
X
High Impedance
High Impedance
Data Out
RAS-Only Refresh
H→L
CAS-Before-RAS Refresh
L→H→L
L→H→L
Read
Write
Row
Row
Col
Col
Hidden Refresh
X
Data In
Not Affected
(PD Bits Valid)
Read Presence Detects
X
X
X
X
X
X
L
Presence Detect
Pin
-60
1
-70
1
PD1 (PD1 - PD4: Addressing/Density)
PD2
0
0
PD3
0
0
PD4
1
1
PD5 (EDO Detection)
PD6 (PD6 - PD7: Speed)
PD7
1
1
1
0
1
1
PD8 (Parity/ECC Designator)
ID0 (DIMM Type/Width)
ID1 (Refresh Mode)
0
0
0
0
0
0
1. PD1-8 are buffered outputs (0 = driven to VOL, 1 = open)
2. ID0-1 are unbuffered outputs (0 = VSS, 1 = open)
3. PDE should be tied high or low at system level if not used
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Absolute Maximum Ratings
Symbol
VCC
Parameter
Power Supply Voltage
Input Voltage
Rating (3.3V)
-0.5 to +4.6
Rating (5.0V)
-1.0 to +7.0
Units
V
Notes
1
1
1
VIN
-0.5 to min (VCC + 0.5, 4.6) -0.5 to min (VCC + 0.5, 7.0)
-0.5 to min (VCC + 0.5, 4.6) -0.5 to min (VCC + 0.5, 7.0)
V
VOUT
Output Voltage
V
TOPR
TSTG
°C
Operating Temperature
Storage Temperature
0 to +70
0 to +70
1
1
°C
-55 to +125
-55 to +125
1
1
1
PD
IOUT
Power Dissipation
2.9
50
60
4.5
50
60
W
Short Circuit Output Current
Short Circuit Output Current (PD)
mA
mA
IOUTPD
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating con-
dition for extended periods may affect reliability.
°
Recommended DC Operating Conditions (TA = 0 to 70 C)
3.3V
Typ
3.3
—
5.0V
Typ
5.0
—
Symbol
Parameter
Units
Notes
Min
3.0
Max
3.6
Min
4.5
Max
5.5
VCC
VIH
VIL
Supply Voltage
V
V
V
1
VCC + 0.5
0.8
VCC + 0.5
0.8
Input High Voltage
Input Low Voltage
2.0
2.4
1, 2
1, 2
-0.5
—
-0.5
—
1. All voltages referenced to VSS.
2. VIH may overshoot to VCC + 1.2V for pulse widths of ≤ 4.0ns with 3.3 Volt, or VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V
for ≤ 8.0ns) with 5.0 Volt. Additionally, VIL may undershoot to -2.0V for pulse widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns). Pulse widths
measured at 50% points with amplitude measured peak to DC reference.
°
Capacitance (TA = 0 to +70 C, VCC = 3.3V ± 0.3V or 5.0V ± 0.5V)
Symbol
CI1
Parameter
Input Capacitance (A0, B0, A1-A10)
Max
13
40
13
18
15
15
5
Units
pF
CI2
Input Capacitance (RAS)
pF
Input Capacitance (CAS, WE, OE)
CI3
pF
CI4
Input Capacitance (PDE)
Input/Output Capacitance (DQX)
Output Capacitance (PD)
Output Capacitance (ID)
pF
CIO1
CO1
CO2
pF
pF
pF
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
DC Electrical Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
Symbol
Parameter
Min. Max.
Units
mA
Notes
1, 2, 3
Operating Current
-60
—
—
810
720
ICC1
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min.)
-70
Standby Current (TTL)
Power Supply Standby Current
(RAS = CAS = VIH)
ICC2
—
18
mA
mA
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS = VIH: tRC = tRC min)
-60
-70
-60
—
—
—
810
720
450
ICC3
1, 2, 3
1, 3
Hyper Page Mode Current
ICC4
Average Power Supply Current, Hyper Page Mode
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
mA
-70
—
—
—
360
9
Standby Current (CMOS)
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
ICC5
mA
mA
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
-60
810
ICC6
1, 3
-70
—
720
+10
Input Leakage Current
All but RAS
-10
II(L)
IO(L)
VOH
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC + 0.3V)), All Other Pins Not Under Test = 0V
µA
µA
V
RAS
-50
-10
+50
+10
Output Leakage Current
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC
)
Output Level (TTL)
Output “H” Level Voltage
(IOUT = -2mA for 3.3V, or IOUT = -5mA for 5.0V)
VCC
0.4
2.4
0.0
Output Level (TTL)
Output “L” Level Voltage
(IOUT = +2mA for 3.3V, or IOUT = +4.2mA for 5.0V)
VOL
V
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
AC Characteristics (T = 0 to +70°C, V = 3.3V ± 0.3V or 5.0V ± 0.5V)
A
cc
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL.
2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the
DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 60ns and
70ns.
4. AC measurements assume tT = 2ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
-60
-70
Symbol
Parameter
Unit
Notes
Min
104
40
10
60
10
5
Max
—
Min
124
50
10
70
12
5
Max
—
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tCP
CAS Precharge Time
—
—
tRAS
tCAS
tASR
tRAH
tASC
RAS Pulse Width
10K
10K
—
10K
10K
—
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
8
—
8
—
2
—
2
—
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tODD
tDZO
tDZC
tT
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
12
10
15
48
10
20
-2
—
40
25
—
—
—
—
—
—
30
10
12
10
17
53
10
25
-2
—
45
30
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
CAS Hold Time
CAS to RAS Precharge Time
OE to DIN Delay Time
3
4
4
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
-2
-2
2
2
1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.
2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD
is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
3. Either tCDD or tODD must be satisfied.
4. Either tDZC or tDZO must be satisfied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Write Cycle
-60
-70
Symbol
Parameter
Write Command Set Up Time
Unit
Notes
1
Min
2
Max
—
Min
2
Max
—
tWCS
tWCH
tWP
ns
ns
ns
ns
ns
ns
ns
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Setup Time
12
10
15
12
-2
—
14
12
17
14
-2
—
—
—
tRWL
tCWL
tDS
—
—
—
—
—
—
2
2
tDH
DIN Hold Time
15
—
17
—
1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If
WCS ≥ tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
t
entire cycle; If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.)and tAWD ≥ tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will
contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is
indeterminate.
2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Read Cycle
-60
-70
Symbol
Parameter
Unit
Notes
Min
—
—
—
—
2
Max
60
20
35
20
—
Min
—
—
—
—
2
Max
70
25
40
25
—
tRAC
tCAC
tAA
Access Time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
1, 2
1, 2
1, 2
Access Time from CAS
Access Time from Address
Access Time from OE
tOEA
tRCS
tRCH
tRRH
tRAL
tCLZ
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
CAS to Output in Low-Z
2
—
2
—
3
3
0
—
0
—
35
2
—
40
2
—
—
—
tOES
tORD
tCDD
tOEZ
tOFF
OE setup time prior to CAS
10
5
—
—
—
20
20
10
5
—
—
—
20
20
ns
ns
ns
ns
ns
OE setup time prior to RAS (Hidden Refresh)
CAS to DIN Delay Time
5
4
20
2
20
2
Output Buffer Turn-off Delay from OE
Output Buffer Turn-off Delay
4, 6
2
2
1. Measured with the specified current load and 100pF.
2. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA
3. Either tRCH or tRRH must be satisfied.
.
4. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
5. Either tCDD or tODD must be satisfied.
6. tOFF is referenced from the rising edge of RAS or CAS , whichever is last.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Read-Modify-Write Cycle
-60
-70
Symbol
Parameter
Read-Modify-Write Cycle Time
Unit
Notes
Min
143
82
Max
—
Min
170
97
Max
—
tRWC
tRWD
tCWD
tAWD
tOEH
ns
ns
ns
ns
ns
RAS to WE Delay Time
—
—
1
1
1
CAS to WE Delay Time
44
—
54
—
Column Address to WE Delay Time
OE Command Hold Time
57
—
67
—
10
—
12
—
1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If
WCS ≥ tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
t
entire cycle; If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.)and tAWD ≥ tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will
contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is
indeterminate.
EDO Mode Cycle
-60
Max.
-70
Max.
Symbol
Parameter
Units
Notes
Min.
10
25
72
10
2
Min.
12
30
84
10
2
tHCAS
tHPC
tHPRWC
tDOH
CAS Pulse Width (EDO Page Mode)
EDO Page Mode Cycle Time (Read/Write)
EDO Page Mode Read Modify Write Cycle Time
Data-out Hold Time from CAS
10K
—
10K
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
tWHZ
Output buffer Turn-Off Delay from WE
WE Pulse Width to Output Disable at CAS High
RAS Hold Time from CAS Precharge
Access Time from CAS Precharge
EDO Page Mode RAS Pulse Width
OE High Pulse Width
15
20
tWPZ
10
40
—
—
10
45
—
—
tCPRH
tCPA
tRASP
tOEP
—
—
40
45
1
60
10
10
125K
—
70
10
10
125K
—
tOEHC
OE High Hold Time from CAS High
—
—
1. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Refresh Cycle
-60
-70
Symbol
Parameter
Unit
Notes
Min
8
Max
—
Min
8
Max
—
CAS Hold Time
(CAS before RAS Refresh Cycle)
tCHR
tCSR
tWRP
tWRH
ns
ns
ns
ns
CAS Setup Time
(CAS before RAS Refresh Cycle)
10
15
8
—
—
—
10
15
8
—
—
—
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Refresh Cycle)
tRPC
tREF
RAS Precharge to CAS Hold Time
Refresh Period
3
—
3
—
ns
—
32
—
32
ms
1
1. 2048 refreshes are required every 32ms.
Presence Detect Read Cycle
-60
-70
Symbol
Parameter
Unit
Notes
Min
—
0
Max
Min
Max
tPD
PDE to Valid Presence Detect Data
10
10
—
0
10
10
ns
ns
1
2
tPDOFF
PDE Inactive to Presence Detects Inactive
1. Measured with the specified current load and 100pF.
2. tPDOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
CAS
tCAS
VIL
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
VIL
Address
Row
Column
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
VIL
NOTE 1
WE
OE
tAA
tOES
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tODD
VIH
VIL
DIN
Hi-Z
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Hi-Z
Valid Data Out
Hi-Z
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H”: or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Write Cycle (Early Write)
tRC
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tCRP
tRCD
tRSH
VIH
VIL
tCAS
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRH
tWRP
tWCS
tWCH
VIH
VIL
tWP
WE
OE
NOTE 1
VIH
VIL
tDS
tDH
VIH
VIL
DIN
Valid Data In
VOH
VOL
DOUT
Hi-Z
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Write Cycle (Late Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
CAS
tCAS
VIL
tRAD
tASR
tASC
tRAH
tCAH
VIH
Address
Row
tWRP
Column
VIL
tWRH
tRCS
tCWL
VIH
VIL
tWP
NOTE 1
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tODD
tDZO
tDS
tWRP
tDZC
VIH
VIL
DIN
Hi-Z
Valid Data In
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
t
OEH greater than or equal to tCWL
: “H” or “L”
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Read-Modify-Write-Cycle
tRWC
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tCRP
tRCD
tRSH
VIH
VIL
tCAS
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tCWD
tRWL
tCWL
tAWD
tWRH
tWRP
tRWD
tWP
VIH
VIL
NOTE 1
tAA
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
VIH
VIL
DIN
Hi-Z
tCAC
DIN
tODD
tCLZ
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
*
tRAC
t
OEH greater than or equal to tCWL
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Read Cycle
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
VIL
CAS
tCSH
tASC
tRAL
tCAH
tASR tRAH
tCAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tWP
tCAC
tCAC
tCPA
tCPA
tOFF
tOES
tOEA
tAA
tAA
VIH
VIL
OE
tOEZ
tRAC
tAA
tDOH
tDOH
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Read Cycle (OE Control)
tRP
tRASP
VIH
VIL
RAS
CAS
tCPRH
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
VIL
tCSH
tASC
tRAL
tCAH
tASR tRAH
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tCAC
tCAC
tCPA
tOFF
tCPA
tOES
tOEA
tAA
tAA
tOES
tOEHC
tOEP
tOES
tOEHC
tOEP
VIH
VIL
OE
tOEZ
tRAC
tAA
tOEA
tOEA
tCAC
tCLZ
tOEZ
tOEZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Read Cycle (WE Control)
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tRSH
tCP
tHCAS
tHCAS
tHCAS
VIH
CAS
VIL
tCSH
tRAL
tASR tRAH
tASC
tASC
tCAH
tASC
tCAH
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tAA
tAA
tRAD
tRCH
tRRH
tRCH
tRCS tRCH
tRCS
tWRH
tWRP
tRCS
tWPZ
tWPZ
VIH
VIL
WE
NOTE 1
tCAC
tOFF
tCAC
tCPA
tCPA
tOES
tOEA
VIH
VIL
OE
tOEZ
tRAC
tAA
tWHZ
tWHZ
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Early Write Cycle
tRP
tRASP
VIH
VIL
RAS
CAS
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
VIL
tRAD
tCSH
tASC
tRAL
tCAH
tCAH
tASR tRAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tRWL
tWCH
tWCH
tWRH
tWRP
tWCS
tWP
tWCS
tWP
tWCH
tWCS
VIH
VIL
tWP
WE
NOTE 1
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DIN
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
OE = Don’t care
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Late Write Cycle
tRP
tRASP
VIH
RAS
VIL
tHPC
tCRP
tRCD
tCP
tCP
tRSH
tHCAS
VIH
CAS
tHCAS
tHCAS
VIL
tRAD
tASR tRAH
tCSH
tASC
tCAH
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tCWL
tCWL
tWRH
tWRP
tRCS
tRCS
tRWL
tWP
tRCS
tWP
tWP
VIH
VIL
WE
NOTE 1
tOEH
tOEH
tOEH
VIH
VIL
OE
tODD
tDS
tDH
tODD
tDS
tDH
tODD
tDS
tDH
VIH
VIL
DIN
Hi-Z
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
EDO Page Mode Read Modify Write Cycle
tRP
tRASP
VIH
VIL
RAS
CAS
tHPRWC
tCRP
tCP
tCP
tRCD
VIH
VIL
tCAS
tCAS
tCAS
tCSH
tASC
tASC
tRAD
tRAH
tRAL
tASR
tASC
tCAH
tCAH
tCAH
VIH
VIL
Address
Column 1
Column 2
Column N
Row
tCWL
tRWL
tCPA
tAA
tCPA
tAA
tCWL
tRWD
tAWD
tCWD
tWRP
tWRH
tAWD
tCWD
tAWD
tCWD
tRCS
tRCS
tRCS
tWP
tWP
tWP
VIH
VIL
WE
OE
NOTE 1
tCAC
tRAC
tAA
tCAC
tCAC
tOEH
tOEH
tOEA
tOEH
tOEA
VIH
VIL
tOEA
tODD
tODD
tODD
tCLZ
tOEZ
DOUT
tDS
tOEZ
DOUT
tDS
tOEZ
tCLZ
tCLZ
VOH
VOL
DOUT
Hi-Z
Hi-Z
DOUT
tDS
tDH
DIN
tDH
DIN
tDH
DIN
VIH
VIL
DIN
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
RAS Only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCRP
tRPC
VIH
CAS
VIL
tRAH
tASR
VIH
Address
Row
VIL
VOH
Hi-Z
DOUT
VOL
: “H” or “L”
Note: WE, OE, DIN are “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
CAS Before RAS Refresh Cycle
tRC
tRAS
tRP
VIH
VIL
RAS
CAS
tRPC
tRPC
tCSR
tCSR
tCP
tCHR
VIH
VIL
tWRH
tWRH
tWRP
tWRP
VIH
VIL
WE
VIH
VIL
OE
tODD
tCDD
VOH
VOL
DIN
Hi-Z
tOEZ
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address is “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
CAS
VIL
tRAL
tWRH
tWRP
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
OE
tORD
tAA
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tODD
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Hidden Refresh Cycle (Write)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
VIL
RAS
CAS
tRSH
tCRP
tRCD
tCHR
VIH
VIL
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tWCS
tWCH
VIH
VIL
tWP
WE
OE
VIH
VIL
tDH
tDS
VIH
VIL
DIN
Valid Data
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Presence Detect Read Cycle
vIH
PDE
vIL
tPDOFF
*
tPD
vOH
PD1-PD8
vOL
Valid Presence Detect
*PD pins must be pulled high at next level of assembly
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Layout Drawing 3.3V/5.0V
133.35
5.25
131.35
5.171
127.35
5.014
Front
(2) 0
3.1877
.1255
6.35
.250
1.27 PITCH
.050
43.18 (3.3V), 42.18 (5.0V)
1.70 (3.3V), 1.661 (5.0V)
1.00 WIDTH
.039
66.68 (3.3V), 65.68 (5.0V)
2.63 (3.3V), 2.586 (5.0V)
SEE DETAIL A/B
Detail B
Detail A
Side
3.3V Version
5.0V Version
4.00
.157 MAX.
SCALE: 4/1
R 1.00
.0393
R 1.00
.0393
2.0
.078
2.0
.078
+
+
_
_
1.27
.050
0.10
.004
Millimeters
Inches
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M2735H
IBM11M2735HB
2M x 72 DRAM MODULE
Revision Log
Rev
Contents of Modification
8/95
Initial Release.
Updated ordering information
Improved power dissipation
Improved DC electrical characteristics: ICC1, ICC3, ICC4, ICC6
Increased timings: tOES, tORD
5/96
Improved timings: tCAH, tCDD, tOEZ, tOFF
The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
Hidden Refresh Cycle (Read) timing diagram was changed to show data being turned off with RAS not CAS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4199
SA14-4615-02
Revised 5/96
Discontinued (9/98 - last order; 3/99 - last ship)
International Business Machines Corp.1996
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.
SA14-4615-02
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