IBM39ENV420 [IBM]

Consumer Circuit, CMOS, PBGA420, 35 X 35 MM, HPBGA-420;


型号：	IBM39ENV420
厂家：	IBM
描述：	Consumer Circuit, CMOS, PBGA420, 35 X 35 MM, HPBGA-420 商用集成电路
文件：	总6页 (文件大小：20K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IBM39eNV422

IBM39eNV420

Summary Data Sheet

Features

eNV SD Digital Video Encoders

Profiles and standards

• Supports MPEG-2 or ATSC user data insertion

• Minimum encoding latency

• Supports up to +/- 200H and +/- 128V search

range

• 4:2:2 Proﬁle at Main Level

• Main Proﬁle at High Level

• Main proﬁle at Main Level

• Simple Proﬁle at Main Level

• Programmable quantization tables

Image resolutions

Output

• Up to 720x512x30 Fps NTSC

• Up to 720x608x25 Fps PAL

• Selectable ES or PES output format

• Produces up to 50 Mbps

Input image pre-processing

• Horizontal noise ﬁlter

• Vertical noise ﬁlter

Memory

• Single SDRAM memory interface

• Requires a minimum 8 MB of 125 MHz SDRAM

• Supports 2 bank and 4 bank memory chips

• Temporal ﬁlter

• Supports horizontal image scaling

• Supports 4:2:2 to 4:2:0 chroma conversion

Technology

• 3.3V and 2.5V power supplies

• 1.6W nominal power dissipation

• IBM CMOS SA-12E (0.18µm) process technol-

ogy

Compression Options

• 4:2:2 or 4:2:0 output chroma format

• Supports ﬁeld or frame encoding

• Variable GOP structure

• 35 mm HPBGA package

• External reference rate control

• Supports dynamically variable parameters

Description

The IBM eNV SD video encoder chip offers flexibility

and provides a compact solution for your SD appli-

cation. The chip supports both MPEG-1 and MPEG-

2 real-time encoding. It handles multiple profiles and

levels including 4:2:2 Profile at Main Level and can

encode picture resolutions up to 720x512 and

720x608 in NTSC and PAL, respectively.

The chip outputs up to 50 Mbps with superior image

quality, making it desirable for high quality, high bit

rate solutions.

The programmable on-chip noise reduction filter

provides an effective solution to achieve the best

image quality at lower bit rates, making a highly

desirable choice for broadcast and distribution appli-

cations requiring VBR and statistical-multiplexing.

The architecture offers a wide range of capability to

encode SD images. The chip can compress images

into either MPEG-2 4:2:2 profile for professional

applications or Main profile for broadcast applica-

tions. It can deliver 4:2:2 or 4:2:0 chroma output for-

mat. The user can program a search range of up to

+/-200H and +/-128V based on their application

needs.

Dynamic changing of encoding parameters such as

GOP structure, bit rate control, and search range in

real time provides added flexibility to optimize pic-

ture quality at the available bandwidth.

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Features

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Block Diagram

External Memory

SDRAM Control

Pixel

Interface

Pixel

Data

DCT/IDCT

Q/IQ

Phase

Lock

Loop

27 MHz

VLE

Output

Interface

Host

Interface

Processor

Bit Stream

External

Processor

Fig. 1. eNV Block Diagram

Pixel Interface

The Pixel Interface supports user selectable CCIR 656 (8-bit) or CCIR 601(16-bit) operation. A 27 MHz pixel

clock is used for CCIR 656 format. It also supports a clock rate of up to 13.5 Mhz clock for the CCIR 601 (16-

bit) mode. This interface is designed to accept pixel data upon completion of the initialization process after

power-on reset.

Phase Lock Loop

The Phase Lock Loop (PLL) takes as input the 27 MHz reference clock, divides it into the system clock rate,

and provides synchronized clock pulses to the entire chip.

Host Interface

Connected to an external processor, the Host Interface communicates user input encoding parameters to the

system through a 16-bit data bus and 8-bit address bus. Data is entered via register writes or via dedicated

Picture and GOP stacks. The Host Interface also offers a means of inputting certain commands to the

encoder’s processor by mailbox, and the reading of select system registers for status and checking.

Block Diagram

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eNV SD Digital Video Encoders

Processor

A dedicated RISC processor programmed to optimize encoding across a broad range of parameters. The

processor acts as an engine for rate control, motion estimation, and motion compensation calculations.

Microcode-based field upgrades are available to the customer and are a key feature of the eNV SD video

encoder.

SDRAM Control

A single memory interface designed to support 125MHz, 32-bit SDRAM. The encoder requires a minimum of

8MB of external memory for full IPB encoding.

Motion Estimation (ME)

A hierarchical motion estimation and compensation unit capable of searching up to +/-200 horizontal pixels

and +/-128 vertical pixels. The ME unit performs past reference searches in the case of P and B pictures, and

future reference and bi-directional searches in the case of B pictures. Adaptive frame/field motion estimation

with interpolation for 1/2 pixel refinement is performed on a per macroblock basis.

DCT/IDCT/Q/IQ/VLE

Dedicated hardware function for coding the bitstream and creating reconstructed reference data for motion

estimation and compensation. The quantizer (Q) and inverse quantizer (IQ) units are capable of holding up to

eight 8x8 user quantization tables (2 intra luma, 2 non-intra luma, 2 intra chroma, 2 non-intra chroma).

Output Interface

Designed for programmable output modes and speeds up to 50Mb/sec. Outputs the bitstream in either ES or

PES format, with encoding statistics available at the output interface.

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Environmental and Electrical Speciﬁcations

The eNV SD chip is designed to operate from 0 to 70 degrees C ambient environment.

Table 1. Operating Range/Ratings of eNV SD

Parameter

Vdd (supply voltage)(maximum)

Value

2.625

2.5 ± 5%

3.465

3.30 ± 5%

Units

Volts

MHz

Vdd (Nominal supply voltage)

Vdd2 (supply voltage)(maximum)

Vdd2 (Nominal supply voltage)

System Clock

0 - 70

0 - 100

-55 to 125

0.5

˚C

Ambient temperature range (operating conditions)

Operating temperature range (Chip Tj)

Storage temperature range

˚C

meters/sec

Watts

Air Flow (minimum)

1.6

Power Dissipation (nominal)

Power Dissipation (maximum)

1.8

Note: The allowable ambient temperature range speciﬁed is based on the module mounted to a 2-signal/2-power plane card

with the speciﬁed airﬂow on both sides of card, vertical orientation.

The drivers and receivers are compatible with 3.3 Volt-tolerant technologies.

Table 2. Physical Information of SD PBGA Package

Parameter

Value

Unit

Module dimension

Module height

Ball pitch

35x35

1.27

0.75

Ball diameter

Environmental and Electrical Specifications

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eNV SD Digital Video Encoders

Printed in the United States of America September, 2001

The following are trademarks of International Business Machines Corporation in the United States, or other countries, or

both:

IBM

IBM Logo

Other company, product, and service names may be trademarks or service marks of others.

All information contained in this document is subject to change without notice. The products described in this document

are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death

to persons. The information contained in this document does not affect or change IBM's product specifications or warran-

ties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property

rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is pre-

sented as an illustration. The results obtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be

liable for damages arising directly or indirectly from any use of the information contained in this document.

IBM Microelectronics Division

1580 Route 52, Bldg. 504

Hopewell Junction, NY 12533-6351

The IBM home page can be found at http://www.ibm.com

The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com

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Revision Log

Rev. Date

Contents of Modiﬁcation

Sept. 04, 2001

Sept. 06, 2001

Sept. 13, 2001

Initial Release (00)

Minor corrections to text, added Figure and Table numbers (01)

Minor changes to text requested by IBM attorney (02)

Revision Log

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