IBM39STB03411PBB06C_技术文档

IBM39STB032xx

IBM39STB034xx

Preliminary STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Features

Overall

PowerPC 405 Host Processor: PPC405B3 CPU

• 16KB Instruction, 8KB Data caches

• Universal Interrupt Controller

• High-End Set-Top Box technology

• Four major subsystems integrated with IBM

on-chip CoreConnect structure.

• Maximum MIPS for OS and application tasks

• Simpliﬁed driver and software development

• Scalable, ﬂexible, and extendible

• 108 MHz/150 MIPS and 162 MHz/225 MIPS

versions available

Memory Subsystem

• DMA Controller

• Cross-Bar Switch

• External Bus Interface Unit (EBIU)

• IDE interface

• Two SDRAM Controllers

• 3.3 V and 2.5 V power supplies

• IBM CMOS SA-12E (0.25 µm) process

technology

Peripheral Subsystem

• General Purpose Timers (GPTs)

• Pulse Width Modulators

• 1284 Parallel Port

• 304-pin PBGA package

MPEG-2 Digital Audio/Video Subsystem

• MPEG-2 Video Decoder

• MPEG-2 Audio Decoder

• Two Smart Card controllers

2

• Two I C Interfaces

• 16550 Serial Communications Port

• Infrared Serial Communications Port

• General Purpose Input/Output (GPIO)

• Serial Controller Port

• MPEG-2 Transport/DVB Descrambler

• Dolby Digital Audio support on selected parts

• Macrovision Copy Protection on selected parts

• Display Controller

• Digital Encoder (DENC) with six outputs

• Anti-Flicker Filter

1

• Modem Serial Interface/Digital Audio Input

Description

IBM STB03xxx Digital Set-Top Box Integrated Con-

troller family are highly integrated silicon devices

specifically developed for digital set-top box (STB)

applications using industry-leading IBM CMOS SA-

12E (0.25 µm) process technology.

Architecturally, the devices consist of four sub-

systems interconnected and tuned using CoreCon-

nect, the IBM multiple-bus, on-chip interconnect

structure:

1. PowerPC host processor

2. Digital audio/video

The STB03xxx is part of the second generation of

IBM products for digital STB applications. PowerPC

processing and peripheral I/O architecture provide a

high level of performance and functionality when

used in audio and video subsystems. The resulting

STB technology is full-functioned and easy to use.

3. Memory interface

4. Peripheral

These high performance subsystems are suited to

advanced interactive STBs with demanding soft-

ware requirements including web browsers and

Java .

The STB03xxx minimizes host processor interven-

tion to maximize MIPS for operating system and

application tasks. Most of the features required in

the back end of typical midrange and high-end

STBs are integrated. Driver and software develop-

ment is facilitated while preserving scaleability, flexi-

bility, and extendibility.

1. This implementation has not yet completed the evaluation

process by Dolby Laboratories and is offered subject to

obtaining approval. A Dolby Digital Audio license is required

from Dolby Laboratories.

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Features

Page 1 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Ordering Information

Part Number

IBM39STB03200PBB09C

IBM39STB03201PBB09C

IBM39STB03210PBB09C

IBM39STB03211PBB09C

IBM39STB03400PBB06C

IBM39STB03401PBB06C

IBM39STB03410PBB06C

IBM39STB03411PBB06C

Performance (est.)

150 MIPS

Clock Speed

108 MHz

Audio

Copy Protection

None

Macrovision

None

MPEG

2

1

MPEG/Dolby Digital

Macrovision

None

MPEG

Macrovision

None

225 MIPS

162 MHz

1

MPEG/Dolby Digital

Macrovision

1. These parts include Dolby Digital enabling software and require the user to obtain a license from Dolby Laboratories Licensing

Corporation. Please see “Dolby Digital Licensing” on page 3.

2. These parts support Macrovision Copy Protection and require that a license be in effect between the purchaser and Macrovision

Corporation. Please see “Macrovision Licensing” on page 3.

Conventions and Notation

Throughout this document, standard IBM notation is used, meaning that bits and bytes are numbered in

ascending order from left to right. Thus, for a 4-byte word, bit 0 is the most significant bit and bit 31 is the least

significant bit.

Overbars, e.g. TxEnb, designate signals that are active low.

Numeric notation is as follows:

Hexadecimal values are in single quotes and preceded by "x" or "X." For example: x’0B00’.

Binary values are spelled out (zero and one) or appear in single quotes and preceded by a "b."

For example: b‘10101’.

Settings of a bit or field are binary numbers but are often displayed in tabular form without quotes or the pre-

ceding "b."

For example:

00 : 30 frames per second

01 : 15 frames per second

11 : 10 frames per second

Ordering Information

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IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Licensing Requirements

Dolby Digital Licensing

Dolby Digital audio enabling software is provided with the IBM39STB0321x and IBM39STB0341x products.

Dolby is a trademark of the Dolby Laboratories. Supply of this implementation of Dolby Technology does not

convey a license or imply a right under any patent, or any other Industrial or Intellectual Property Right of

Dolby Laboratories, to use this implementation in any end-user or ready-to-use final product. Companies

planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Cor-

poration before designing such products. Additional per-chip royalties may be required and are to be paid by

the purchaser to Dolby Laboratories, Inc. Details of the OEM Dolby Digital license may be obtained by writing

to:

Dolby Laboratories Inc.

Dolby Laboratories Licensing Corporation

Attn: Intellectual Property Manager

100 Potrero Avenue

San Francisco, CA 94103-4813

Macrovision Licensing

Macrovision Copy Protection is supported in the IBM39STB032x1 and IBM39STB034x1 products. These

devices are protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual

property rights. The use of Macrovision’s Copy Protection technology in the device must be authorized by

Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized

in writing by Macrovision.

Reverse engineering or disassembly is prohibited. A valid Macrovision license must be in effect between the

STB03xx1 purchaser and Macrovision Corporation. Additional per-chip royalties may be required and are to

be paid by the purchaser to Macrovision Corporation.

Macrovision Corporation

1341 Orleans Avenue

Sunnyvale, CA 94089

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Licensing Requirements

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IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Architecture and Subsystem Information

Block Diagram

Interrupts

OPB Bus

SRAM

GPT

PWM

JTAG

TRACE

IDE

IEEE

1284

DMA

Controller

PPC405B3

CPU

UIC

PER.

DEVICE

FLASH

ROM

Smart

Card0

16K-I

8K-D

Cache

EBIU

Smart

Card1

OPB

Bridge

PLB0

PLB1

SDRAM0

Controller

2

SDRAM

I C0

SDRAM1

Controller

Transport

DVB

2

I C1

Descrambler

Serial0/

16550

NIM

Descrambler

Serial1/

Infrared

GPIO

Serial

Control

Port

Audio

Decoder

Video

Decoder

Audio

D/A

OSD

Modem

Interface

Digital

IEC-60958

Encoder

DAC

Ext

Digital

Encoder

2D/3D

Graphics

Architecture and Subsystem Information

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IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

PowerPC 405B3 Host Processor Subsystem

The PowerPC 405B3 (PPC405B3) subsystem handles all system initialization and control and also provides

power and flexibility for product differentiation.

PPC405B3 Subsystem

PPC405B3 Processor

Interfaces

CPU

Interrupt Controller Interface

UIC

Clocks

Power Mgmt

Timers: PIT, FIT, 64-bit base

Multiplier/Divider

DCRs

Interrupts

JTAG (See Note)

RISC Execution Unit

Core Clocking

Thirty-two 32-bit GPRs

MMU

Data

Cache

Controls

Instruction

Cache

Controls

16KB

I-cache

8KB

D-cache

Array

PLB Master

Note: The JTAG interface is used for development.

PowerPC 405B3 CPU

The PPC405B3 provides high performance and low power consumption. The CPU executes at sustained

speeds of greater than one cycle per instruction at 108 or 162 MHz. Interrupt latency is three cycles, the best

time for critical interrupts.

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Architecture and Subsystem Information

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IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

On-chip instruction is compatible with PowerPC User Instruction Set Architecture, with branch prediction exe-

cution for most instructions. There are 32 x 32 bit general purpose registers. Instruction and data cache

arrays improve system throughput. The CPU has a separate two-way set-associative 16KB instruction cache

and an 8KB write-back/write-through data cache. Multiply and divide instructions are performed in hardware

and are not emulated in software.

Universal Interrupt Controller

The Universal Interrupt Controller (UIC) provides all necessary control, status, and communication functions

between all sources of interrupts and the PPC405B3. The UIC combines STB03xxx interrupts and presents

them to the PPC405B3’s critical or non-critical inputs. All interrupts can be programmed to generate either

critical or non-critical output. Interrupts can be level- or edge-sensitive and interrupt polarity is programmable.

An optional read-only vector is used to reduce critical interrupt servicing latency. This vector is generated by

combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and

a vector base address register. A configurable priority control bit determines whether the least significant or

most significant bit in the status register has the highest priority.

Clock and Power Management

For power-saving purposes, a Clock and Power Management (CPM) input is used to shut down clocks and

device functions. A reset is required to activate a unit.

Memory Interface Subsystem

The memory interface subsystem provides the system memory controller interface for SRAM, FLASH Mem-

ory, ROM, and SDRAM. It also provides the Direct Memory Access (DMA) interfaces for these memories. A

key advantage of the memory interface is its ability to gain concurrent access (one function to SDRAM0 and

one function to SDRAM1) and mutual access (a given function can access either port).

Memory Subsystem

FLASH,

DMA

EBIU

ROM, etc.

SDRAM

PLB0

PLB1

EBIU

SDRAM0

SDRAM

SDRAM1

Direct Memory Access Controller

The four-channel DMA controller is a processor local bus master that allows faster data transfer between

memory and peripherals than with program control. The controller supports memory-to-memory, peripheral-

to-memory, and memory-to-peripheral transfers. The DMA controller allows the PPC405B3 processor to exe-

cute instructions with no bus contention when the PPC405B3 is executing from cache. DMA is useful when

Architecture and Subsystem Information

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IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

the overhead associated with the controller setup is minimal compared to the time it would take to move data

using program control load and store instructions.

Each DMA channel has an independent set of registers for data transfer. The registers store data for control,

source address, destination address, and transfer count. Each channel also supports chained DMA opera-

tions, therefore every channel also includes a chained count register in which case source address registers

function as chained address registers. All DMA channels report their status to the DMA execution unit.

The DMA controller also supports:

• Internal DMA channels for 1284 parallel port, Smart Card interface, 16550 serial communications control-

ler, infrared communications controller, etc.

• 16- and 32-bit peripherals (on-chip peripheral bus and external)

• 32-bit addressing

• Address increment or decrement

• Internal data buffering capability

• Memory-mapped peripherals

Processor Local Bus

The Processor Local Bus (PLB) interfaces directly with the PPC405B3 and the other major subsystems (see

“Block Diagram,” on page 4). The STB03xxx uses three PLBs to provide high bandwidth between the function

masters and the external memory interfaces for ROM, Flash, and SDRAM, etc. The STB03xxx PLB architec-

ture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces.

External Bus Interface Unit

The External Bus Interface Unit (EBIU) expands the local bus to transfer data between the PLB and a wide

range of memory and peripheral devices attached to the external bus (see the following list). The EBIU can

control up to eight devices or banks or regions of FLASH memory (128 MB), and a low latency maximizes

system performance.

The EBIU supports:

• A direct connect SRAM/ROM/PIA interface for

- up to eight SRAM/ROM/PIA banks with programmable address select

- programmable or device-paced wait states

- burst mode (BME) and single-cycle transfers

• 16- and 32-bit byte addressable bus width

• Programmable target word ﬁrst or sequential cache line ﬁlls

• IDE interface

• supports ATA-3 Mode 4 register and PIO transfers

• supports Mode 2 Multiword DMA transfers (see ANSI X3.298-1997, AT Attachment-3 Interface (ATA-

3))

• DVB Common Interface Support

• External bus master with support for device master and master/slave

• Common bank-speciﬁc programmability

• Device-paced ready input

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Architecture and Subsystem Information

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IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

SDRAM Controller

The SDRAM Controller transfers data between the PLB and up to two SDRAM memory banks attached to the

external bus. The Controller implements address and data pipelining and supports 16Mb and 64Mb SDRAMS

concurrently. It also provides the following:

• Direct-connect SDRAM interface

• High bandwidth with a narrow 16-bit interface

• Page interleaving

• Programmable address select

• Programmable rates for automatic SDRAM refresh

• Software-initiated and self refresh modes for power savings

Crossbar Switch

The PLB Crossbar Switch (CBS) creates a flat memory model and implements Unified Memory Architecture

(UMA), which connects multiple PLB master buses to multiple PLB slave buses, thus allowing two sets of

PLB buses to intercommunicate. Processor, transport, and the audio and video decoders can access mem-

ory through either memory controller.

Digital Audio/Video Subsystem

The MPEG-2 Digital Audio/Video subsystem provides fully-synchronized playback of digital video and audio

programs, with a minimum of interaction from the PPC405B3 processor.

Audio PLL

DVB Descrambler

MPEG-2 Transport

MPEG-2

Dolby Digital

Audio Decoder

to Audio D/A and IEC60958

MPEG-2

Video

Decoder

OSD

DENC

PLB0

MPEG-2 Video Decoder with OSD

The MPEG-2 video decoder provides decompression, decoding, and synchronized playback of digital video

streams with a minimum of host support. It produces interlaced video output and can support MPEG-2 com-

pressed data streams up to an average rate of 15 Mbps. The video decoder is also backward compatible to

support the ISO/IEC International Standard 11172-2 (11/93) (also called “MPEG-1 Standard”). It supports the

ISO/IEC 13818-2 Main Profile at Main Level.

Architecture and Subsystem Information

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IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

The decoder also supports MPEG-2 MP@ML compliance with 2MB memory. Only 2MB of memory are

needed to decode full CCIR601 resolution NTSC and PAL encoded MPEG-2 bitstreams. It performs real-time

decoding of all resolutions in 16-pixel multiples, up to and including 720x480x30 or 720x576x25. Horizontal

and vertical ﬁlters deliver high-quality video. Chrominance ﬁltering and up-sampling to provide CCIR601 4:2:2

video output. Pan and scan are supported in 1/16 pel accuracy for 16:9 source material. Video rates range

from 1.5 Mbps to 15 Mbps (higher in bursts).

The MPEG-2 video decoder supports the European DVB standard and accepts Packetized Elementary or

Elementary MPEG-2 streams. It uses Packetized Elementary Stream (PES) video decoding to extract the

Presentation Time Stamp (PTS), and handles user data and other PES layer bit fields through memory

access from the PPC405B3. Input can be from transport or directly from system memory. Outputs are pro-

vided for video-only and for video-with-OSD.

The decoder can insert data in the vertical blanking interval (VBI) with VBI Output Support. It supports decod-

ing of still or fixed images and display of scaled video images. It also features:

• Letterbox format display

• Selectable anti-ﬂicker ﬁltering

• Output interface ﬂexibility (programmable controls)

• Composite blanking and Field ID signals

• V-sync and H-sync signals

• CCIR656 master and slave modes

• Programmable signal polarity

• Sophisticated error concealment

• 3:2 pull-down support.

• Closed caption, teletext, or mixed (VPS)

• (1/4x, 1/2x, 2x) and three graphic planes

• Automated video channel change and time-base change features

• Blending of external graphics.

A multi-plane on-screen display (OSD) uses bitmap data in memory to be merged with or displayed in place

of the motion video data. Three OSD planes (the cursor, graphics and image planes) are provided for

increased display flexibility. The OSD includes:

• Programmable background color

• Multi-region link list graphic and image plane OSD with a color table for each region

• Programmable bitmap resolution on a region-by-region basis

• 64 x 64 pixel, 16-color cursor plane with blending controls

• Overlay and video blending of graphic plane

• Enhanced color mode for 24-bit color (YUV) in Direct Color and CLUT modes with 8-bit alpha blending

• Video shading in graphic plane OSD area

• OSD control output for external multiplexer (picture-in-picture support)

• Tiling capability in image and graphic planes

• Scrolling of image and graphic planes

• Horizontal scaling of image plane bitmaps

• Animation support

• 16 MB OSD addressing range to support more and larger bitmaps.

MPEG-2 Transport and DVB Descrambler

The MPEG-2 transport demultiplexer provides ISO / IEC 13818-1 MPEG-2 transport system layer demulti-

plexing. Its integrated digital video broadcasting (DVB) descrambler complies with DVB system layer require-

ments and may be turned off for non-DVB applications. Peak input rates are 100-Mbps (parallel) or 60-Mbps

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Architecture and Subsystem Information

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IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

(serial), or 88-Mbps (parallel) or 60-Mbps (serial) with the optional descrambler. Packet Identifier (PID) filter-

ing is based on 32 programmable entries with detection and notification of errors and lost packets. Hardware-

based clock recovery on program clock references (PCRs) reduces processor load by:

- Calculating clock difference between PCR and System Time Clock (STC)

- Modulating output to drive an external VCXO

- Using an optional internal clock-recovery algorithm based on clock difference

Transport and descrambler features include:

• Internal DVB (1.0 or 1.1) descrambler, including ﬁltering and storage of eight control word pairs

• Auxiliary output port for real-time data transfers:

- 8-bit mode at 1X, 1/2X, 1/3X, 1/4X and 1/8X of the system clock speed

• Table section ﬁltering:

- 64 separate 4-byte ﬁlter blocks with bit-level masking with full match/not match capability

- Multiple ﬁlters can be linked to extend ﬁltering depth in 4-byte increments

- Multiple ﬁlters per PID

- Filters program-speciﬁc information (PSI), service information (SI), private tables

- Handles multiple sections per packet and sections that span packets

- Optional CRC checking of section data

• Selective routing of some or all packet data to system memory:

- Based on 32 separate queues (one per PID)

- Routing entire packets, payloads, adaptation ﬁelds, table sections (after ﬁltering) and private data

• Direct transfer of audio / video (PES) data to decoders

• Simpliﬁed channel changes, time-base changes and error ﬂagging / concealment through direct commu-

nication with decoders

• Interface for a Transport Assist Processor to provide additional processing:

- Extended ﬁltering / parsing of tables, private data, adaptation ﬁelds, and PES headers

- Ability to selectively route alternative data ﬁelds to system memory

MPEG-2/Dolby Digital Audio Decoder

The Audio Decoder receives and decodes either ES (Elementary Stream) or PES (Packetized Elementary

Stream) audio data. The audio compute engine is a generic DSP processor that decodes MPEG, Dolby Digi-

1

tal , or 16-, 18- or 20-bit unformatted Pulse Code Modulation (PCM) audio data via individual software pro-

grams.

The host processor downloads each program load to the Audio Decoder following initialization. The Audio

Decoder generates up to two channels of decoded PCM for MPEG and PCM audio playback output. It pro-

vides 2-channel MPEG audio output and 6-channel Dolby Digital down-mixed to either two channels or six

channels of Dolby Digital output. Unpacketized PCM (UPCM) plays back at sampling frequencies of 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz, along with quantization sample width selections of 16-, 18-

or 20-bit input and 16 or 20-bit output.

The Audio Decoder:

• Decodes Dolby Digital, described in the ATSC Speciﬁcation “Digital Audio Compression” (A/52).

• Decodes MPEG-1 and MPEG-2 audio (Layers I and II) and 2-channel output, including single channel,

stereo, joint stereo, and dual channel modes.

1. This feature available only on STB03x1x, Dolby Digital license required

Architecture and Subsystem Information

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IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

• Performs MPEG-1 and MPEG-2 PES audio parsing, and also accepts audio elementary streams. Parses

and stores ancillary data into external memory for later use by the host processor.

• Supports 16-kHz, 22.05-kHz, 24-kHz, 32-kHz, 44.1-kHz, and 48-kHz audio sampling frequencies.

• Supports audio/video synchronization through PTS/STC comparison with each audio frame.

• Supports Karaoke Mode for Dolby Digital and PCM playback.

• Supports an encoded audio bit rate up to 640 Kbps. This bit rate only pertains to encoded bitstream data.

• Includes Audio Clip Mode for PES, ES, and PCM formats with byte address granularity and 2MB maxi-

mum per clip buffer.

• Allows PCM Mixing with primary audio stream input including sample rate conversion. PCM audio data

supplied via secondary clip mode feature.

• Supports expandable rate buffer size selectable from 4K to 64K (in 4K increments).

• Uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity).

• Has a re-locatable PTS Value and Ancillary data region, using a programmable base register with 128-

byte location granularity.

• Uses a locatable Audio Temporary Data and Decoded Audio Data Bank region (programmable base reg-

ister with 128-byte location granularity with additional offset register).

• Includes 256x and 512x DAC sampling clock frequency conﬁgurations.

• Has a programmable stream ID register with corresponding 8-bit enable ﬁeld.

• Provides three PCM output formats in 16- or 20-bit precision:

2

- I S

- Left-justiﬁed

- Right-justiﬁed

• Performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchroni-

zation or detection of CRC errors.

• Performs MPEG error checking using frame size calculation for each frame.

• Provides de-emphasis pins that interface to external de-emphasis circuitry.

• Provides Dolby Surround Mode (dsurmod) pins that interface to external surround mode circuitry.

• Provides a programmable interface that supports the following:

- Play, stop, and mute

- Rate buffer purge to support channel and mode changes

- Provides a compressed buffer full indicator

- Synchronization enable/disable for PTS-STC comparison

• Includes SPDIF meeting IEC61937 and IEC60958 specs.

• Supports enhanced IEC61937 S/P DIF Channel Status bit by including 16 SPDIF Channel Status bits,

with host control over most of the bits.

• Inserts host-controlled validity bit into SPDIF sub-frame via DCR register.

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Architecture and Subsystem Information

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IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

• Performs audio attenuation in 64 steps, with smooth transitions between steps.

• Provides tone generation with up to 128 generated tones at 31 different durations with seven levels of

attenuation via processor command.

• Supports automated channel change.

• Supports automated time base change.

1

NTSC/PAL Digital Encoder Unit with Macrovision Copy Protection

The multi-standard Digital Encoder converts digital audio/video data into analog National Television System

Committee (NTSC) or Phase Alternate Line (PAL) data output formats (see Macrovision Licensing on page

3). It provides up to six concurrent analog video outputs, including S-Video, composite video, YPbPr, and

RGB. The encoder is compatible with SCART connectors, with support for Macrovision Copy Protection Revi-

sion 7. Analog outputs are driven by 10-bit D/A converters, operating at 27 MHz. The outputs drive standard

video levels into 75-Ω loads. It supports closed caption, teletext insertion, and Line 23 WSS (Wide-screen

Signaling) per ITU-R BT.1119. There is a switchable pedestal with gain compensation. Playback of synchro-

nized video data can be locked to the incoming composite video stream.

Additional Interfaces

External Graphics and Video (EGV) Port

External Graphics and Video (EGV) ports provide flexibility for interfacing external graphics and video compo-

nents. When the EGV is used as an output, its signals may be routed to an external graphics device or

DENC. When used as an input, either the internal OSD graphics can be replaced with data from an external

graphics device, or external digital video data (from an analog signal converted to digital via DSMD, for exam-

ple) could replace the internally decoded MPEG video. In the latter case, the external digital video can be

merged/blended with the internal OSD graphics.

1. This feature is available only on STB03xx1, Macrovision license required.

Architecture and Subsystem Information

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IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Peripheral Subsystem

IBM STB03xxx

Peripheral Subsystem

GPT / PWM

IEEE 1284

SmartCard (2)

IIC (2)

OPB

Bridge

16550 Serial Com

Infrared Serial Com

GPIO

Serial Control Port

Modem Interface

General Purpose Timer

The General Purpose Timer (GPT) is an on-chip peripheral bus (OPB) function that provides a separate time

base counter and additional system timers beyond those defined in the PPC405B3.

Three Inter-Character (IC) time-out timers are also implemented in this functional unit in the GPT. These tim-

ers receive the count signal inputs from other units they are timing. Each timer is a 10-bit down counter

loaded with a programmable value (TOUT) upon the active edge of the count signal input. Once loaded, the

IC timer counts down TOUT number of TCLK cycles until it reaches zero (that is, when the IC timer has

expired). When a timer expires, it sets its corresponding bit in the IC interrupt status register.

There is a separate time base inside the GPT, distinct from the time base within the PPC405B3. Two event

timers capture unique input events and there are two compare timers with unique outputs. Separately config-

urable and programmable synchronization controls edge detection and output levels. There are two reset

inputs, one for the entire GPT unit, and one for the time base.

Pulse Width Modulation

The pulse width modulation (PWM) function produces two square wave outputs with a variable duty cycle

under program control. The duty cycle varies from 100 percent to zero percent in steps of 1/256. There is a

control register with two bits for each PWM. This register controls the active status of the PWM, and deter-

mines what its inactive output level should be. When the PWM control register is set to disable a PWM, the 8-

bit period counter will be inactive to minimize power.

The pulse width modulation portion of the GPT contains two identical blocks, each containing an 8-bit pro-

grammable and reloadable down counter and control logic. A time-base generator that is a free-running

counter (TCLK based) generates the frequency of the pulse-width modulated output.

STB03_sds_041800.fm.01

April 18, 2000

Architecture and Subsystem Information

Page 13 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

IEEE 1284 Parallel Port

The IEEE 1284 Parallel Port is implemented as either the host side or peripheral side of the parallel port data

1

2

bus. The parallel port bidirectional interface supports IEEE Std. 1284 extended capability port (ECP) , byte ,

3

4

nibble , and compatibility modes of operation. The parallel port also monitors IEEE Std. 1284 negotiation

mode events, which allows the host to determine the capabilities of an attached peripheral and to set the

interface into one of the four operational modes. The parallel port supports byte-wide FIFO but does not sup-

port Enhanced Parallel Port (EPP) mode. Two Direct Memory Access (DMA) channels for transmit and

receive allow independent data transfers from other peripherals. The IEEE 1284 Parallel Port is compatible

with existing parallel port hosts, and an Inter-Character Time-out Facility provides support with the

GPT/PWM.

Inter-Integrated Circuit (IIC) Units

Two unique IIC units are used to provide two independent IIC interfaces and provide a simple to use, highly

programmable interface between the OPB and the industry standard IIC serial bus. They provide full man-

2

agement of all IIC bus protocols, compliant with Phillips Semiconductors I C Speciﬁcation, dated 1995, and

support a ﬁxed V IIC interface. These IICs can be programmed to operate as master, as slave, or as both

DD

master and slave on the IIC interface. In addition to sophisticated IIC bus protocol management, the IICs pro-

vide full data buffering between the OPB and the IIC bus.

The IIC units offer 5 V tolerant I/O for both 100- and 400-kHz operation with 8-bit data transfers and 7-bit and

10-bit address decode/generation. There is one programmable interrupt request signal, two independent 4 x

1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers.

Smart Card Interface Units

The Smart Card Interface Units handle communications between an Integrated Circuit Card and the host

CPU. These 5 V tolerant I/O devices have a software-based control structure and are designed for use with

asynchronous transmissions. They feature hardware activation/deactivation and reset with software overrides

and byte-wide FIFO support. They are compatible with ISO/IEC 7816-3 and support T0 and T1 protocols. The

Interface Units support 2-channel DMA with 8-bit memory-mapped registers and hardware error checking. An

Inter-Character Time-out Facility provides timing support from the GPT/PWM.

16550 Serial Communication Controller

The 16550 Serial Communication Controller is a universal asynchronous receiver/transmitter (UART) with

FIFOs, and is compatible with the 16550 part numbers manufactured by National Semiconductor (NS) Corpo-

ration. It is also compatible with National Semiconductor 16450 (non-FIFO version). Serial interface charac-

teristics are fully programmable with complete modem control functions and status reporting capability. The

controller supports:

• 5-, 6-, 7-, or 8-bit characters

• Even, odd, or no parity bit generation and detection

• 1-, 1.5-, or 2-stop-bit generation

• Variable baud rate and a programmable baud rate generator

1. ECP refers to the extended capability port. An asynchronous, byte-wide, bidirectional channel.

2. Byte refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host.

3. Nibble refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host.

4. Compatibility refers to an asynchronous, byte-wide forward (host-to-peripheral) channel.

Architecture and Subsystem Information

Page 14 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

There is also support for two DMA channels with a 16-byte FIFO for transmit/receive path. Internal loopback

is provided for diagnostics and an Inter-Character Timeout Facility provides timing support from the

GPT/PWM.

Infrared Serial Communications Controller

In addition to standard UART functions, the Serial/Infrared Communications Controller can use an alternate

mode (IrDA mode) to transfer and receive infrared characters. IrDA transmissions are specified by the Infra-

red Data Association (IrDA) Specification 1.1. IrDA mode supports RS-232 and infrared communications up

to 1.152 Mbps with automatic insertion/removal of standard ASYNC communication bits. The controller

includes:

• A programmable baud rate generator

• Individual enable for receiver and transmitter interrupts

• Internal loopback and auto-echo modes

• Full-duplex operation

• Programmable serial interface

• Status reporting capability

• Individual receiver and transmitter DMA support

• Auto-handshaking mode for receiver and transmitter

• Transmitter pattern generation capability

• Serial clock frequency up to 1/2 system clock frequency

• Inter-Character Timeout Facility support from the GPT/PWM

Modem Interface

The Modem Interface provides a glueless communication from the device to and from many standard and

economical telephony CODECs (Note: CODECs are the Audio ADC/DAC devices). The PPC405B3 CPU and

applicable software can be used to implement an inexpensive interface for a modem. The external interface

supports industry standard 4-wire parameters, consisting of transmit data, receive data, clock, and frame

sync. Two channels of DMA allow off-loading data from the CPU. The Modem Interface supports digital audio

MIC input, status reporting, and interrupt generation.

Serial Control Port

The Serial Control Port (SCP) is a full-duplex, synchronous, character-oriented (byte) port that allows the

exchange of data with other SCP bus-compatible serial devices. The SCP is a slave device to the OPB bus,

and supports a three-wire interface to the serial port (receive, transmit, and clock). It provides a glueless

serial interface to many microcontrollers, with clock inversion and reverse data. The port includes a program-

mable clock rate divider (Sysclk/4 to Sysclk/1024), and bit rate is supported up to 1/4 the frequency of the

system clock.

General Purpose I/O Controller

The General Purpose I/O (GPIO) controller enables the multiplexing of module I/Os, with functions that

include programmable open-drain output conversion, registered input and output functions, and simplified

GPIO definition.

STB03_sds_041800.fm.01

April 18, 2000

Architecture and Subsystem Information

Page 15 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Pin and I/O Information

Pinout Diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y AA AB AC

LEGEND:

V

Ground

I/O Pin

DD33

DD25

Pin and I/O Information

Page 16 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Signal Pins Sorted by Signal Name

Grid (Pin)

Position

Grid (Pin)

Signal

Group

Signal

Group

Bus Interface

Position

AB15

AB16

AB17

AA16

AA15

AUD_VDDA0

N22

K20

AA2

AC3

AC4

AB5

AC5

AA5

AB9

AA9

AC8

AB8

AC7

AB7

AC6

AB6

AB4

Y6

PLL Analog PWR + GND BI_DATA2

PLL Analog PWR + GND BI_DATA3

AUD_VDDA1

Bus Interface

BI_ADDRESS8 (MSB)

BI_ADDRESS9

BI_ADDRESS10

BI_ADDRESS11

BI_ADDRESS12

BI_ADDRESS13

BI_ADDRESS14

BI_ADDRESS15

BI_ADDRESS16

BI_ADDRESS17

BI_ADDRESS18

BI_ADDRESS19

BI_ADDRESS20

BI_ADDRESS21

BI_ADDRESS22

BI_ADDRESS23

BI_ADDRESS24

BI_ADDRESS25

BI_ADDRESS26

BI_ADDRESS27

BI_ADDRESS28

BI_ADDRESS29

BI_ADDRESS30

Bus Interface

BI_DATA4

BI_DATA5

BI_DATA6

BI_DATA7

BI_DATA8

BI_DATA9

AC14 Bus Interface

Y14 Bus Interface

AC15 Bus Interface

AC16 Bus Interface

AC17 Bus Interface

BI_DATA10

BI_DATA11

BI_DATA12

BI_DATA13

BI_DATA14

BI_DATA15 (LSB)

BI_OE

Y17

Y16

Bus Interface

AB14

AB13

AC13 Bus Interface

BI_READY

BI_RW

AA10

AB10

Y11

Bus Interface

BI_WBE0

Bus Interface

AA6

Y7

CI_CLOCK

CI_DATA0 (MSB)

CI_DATA1

CI_DATA2

CI_DATA3

CI_DATA4

CI_DATA5

U20

Y23

Channel Interface

AA7

Y8

Y22

W23

W21

W22

V20

AA8

Y10

AC9

BI_ADDRESS31

(LSB)/BI_WBE1

AC10 Bus Interface

Y13 Bus Interface

CI_DATA6

V23

Channel Interface

BI_CS0

BI_CS1

BI_CS2

CI_DATA7 (LSB)

CI_DATA_ENABLE

CLK_VDDA

V21

V22

C9

Channel Interface

AB12 Bus Interface

AA12 Bus Interface

Channel Interface

PLL Analog PWR + GND

DAC Analog PWR +

GND

BI_CS3

AC12 Bus Interface

AA13 Bus Interface

AA14 Bus Interface

DAC1_AGND0

DAC1_AGND1

DAC1_AGND2

L1

J1

DAC Analog PWR +

GND

BI_DATA0 (MSB)

BI_DATA1

DAC Analog PWR +

GND

G3

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 17 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Signal Pins Sorted by Signal Name (Continued)

Grid (Pin)

Position

Grid (Pin)

Position

Signal

DAC1_AVDD0

Group

Signal

DA_SERIAL_DATA0

DV1_DATA0 (MSB)

DV1_DATA1

Group

DAC Analog PWR +

GND

L3

V4

E3

E2

E1

Audio

DAC Analog PWR +

GND

DAC1_AVDD1

DAC1_AVDD2

DAC1_AVDD3

K2

J3

Video and Graphics

DAC Analog PWR +

GND

DAC Analog PWR +

GND

G2

DV1_DATA2

DAC1_BOUT

H4

F1

K3

L4

L2

H3

H2

Video and Graphics

DV1_DATA3

D2

D1

C2

C1

B3

F2

F4

Video and Graphics

DAC1_BREF_OUT

DAC1_GOUT

DV1_DATA4

DV1_DATA5

DAC1_GREF_OUT

DAC1_ROUT

DV1_DATA6

DV1_DATA7 (LSB)

DV1_HSYNC

DAC1_RREF_OUT

DAC1_VREF_IN

DV1_PIXEL_CLOCK

DAC Analog PWR +

GND

DAC2_AGND0

DAC2_AGND1

DAC2_AGND2

DAC2_AVDD0

DAC2_AVDD1

DAC2_AVDD2

DAC2_AVDD3

M2

P3

U1

M1

N4

P4

T2

DV1_VSYNC

F3

Y2

Video and Graphics

Direct Memory Access

Ground

DAC Analog PWR +

GND

EDMAC3_ACK/IDE_ACK

DAC Analog PWR +

GND

EDMAC3_REQ/IDE_REQ

AA1

B1

DAC Analog PWR +

GND

DAC Analog PWR +

GND

B2

Ground

DAC Analog PWR +

GND

B22

B23

Ground

DAC Analog PWR +

GND

Ground

DAC2_BOUT

T3

U2

N3

N1

M3

T1

Video and Graphics

Audio

GND

C21

D4

Ground

DAC2_BREF_OUT

DAC2_GOUT

D20

Y4

DAC2_GREF_OUT

DAC2_ROUT

Y20

AA3

AA21

AB1

AB2

AB22

DAC2_RREF_OUT

DAC2_VREF_IN

DA_BIT_CLOCK

DA_IEC_958

R3

V1

W1

V3

Audio

DA_LR_CHANNEL_CLOCK

Audio

DA_OVERSAMPLING_CLO

CK

V2

Audio

GND

AB23

Ground

Pin and I/O Information

Page 18 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Signal Pins Sorted by Signal Name (Continued)

Grid (Pin)

Position

Grid (Pin)

Position

Signal

Group

Signal

Group

GND

AC1

Ground

GPIO_22

GPIO_23

GPIO_24

GPIO_25

GPIO_26

GPIO_27

GPIO_28

GPIO_29

GPIO_30

GPIO_31

R2

R1

P2

General Purpose I/O

Global

AC2

AC22 Ground

AC23 Ground

P1

A1

A2

Ground

N2

K4

A22

A23

C3

K1

C6

G23

G21

C8

C7

D12

M20

Y12

G_SYSTEM_CLOCK

G_SYSTEM_RST

Global

Inter-Integrated Circuit

(IIC)

GND

M4

Ground

I2C0_SCL

I2C0_SDA

U4

U3

Inter-Integrated Circuit

(IIC)

GPIO_0

N23

General Purpose I/O

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_18

GPIO_19

GPIO_20

GPIO_21

N21

G4

General Purpose I/O

INT0

AA17

AB3

J23

Interrupt

INT1

Interrupt

AC11 General Purpose I/O

INT2

Interrupt

A15

H20

General Purpose I/O

INT3

K22

K23

K21

J21

Interrupt

MUX0_0

MUX0_1

MUX0_2

MUX0_3

MUX0_4

MUX0_5

MUX0_6

MUX0_7

MUX0_8

MUX0_9

MUX0_10

MUX0_11

MUX0_12

MUX0_13

MUX0_14

MUX0_15

MUX0_16

Multiplexed I/O

AA18 General Purpose I/O

AC18 General Purpose I/O

AB20 General Purpose I/O

L23

L22

L21

L20

M21

N20

P21

P22

P23

M22

M23

J22

B7

A7

D7

B8

A8

D8

B9

General Purpose I/O

AB11 General Purpose I/O

AA11 General Purpose I/O

G1

H1

J2

General Purpose I/O

H21

H23

T4

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 19 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Signal Pins Sorted by Signal Name (Continued)

Grid (Pin)

Position

Signal

Group

Signal

Group

Position

G20

B20

A21

C23

D23

E21

F21

F23

G22

F20

F22

E23

E22

D22

C22

B21

A20

H22

Y1

MUX0_17

MUX0_18

MUX0_19

MUX0_20

MUX0_21

MUX0_22

MUX0_23

MUX0_24

MUX0_25

MUX0_26

MUX0_27

MUX0_28

MUX0_29

MUX0_30

MUX0_31

MUX0_32

MUX0_33

MUX0_34

MUX1_0

MUX1_1

MUX1_2

MUX2_0

MUX2_1

MUX2_2

MUX2_3

MUX3_0

MUX3_1

MUX3_2

MUX3_3

MUX3_4

MUX3_5

MUX3_6

MUX3_7

MUX3_8

MUX3_9

MUX3_10

Multiplexed I/O

Reserved - Tie to 3.3 V

SC0_CLK

B6

Global

AB21

Y18

Smart Card Interface 0

SC0_DETECT

SC0_IO

AC21 Smart Card Interface 0

SC0_RESET

AA23

AA22

AA19

AB18

Smart Card Interface 0

Smart Card Interface 1

SC0_VCC_COMMAND

SC1_CLK

SC1_DETECT

SC1_IO

AC19 Smart Card Interface 1

AB19 Smart Card Interface 1

AC20 Smart Card Interface 1

SC1_RESET

SC1_VCC_COMMAND

SD1_ADDRESS0 (MSB)

SD1_ADDRESS1

SD1_ADDRESS2

SD1_ADDRESS3

SD1_ADDRESS4

SD1_ADDRESS5

SD1_ADDRESS6

SD1_ADDRESS7

SD1_ADDRESS8

SD1_ADDRESS9

SD1_ADDRESS10

SD1_ADDRESS11

SD1_ADDRESS12

SD1_ADDRESS13 (LSB)

SD1_CAS

C16

A17

B16

B17

D16

C17

D17

C18

D18

C19

B19

A19

B18

A18

B15

D14

A16

D10

B10

D11

B11

C12

A12

C13

D13

SDRAM1 Controller

W2

W3

A3

B4

A4

B5

U23

U21

U22

T20

T23

T21

T22

R23

R21

R22

P20

SD1_CLK

SD1_CS0

SD1_DATA0 (MSB)

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD1_DATA4

SD1_DATA5

SD1_DATA6

SD1_DATA7

Pin and I/O Information

Page 20 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Signal Pins Sorted by Signal Name (Continued)

Grid (Pin)

Position

Signal

SD1_DATA8

Group

Signal

Group

2.5 V Power

Position

A13

B13

B12

A11

C11

A10

C10

A9

SDRAM1 Controller

Serial1 / Infrared

VDD25

VDD33

D3

D5

SD1_DATA9

2.5 V Power

3.3 V Power

SD1_DATA10

SD1_DATA11

SD1_DATA12

SD1_DATA13

SD1_DATA14

SD1_DATA15 (LSB)

SD1_DQMH

D19

D21

E4

E20

W4

W20

Y3

C14

B14

C15

A14

A6

SD1_DQML

Y5

SD1_RAS

Y19

Y21

D9

SD1_WE

SERIAL1/INFRARED_CTS

SERIAL1/INFRARED_RTS

SERIAL1/INFRARED_RXD

SERIAL1/INFRARED_TXD

VDD25

D6

Serial1 / Infrared

D15

J4

A5

Serial1 / Infrared

C5

Serial1 / Infrared

J20

R4

AA4

2.5 V Power

VDD25

AA20 2.5 V Power

R20

Y9

VDD25

C4

2.5 V Power

VDD25

C20

Y15

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 21 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

.

Signal Pins Sorted by Pin Number

Grid (Pin)

Position

Grid (Pin)

Position

Signal

Group

Signal

Group

Bus Interface

A1

A2

GND

Ground

AA13 BI_DATA0 (MSB)

AA14 BI_DATA1

AA15 BI_DATA6

AA16 BI_DATA5

AA17 INT0

GND

Bus Interface

Interrupt

A3

MUX2_0

MUX2_2

Multiplexed I/O

A4

A5

SERIAL1/INFRARED_RXD Serial1 / Infrared

SERIAL1/INFRARED_CTS Serial1 / Infrared

A6

AA18 GPIO_6

General Purpose I/O

Smart Card Interface 1

2.5 V Power

A7

GPIO_10

General Purpose I/O

SDRAM1 Controller

General Purpose I/O

SDRAM1 Controller

Multiplexed I/O

Ground

AA19 SC1_CLK

AA20 VDD25

A8

GPIO_13

A9

SD1_DATA15 (LSB)

SD1_DATA13

SD1_DATA11

SD1_DATA5

SD1_DATA8

SD1_WE

AA21 GND

Ground

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA22 SC0_VCC_COMMAND

AA23 SC0_RESET

Smart Card Interface 0

Ground

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

GND

Ground

INT1

Interrupt

GPIO_4

BI_ADDRESS22

BI_ADDRESS11

BI_ADDRESS21

BI_ADDRESS19

BI_ADDRESS17

BI_ADDRESS14

Bus Interface

General Purpose I/O

Bus Interface

Smart Card Interface 1

General Purpose I/O

Smart Card Interface 0

Ground

SD1_CS0

SD1_ADDRESS1

SD1_ADDRESS13 (LSB)

SD1_ADDRESS11

MUX0_33

MUX0_19

AB10 BI_RW

GND

AB11 GPIO_16

AB12 BI_CS1

GND

Ground

EDMAC3_REQ/IDE_REQ

BI_ADDRESS8 (MSB)

GND

Direct Memory Access

Bus Interface

AB13 BI_DATA15 (LSB)

AB14 BI_DATA14

AB15 BI_DATA2

AB16 BI_DATA3

AB17 BI_DATA4

AB18 SC1_DETECT

AB19 SC1_RESET

AB20 GPIO_8

Ground

VDD25

2.5 V Power

BI_ADDRESS13

BI_ADDRESS24

BI_ADDRESS26

BI_ADDRESS28

BI_ADDRESS15

Bus Interface

AB21 SC0_CLK

AB22 GND

AA10 BI_READY

AA11 GPIO_17

AA12 BI_CS2

Bus Interface

General Purpose I/O

Bus Interface

AB23 GND

Ground

AC1

GND

Ground

Pin and I/O Information

Page 22 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Signal Pins Sorted by Pin Number (Continued)

Grid (Pin)

Position

Signal

Group

Signal

Group

Position

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

GND

Ground

B15

B16

B17

B18

B19

B20

B21

B22

SD1_CAS

SDRAM1 Controller

Multiplexed I/O

BI_ADDRESS9

BI_ADDRESS10

BI_ADDRESS12

BI_ADDRESS20

BI_ADDRESS18

BI_ADDRESS16

BI_ADDRESS30

Bus Interface

SD1_ADDRESS2

SD1_ADDRESS3

SD1_ADDRESS12

SD1_ADDRESS10

MUX0_18

MUX0_32

Multiplexed I/O

GND

Ground

BI_ADDRESS31

(LSB)/BI_WEB1

AC10

Bus Interface

B23

GND

Ground

AC11 GPIO_3

AC12 BI_CS3

General Purpose I/O

Bus Interface

C1

C2

DV1_DATA6

DV1_DATA5

GND

Video and Graphics

Ground

AC13 BI_OE

Bus Interface

C3

AC14 BI_DATA7

AC15 BI_DATA9

AC16 BI_DATA10

AC17 BI_DATA11

AC18 GPIO_7

AC19 SC1_IO

AC20 SC1_VCC_COMMAND

AC21 SC0_IO

AC22 GND

Bus Interface

C4

VDD25

2.5 V Power

Bus Interface

C5

SERIAL1/INFRARED_TXD Serial1 / Infrared

Bus Interface

C6

GPIO_29

General Purpose I/O

Global

Bus Interface

C7

G_SYSTEM_RST

G_SYSTEM_CLOCK

CLK_VDDA

SD1_DATA14

SD1_DATA12

SD1_DATA4

SD1_DATA6

SD1_DQMH

SD1_RAS

General Purpose I/O

Smart Card Interface 1

Smart Card Interface 0

Ground

C8

Global

C9

PLL Analog PWR + GND

SDRAM1 Controller

2.5 V Power

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

AC23 GND

Ground

B1

B2

GND

Ground

GND

Ground

B3

DV1_DATA7 (LSB)

MUX2_1

Video and Graphics

Multiplexed I/O

Global

SD1_ADDRESS0 (MSB)

SD1_ADDRESS5

SD1_ADDRESS7

SD1_ADDRESS9

VDD25

B4

B5

MUX2_3

B6

Reserved - Tie to 3.3 V

GPIO_9

B7

General Purpose I/O

SDRAM1 Controller

B8

GPIO_12

GND

Ground

B9

GPIO_15

MUX0_31

Multiplexed I/O

B10

B11

B12

B13

B14

SD1_DATA1

SD1_DATA3

SD1_DATA10

SD1_DATA9

SD1_DQML

MUX0_20

Multiplexed I/O

DV1_DATA4

DV1_DATA3

VDD25

Video and Graphics

2.5 V Power

D2

D3

D4

GND

Ground

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 23 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Signal Pins Sorted by Pin Number (Continued)

Grid (Pin)

Position

Grid (Pin)

Position

Signal

Group

Signal

DAC1_AVDD3

Group

D5

D6

VDD25

2.5 V Power

G2

G3

DAC Analog PWR + GND

General Purpose I/O

Multiplexed I/O

SERIAL1/INFRARED_RTS Serial1 / Infrared

DAC1_AGND2

GPIO_2

D7

GPIO_11

General Purpose I/O

3.3 V Power

G4

D8

GPIO_14

G20

G21

G22

G23

H1

MUX0_17

D9

VDD33

GPIO_31

General Purpose I/O

Multiplexed I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

E1

SD1_DATA0 (MSB)

SD1_DATA2

GND

SDRAM1 Controller

Ground

MUX0_25

GPIO_30

General Purpose I/O

Video and Graphics

General Purpose I/O

Multiplexed I/O

GPIO_19

SD1_DATA7

SD1_CLK

SDRAM1 Controller

3.3 V Power

H2

DAC1_VREF_IN

DAC1_RREF_OUT

DAC1_BOUT

GPIO_5

H3

VDD33

H4

SD1_ADDRESS4

SD1_ADDRESS6

SD1_ADDRESS8

VDD25

SDRAM1 Controller

2.5 V Power

H20

H21

H22

H23

J1

MUX0_15

MUX0_34

Multiplexed I/O

MUX0_16

Multiplexed I/O

GND

Ground

DAC1_AGND1

GPIO_20

DAC Analog PWR + GND

General Purpose I/O

DAC Analog PWR + GND

3.3 V Power

VDD25

2.5 V Power

J2

MUX0_30

Multiplexed I/O

J3

DAC1_AVDD2

VDD33

MUX0_21

Multiplexed I/O

J4

DV1_DATA2

DV1_DATA1

DV1_DATA0 (MSB)

VDD25

Video and Graphics

2.5 V Power

J20

J21

J22

J23

K1

VDD33

3.3 V Power

E2

MUX0_2

Multiplexed I/O

E3

MUX0_14

Multiplexed I/O

E4

INT2

Interrupt

E20

E21

E22

E23

F1

VDD25

2.5 V Power

GPIO_28

General Purpose I/O

DAC Analog PWR + GND

Video and Graphics

General Purpose I/O

PLL Analog PWR + GND

Multiplexed I/O

MUX0_22

Multiplexed I/O

K2

DAC1_AVDD1

DAC1_GOUT

GPIO_27

MUX0_29

Multiplexed I/O

K3

MUX0_28

Multiplexed I/O

K4

DAC1_BREF_OUT

DV1_HSYNC

DV1_VSYNC

DV1_PIXEL_CLOCK

MUX0_26

Video and Graphics

Multiplexed I/O

K20

K21

K22

K23

L1

AUD_VDDA1

MUX0_1

F2

F3

INT3

Interrupt

F4

MUX0_0

Multiplexed I/O

F20

F21

F22

F23

G1

DAC1_AGND0

DAC1_ROUT

DAC1_AVDD0

DAC1_GREF_OUT

MUX0_6

DAC Analog PWR + GND

Video and Graphics

DAC Analog PWR + GND

Video and Graphics

Multiplexed I/O

MUX0_23

Multiplexed I/O

L2

MUX0_27

Multiplexed I/O

L3

MUX0_24

Multiplexed I/O

L4

GPIO_18

General Purpose I/O

L20

Pin and I/O Information

Page 24 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Signal Pins Sorted by Pin Number (Continued)

Grid (Pin)

Position

Signal

Group

Signal

Group

Position

L21

L22

L23

M1

MUX0_5

MUX0_4

MUX0_3

Multiplexed I/O

DAC Analog PWR + GND

Video and Graphics

Ground

T1

T2

DAC2_RREF_OUT

DAC2_AVDD3

DAC2_BOUT

GPIO_21

Video and Graphics

DAC Analog PWR + GND

Video and Graphics

General Purpose I/O

Multiplexed I/O

T3

DAC2_AVDD0

DAC2_AGND0

DAC2_ROUT

GND

T4

M2

T20

T21

T22

T23

U1

MUX3_3

M3

MUX3_5

Multiplexed I/O

M4

MUX3_6

Multiplexed I/O

M20

M21

M22

GND

Ground

MUX3_4

Multiplexed I/O

MUX0_7

Multiplexed I/O

DAC2_AGND2

DAC2_BREF_OUT

DAC Analog PWR + GND

Video and Graphics

MUX0_12

U2

Inter-Integrated Circuit

(IIC)

M23

N1

MUX0_13

Multiplexed I/O

U3

U4

I2C0_SDA

I2C0_SCL

Inter-Integrated Circuit

(IIC)

DAC2_GREF_OUT

Video and Graphics

N2

N3

GPIO_26

General Purpose I/O

Video and Graphics

DAC Analog PWR + GND

Multiplexed I/O

U20

U21

U22

U23

V1

CI_CLOCK

MUX3_1

Channel Interface

Multiplexed I/O

Audio

DAC2_GOUT

DAC2_AVDD1

MUX0_8

N4

MUX3_2

N20

N21

MUX3_0

GPIO_1

General Purpose I/O

DA_BIT_CLOCK

DA_OVERSAMPLING_CLO

CK

N22

AUD_VDDA0

PLL Analog PWR + GND

V2

Audio

N23

P1

GPIO_0

General Purpose I/O

DAC Analog PWR + GND

Multiplexed I/O

V3

V4

DA_LR_CHANNEL_CLOCK Audio

GPIO_25

GPIO_24

DAC2_AGND1

DAC2_AVDD2

MUX3_10

MUX0_9

DA_SERIAL_DATA0

CI_DATA5

Audio

P2

V20

V21

V22

V23

W1

W2

W3

W4

W20

W21

W22

W23

Y1

Channel Interface

Audio

P3

CI_DATA7 (LSB)

CI_DATA_ENABLE

CI_DATA6

P4

P20

P21

P22

P23

R1

Multiplexed I/O

DA_IEC_958

MUX1_1

MUX0_10

MUX0_11

GPIO_23

GPIO_22

DAC2_VREF_IN

VDD33

Multiplexed I/O

2.5 V Power

Multiplexed I/O

MUX1_2

General Purpose I/O

Video and Graphics

3.3 V Power

VDD25

R2

VDD25

2.5 V Power

R3

CI_DATA3

Channel Interface

Multiplexed I/O

Direct Memory Access

2.5 V Power

R4

CI_DATA4

R20

R21

R22

R23

VDD33

3.3 V Power

CI_DATA2

MUX3_8

Multiplexed I/O

MUX1_0

MUX3_9

Multiplexed I/O

Y2

EDMAC3_ACK/IDE_ACK

VDD25

MUX3_7

Multiplexed I/O

Y3

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 25 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Signal Pins Sorted by Pin Number (Continued)

Grid (Pin)

Position

Grid (Pin)

Position

Signal

Group

Signal

Group

Bus Interface

Y4

Y5

GND

Ground

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

BI_DATA8

VDD33

VDD25

2.5 V Power

Bus Interface

3.3 V Power

Bus Interface

Ground

3.3 V Power

Bus Interface

Y6

BI_ADDRESS23

BI_ADDRESS25

BI_ADDRESS27

VDD33

BI_DATA13

BI_DATA12

SC0_DETECT

VDD25

Y7

Y8

Smart Card Interface 0

2.5 V Power

Y9

Y10

Y11

Y12

Y13

BI_ADDRESS29

BI_WBE0

GND

Ground

VDD25

2.5 V Power

GND

CI_DATA1

CI_DATA0 (MSB)

Channel Interface

BI_CS0

Bus Interface

Pin and I/O Information

Page 26 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

STB03xxx Multiplexed I/O Signal Table

STB03xxx has four sets of multiplexed I/O signals: Mux0, Mux1, Mux2, and Mux3. At reset, the

multiplexed I/O signals are tristated, unless noted.

The muxtiplexed I/O can be selected by column in the following tables. For example, if Input/Output 1 is

selected, Input/Output 2 and Input/Output 3 are not available.

Blank entries indicate reserved multiplexing.

Multiplexed I/O Signal Table

Bit #

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Input/Output 1

SD0_ADDRESS0 (MSB)

Type

O

Input/Output 2

IEEE1284_PD0 (MSB)

Type

I/O

O

SD0_ADDRESS1

SD0_ADDRESS2

SD0_ADDRESS3

SD0_ADDRESS4

SD0_ADDRESS5

SD0_ADDRESS6

SD0_ADDRESS7

SD0_ADDRESS8

SD0_ADDRESS9

SD0_ADDRESS10

SD0_ADDRESS11

SD0_ADDRESS12

SD0_ADDRESS13

SD0_CS0

O

IEEE1284_PD1

IEEE1284_PD2

IEEE1284_PD3

IEEE1284_PD4

IEEE1284_PD5

IEEE1284_PD6

IEEE1284_PD7

IEEE1284_AUTOFEED

IEEE1284_SELECT_IN

IEEE1284_BUSY

IEEE1284_SELECT

IEEE1284_PE

IEEE1284_ERROR

IEEE1284_ACK

IEEE1284_PDIR

IEEE1284_INIT

IEEE1284_STROBE

BI_DATA16

O

SD0_RAS

O

SD0_CAS

O

I/O

SD0_WE

O

SD0_DATA0

I/O

SD0_DATA1

BI_DATA17

SD0_DATA2

BI_DATA18

SD0_DATA3

BI_DATA19

SD0_DATA4

BI_DATA20

SD0_DATA5

BI_DATA21

SD0_DATA6

BI_DATA22

SD0_DATA7

BI_DATA23

SD0_DATA8

BI_DATA24

SD0_DATA9

BI_DATA25

SD0_DATA10

BI_DATA26

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 27 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Multiplexed I/O Signal Table (Continued)

Bit #

29

Input/Output 1

Type

I/O

O

Input/Output 2

Type

I/O

O

SD0_DATA11

SD0_DATA12

SD0_DATA13

SD0_DATA14

SD0_DATA15

SD0_CLK

BI_DATA27

BI_DATA28

BI_DATA29

BI_DATA30

30

31

32

33

BI_DATA31 (LSB)

IEEE1284_HOST

34

Multiplexed I/O Signal Table - Mux1

Bit #

00

Input/Output 1

Type

Input/Output 2

Type

I/O

EDMAC2_ACK

EDMAC2_REQ

EDMAC2_EOT

O

I

EBM_HOLDACK

EBM_HOLDREQ

EBM_BUSREQ

01

02

I/O

Multiplexed I/O Signal Table - Mux2

Bit #

00

Input/Output 1

SERIAL0/16550_TXD

Type

Input/Output 2

Type

O

I

SSP_TXD

SSP_RXD

SSP_CLK

SSP_FS

O

01

02

03

SERIAL0/16550_RXD

SERIAL0/16550_CTS

SERIAL0/16550_RTS

I

O

I/O

Multiplexed I/O Signal Table - Mux3

Bit #

Input/Output 1

Type

Input/Output 2

Type

I/O

Input/Output 3

Type

Input/Output 4

Type

O

SERIAL1/INFRARE

D_DSR

IEEE1284_PD0

(MSB)

00

HSP_DATA0

O

I

RT_TS1E

(through GPIO bit 31

alt rcv 2)

SERIAL1/INFRARE

D_DTR

O

01

02

HSP_DATA1

HSP_DATA2

O

IEEE1284_PD1

IEEE1284_PD2

I/O

O

I

RT_TS2E

RT_TS1O

RW_TMS

(through GPIO bit 11

alt rcv 1

RW_TDI

O

03

04

HSP_DATA3

HSP_DATA4

O

IEEE1284_PD3

IEEE1284_PD4

I/O

I

RT_TS2O

RT_TS3

(through GPIO bit 12

alt rcv 1)

RW_TCK

(through GPIO bit 13

alt rcv 1)

Pin and I/O Information

Page 28 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Multiplexed I/O Signal Table - Mux3 (Continued)

Bit #

05

Input/Output 1

HSP_DATA5

Type

O

Input/Output 2

Type

I/O

Input/Output 3

RW_TDO

Type

O

Input/Output 4

RT_TS4

Type

O

IEEE1284_PD5

RW_HALT

O

06

HSP_DATA6

O

IEEE1284_PD6

IEEE1284_PD7

I/O

I

RT_TS5

(through GPIO bit 15

alt rcv 1)

SERIAL0/16550_DS

R

O

07

08

09

HSP_DATA7

HSP_CLOCK

O

I/O

I

RT_TS6

RT_CLK

(through GPIO bit 5

alt rcv 3)

IEEE1284_

STROBE

SERIAL0/16550_DT

R

O

I

SERIAL0/16550_DC

D

HSP_DATA_

ENABLE

IEEE1284_ACK

IEEE1284_INIT

(through GPIO bit 6

alt rcv 3)

SERIAL0/16550_RI

HSP_PACKET_

START

10

O

I/O

I

(through GPIO bit 8

alt rcv 3)

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 29 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

General Purpose I/O (GPIO)

The following table describes the GPIO bits. For each GPIO bit only one signal can be selected at a time.

Each table row lists the signal associated with each logical GPIO bit number. The ﬁrst column lists the

GPIO bit number. The second column lists the signal connected as input or output to the ﬁrst alternate

GPIO multiplexer. The signal name is listed ﬁrst, followed by the signal description. The third column

gives the direction of the signal listed in column 2. The same format is used for columns 4 through 7.

Blank entries indicate reserved GPIO multiplexing.

GPIO bit number refers to the device GPIO signal name, not the physical device pin number.

After reset all GPIOs are programmed as inputs, with the exception of GPIO0 bit 29 (PWM output),

which defaults to an open-drain output, and GPIO bit 14 (JTAG TDO output), which defaults to an output

(if BI_DATA[4] is set to ‘0’ during reset).

General Purpose I/O Bits

Bit #

00

Input/Output Mux 1

I2C1_SCL

Type

Input/Output Mux 2

Type

O

Input/Output Mux 3

DA_SURMOD0

Type

O

I/O DA_DEEMPHASIS0

I/O DA_DEEMPHASIS1

01

I2C1_SDA

O

DA_SURMOD1

O

AV_CSYNC

BI_CS4

GPT_FreqGenOut

DA_SURMOD0

INT4

I

O

I

02

03

O

SYS_CLK

BI_CS5

DA_SURMOD1

INT5

O

I

O

04

05

06

07

08

EDMAC0_REQ

EDMAC0_ACK

SCP_TXD

I

SD1_CS1

O

I

SERIAL0/16550_DTR

SERIAL0/16550_DSR

SERIAL0/16550_DCD

TS_BCLKEN

O

I

O

I

SD0_CS1

CI_PACKET_START

CI_DATA_ERROR

TS_REQ

I

SCP_RXD

SCP_CLK

I

O

SERIAL0/16550_RI

I

PWM0

GPT_COMP0

GPT_CAPT0

BI_CS6

I

O

09

10

O

PWM1

GPT_COMP1

GPT_CAPT1

BI_CS7

I

O

11

12

13

14

RW_TMS

RW_TDI

I

SSP_TXD

SSP_RXD

SSP_CLK

SSP_FS

O

I

BI_CS6

BI_CS7

INT6

O

I

RW_TCK

RW_TDO

RW_HALT

I

O

I/O INT7

I

SERIAL0/16550_CLK - External

SERIAL0/16550 Clock Input

SYS_CLK

15

I

O

16

17

DA_SERIAL_DATA1

DA_SERIAL_DATA2

O

BI_CS4

O

BI_CS5

HSP_ERROR

O

I

DV_TRANSPARENCY_

GATE

DV2_PIXEL_CLOCK

SERIAL1/INFRARED_CLK -

External SERIAL1/INFRARED

Clock Input

18

I/O

I

Pin and I/O Information

Page 30 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

General Purpose I/O Bits (Continued)

Bit #

19

20

21

22

23

24

25

26

27

28

29

Input/Output Mux 1

TTX_REQ

Type

Input/Output Mux 2

Type

Input/Output Mux 3

Type

I/O DV2_VSYNC

I/O

TTX_DATA

I/O DV2_HSYNC

I/O

DV2_DATA0 (MSB)

DV2_DATA1

I/O IEEE1284_AUTOFEED

I/O IEEE1284_SELECT_IN

I/O IEEE1284_BUSY

I/O IEEE1284_SELECT

I/O IEEE1284_PE

I/O INT8

I

I/O INT9

DV2_DATA2

I/O

O

DV2_DATA3

DV2_DATA4

DV2_DATA5

I/O IEEE1284_ERROR

I/O IEEE1284_PDIR

I/O IEEE1284_HOST

DV2_DATA6

DV2_DATA7

O

DENC_PWM_OUTPUT

O

XPT_PWM_OUTPUT

O

EDMAC1_REQ

BI_WBE2

SERIAL1/INFRARED_DTR

SD0_DQMH

I

O

30

31

O

EDMAC1_ACK

SERIAL1/INFRARED_DSR

BI_WBE3

SD0_DQML

I

O

STB03_sds_041800.fm.01

April 18, 2000

Pin and I/O Information

Page 31 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Electrical Information

The following tables give the absolute ratings for various electrical characteristics.

Drivers/Receivers

Four types of I/O drivers and receivers are used on the STB03xxx device, as follows:

.

I/O Driver Types

Driver/

Receiver

Type

Characteristics

Used on I/O signals:

G_SYSTEM_RESET, GPIO[2], GPIO[29],

SC0_IO, SC0_CLK, SC0_DETECT, SC0_RESET,

SC0_VCC_COMMAND, SC1_IO, SC1_CLK,

SC1_DETECT, SC1_RESET,

5 V tolerant, no pull-up or pull-down

(external pull-up is required)

BP3365

SC1_VCC_COMMAND,

BI_READY

5 V tolerant, no pull-up or pull-down

(external pull-up is required)

I2C0_SDA, I2C0_SCL,

GPIO[0], GPIO[1]

BP3335

BT3350PU

BT3365PU

3.3 V I/O with pull-up

BI_DATA[0:15], MUX0[18:33]

all other digital I/O signals

DC Electrical Characteristics

The table, “DC Electrical Characteristics,” gives the absolute ratings for various electrical

characteristics. The temperature is 70° C in all cases.

DC Electrical Characteristics

Driver / Receiver

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

1

V

High Level Input Voltage

Low Level Input Voltage

2.00

5.50

0.80

IH

2

V

-0.60

V

IL

V

= Min,

= 17.0 mA

BP3335

CC

V

High Level Output Voltage

Low Level Output Voltage

2.40

V

OH

I

OH

V

= Min,

= 11.0 mA

CC

V

0.4

OL

I

OL

1

V

High Level Input Voltage

Low Level Input Voltage

2.00

5.50

0.80

V

IH

2

V

-0.60

IL

V

= Min,

= 9.0 mA

BP3365

CC

V

High Level Output Voltage

Low Level Output Voltagec

2.40

V

OH

I

OH

V

= Min,

= 6.0 mA

CC

V

0.4

OL

I

OL

1. Maximum V applies to overshoot only.

IH

2. Minimum V applies to undershoot only.

IL

3. 5.0 volt tolerant Driver/Receiver, see graph, page 34.

Electrical Information

Page 32 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

DC Electrical Characteristics (Continued)

Driver / Receiver

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

1

V

High Level Input Voltage

Low Level Input Voltage

2.00

4.0

IH

2

V

-0.60

0.80

V

IL

V

= Min,

= 12.0 mA

BT3350PU

CC

V

High Level Output Voltage

Low Level Output Voltage

2.40

V

OH

I

OH

V

= Min,

= 8.0 mA

CC

V

0.4

OL

I

OL

1

V

High Level Input Voltage

Low Level Input Voltage

2.00

4.0

V

IH

2

V

-0.60

0.80

IL

V

= Min,

= 9.0 mA

BT3365PU

CC

V

High Level Output Voltage

Low Level Output Voltage

2.40

V

OH

I

OH

V

= Min,

= 6.0 mA

CC

V

0.4

OL

I

OL

BT3350PU, BT3365PU

I

Maximum Input Current

Supply Current, 2.5 V

Supply Current, 3.3 V

V

= 0 V

-250

µA

I

IN

3

BP3335, BP3365

I

N/A

I

V

= Max

TBD

mA

CC

I

V

= Max

CC330

V

= Nom,

CC

All

C

Input Capacitance

2.6

pF

I

V = Nom

I

All

ESD

PD

Electro Static Discharge

Power Dissipation

-3000

3000

V

N/A

2.5

W

1. Maximum V applies to overshoot only.

IH

2. Minimum V applies to undershoot only.

IL

3. 5.0 volt tolerant Driver/Receiver, see graph, page 34.

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 33 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

BP33 Receiver Maximum Input Leakage DC Current Input Speciﬁcations

Function

I (µA)

ih

il

Without pull-up element or pull-down element

With pull-up element

0 at V = LPDL

0 at V = MPUL

in

-250 at V = LPDL

0 at V = MPUL

in

BP33 Receiver Input Current/Voltage Curve

Current (µA)

0.00

- 50.00

-100.00

-150.00

-200.00

-250.00

-300.00

-350.00

-400.00

-450.00

-500.00

-550.00

Voltage (V)

0.00

1.00

2.00

3.00

4.00

5.00

Note: 0˚C, 3.6V, best case process.

The absolute maximum ratings in the following table are stress ratings only. Operation at or beyond these

maximum ratings may cause permanent damage to the device.

Electrical Information

Page 34 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

.

Absolute Maximum Ratings

Parameter

Maximum Rating

3.0 V

Supply voltage with respect to GND, 2.5 V supply

Supply voltage with respect to GND, 3.3 V supply

Case temperature under bias

3.9 V

TBD

Storage temperature

-65° C to 150° C

Operating Conditions

The STB03xxx Digital Set-Top Box Integrated Controller can interface to either 3.3 V or 5 V technologies. 5 V

interfaces are supported only for drivers/receivers supporting 5 V tolerance (see Drivers/Receivers). The

range for supply voltages is specified for five-percent margins relative to a nominal 2.5 V and 3.3 V power

supply.

Note: Device operation beyond the conditions specified in the table below is not recommended. Extended

operation beyond the recommended conditions may affect device reliability.

Recommended Operating Conditions

Symbol

Parameter

Min

Max

2.62

Unit

V

Supply Voltage, 2.5 V

Supply Voltage, 3.3 V

2.38

CC

V

3.14

3.47

V

C

CC330

T

Operating Free Air Temperature

0°

70°

A

Power Considerations

Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external

source/sink current requirements.

Power Sequencing

The 2.5 V power supply must maintain the following relationship whenever the 3.3 V power supply voltage is

greater than 0.4 V:

2.5 V power supply voltage >= 0.4 V

Supply excursions outside this range must be limited to less than 25 ms duration during each power-up or

power-down event.

General Recommendation

System designs that derive the 2.5 V supply from a regulator running from the 3.3 V supply are recommended

to ensure a fixed relationship between the two voltage supplies. Such usage substantially reduces the poten-

tial for the 3.3 V supply to be present without the 2.5 V supply.

Recommended Connections

Power and ground pins should all be connected to separate power and ground planes in the circuit board to

which the STB03xxx is mounted. Unused input pins must be tied inactive, either high or low.

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 35 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Recommended Connections for Analog I/O Pins

L3

DAC1_AVDD0

K2

DAC1_AVDD1

J3

DAC1_AVDD2

G2

DAC1_AVDD3

1 nH

2.5 V

M1

N4

DAC2_AVDD0

DAC2_AVDD1

DAC2_AVDD2

DAC2_AVDD3

22 mF

.1 mF

P4

T2

1 nF

L4

DAC1_GREF_OUT

DAC2_GREF_OUT

DAC1_RREF_OUT

DAC2_RREF_OUT

N1

H3

(For a 75 W DAC Output Load)

784

T1

784

F1

U2

DAC1_BREF_OUT

DAC2_BREF_OUT

1 nF

1.2 mF

2.5V

C9

CLK_VDDA

.1 mF

1.2 mH

N22

K20

AUD_VDDA0

AUD_VDDA1

2.5 V

5 K

.1 mF

Electrical Information

STB03_sds_041800.fm.01

April 18, 2000

Page 36 of 55

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

I/O Timing Diagrams

AC Speciﬁcation

Note 1. Clock timing and switching characters are speciﬁed in accordance with operating conditions in

Recommended Operating Conditions on page 35. AC speciﬁcations assume a 30 pF output load. All input

slow rates must be 5 ns or less, unless otherwise speciﬁed (rise and fall times measured between 0.8 V

and 2.0 V). Also, all input clocks must have a 40–60% duty cycle, unless otherwise speciﬁed.

Note 2. The internal SysClk is shown in the diagrams to indicate the relationship of the number of cycles

between various signal edges on the timing diagram.

Note 3. Where multiple interfaces share the same timing diagram, the signals names are listed using an

‘n’ to indicate that the timings apply to both interfaces. For example, the SD0 and SD1 interface signal

names in the SDRAM interface timing diagram are listed as ‘SDn’.

G_SysClk Timing

TCF

TCL

TCR

TCH

2.0 V

1.5 V

0.8 V

TC

SysClk Timing Values

Symbol

Parameter

Min

Max

Units

MHz

ns

F

SysClk clock input frequency

(Nominal 27)

C

1

T

Clock edge stability

0.15

CS

CH

Clock input high time

Clock input low time

15

ns

T

ns

CL

2

T

Clock input rise time

0.6

ns

CR

2

T

Clock input fall time

ns

CF

Note 1. Cycle-to-cycle jitter allowed between any two edges.

Note 2. Rise and fall times measured between 0.8 V and 2.0 V.

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 37 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

G_System_Reset Timing

Power-On Timing

Input

V

DD

G_SYSTEM_CLOCK

VALID

t1

Input

G_SYSTEM_RESET

t3

VALID

t2

Conﬁguration Pins

(BI_DATA[0:7], MUX2[0])

Edge Timing

t5

t4

2.0 V

0.8 V

G_SYSTEM_RESET

G_SYSTEM_RESET Timing Values

Symbol

Parameter

Min

Max

Units

µs

ns

T

Clock to Reset inactive

Input setup time

Input hold time

Input rise time

152

0

1

2

3

4

5

80

ns

37

ns

Input fall time

ns

Note: External logic must drive G_SYSTEM_RESET low during power-on, using an open-drain driver.

Electrical Information

Page 38 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

SRAM Interface Timing

t1

Internal SYSCLK

Output

t3

t2

t4

t6

Output

BI_ADDRESS

BI_CS

VALID

t5

Output

t7

Output

BI_OE

t8

t9

Output

BI_WBE

BI_R/W

t10

t11

Output

TWT +1

t13

t12

BI_DATA

(to STB03xxx)

VALID

t15

Input

t14

BI_DATA

Output

(from STB03xxx)

SRAM Interface Timing Values

Symbol

Parameter

Min

Max

19.25

12

Units

T

At SYSCLK = 54 MHz

ns

1

2

3

4

5

6

7

8

9

Address output valid time

Address output hold time

Chip Select output valid time

Chip Select output hold time

3

12

Output Enable output valid time

Output Enable output hold time

Write Byte Enable output valid time

Write Byte Enable output hold time

Read/Write output valid time

Read/Write output hold time

Data input setup time

T

10

11

12

3

7

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 39 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

SRAM Interface Timing Values (Continued)

Symbol

Parameter

Min

3

Max

15

Units

ns

T

Data input hold time

Data output valid time

Data output hold time

13

14

16

ns

3

ns

SDRAM Interface Timing Diagram

t1

SDn_CLK

Output

SDn_DATA,

Controls

Output

Input

VALID

t2

t3

SDn_DATA

t4

t5

SDRAM Interface Timing Values

Symbol

Parameter

Min

Max

Units

ns

T

SD_clk clock period (at SYSCLK = 54 MHz)

Output valid time

9.25

1

2

3

4

5

7.25

ns

Output hold time

1

ns

Input setup time

ns

Input hold time

2.5

ns

Notes:

T

= (2, 3, or 4) x t1 – controlled by SDRAMC Bank Register bits [21:22]

RCD

= (5 or 6) x t1 – controlled by SDRAMC System Register bit 4

RAS

= (2, 3, or 4) x t1 – controlled by SDRAMC Bank Register bits [25:26]

= (7, 8, 9, or 10) x t1 – controlled by SDRAMC Bank Register bits [30:31]

RP

RC

Electrical Information

Page 40 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Video Input Interface Timing

t

1

Input

DVn_PIXEL_CLOCK

DVn_VSYNC

VALID

t

3

2

DVn_DATA

DVn_HSYNC

VALID

Input

t

3

4

Video Input Timing Values

Symbol

Parameter

Min

Max

Units

ns

T

Pixel clock period

Input setup time

Input hold time

Input setup time

37

1

2

3

4

16

4

ns

11

Video Output Interface Timing

t1

DVn_PIXEL_CLOCK

Output

DVn_DATA

DVn_HSYNC

DVn_VSYNC

VALID

t2

t3

Video Output Timing Values

Symbol

Parameter

Min

4

Max

37

Units

ns

T

Pixel Clock period

Output valid time

Output hold time

1

2

3

15

ns

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 41 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Transport Input Interface Timing

t1

Input

CI_CLOCK

CI_DATA

CI_PACKET_START

CI_DATA_ENABLE

VALID

t2

t3

Transport Input Interface Timing Values

Symbol

Parameter

Min

Max

Units

ns

T

CI_CLOCK period

Input setup time

Input hold time

15

4

1

2

3

ns

3

ns

Transport Auxiliary Output Interface Timing

t1

Output

HSP_CLOCK

HSP_DATA

VALID

HSP_DATA_ENABLE

HSP_PACKET_START

t2

t3

Transport Auxiliary Output Interface Timing Values

Symbol

Parameter

HSP_clock period (at SYSCLK = 54 MHz)

Output valid time

Min

Max

Units

ns

T

19.25

1

2

3

10

ns

Output hold time

2

ns

Electrical Information

Page 42 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

DVB-CI (PCMCIA) Interface Timing

SYSCLK

Output

BI_ADDRESS

Output

VALID

BI_DATA (output)

VALID

BI_CS1

Output

4 cycles

3 cycles

BI_ADDRESS [14] (PCMCIA_iowr)

BI_ADDRESS [15] (PCMCIA_iowr)

>

BI_RW

(PCMCIA_we)

(PCMCIA_oe)

]

t1 t2

RMI_OE

Input

BI_DATA (input)

VALID

t3 t4

BI_READY (PCMCIA_wait)

Internal

Signal

INT_cs

(from EBIU)

1 + TWT

(If Ready is not used)

TH

(TH must be > 4 cycles)

DVB-CI (PCMCIA) Interface Timing Values

Symbol

Parameter

Min

5

Max

Units

T

Input set-up time

Input hold time

Input set-up time

Input hold time

ns

1

2

3

4

3

15

2

Note 1. Refer to the SRAM timing diagram for DVB-CI output timing values on page (SRAM page).

Note 2. BI_READY can also be conﬁgured as an asynchronous input.

Audio Output Timing

t1

DA_BIT_CLOCK

Output

DA_LR_CHANNEL_CLOCK,

DA_SERIAL_DATA (0:2)

VALID

t2

t3

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 43 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Audio Output Timing Values

Symbol

Parameter

DA_bit_clock period (1/[64 x 48 kHz])

Output valid time

Min

326

Max

18

Units

ns

T

1

2

3

ns

Output hold time

0

ns

IEEE 1284 Timings

Compatibility Mode Handshake

Valid Data

PData

nStrobe

T

1

Busy

T

1

nAck

T

1

T

1

nSelectIn

Compatibility Mode Handshake Timing Values

Symbol

Parameter

Min

750

Max

Units

ns

T

Host

1

2

3

4

5

6

7

8

Strobe

Hold

750 ns

750

500 µs

ns/µs

ns

Ready

Busy

0

ns

500

ns

Reply

0

500 ns

0

ns

Acknowledge (Ack)

nBusy

10 µs

ns/µs

ns

Electrical Information

Page 44 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

IEEE 1284 Mode Handshake Timing Values

Symbol

Parameter

Min

Max

1

Units

sec

T

Host response time

0

H

T

Infinite response time

0

Infinite

35

T

Peripheral response time

0

ms

L

R

P

D

T

Peripheral response time (ECP mode only)

Minimum setup or pulse width

0

0.5 µs

0

µS

Minimum data setup time (ECP Modes only)

Nibble Mode Handshake

HostBusy

(nAutoFd)

PtrClk

(nAck)

Data Bit 4

Data Bit 5

Data Bit 6

Data bit 7

nError

Select

PError

Busy

Data Bit 0

Data Bit 1

Data Bit 2

Data bit 3

1284 Active

(nSelectIn)

TL

TP TH

TP

TL

TH

T

TL

Note: See the table, “IEEE 1284 Mode Handshake Timing Values,” for symbol values.

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 45 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Byte Mode Handshake

HostBusy

(PPU_nAutoFd)

HostClk

(PPU_nStrobe)

PtrClk

(PPU_nAck)

nDataAvail

Ptr to Host Data not available

Ptr to Host Data available

(PPU_nError)

PData

TP TH

TL

TP

T

TP

TP TH

TL

TH

TL

Note: See the table, “IEEE 1284 Mode Handshake Timing Values,” on page 45 for symbol values.

ECP Forward Mode Handshake

HostClk

(nStrobe)

PeriphAck

(Busy)

PData

Byte 0

nCmd

Byte 1

nCmd

HostAck

(nAutoFd)

TD

TR

TH

TD

T

TL

T

Note: See the table, “IEEE 1284 Mode Handshake Timing Values,” on page 45 for symbol values.

Electrical Information

Page 46 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

ECP Reverse Mode Handshake

nAckReverse

(PError)

HostAck

(nAutoFd)

PeriphClk

(nAck)

Byte1

PData

Byte 0

nCmd

PeriphAck

(Busy)

nReverseRequest

(nInit)

TD

T

TL TH T

TD T

TL TH

T

Note: See the table, “IEEE 1284 Mode Handshake Timing Values,” on page 45 for symbol values.

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 47 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Negotiation Phase

1284 Active

(PPU_nSelectIn)

AckDataReq

(PPU_PError)

PData

Extensibility Data Byte

HostBusy

(PPU_nAutoFd)

HostClk

(PPU_nStrobe)

PtrClk

(PPU_nAck)

nDataAvail

(PPU_nError)

XFlag

(Select)

T

TP

TL

TH

TP

TL

TP

Note: See the table, “IEEE 1284 Mode Handshake Timing Values,” on page 45 for symbol values.

IIC Timing

Sys Clk

Output

t1

IIC_SDA

IIC_SCL

Output

IIC Timing Values

Symbol

Parameter

Output valid time (falling edge)

Min

Max

15

Units

ns

T

1

Note: SDA and SCL outputs are open-drain.

Electrical Information

Page 48 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Smart Card (SCI) Timing

SYSCLK

SC_CLK

t1

Output

t2

SCn_IO

Output

SCI Timing Values

t1 = (2 x SCCLK_CNT0) SYSCLK periods

t2 = bit width = variable from 32 to 512 SC_clk periods = SCETU x SC_clk periods

Note: SC_DETECT, SC_RESET, SC_SELECT, and SC_VCC_COMMAND are synchronous to the system

clock and are not shown here.

Modem Serial Interface Timing

MODEM_CLK

Input

MODEM_CLK

t1

t2

Input

MODEM_RXD

MODEM_FR

t3

t1

Output

MODEM_TXD

MODEM_FR

t4

Output

Modem CODEC Timing Values

Symbol

Parameter

Min

15

3

Max

Units

ns

T

Input setup time

Input hold time

Output hold time

Output valid time

1

2

3

4

ns

3

ns

16

ns

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 49 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Note 1. MODEM_CLK can be conﬁgured to send and receive data on the rising or falling clock edge.

Note 2. MODEM_FR can be an input or an output.

Serial Control Port Timing

Internal

SYSCLK

t2

t1

Output

SMC_CLK

SMC_TXD

t3

t4

Output

Input

t6

t5

SMC_RXD

SCP Timing Values

Symbol

Parameter

Min

Max

80.8

12

Units

T

SMC_clk period

ns

1

2

3

4

5

6

Output valid time

Output hold time

Input setup time

Input hold time

13

4

10

3

Note: This timing diagram assumes the CI bit in the SCP SPMODE register is set to 0. If CI is set to 1, the LK

signal is inverted.

Electrical Information

Page 50 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Additional Timing Information

Interface

Timing Information

2

Compliant with Philips Semiconductors I C Specification, dated 1995.

IIC

Interface is asynchronous.

Direct connect

Compatible with ISO/IEC 7816-3.

Interface is asynchronous.

Direct connect.

Smart Card (SC)

Serial0/16550

Functionally identical to National Semiconductor NS16450 in character mode (after reset).

Interface is asynchronous.

External transceiver logic is required.

Functionally identical to IBM PowerPC403 Serial Port Unit (SPU) (after reset).

Compatible with the IrDA Specification 1.1

IrDA 1.0 SIR with data rates up to 115.2 Kbps

IrDA 1.1 FIR with data rates up to 1.152 Mbps

Interface is asynchronous

Serial1/Infrared

External transceiver logic is required

External Interrupts

DMA

Inputs are asynchronous

External DMA request inputs are asynchronous

Capture timer inputs are asynchronous

Interface is asynchronous

GPT

External Bus Master

Compatible with IBM RISCWatch probe

Direct connect to probe

RISCWatch

RISCTrace

Contact your IBM Applications Engineer for more information

Compatible with IBM RISCTrace probe

Direct connect to probe

Contact your IBM Applications Engineer for more information

STB03_sds_041800.fm.01

April 18, 2000

Electrical Information

Page 51 of 55

IBM39STB032xx

IBM39STB034xx

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Preliminary

Mechanical Information

Package Diagram

Top of Package (BGA Side Down)

Digital Set-T

op Bo

x

Integ

rated Controller

IBM P/N

Po

werPC

XXXXXXX

ZZWWMMMM

Date Code

IBM39 STB03xxx xxx xxx

0.25

C

OEM P/N

31

B

1.22

15.5

.610

0.15

C

27.94

1.1

1.27

.050

C

1

2

3

4

5

E52P

SUBSTRATE

6

7

8

GLOB

TOP

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Cu

STIFFENER

Cavity

12.75 [0,502]

(304X

0. 0.15 SOLDER BALL

M

0.30

0.10

C

A

B

Bottom of Package (BGA Side Up)

M

Mechanical Information

Page 52 of 55

STB03_sds_041800.fm.01

April 18, 2000

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Development Support

With IBM tools and the IBM PowerPC Embedded Tools Program, you receive the support you need to

develop and debug your STB applications quickly.

IBM Tools

IBM offers Windows 95/98 − hosted development tools for STB applications that include:

• STB and processor reference design and evaluation kits, including board, compiler, debugger, ROM

source, schematics, etc.

• RISCWatch debugger, with in-circuit, ROM monitor, RTOS-aware debugging and real-time non-invasive

trace capability

• Metaware High C/C++ compiler, highly optimized for the PowerPC processors

Debug

The STB03xxx facilitates development through its JTAG test access port.

With IBM RISCWatch or other third-party debugger on a workstation, you can single-step the processor and

interrogate the internal processor state.

Additionally, the real-time debug port supports tracing the executed instruction stream out of the instruction

cache. The trace status signals provide trace information in real-time instruction trace debug mode. This

mode does not alter the performance of the processor.

Third-Party Tool Support

Through the IBM PowerPC Embedded Tools Program, you have access to hundreds of tools offered by over

75 industry-leading vendors. Often, the tools you currently use support PowerPC embedded processor prod-

ucts, such as the IBM STB010XX Digital Set-Top Box Integrated Controllers. For a list of the tools that are

offered, visit IBM’s tool support Web page at:

http://www.chips.ibm.com/products/powerpc/tools/

Note: This document contains information on products in the sampling and/or initial production phases of

development. This information is subject to change without notice. Verify with your IBM field applications

engineer that you have the latest version of this document before finalizing a design.

STB03_sds_041800.fm.01

April 18, 2000

Development Support

Page 53 of 55

Revision Log

Revision

Contents of Modiﬁcation

March 24, 2000

March 31, 2000

April 11, 2000

April 18, 2000

Initial Release (revision 00).

Update to GPIO table (revision 01).

Update to Video Input Interface Timing diagram and table (revision 02).

Various corrections to figures and tables (revision 03).

IBM39STB032xx

IBM39STB034xx

Preliminary

STB032xx and STB034xx Digital Set-Top Box Integrated Controllers

Copyright and Disclaimer

Copyright International Business Machines Corporation 2000.

Printed in the United States of America February 2000

The following are trademarks of International Business Machines Corporation in the United States, or other countries, or

both:

IBM

IBM Logo

CoreConnect

PowerPC logo PowerPC 405

Dolby is a trademark of Dolby Laboratories.

Java and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the

United States and/or other countries.

Windows is a trademark of Microsoft Corporation in the United States and/or other countries.

Other company, product, and service names may be trademarks or service marks of others.

All information contained in this document is subject to change without notice. The products described in this document

are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death

to persons. The information contained in this document does not affect or change IBM's product specifications or warran-

ties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property

rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is pre-

sented as an illustration. The results obtained in other operating environments may vary. Product name is subject to

change.

While the information contained herein is believed to be accurate, such information is preliminary, and should not be

relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.

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STB03_sds_041800.fm.01

April 18, 2000

STB03_sds_041800.fm.01

April 18, 2000

Revision Log

Page 55 of 55


型号：	IBM39STB03411PBB06C
厂家：	IBM
描述：	Consumer Circuit, CMOS, PBGA304, PLASTIC, BGA-304 商用集成电路
文件：	总55页 (文件大小：642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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