IC-MR_技术文档

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 1/44

FEATURES

APPLICATIONS

♦ Fast position decoding for

safety-oriented encoder systems

♦ Motor feedback systems

♦ Fast 13-bit sine-to-digital conversion within 2 µs

♦ Precision PGA for differential and single-ended signals of

up to 500 kHz

♦ Voltage or current input mode with signal monitoring

♦ Adjustable signal conditioning for offset, amplitude, and phase

♦ Input signal stabilization through LED or MR bridge current

control of up to 50 mA

♦ 8-bit parallel and serial I/O interfaces (BiSS, SSI, and SPI)

♦ Absolute data interface (ADI: BiSS/SSI) for position preset

♦ Period counter of up to 50 bits with selectable

singleturn/multiturn splitting

♦ Position data preset using ST/MT offset registers

♦ 12-bit A/D converter for temperature sensing

♦ Special functions for safety applications (signal monitoring, life

counter, and extended CRC)

PACKAGES

♦ Current-limited, differential 1 Vpp sine/cosine outputs to 100 Ω

♦ Device conﬁgurable through I/O interfaces or a serial

EEPROM

QFN48 7x7

♦ Single-sided 5 V operation from -40 to +110 °C

BLOCK DIAGRAM

TMS T0

T1

T2

ACO

VDD

VDDA

SIGNAL CONDITIONING

U / U

Conditioning

PSO

NSO

PSI

NSI

I / U

U / U

Conditioning

I / U

VREF

PCI

SIN ²+ COS²= 1

Amplitude

Control

Filter

U / U

PCO

NCO

I / U

NCI

U / U

Conditioning

I / U

SCL

SDA

ASLI

ABSOLUTE DATA

INTERFACE

(ADI)

iC-MR

AMAO

PERIOD COUNTER

INTERPOLATOR

EEPROM

INTERFACE

37...34-bit

13-bit

SAFETY

RESET

NERR

FEATURES

OFFSET

NRES

REGISTER

Configuration / CRC

Error Monitor

Life Counter

SERIAL I/O INTERFACE

BiSS SSI SPI

12-bit

ADC

PARALLEL I/O INTERFACE

A/D CONVERTER

D7 D6 D5 D4 D3 D2 D1 D0

NWR

NRD NL NCS

MAI

SLO

SLI

GND

GNDA

http://www.ichaus.com

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 2/44

DESCRIPTION

Device iC-MR is a universal sine-to-digital converter The control unit operating limits are also monitored

with signal conditioning and various interfaces for so that an alarm can be signaled through the I/O in-

conﬁguration and data communication. Microcon- terface and/or at error output NERR, depending on

trollers can be connected up through a parallel I/O the conﬁguration, with dirt or ageing of optical sys-

interface with an 8-bit bus width (12.5 MHz) or using tems.

a serial I/O interface (4-pin SPI, 20 MHz). The serial

I/O interface can function as a sensor interface either Sine-to-digital conversion is performed by a fast inter-

in BiSS C protocol (up to 10 MHz, bidirectional) or in polator with a sample-&-hold circuit which resolves a

SSI protocol (up to 4 MHz).

sine period with 13 bits either continuously or on re-

quest. In parallel and independent of the interpola-

In the analog signal path iC-MR has precision input tor a conﬁgurable 37-bit period counter logs the sine

ampliﬁers with an adjustable gain for differential or and cosine zero crossings. This period counter is

referenced voltage signals of 10 mV peak to 1 V peak programmable and can take its start value from the

or for current signals of approx. 10 µA to 300 µA (in- serial absolute data interface (ADI); the correspond-

put pins PSI, NSI, PCI, and NCI). A separate mea- ing interface master operates either in BiSS C or SSI

surement input (VREF) enables signals to be refer- protocol.

enced to the sensor’s reference voltage.

For position measurement applications iC-MR differ-

The downstream signal conditioning unit can com- entiates between multiturn and singleturn data using

pensate for typical sine/cosine sensor signal errors, a selectable intersection on the period counter. The

such as offset, amplitude, and phase errors. The position can be corrected accordingly using the mul-

conditioned signals are ﬁltered and output through titurn and singleturn offset values.

analog line drivers with an amplitude of typically

250 mV (output pins PSO, NSO, PCO, and NCO). A An integrated 12-bit A/D converter digitizes linear

differential 1 Vpp signal to 100 Ω is available for line measurement voltages at pin ADC for the evaluation

transmission.

of KTY temperature sensors, for example. Measure-

ment of the calibratable converter is observed by set-

A control signal is gained from the conditioned sig- table threshold values so that a permissible operating

nals to stabilize the sine/cosine output signals. This temperature range with a lower and upper tempera-

can adjust the transmitting LED of optical encoder ture threshold can be monitored.

systems using the integrated 50 mA driver stage (out-

put ACO). With magnetic sensors this driver output After power-on iC-MR collects its CRC protected

supplies the MR measuring bridges or can be used conﬁguration data from an external I²C-EEPROM or

to feedback the bridge supply voltage. By tracking waits for the conﬁguration from one of the I/O inter-

the sensor supply, sensor temperature and ageing ef- faces. An undervoltage reset zeroes internal reg-

fects are compensated for, the input signals are sta- isters and is shown as a reset pulse at pin NRES,

bilized, and precise calibration of the input signals is which also serves as a reset input (low active).

maintained. This makes a constant interpolation ac-

curacy possible across the entire operating tempera- Errors can always be masked and allocated to an

ture range.

error byte (and displayed at error message output

NERR) or a warning byte. The internal status reg-

At the same time the sensor is monitored for proper isters are available to the I/O interfaces which have a

functioning. The amplitude and offset of the input sig- number of different commands (software reset, mem-

nals at pins PSI, NSI, PCI, and NCI are checked, en- ory veriﬁcation, and error simulation).

abling wire-breakage or short circuits to be detected.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 3/44

CONTENTS

PACKAGING INFORMATION

4

Acquiring position data . . . . . . . . . . . . . 28

EEPROM INTERFACE 29

PIN CONFIGURATION QFN48-7x7

(topview) . . . . . . . . . . . . . . . . .

4

5

6

Address range . . . . . . . . . . . . . . . . . 29

Accessing external memory banks . . . . . . 30

Startup and selection of I/O interface . . . . . 30

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

PARALLEL I/O INTERFACE

31

ELECTRICAL CHARACTERISTICS

Reading out registers . . . . . . . . . . . . . 31

Writing to registers . . . . . . . . . . . . . . . 31

Reading out position data . . . . . . . . . . . 31

OPERATING CONDITIONS:

PARALLEL I/O INTERFACE

11

OPERATING CONDITIONS:

SERIAL I/O INTERFACE

SERIAL I/O INTERFACE: BiSS C

34

12

14

15

18

Conﬁguration . . . . . . . . . . . . . . . . . . 34

Register communication . . . . . . . . . . . . 35

Commands . . . . . . . . . . . . . . . . . . . 35

Conﬁguration examples . . . . . . . . . . . . 35

CONFIGURATION PARAMETERS

REGISTER MAP

SERIAL I/O INTERFACE: SSI

36

OPERATING MODES

Conﬁguration . . . . . . . . . . . . . . . . . . 36

Conﬁguration examples . . . . . . . . . . . . 36

Calibration modes . . . . . . . . . . . . . . . 18

BIAS CURRENT SOURCE AND SIGNAL

FILTER

18

SERIAL I/O INTERFACE: SPI

37

Bias current source . . . . . . . . . . . . . . . 18

Signal ﬁlter . . . . . . . . . . . . . . . . . . . 18

Register access . . . . . . . . . . . . . . . . 37

Cyclic readout . . . . . . . . . . . . . . . . . 37

SIGNAL CONDITIONING

19

ABSOLUTE DATA INTERFACE (ADI)

SAFETY FEATURES

37

40

Input conﬁguration . . . . . . . . . . . . . . . 19

Gain settings SIN and COS . . . . . . . . . . 20

Offset calibration SIN and COS . . . . . . . . 20

Phase correction SIN vs. COS . . . . . . . . 21

Diagnostic data . . . . . . . . . . . . . . . . . 22

CRC Veriﬁcation . . . . . . . . . . . . . . . . 40

Safety register . . . . . . . . . . . . . . . . . 40

Status and command register . . . . . . . . . 41

Error mask . . . . . . . . . . . . . . . . . . . 41

Life counter . . . . . . . . . . . . . . . . . . . 42

AMPLITUDE CONTROL

23

12-BIT A/D CONVERTER

24 DESIGN REVIEW: Application notes

26 REVISION HISTORY

43

INTERPOLATOR AND CYCLE COUNTER

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 4/44

PACKAGING INFORMATION

PIN CONFIGURATION QFN48-7x7

(topview)

PIN FUNCTIONS

No. Name Function

13 D7

14 D6

15 D5

16 D4

17 D3

18 D2

19 D1

20 D0

Par. Interface, data line

21 NWR Par. Interface, write signal*

22 NRD Par. Interface, read signal*

23 NL

Par. Interface, storage signal*

Ser. Interface, data acquisition*

24 NCS Par. Interface, chip select*

Ser. Interface, chip select*

25 MAI

26 SLO Ser. Interface, data output

27 SLI Ser. Interface, data input

Ser. Interface, clock input

28 ASLI Absolute Data Interface, data input

29 AMAO Absolute Data Interface, clock output

30 TMS Test Mode Selection Input

31 NRES Reset Signal, input/indication output*

32 n.c.

33 T2

Test Pin

34 n.c.

35 ADC 12-bit ADC Input, temperature sensor

36 n.c.

PIN FUNCTIONS

No. Name Function

37 T0

38 T1

39 n.c.

40 NSI

41 PSI

Test Pin

1 ACO Signal Level Controller, high-side current

source output

2 VDDA +5V Supply Voltage, analog

3 GNDA Ground, analog

Sine Input, inverted

Sine Input

42 VREF Reference Voltage, input/output

4 PSO Sine Output

5 NSO Sine Output, inverted

6 PCO Cosine Output

43 PCI

44 NCI

45 n.c.

46 n.c.

47 n.c.

48 n.c.

Cosine Input

Cosine Input, inverted

7 NCO Cosine Output, inverted

8 NERR Error Signal, input/indication output*

9 VDD +5V Supply Voltage, digital

10 GND Ground, digital

11 SDA EEPROM Interface, data line I²C

12 SCL EEPROM Interface, clock line I²C

n.c.:

Pin is not connected.

*) Pin is low active.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 5/44

ABSOLUTE MAXIMUM RATINGS

Beyond these values damage may occur; device operation is not guaranteed.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

-0.3

Max.

G001 VDDA

G002 VDD

G003 V()

Voltage at VDDA

Voltage at VDD

6

V

Voltage at ACO, PSO, NSO, PCO,

NCO, NERR, SDA, SCL, D(7...0),

NWR, NRD, NL, NCS, MAI, SLO, SLI,

ASLI, AMAO, TMS, NRES, ADC, PSI,

NSI, VREF, PCI, NCI

VDDA

+0.3

G004 I(VDDA)

G005 I(VDD)

G006 Vd()

Current in VDDA

-100

400

100

2

mA

kV

Current in VDD

ESD Susceptibility at all pins

HBM 100 pF discharged through 1.5 kΩ, all

pins versus GNDA

G007 Tj

G008 Ts

Chip Temperature

-40

150

°C

Storage Temperature

THERMAL DATA

Item Symbol

No.

Parameter

Conditions

Unit

Min. Typ. Max.

-40 110

T01 Ta

Operating Ambient Temperature Range package QFN48

°C

T02 Rthja

Thermal Resistance

Chip to Ambient

QFN48 soldered to PCB according to

JEDEC 51

30

K/W

All voltages are referenced to ground unless otherwise stated.

All currents ﬂowing into the device pins are positive; all currents ﬂowing out of the device pins are negative.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 6/44

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

General

001 VDDA,

VDD

Permissible Supply Voltage

4.5

5

5.5

V

002 I(VDDA)

003 I(VDD)

VDDA Supply Current

VDD Supply Current

Clamp Voltage hi

at digital inputs ASLI, SLI, MAI, I() = 4 mA

NCS, NL, NRD, NWR, NRES,

NERR, SDA, SCL, TMS

25

5

50

mA

V

004

Vc()hi

Vc()hi = V() - V(VDD),

0.3

1.2

005

Vc()hi

Clamp Voltage hi

at digital inputs D(7...0)

Vc()hi = V() - V(VDD),

I() = 1.6 mA

1.2

11

V

006 Vcz()hi

007 Vc()lo

Clamp Voltage hi

I() = 4 mA

at ACO, VDDA, PSO, NSO, PCO,

NCO, AMAO, SLO, ADC, PSI,

NSI, VREF, PCI, NCI

Clamp Voltage lo

I() = -4 mA

-1.2

-0.3

V

at ACO, VDDA, PSO, NSO, PCO,

NCO, AMAO, SLO, ADC, PSI,

NSI, VREF, PCI, NCI

Bias Current Source, Reference Voltages, Input/Output VREF

101 IBP

102 VPAH

103 V05

Bias Current Source

IBP calibrated to 200 µA

referenced to GNDA

92.5

45

100

50

107.5

55

%

Reference Voltage VPAH

Reference Voltage V05

Internal Ref. Voltage VREFI

%VDDA

mV

450

500

550

104

VREFI

DCPOS = 1

DCPOS = 0

1.35

2.25

1.5

2.5

1.65

2.75

V

105 Vin()

106 Rin()

Permissible Input Voltage at

VREF

SELREF = 0x3

0.5

VDDA

− 2

30

V

Input Resistance at VREF

SELREF = 0x3, REFVOS = 0x3, UIN = 1,

TUIN = 0, Rin() referenced to VREFin()

20

26

kΩ

107 Vref()out

108 I0()

Output Voltage at VREF

Leakage Current at VREF

SELREF = 0x2, I() = 0

SELREF = 0x0 or 0x1

100

%VREFI

µA

-1

+1

12-bit A/D Converter, Measuring Input ADC

601 RESOadc A/D Converter Resolution

12

bit

602 t()adc

603

A/D Conversion Time

1.1

ms

Vin()FS

Maximum Full Scale Input

Voltage

ADCSLOP = 0xFF

ADCSLOP = 0x00

2.5

2.0

V

604 INL()

A/D Conversion Nonlinearity

±0.95

LSB

Signal Conditioning, Inputs: PSI, NSI, PCI, NCI

701

Vin()sig

Permissible V Mode Input Voltage

UIN = 1, TUIN = 0

0.75

-0.1

VDDA

− 1.5

VDDA

+ 0.1

V

UIN = 1, TUIN = 1, DCPOS = 1

702 Iin()

703 Rin()

V Mode Input Current

UIN = 1, TUIN = 0

-100

16.4

100

nA

V Mode Input Resistance

Permissible I Mode Input Current

UIN = 1, TUIN = 1, vs. VREFin, Tj = 27 °C,

20

23.6

kΩ

704

Iin()sig

UIN = 0, DCPOS = 0

UIN = 0, DCPOS = 1

-300

10

-10

300

µA

705 CTR()sig Permissible Signal Contrast Ratio current ratio of Iin()pkpk vs. Iin()dc

0.125

1

706

Rin()

I Mode Input Resistance

Tj = 27 °C, vs. VREFin;

UIN = 0, RIN = 00

UIN = 0, RIN = 01

UIN = 0, RIN = 10

UIN = 0, RIN = 11

1.1

1.6

2.2

3.2

1.6

2.3

3.2

4.6

2.1

3.0

4.2

6.0

kΩ

707 TC(Rin)

708 Vin()os

Temperature Coefﬁcient of Rin

Offset Voltage of Input Stage

0.15

%/K

µV

referenced to side of input;

300

GR = 0x4, GFC = 0x1F, GFS = 0x7C0

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 7/44

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

709

Vin()diff

Recommended Differential Input

Voltage

Vin()diff = V(PSI) − V(NSI), respectively

Vin()diff = V(PCI) − V(NCI);

TUIN = 0

20

80

1000

4000

mVpp

TUIN = 1

710 Vcore()

711

Recommended Internal Signal

Level

G * Vin()diff, MODE = 0x01

6

Vpp

GF, GC

Selectable Gain Factors

TUIN = 0

TUIN = 1

2

0.5

100

25

712 ∆GFdiff

713 ∆GFabs

Differential Gain Accuracy

Absolute Gain Accuracy

referenced to ﬁne gain range (GFS, GFC)

-1

1

LSB

referenced to ﬁne gain range (GFS, GFC),

guaranteed range of monotony

-20

20

714 ∆GRabs Gain Accuracy

referenced to coarse gain range (GR)

-8

8

%

715

716

717

718

VOScal1

VOScal2

VOScal3

VOScal4

Offset Calibration Range

measured at output, source V(ACO) = 3 V,

REFVOS = 00, MODE =0x01;

ORS, ORC = 00

ORS, ORC = 01

ORS, ORC = 10

±450

±900

±2700

±5400

mV

ORS, ORC = 11

measured at output, source V05,

REFVOS = 01, MODE = 0x01;

ORS, ORC = 00

ORS, ORC = 01

ORS, ORC = 10

±1500

±3000

±9000

±18000

mV

ORS, ORC = 11

measured at output, source V025,

REFVOS = 10, MODE = 0x01;

ORS, ORC = 00

ORS, ORC = 01

ORS, ORC = 10

±750

±1500

±4500

±9000

mV

ORS, ORC = 11

measured at output, source VDC = 125 mV,

REFVOS = 11, MODE = 0x01;

ORS, ORC = 00

ORS, ORC = 01

ORS, ORC = 10

±375

±750

±2250

±4500

mV

ORS, ORC = 11

719 ∆VOSdiff Differential Linearity Error of

-0.5

0.5

LSB

Offset Correction

720 ∆VOSint Integral Linearity Error of Offset

-100

100

LSB

Correction

721 PHIcal

Phase Correction Range

sine vs. cosine signal

±10.4

°

722 ∆PHIdiff

Differential Linearity Error of

Phase Correction

-0.25

-20

0.25

20

LSB

723 ∆PHIint

Integral Linearity Error of Phase

Correction

LSB

kHz

724

ﬁn()max

Permissible Input Frequency

angle accuracy better 8 bit

500

250

725 fhc()

Input Ampliﬁer Cut-off Frequency

(-3 dB)

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 8/44

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Amplitude Control, Output ACO

801

Vs()hi

Saturation Voltage hi

Vs()hi = VDD − V();

ACOR = 00, I() = -5 mA

ACOR = 01, I() = -10 mA

ACOR = 10, I() = -25 mA

ACOR = 11, I() = -50 mA

1

V

802

Isc()hi

Short-Circuit Current hi in ACO

V() = 0 V ... VDD − 1 V;

ACOR = 00

-10

-20

-50

-5

mA

ACOR = 01

ACOR = 10

ACOR = 11

-10

-25

-50

-100

803 tr()

Rise Time Current Source ACO I(ACO): 0 % → 90 % of setpoint

1

ms

µs

804

tset()

Settling Time Current Source

ACO

square control active,

400

I(ACO): 50 % → 100 % of setpoint

Vscq() = Vpp(V(PSO) - V(NSO)), respectively

Vscq() = Vpp(V(PCO) - V(NCO));

ACOC = 0x19

805

Vscq()

Regulated Mean Target

Amplitude with Square Control

500

mV

806

Vdc()

Regulated Mean Setpoint with

Sum Control

ACOD = 0x00

ACOD = 0x7F

166

551

mV

807 It()min

808 It()max

809 Vt()min

810 Vt()max

Signal Filter

Monitoring of ACO Output Cur-

rent, lower threshold

referenced to current range ACOR

referenced to Vscq()

3

%Isc

%

Monitoring of ACO Output Cur-

rent, upper threshold

90

Monitoring of Signal Level 1,

lower threshold

40

Monitoring of Signal Level 2,

upper threshold

referenced to Vscq()

135

%

901

fc()

Cut-off Frequency

Phase Shift

ENF = 1, SELBP = 0; ﬁn < 10 Hz

ﬁn > 100 kHz

15

2400

kHz

902

PHI()

ENF = 1, SELBP = 0,

1.5

°

ﬁn = 100 kHz for sine and cosine

Analog Outputs PSO, NSO, PCO and NCO

A01

Vpk()max Permissible Maximum Output

Amplitude

VDDA = 4.5 V, DC level VDDA/2,

RL = 50 Ω vs. VDDA/2

300

275

mV

A02 Vpk()

Output Amplitude with Sensor

Tracking by Output ACO

ACOC = 0x19

CL = 250 pF

225

500

250

A03 fc

Cut-off Frequency

kHz

µV

A04 Vos

Output Offset Voltage

Short-Circuit Current hi

Short-Circuit Current lo

Slew Rate

±200

-20

20

A05 Isc()hi

A06 Isc()lo

A07 SR()

A08 Rout()

A09 fout()cal

V() = 0 V

-40

15

-15

40

mA

V/µs

kΩ

V() = VDD

RLdiff = 100 Ω, CL = 25 pF

MODE = 0x01 (Analog 1)

MODE = 0x01 (Analog 1), CL = 200 pF

5

Test Signal Source Resistance

5

Permissible Test Signal Output

Frequency

2

kHz

Signal Level Monitoring

B01 Vpp()max Signal Level Monitoring,

upper threshold

referenced to target amplitude of converter and

analog output, see Figure 1

110

10

150

50

%Vpp

mV

B02 Vpp()min Signal Level Monitoring,

lower threshold

referenced to target amplitude of converter and

analog output, see Figure 1

B03 Vpp()hys Signal Level Monitoring,

Hysteresis

referenced to Vpp()min, Vpp()max

referenced to VPAH, see Figure 2

30

140

70

B04 Vdc()max Mean Value Monitoring,

upper threshold

120

50

%VPAH

B05 Vdc()min Mean Value Monitoring,

lower threshold

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 9/44

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

13-bit Interpolator

C01 tipo

Conversion Time

ACQMODE = 00, see Figure 5

Vpk() = 250 mV

2

µs

C02 AAabs

Absolute Conversion Accuracy

LSB

Reset Input / Reset Indication Output NRES

K01 VDDon

K02 VDDoff

K03 VDDhys

K04 Vt()hi

K05 Vt()lo

K06 Vt()hys

K07 Ipu()

VDD Turn-on Threshold

VDD Turn-off Threshold

VDD Hysteresis

increasing voltage at VDD vs. GND

decreasing voltage at VDD vs. GND

VDDhys = VDDon - VDDoff

2.6

2.3

400

4.3

4.0

V

mV

V

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

2

0.8

300

-750

V

Vt()hys = Vt()hi - Vt()lo

500

mV

µA

mV

mA

Pull-up Current

-300

-60

400

80

K08 Vs()lo

K09 Isc()lo

Oscillator

Output Saturation Voltage lo

Output Short-Circuit Current lo

I() = 4 mA

V() = 0.4 V...VDD

4

M01 fosc

Internal Oscillator Frequency

15

MHz

EEPROM Interface SCL, SDA

N01 Vs()lo

N02 Isc()

N03 Vt()hi

N04 Vt()lo

N05 Vt()hys

N06 Ipu()

N07 Vpu()

N08 fclk()

Saturation voltage lo

I() = 4 mA

400

80

2

mV

mA

V

Short-Circuit Current lo

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

4

0.8

100

-750

V

Vt()hys = Vt()hi - Vt()lo

V() = 0 V...VDD - 1 V

250

mV

µA

V

Input Pull-up Current

-300

-60

0.4

Input Pull-up Voltage

Vpu() = VDD - V(), I() = -5 µA

Clock Frequency at SCL

100

120

130

kHz

N09

tbusy()cfg Duration of Conﬁguration Phase

IBP not adjusted;

read in of EEPROM

no EEPROM connected

5

1

ms

Serial Interface MAI, SLO, SLI

O01 Vt()hi

O02 Vt()lo

O03 Vt()Hys

O04 Ipu()

O05 Ipd()

Threshold Voltage hi at SLI, MAI

2

V

Threshold Voltage lo at SLI, MAI

Hysteresis at SLI, MAI

0.8

300

-150

8

Vt()hys = Vt()hi - Vt()lo

500

-60

60

mV

µA

Pull-up Current at MAI

-8

Pull-down Current at SLI

150

O06

fclk()

Permissible Clock Frequency at

MAI

SSI protocol

BiSS C protocol

SPI

4

10

MHz

O07 tp()

Propagation Delay at SLO versus

Clock Edge MAI

10

50

ns

O08 tbusy()

Processing Time

Adaptive Timeout

ACQMODE = 00, see Figure 5

t()ipo

O09

t_timeout

1/fosc

1.5*t_MAS

+

3/fosc

O10 Vs()hi

O11 Vs()lo

O12 Isc()hi

O13 Isc()lo

Saturation Voltage hi at SLO

Saturation Voltage lo at SLO

Short-circuit Current hi at SLO

Short-circuit Current lo at SLO

Vs()hi = VDD - V(), I() = -4 mA

I() = 4 mA

400

-4

mV

mA

V() = 0 V...VDD - 0.4 V

V() = 0.4 V...VDD

-80

4

80

Parallel Interface D(7...0), NWR, NRD, NL, NCS

P01 Vt()hi

P02 Vt()lo

P03 Vt()hys

P04 Ipu()

Threshold Voltage hi

Threshold Voltage lo

Input Hysteresis

D(7...0) as input

2

V

D(7...0) as input

0.8

300

-70

D(7...0) as input, Vt()hys = Vt()hi - Vt()lo

500

-30

mV

µA

Pull-up Current at D(7...0)

-5

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 10/44

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

P05 Ipu()

Pull-up Current at NWR, NRD,

NL, NCS

-150

-60

-8

µA

mV

mA

P06

Vs()hi

Saturation Voltage hi

at D(7...0) Outputs

Vs()hi = VDD - V(), I() = -1.6 mA

I() = 1.6 mA

400

-1.6

50

P07 Vs()lo

P08 Isc()hi

P09 Isc()lo

Saturation Voltage lo

at D(7...0) Outputs

Short-circuit Current hi

at D(7...0) Outputs

V() = 0 V...VDD - 0.4 V

V() = 0.4 V...VDD

-50

1.6

Short-circuit Current lo

at D(7...0) Outputs

Absolute Data Interface ASLI, AMAO

Q01 Vt()hi

Q02 Vt()lo

Q03 Vt()hys

Q04 Ipu()

Threshold Voltage hi at ASLI

2

V

Threshold Voltage lo at ASLI

Hysteresis at ASLI

0.8

300

-150

V

Vt()hys = Vt()hi - Vt()lo

500

-60

mV

µA

mV

mA

Pull-up Current at ASLI

-8

Q05 Vs()hi

Q06 Vs()lo

Q07 Isc()hi

Q08 Isc()lo

Saturation Voltage hi at AMAO

Saturation Voltage lo at AMAO

Vs()hi = VDD - V(), I() = -1.6 mA

I() = 1.6 mA

400

-1.6

50

Short-circuit Current hi at AMAO V() = 0 V...VDD - 0.4 V

Short-circuit Current lo at AMAO V() = 0.4 V...VDD

-50

1.6

Q09

fclk()

Clock Frequency at AMAO

GET_ADI = 0, SSI_ADI = 1 (SSI protocol)

GET_ADI = 0, SSI_ADI = 0 (BiSS C protocol)

1/16

1/2

fosc

Error Signal Input/Output NERR

R01 Vt()hi

R02 Vt()lo

R03 Vt()hys

R04 Ipu()

Threshold Voltage hi

2

V

Threshold Voltage lo

Input Hysteresis

0.8

100

-750

V

Vt()hys = Vt()hi - Vt()lo

150

mV

µA

mV

mA

Pull-up Current

-300

-60

400

60

R05 Vs()lo

R06 Isc()lo

Saturation Voltage lo

Short-circuit Current lo

I() = 4 mA

V() = 0.4 V...VDD

4

1 Vpp

V(PCOS) - V(NCOS)

V(PSIN) - V(NSIN)

90°

VDDA

Vdc()max

180°

0°

φ

V(PSIN)

V(PCOS)

V(NCOS)

V(NSIN)

270°

0°

270°

360°

90°

180°

Vdc()min

0V

Vpp()min

Vpp()max

Figure 1: Differential voltage thresholds for maximum Figure 2: Maximum and minimum voltage thresholds

and minimum alarm for DC check

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 11/44

OPERATING CONDITIONS: PARALLEL I/O INTERFACE

Operating conditions: VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

I001 t_sAW

I002 t_hWA

I003 t_sDW

I004 t_hWD

I005 tWL

I006 tRL

Setup Time:

addresses stable before NWR hi → lo

Hold Time:

addresses stable after NWR lo → hi

Setup Time:

data stable before NWR hi → lo

Hold Time:

data stable after NWR lo → hi

Signal Duration:

NWR at low level

50

80

50

80

ns

Signal Duration:

NRD at low level

I007 t_pRD1

I008 t_pRD2

I009 tWW

I010 tWR

Propagation Delay:

data stable after NRD hi → lo

Propagation Delay:

data bus high ohmic after NRD lo → hi

Signal Duration:

between NWR lo → hi and hi → lo

Signal Duration:

CL = 10 pF

between NWR lo → hi and NRD hi → lo

or NRD lo → hi and NWR hi → lo

I011 tRR

I012 tCL

Signal Duration:

80

ns

between NRD lo → hi and hi → lo

Signal Duration:

between NCS hi → lo and NRD hi → lo

or NCS hi → lo und NWR hi → lo

Signal Duration:

I013 tCH

80

ns

between NRD lo → hi and NCS lo → hi

NCS

tCH

tCL

ADDRESS

DATA_IN

DATA_OUT

D(7:0)

NWR

NRD

t AW

h

t DW

s

t DW

h

t RD1

p

t RD2

p

t AW

s

tWL

tWW

tWR

tRL

tRR

Figure 3: Parallel interface timing.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 12/44

OPERATING CONDITIONS: SERIAL I/O INTERFACE

Operating conditions: VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA Tj = -40...125 °C

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

SSI protocol (INTCFG = 00, NESSI = 0)

I111 t_MAS

I112 t_MASh

I113 t_MASl

I114 t_req

Permissible Clock Period

250

125

ns

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

REQ Signal Lo Level Duration

BiSS C protocol (INTCFG = 00, NESSI = 1)

I115 t_MAS

I116 t_MASh

I117 t_MASl

Permissible Clock Period

100

50

ns

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

50

SPI protocol (INTCFG = 10)

I118 t_MAS

I119 t_MASh

I120 t_MASl

I121 t_CL

Permissible Clock Period

100

50

ns

Clock Signal Hi Level Duration

Clock Signal Lo Level Duration

50

Signal Duration:

50

between NCS hi → lo and MAI hi → lo

Signal Duration:

I122 t_CH

50

ns

between MAI lo → hi and NCS lo → hi

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 13/44

t

MAS

req

REQ

MAI

DATA

SLO

t

timeout

t

pMASLO

MASh MASl

Figure 4: SSI protocol timing.

MAI

START

DATA

SLO

t

busy

Figure 5: BiSS C protocol timing with conversion time t()IPO (ACQMODE = 00)

t

MAS

MAI

START

DATA

SLO

t

timeout

t

pMASLO

MASh MASl

t

timeout

Figure 6: BiSS C protocol timing without conversion time t()IPO (ACQMODE = 00)

NCS

MAI

SLI

SLO

t

MAS

t

CH

t

CL

MASh

MASl

Figure 7: SPI protocol timing.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 14/44

CONFIGURATION PARAMETERS

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . Page 29

CFG_E2P

BSEL

INTCFG

EDS range selection

Bank selection

Interface selection

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18

MODE Operating mode

Bias Current Source and Filter . . . . . . . . . . . . page 18

Parallel I/O Interface . . . . . . . . . . . . . . . . . . . . . . Page 31

FULL_CYC Cyclic telegram length

CFGBIAS

ENF

SELBP

NEFDR

Bias calibration

Signal ﬁlter activation

Signal ﬁlter cut-off frequency

Signal ﬁlter dead band

Serial I/O Interface: BiSS C . . . . . . . . . . . . . . . Page 34

NESSI

ENLC

SSI protocol selection

Life counter enable

Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . page 19

INMODE

Input mode

ENXCRC

CRCS

TMPSCD

Extended CRC protection

CRC start value

Temperature data enable (BiSS)

differential/single-ended

Current/voltage operation

Input resistance

UIN

RIN

TUIN

DCPOS

SELREF

GR

GFS

GFC

Input voltage divider

Reference voltage input

Input reference voltage selection

Coarse gain

Fine gain sine

Fine gain cosine

Serial I/O Interface: SSI . . . . . . . . . . . . . . . . . . . Page 36

NESSI

SSI protocol selection

SSI ring mode selection

SSI with error bit

SSIRING

SSIERR

SSIMODE

SSI protocol options

REFVOS

MPS

MPC

ORS

ORC

OFS

OFC

PH

DIAG

Offset reference source

Center potential sine

Center potential cosine

Offset adjustment range sine

Offset adjustment range cosine

Offset adjustment sine

Offset adjustment cosine

Phase correction sin/cos

Diagnosis register

Serial I/O Interface: SPI . . . . . . . . . . . . . . . . . . . Page 37

Absolute Data Interface (ADI) . . . . . . . . . . . . . Page 38

STP_ADI

CYC_ADI

DL_ADI

Startup with absolute data

Cyclic reading of absolute data

Data length absolute data interface

Synchronisation bits absolute data in-

terface

SYNC_ADI

SSI_ADI

GET_ADI

Protocol of absolute data interface

BiSS chain with absolute data inter-

face

Amplitude Control . . . . . . . . . . . . . . . . . . . . . . . . Page 23

ACOT

ACO Output control mode

ACO Output current range

Setpoint square control (amplitude)

Setpoint sum control (DC value)

Control mode

ACOR

ACOC

ACOD

LCMODE

CHK_ADI

Cyclic check of absolute data

Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 40

CRCCFG

NRDOK

SEC_HI

CRC test value of conﬁguration

Selection of read/write protection

Safety register for conﬁguration sec-

tion

Safety register for EDS memory sec-

tion

12 bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . Page 24

ADCSLOP

ADCOFF

TEMPHI

Maximum ADC input voltage

Digital temperature offset

Upper temperature threshold

Lower temperature threshold

SEC_LO

TEMPLO

STATUS

CMD

ERROR

EMSK

Status byte

Command register

Error byte

Interpolator and Cycle Counter . . . . . . . . . . . Page 26

CODERES

DIR

Cycle counter resolution

Code inversion

Error mask

MTOFF

Multiturn offset

WMSK

Warning mask

STOFF

Singleturn offset

RES_ERR

THR_FAMP

TO_FAMP

EN_FAMP

Error reset

STRESO

MTRESO

ACQMODE

Singleturn resolution

Multiturn resolution

Position data acquisition

Amplitude error ﬁlter threshold

Amplitude error ﬁlter timeout

Amplitude error ﬁltering

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 15/44

REGISTER MAP

Conﬁguration and output data register

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Amplitude control (conﬁguration)

0x00

0x01

ACOT(0)

ACOR(1:0)

ACOC(4:0)

ACOD(6:0)

ACOT(1)

Signal conditioning (conﬁguration)

GFS(3:0)

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

LCMODE

GFS(10:4)

GR(2:0)

-

GFC(7:0)

MPS(3:0)

-

GFC(10:8)

-

MPS(9:4)

MPC(7:0)

ORS(1:0)

ORC(1:0)

-

MPC(9:8)

OFS(7:0)

OFC(7:0)

0

OFS(10:8)

OFC(10:8)

PH(3:0)

NEFDR

SELREF(1:0)

PH(9:4)

INMODE

DCPOS

CFGBIAS(3:0)

REFVOS(1:0)

TUIN

SELBP

0

RIN(1:0)

UIN

ENF

0

MODE(1:0)

0

1

0

12-bit A/D converter and temperature monitoring (conﬁguration)

0x11

0x12

0x13

0x14

0x15

0x16

0x17

ADCSLOP(7:0)

ADCOFF(7:0)

ADCOFF(15:8)

TEMPLO(7:0)

TEMPLO(15:8)

TEMPHI(7:0)

TEMPHI(15:8)

Interfaces (conﬁguration)

0x18

0x19

0x1A

INTCFG(1:0)

FULL_CYC

ENLC

GET_ADI

STP_ADI

ENXCRC

CYC_ADI

TMPSCD

SSIRING

SSIERR

ACQMODE(1:0)

NESSI

SSIMODE(1:0)

DL_ADI(4:0)

SYNC_ADI(1:0)

SSI_ADI

Offset & interpolator (conﬁguration)

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

STOFF(1:0)

0

DIR

CODERES(1:0)

STOFF(9:2)

STOFF(17:10)

STOFF(25:18)

MTOFF(7:0)

MTOFF(15:8)

MTOFF(23:16)

Mask register for error and warning (conﬁguration)

0x22

0x23

EMSK_EXT

EMSK_ABS

EMSK_IPO

WMSK_IPO

EMSK_KNF

EMSK_SYN

EMSK_TMP

EMSK_AMP

EMSK_RGL

WMSK_EXT WMSK_ABS

WMSK_KNF WMSK_SYN WMSK_TMP WMSK_AMP WMSK_RGL

Data resolution (conﬁguration)

0x24 MTRESO(2:0)

STRESO(4:0)

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 16/44

Conﬁguration and output data register

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Safety register (conﬁguration)

0x25

0x26

NRDOK

CFG_E2P(1:0)

SEC_HI(6:0)

SEC_LO(5:0)

CRC conﬁguration (conﬁguration)

0x27

0x28

0x29

0

CRCS(15:8)

CRCS(7:0)

Extended conﬁguration

0x2A

0x2B

0x2C

. . .

0

TO_FAMP

0

EN_FAMP

0

THR_FAMP(1:0)

0

CRC sum (EEPROM) (conﬁguration)

0x2E

0x2F

. . .

CRCCFG(15:8)

CRCCFG(7:0)

Bank select (conﬁguration)

0x40

-

BSEL(4:0)

Device data (conﬁguration)

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

. . .

EDSBANK(7:0)

PROFILE(15:8) (Position)

PROFILE(7:0) (Position)

SERIAL_ID(31:24)

SERIAL_ID(23:16)

SERIAL_ID(15:8)

SERIAL_ID(7:0)

PROFILE(15:8) (Temperature)

PROFILE(7:0) (Temperature)

Diagnostic data (output data)

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

RG_MAX

AMP_MAX

DC_MAX

CMP_MAX

RG_MIN

AMP_MIN

DC_MIN

CMP_MIN

reserved

Status byte / command register (output data)

0x60 INIT ERR WARN

Position (output data)

EWKH

EWKL

BUSY

ADV

PDV

0x61

0x62

0x63

0x64

0x65

0x66

0x67

ST(1:0)

-

ST(9:2)

ST(17:10)

ST(25:18)

MT(7:0)

MT(15:8)

MT(23:16)

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 17/44

Conﬁguration and output data register

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Life counter (output data)

0x68

LC(7:0)

Error byte (output data)

0x69

ERR_EXT

ERR_ABS

ERR_IPO

ERR_KNF

ERR_SYN

ERR_TMP

ERR_AMP

ERR_RGL

Temperature (output data)

0x6A

0x6B

TEMP(7:0)

TEMP(15:8)

CRC sum of output data (output data)

0x6C

0x6D

. . .

CRCPOS(7:0)

CRCPOS(15:8)

Device data (conﬁguration)

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

DEV_ID(47:40) (Temperature)

DEV_ID(39:32) (Temperature)

DEV_ID(31:24) (Temperature)

DEV_ID(23:16) (Temperature)

DEV_ID(15:8) (Temperature)

DEV_ID(7:0) (Temperature)

DEV_ID(47:40) (Position)

DEV_ID(39:32) (Position)

DEV_ID(31:24) (Position)

DEV_ID(23:16) (Position)

DEV_ID(15:8) (Position)

DEV_ID(7:0) (Position)

MNFCT_ID(15:8)

MNFCT_ID(7:0)

Table 6: Register map

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 18/44

OPERATING MODES

In order to calibrate iC-MR, to adjust the input signals, ing the register MODE. The output functions of PSO,

as well as to test iC-MR the operation mode must be NSO, PCO and NCO change according to the various

altered. The operating mode can be selected by us- operating modes.

MODE(1:0)

MODE(4:2)

ADR 0x0F; bit 1:0

ADR 0x10; bit 2:0

Code

0x00

0x01

0x02

0x03

0x04

...

Operating mode

Normal operation *

Analog 1

Analog 2

Bypass

Pin PSO

PSO

PS_W

SVDC

PSI

Pin NSO

NSO

NS_W

CVDC

NSI

Pin PCO

PCO

PC_W

VREFI

PCI

Pin NCO

NCO

NC_W

IBP

NCI

iC-Haus internal

0x1F

iC-Haus internal

Note: *) Measurement condition: ENOCC = 1, ENOCM = 1, TIIN = 0, TIPOL = 0, TLDOS = 0

Table 7: Operating mode

Calibration modes

rent source (IBP), reference potential input (VREFI),

In operation mode Analog 1 the adjusted sine and co- as well as center potentials of calibration circuits for

sine signals are being provided (PS_W, NS_W, PC_W sine (SVDC) and cosine (CVDC) can be measured.

und NC_W). In operation mode Analog 2 bias cur-

BIAS CURRENT SOURCE AND SIGNAL FILTER

Bias current source

Signal ﬁlter

The calibration of the bias current source in operating In order to decrease the adjusted analog signals’ noise

mode Analog 2 is required for adherence to the given iC-MR uses a signal ﬁlter which can be activated

Electrical Characteristics and instrumental in the deter- through register bit ENF.

mination of the chip timing (e.g. SCL clock frequency).

For adjusting the bias current source, the voltage drop

is being measured using a 10 kΩ resistor from pin NCO

to pin GNDA. The setpoint of 200 µA is reached with a

measurement voltage of 2 V.

ENF

Code

0

Addr 0x0F, bit 2

Function

Signal ﬁlter deactivated

Signal ﬁlter active

1

Table 9: Signal ﬁlter activation

Low pass cutoff frequencies can be adjusted using

SELBP.

SELBP

Addr. 0x0F; bit 3

Function

CFGBIAS Addr 0x0F, bit 7:4

Code

31

31−k

Code k

IBP ∼

Code k

(signed)

IBP ∼

31−k

0

1

7.5 kHz

15 kHz

(signed)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

100 %

103 %

107 %

111 %

115 %

119 %

124 %

129 %

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

79 %

81 %

84 %

86 %

88 %

91 %

94 %

97 %

Table 10: Signal ﬁlter cutoff frequency (ﬁn < 10 Hz)

The ﬁlter’s dead band can be activated using NEFDR.

NEFDR

Addr. 0x0C; bit 3

Function

Code

0

1

Filter dead band active

Table 8: Adjustment of bias current source

Filter dead band deactivated

Table 11: Signal ﬁlter dead band

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 19/44

SIGNAL CONDITIONING

Input conﬁguration

Signal adjustment is possible only in operating modes

All input stages are conﬁgured as instrumentation am- Analog 1 and Analog 2. Figure 8 shows the sine chan-

pliﬁers and thus directly suitable for differential input nel’s conditioning unit; the cosine channel’s set-up is

signals. Referenced input signals can be processed equivalent to it.

by applying the input signals’ reference voltage to neg-

ative inputs.

PSIN1

PSI

GFS

0.5 V

PSIN2

0.25 V

x

GR

OR

OF

0.05 x V(ACO)

VDC

NSIN2

NSIN1

NSI

GFS

VPAH

SVDC

k

VREF

SELREF

VREFI

Figure 8: Signal-conditioning unit (sine channel)

INMODE

Addr 0x0E, bit 7

are typical, refer to Electrical Characteristics for toler-

ances.

Code

Function

0

1

Differential input signals

Single-ended input signals

The input resistance should be set so that center po-

tentials SVDC and CVDC are between 125 mV and

250 mV (testable in operating mode Analog 2).

Table 12: Input mode differential/single-ended

Both voltage and current signals can be accepted as

input signals. For selection use register bit UIN.

RIN

Code

00

Addr 0x0E, bit 2:1

Nominal Rin() Internal Rui()

Mode

UIN

Code

0

Addr 0x0E, bit 0

Function

1.7 kΩ

2.5 kΩ

3.5 kΩ

4.9 kΩ

1.6 kΩ

2.3 kΩ

3.2 kΩ

4.6 kΩ

Current input

01

Current input

Voltage input

10

1

11

Table 13: Operating mode current/voltage

Table 14: Input resistance

In current mode an input restistor Rin() becomes ac-

tive at each input pin, converting the current signal into In voltage mode a voltage divider can be selected for

a voltage signal. The input resistance Rin() consists high input amplitudes. This voltage divider reduces the

of a pin resistor and the resistor Rui(), which is con- input signal’s amplitude to about 25%. The internal cir-

nected to the adjustable bias source VREFI. Tab. 14 cuit corresponds to the circuit in current mode, just the

shows the selection options. Indicated values of Rin() resistor connecting the pin is altered.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 20/44

1.5

TUIN

Code

0

Addr 0x0E, bit 3

Nominal Rin() Internal Rui()

Mode

high

Voltage input

impedance

1

20 kΩ

5 kΩ

Voltage input

Px

Nx

Table 15: Input voltage divider

VPNx

R0

VPx

DCPOS

Addr 0x0E, bit 6

VNx

Code

VREFI

2.5 V

Sensor type

GND

0

1

Lowside current drain (I Mode)

Highside current source (I Mode)

1.5 V

Figure 9: Measuring the differential signal ampli-

tudes

Table 16: Input reference voltage

3. Using ﬁne gain factor GFS the sine signal amplitude

is then adjusted to 6 Vpp.

Parameter DCPOS determines the input reference

voltage. In the generation of center potentials SVDC

and CVDC it also determines whether the reference

voltage VREFin() is being subtracted from the sum of

the particular input signals or the sum is being sub-

tracted from VREFin().

4. The cosine signal amplitude can then be adjusted

to the sine signal amplitude using ﬁne gain factor GFC.

GR

Addr 0x02, bit 2:0

Code

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Factor

2.0

Parameter SELREF conﬁgures the input voltage refer-

ence.

4.1

5.3

6.7

SELREF

Code

Addr 0x0D, bit 7:6

8.7

VREFin()

internal

external

Pin function VREF

10.5

13.2

16.0

0x0, 0x1

0x2

high impedance

Output*: output of VREFI

0x3

Input**: external reference

replaces VREFI

Table 18: Coarse gain

Notes

*) Do not load, buffer recommended.

**) See Elec.Char. No.105 for permissible input

voltage.

GFS

GFC

Code

0x000

0x001

...

Addr 0x03, bit 6:0, Addr 0x02, bit 7:4

Addr 0x05, bit 2:0, Addr 0x04, bit 7:0

Table 17: Input reference source selection

Factor

1.0

1.0009

6.25^(GFx/1984)

6.6245

Gain settings SIN and COS

The gain is set in four steps:

0x7FF

Table 19: Fine gain sine, cosine

1. The sensor supply controller is shut down and

the constant current source for the ACO output set to

a suitable output current (register ADJ; current value

close to the later operating point).

Offset calibration SIN and COS

In order to calibrate the offset the reference source

must ﬁrst be selected using register REFVOS. Two

ﬁxed voltages and two dependent sources are avail-

able for this purpose. The ﬁxed voltage sources should

be selected for external sensors which provide stable,

self-regulated signals.

2. The coarse gain range is selected so that differen-

tial signal amplitudes of ca. 6 Vpp are produced at the

core of the converter (signal PS_W versus NS_W and

PC_W versus NC_W).

So that photosensors can be operated in optical en-

coders iC-MR tracks changes in offset voltages via the

signal-dependent source VDC when used in conjunc-

The signals at the converter core output in calibration

mode Analog 1 are ampliﬁed by factor 3.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 21/44

tion with the controlled sensor current source for LED is reached when the DC rate of the differential signals

supply (output ACO). The VDC potential automatically V(PSO)-V(NCO) and V(PCO)-V(NCO) is zero.

tracks higher photocurrents. In order to use this func-

tion intermediate potentials SVDC and CVDC have to

ORS

ORC

Code

0x0

Addr 0x08, bit 5:4

be adjusted to a minimal AC ripple using the selectable

k factor of parameters MPS and MPC (see Table 21).

If the gain setting is altered, this calibration has to be

repeated. When single-ended operating mode is se-

lected via register bit INMODE (see Table 12) MPS

and MPC have no impact and the applied voltage at

the negative input replaces the conﬁgurable sum volt-

age in the VDC generation.

Addr 0x0A, bit 5:4

Range

maxVOS = 3 * VOSREF

maxVOS = 6 * VOSREF

maxVOS = 18 * VOSREF

maxVOS = 36 * VOSREF

0x1

0x2

0x3

Note

The maximum offset calibration range refers to the

internal calibrated signals (calibration mode Analog

1, see page 18)

The feedback of pin voltage V(ACO) fulﬁlls the same

task as source VDC when MR bridge sensors are sup-

plied by the controlled sensor current source. In this

case the justiﬁcation of intermediate potentials MPS

and MPC is unnecessary.

Table 22: Offset calibration range sine, cosine

The principle interpolation accuracy of the sine/cosine

signals in dependancy with the selected calibration

range as well as the size of an LSB are exemplarily

illustrated for some values in the following table.

REFVOS

Code

Addr 0x0E, bit 5:4

Source type

0x0

Feedback of pin voltage V(ACO): V(ACO)/20

for supply-dependent diff. voltage signals

for Wheatstone measuring bridges

to measure VDDS

Range

x Source

maxVOS

Cal. step

size (LSB)

Limitation of

angle precision

@ 100 % (6 Vpp)

@ 50 % (3 Vpp)

0x1, 0x2

Fixed reference:

3 x 0.25 V

6 x 0.25 V

6 x 0.5 V

750 mV

1.5 V

3 V

733 µV

none (>13 bit)

0x1 = V05 of 500 mV, 0x2 = V025 of 250 mV

for single-ended current or voltage signals

for single-ended or differential stabilized signals

(regulated sensors, frequency generator)

1466 µV

2933 µV

8798 µV

0.03°, >13 bit

0.06°, ca. 12 bit

0.06°, ca. 12.5 bit

0.11°, ca. 11.7 bit

0x3

Self-tracking sources VDC1, VDC2 (125...250 mV)

for differential current signals

for differential voltage signals*

18 x 0.5 V

9 V

0.17°, ca. 11 bit

0.34°, ca. 10 bit

Note

*) Requires SELREF = 0x3 and the supply of pin

VREF with the sensor’s reference potential (see

Elec. Char. No. 105 for acceptable input voltage).

Table 23: Offset calibration and impact on the angle

precision

Table 20: Offset reference source

OFS

OFC

Code

0x000

0x001

...

Addr 0x09, bit 7:0, Addr 0x0A, bit 2:0

Addr 0x0B, bit 7:0, Addr 0x0C, bit 2:0

MPS

MPC

Code

0x000

0x001

...

Addr 0x06, bit 5:0, Addr 0x05, bit 7:4

Addr 0x08, bit 1:0, Addr 0x07, bit 7:0

VDC = k ∗ VPi + (1 − k) ∗ VNi

k = 0.33

Factor OF

Code

0x400

0x401

...

Factor OF

0

0.00098

−0.00098

−0.00098 ∗ OFx

−1

0.00098 ∗ OFx

1

k = 0.33032

0x3FF

0x7FF

...

k = 0.33 + Code · 0.00032

0x200

...

k = 0.50 (center setting)

Table 24: Offset calibration sine, cosine

...

0x3FF

Note

k = 0.66

Adjustment required only if VOSREF = 0x3

The calibrated offset is generated through

VOS() = maxVOS ∗ OF

Table 21: Intermediate potentials sine, cosine

Phase correction SIN vs. COS

The offset calibration range is dependent on the se- The phase shift between sine and cosine can be ad-

lected REFVOS source and is adjusted using registers justed using register value PH. If the phase error is

ORS and ORC. The actual offset calibration happens too high, some calibration parameters may have to be

through adjusting factors OFS and OFC after having adjusted again (those are amplitudes, intermediate po-

selected the calibration range. The calibration target tentials and offset voltages).

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 22/44

PH

Addr 0x0D, bit 5:0, Addr 0x0C, bit 7:4

DIAG

Bit

Addr. 0x5A; bit 7...0

Description

R

Code

0x000

0x001

...

Correction angle

+0

Code

0x200

0x201

...

Correction angle

−0

Name

7

RG_MAX

Transmit current control maximum

error

+0.0204

−0.0204

6

AMP_MAX

Amplitude monitoring maximum

error

+0.0204 ∗ PH

+10.42

−0.0204 ∗ PH

−10.42

0x1FF

0x3FF

5

4

DC_MAX

Offset monitoring maximum error

CMP_MAX

Cont. amplitude monitoring

maximum error

Table 25: Phase correction sine vs. cosine

3

2

RG_MIN

Transmit current control minimum

error

AMP_MIN

Amplitude monitoring minimum

error

Diagnostic data

1

0

DC_MIN

Offset monitoring minimum error

The address 0x5A contains diagnosis data. Errors in

signal conditioning (amplitude monitoring) and trans-

mitter current control (ACO) are also reported in er-

ror byte 0x69 as ERR_AMP and ERR_RGL (see page

41).

CMP_MIN

Cont. amplitude monitoring

minimum error

Table 26: Diagnostic register 0x5A

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 23/44

AMPLITUDE CONTROL

iC-MR allows the amplitude of the output signals at Square control mode keeps the sum of the sine/cosine

pins PSO, NSO, PCO, and NCO to be kept constant amplitude squares at a constant value. Register ACOC

- regardless of temperature and ageing effects - by adjusts the setpoint for analog output ACO according

tracking the sensor supply. For this purpose iC-MR to Table 31.

has a controlled current source at pin ACO which can

ACOC

Code

0x00

Addr 0x00, bit 4:0

power the external sensor. The driver capability of this

current source is selected by ACOR (Table 27), the

control modes by ACOT (Table 28).

Square mode ACOT = 00

Vpp() ≈ 300 mV (60 %)

Vpp() ≈ 305 mV (61 %)

0x01

ACOR

Code

00

Addr 0x00, bit 6:5

Function

77

...

Vpp() ≈ 300 mV

77−(1.25∗Code)

5 mA - range

10 mA - range

25 mA - range

50 mA - range

0x19

...

Vpp() ≈ 500 mV (98 %)

...

01

10

0x1F

Vpp() ≈ 600 mV (120 %)

11

Table 31: AC Setpoint square control

Table 27: ACO Output current range (for control oper-

ation and constant current source)

~

Vpp() 500 mV

~

ACOT

Code

00

Addr 0x01, bit 0; Addr 0x00, bit 7

Function

~

Vpk() 250 mV

~

SIN/COS square control

Sum control

01

ϕ

10

Combined Sum and SIN/COS square control

Constant current source

As cos(ϕ)

11

Table 28: ACO Output control principle

LCMODE

Addr 0x02, bit 3

Function

Vt(max)

Vt(min)

Code

0

1

Optimized control

Standard control

Figure 10: Signal monitoring with square control

(example: ACOC = 0x19; for Vt()min or

Vt()max; see Elec. Char. Nos. 809 and

810).

Table 29: Control mode

In sum control mode the sine and cosine DC values

(SVDC and CVDC) are added together and regulated

to the setpoint. The setpoint is conﬁgured using regis-

ter ACOD according to Table 30.

As opposed to square mode, sum mode gives a higher

accuracy. However, at higher signal frequencies it can-

not compensate for a reduction in the signal amplitude

caused by the ampliﬁer cut-off frequency of the sen-

sors. The device thus has a combined control mode

which utilizes both control modes, sum and square

(see Table 28). In this mode sum control is applied at

low frequencies, with square control coming into play

at frequencies exceeding the cut-off frequency of the

sensor’s ampliﬁers. So that this control mode functions

correctly, the set signal amplitude for square control

mode must be lower than that for sum control.

ACOD

Code

0x00

Addr 0x01, bit 7:1

Sum mode ACOT = 01

VDC1 + VDC2 ≈ 166 mV

VDC1 + VDC2 ≈ 167 mV

0x01

109

...

VDC1 + VDC2 ≈ 166 mV

VDC1 + VDC2 ≈ 551 mV

109−(0.6∗Code)

0x7F

Table 30: DC Setpoint sum control

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 24/44

ACOC

Code

0x00

Addr 0x00, bit 4:0

Constant current source ACOT = 11

The control’s operating range and the input signal am-

plitudes supplied to the control unit are both monitored.

Should any error occur during monitoring, these can be

output.

I(ACO) ≈ 3.125 % Isc(ACO)

I(ACO) ≈ 6.250 % Isc(ACO)

0x01

...

I(ACO) ≈ 3.125 % * (Code + 1) * Isc(ACO)

So that the signals at the input pins PSO, NSO, PCO,

and NCO can be calibrated without control interfer-

ence, the current source at pin ACO can be set to a

constant current (Table 28).

0x1F

Note

I(ACO) ≈ 100 % Isc(ACO)

Isc(ACO) see characteristics no. 802

Table 32: Setpoint current source (ACO output cur-

rent)

12-BIT A/D CONVERTER

The IC features a 12-bit A/D converter, which output Registers TEMPHI and TEMPLO deﬁne the upper and

data is stored in the TEMP register and can be read lower thresholds for error output. If the current con-

out from here through the interfaces. The A/D con- verter value is above TEMPHI or below TEMPLO, the

verter operates constantly, updating the data in regis- ERR_TMP alarm bit is set in the error register. The

ter TEMP after each conversion. The TEMP register internal ADC can be utilized to continuously record

cannot be read by bytewise access to addresses 0x6A an external temperature, for which a temperature-

and 0x6B, as otherwise it is not guaranteed that a con- dependent voltage is applied at pin ADC. This can be

tiguous data word is read out. The temperature data generated by a KTY temperature sensor. A tempera-

must be read out by the cyclic telegram.

ture monitor can be created using thresholds TEMPHI

and TEMPLO. By way of example, the following de-

The A/D converter can be calibrated using registers scribes the evaluation of temperature sensor KTY 84.

ADCSLOP and ADCOFF. Register ADCSLOP has 8

bits and is used to set the maximum voltage the con-

verter can process at pin ADC. The allocation of the

register data in ADCSLOP to the maximum voltage is

expressed in Table 33. Using the second calibration

register ADCOFF, which has 16 bits, an offset can be

added to the converter’s digital output data.

TEMPLO

TEMPHI

Code

Addr. 0x14...0x15;

R/W

Addr. 0x16...0x17;

R/W

Temperature threshold

0x7FFF

...

+3276.7 °C

...

0x07D0

...

+200.0 °C

...

ADCSLOP

Code

0x00

Addr. 0x11; bit 7...0

Full scale level for VDDA = 5V

2.0 V

R/W

0x0001

0x0000

0xFFFF

...

+0.1 °C

0.0 °C

-0.1 °C

0x01

2.00196 V

...

2.0 V + 1.96 mV * ADCSLOP

2.5 V

0xFE70

...

-40 °C

0xFF

...

0x8000

Note

-3276.8 °C

Table 33: Maximum ADC input voltage ADC

Thresholds for example KTY 84

Table 35: Temperature thresholds

ADCOFF

Addr. 0x12...0x13;

Function

R/W

Code

0x7FFF

...

TEMP = TEMP(int) + 32767

Figure 11 shows a schematic circuit diagram for the

evaluation of the KTY. A resistor of approximately 2.3

kΩ is switched in series with the KTY sensor to lin-

earize the voltage supplied by the KTY. This results in

a linear temperature voltage.

0x0001

0x0000

0xFFFF

...

TEMP = TEMP(int) + 1

TEMP = TEMP(int)

TEMP = TEMP(int) - 1

0x8000

TEMP = TEMP(int) - 32768

Table 34: Digital temperature offset value

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 25/44

+5V

V(ADCSLOP)

2,3kΩ

12kΩ

VDDA

ADC

V(KTY84)

KTY84

12 Bit

16 Bit

TEMP

12 Bit

ADC

16 Bit

ADCOFF

Figure 11: Schematic circuit diagram for the evaluation of KTY sensors.

The temperature is output according to Table 36 as a To obtain the output given in Table 36 the evaluation

16-bit value in two’s complement format with a resolu- circuitry is calibrated as follows:

tion of 1/10°C.

1. The maximum convertible voltage is set and thus

the increase in the converter using register AD-

CSLOP. ADCSLOP’s register is set so that there

is a difference of 2,400 between the converter

values at R(KTY84) = 359 Ω and R(KTY84) =

1,722 Ω.

TEMP

Code

0x7FFF

...

Addr 0x6B, 0x6A, bits: 15..8, 7..0

Temperature

+3276.7 °C

...

Validity

Out of

measuring range

0x07D0

...

+200.0 °C

...

0x0001

0x0000

0xFFFF

...

+0.1 °C

0.0 °C

-0.1 °C

...

2. To map ADC’s output onto the range of values

given in Table 36, an offset is added through reg-

ister ADCOFF. The data in register ADCOFF is

set so that 0xFE70 is read at R(KTY84) = 359 Ω

and, correspondingly, 0x07D0 at R(KTY84) =

1,722 Ω.

Measuring range

0xFE70

...

-40 °C

...

Out of

0x8000

-3276.8 °C

measuring range

(a) Read out converter data from regis-

ter TEMP with ADCOFF = 0x0000 at

R(KTY84) = 359 Ω.

Table 36: Temperature data output format

(b) Calibration data = converter data + 400

(c) Write the calibration data to register AD-

COFF.

Figure 12: Calibrating the temperature sensor to the

output format

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 26/44

INTERPOLATOR AND CYCLE COUNTER

The conﬁgurable 37-bit cycle counter comparates the at 13-bit interpolation, the value ’10’ is accrued as the

sine and cosine signals and counts the signal cycles conﬁguration for CODERES.

independent of requests for position data. The inter-

polator resolves one signal cycle of the calibrated sine

and cosine signals to 13 bits for each position data re-

quest and synchronizes this with the cycle counter in

order to ensure a consistent position data word at all

times.

Using register CODERES it is possible to adapt the

bit length of the cycle counter to the output format. If,

for example, a total data length of 48 bits is required

CODERES

Addr. 0x1B; bit 1...0

R/W

Code

00

Counter depth

37 bit (24 bit MT, 13 bit ST)

36 bit (24 bit MT, 12 bit ST)

35 bit (24 bit MT, 11 bit ST)

34 bit (24 bit MT, 10 bit ST)

01

10

11

Table 37: Cycle counter resolution

36

3

12

0

Period Counter (36:3)

Interpolation (12:0)

CODERES

Period Counter (36:0)

Interpolation (12:0)

36

0

12

0

Figure 13: Adjusting the counter depth

STOFF

Addr. 0x1E; bit 7...0

Addr. 0x1D; bit 7...0

Addr. 0x1C; bit 7...0

Addr. 0x1B; bit 7...6

R/W

iC-MR’s output code direction can be inverted by bit

DIR.

Code

0x00

Function

Offset value

DIR

Code

0

Addr. 0x1B; bit 2

Code direction

R/W

0x3FFFFFF

Code direction not inverted

Code direction inverted

1

Table 39: Singleturn offset

Table 38: Inversion of code direction

MTOFF

Addr. 0x21; bit 7...0

Addr. 0x20; bit 7...0

Addr. 0x1F; bit 7...0

Function

R/W

Code

0x00

Offset value

An offset for singleturn (STOFF) and multiturn

(MTOFF) data can be deﬁned to adapt the absolute

position data. These offsets are subtracted from the

existing data.

0xFFFFFF

Table 40: Multiturn offset

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 27/44

Interpolation

Period Counter

-

MTOFF

STOFF

Multiturn

Singleturn

24 bit

26 bit

Figure 14: Setting the offset

STRESO selects the internal resolution of the single- If required, MTRESO selects the internal resolution of

turn data for the serial interface in SPI protocol and the multiturn data for the serial interface in SPI proto-

the parallel interface. If the internal resolution is re- col and the parallel interface. If the internal resolution

duced, the data is output ﬂush left. Should a longer is reduced, the multiturn data is output ﬂush right. The

output data length thus be required, the data is ﬁlled upper bits are zeroed. The output data length is de-

with zeros. This generates a permanently contiguous pendent on the selected output interface.

position data word from the right-aligned multiturn data

and the left-aligned singleturn data. The interpolator

data resolution of 13 bits is ﬁxed; only its length in the

position data word can be selected using CODERES

(Table 37).

MTRESO

Code

0x0

Addr. 0x24; bit 7...5

R/W

Multiturn resolution

24 bit

20 bit

16 bit

12 bit

8 bit

0x1

0x2

STRESO

Code

0x00

0x01

...

Addr. 0x24; bit 4...0

Singleturn resolution

R/W

0x3

0x4

26 bit

25 bit

...

0x5

4 bit

0x6

0 bit

0x7

0 bit

0x0E

...

12 bit

...

Note

Not valid for serial interface with BiSS/SSI protocol

Table 42: Multiturn resolution

0x19

0x1A

...

1 bit

0 bit

...

0x1F

Note

0 bit

Not valid for serial interface with BiSS/SSI protocol

Table 41: Singleturn resolution

24 bit

26 bit

Multiturn

Singleturn

MTRESO

STRESO

Position Data

Figure 15: Reducing the internal data length

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 28/44

Acquiring position data

able to both the parallel and serial interfaces with SSI

There are three different operating modes for acquiring and BiSS C protocol.

position data which are selected by ACQMODE.

In continuous conversion mode position data is gen-

erated continuously regardless of external requests

for position data. The data output is the last data to

be converted (the processing time is therefore also

hidden; the exact moment of conversion remains un-

known, however).

ACQMODE

Addr. 0x19; bit 7...6

Function

R/W

Code

00

Normal conversion with processing time

Pipeline conversion without processing time

01

10

Continuous conversion without processing time

11

Continuous conversion with

interpolated interim values *

In continuous conversion mode with interpolated inter-

mediate data, interpolated position data is output at all

times (as opposed to the last data converted). This

conversion mode is only available to the serial inter-

face with SSI protocol, as no waiting period is possible

in SSI protocol.

Note

*) Only for serial interface with SSI protocol

Table 43: Position data acquisition

In normal converter mode, new data is generated for

each request for position data and this only output at

the end of conversion.

If a continuous conversion mode is active (ACQ-

MODE = 10 or 11), conversion can be temporarily in-

terrupted by pin NL using the enable acquire function.

In pipeline mode data is also generated on each re-

quest; however, with each new request the data from

the last conversion is output in order to hide the pro-

cessing time. In this mode the PDV bit is set stati-

cally in the status byte; the ERR_IPO bit in the error

byte, however, continues to signal the status or pro-

cessing time of the interpolator. Pipeline mode is avail-

NL (Enable Acquire Function)

Function

Convert as soon as the interpolator is free

Do not convert

Level

1

0

Table 44: Special Function of Pin NL

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 29/44

EEPROM INTERFACE

Address range

The CONF section includes addresses 0x00-0x7F, i.e.

The address range on iC-MR is divided into three con- memory banks 0 and 1. The length of area EDS can be

secutive areas:

conﬁgured using register CFG_E2P. The USER sec-

tion comes directly after the EDS area. The allocation

thereof is described in Figure 16.

• CONF: the iC-MR conﬁguration register

• EDS: Electronic-Data-Sheet

• USER: user area to be conﬁgured as required.

iC-MR internal

linear address-

space divided into n

banks of size 64

byte

address-space visible via I/O interface

bank n-1

bank 3

bank 2

bank 1

bank 0

ADR

0x00

0x3F

0x40

0x7F

0x80

0x3F

0x40

BSEL

selects

0xBF

0xC0

EDSBANK

profile ID

serial number

0xFF

SLAVE-registers

STATUS

BiSS-ID

0x7F

Figure 16: Schematic diagram of the bankwise memory addressing

Memory areas CONF and EDS are protected by sep- The BSEL register is used to switch to other mem-

arate write-protection mechanisms (see Safety Fea- ory banks on the external EEPROM. After an iC-MR

tures). The memory banks beyond the selected EDS startup bank 0 is selected which mirrors the internal

area (USER section) are not write-protected.

registers. If a different memory bank is selected to

provide access to EEPROM data, this is displayed at

addresses 0x00-0x3F.

CFG_E2P

Addr. 0x26; bit 7...6

Banks per range

(64 byte each)

R/W

BSEL

Code

00000

00001

00010

...

Addr. 0x40; bit 4...0

R/W

Bank at addresses 0x00...0x3F

Bank 0*

Code

00

01

10

11

Bytes

256

512

1024

2048

CONF EDS

USER EEPROM, Type

Bank 1

2

1

4

12

24

1

2

6

2 kbit, as of C02

4 kbit, as of C04

8 kbit, as of C08

16 kbit, as of

C016

Bank 2

...

11111

Note

Bank 31

*) Corresponds to internal registers

Table 45: EDS range selection

Table 46: Bank selection

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 30/44

Accessing external memory banks

Read and write accesses to data in the external EEP-

Register banks 2 to 31 store data in an external EEP- ROM may only be made if an EEPROM is connected

ROM. If an address is accessed which is not physically up when iC-MR is started. Autoincrement accesses

present on iC-MR (see Figure 16), communication with to external addresses are not possible. Error bit

the external EEPROM is initiated. If the parallel inter- ERR_KNF is updated following each external access

face or serial interface is active in SPI mode, the end (e.g. it is set if the storage time on the EEPROM is

of I²C communication can be recognized by reading undershot, or cancelled if access was successful).

out the status byte (address 0x60, bit 2 BUSY). Only

after this is it possible to again access the internal reg-

isters or external EEPROM registers. When the serial

Startup and selection of I/O interface

Register INTCFG deﬁnes which I/O interface is used.

interface is run in BiSS protocol, iC-MR automatically

Either a parallel or serial interface is available. The se-

requests the processing time necessary for EEPROM

rial interface can be run on BiSS, SSI, or SPI protocol.

Only one of the two interfaces may be active. During

access.

the startup phase register INTCFG is set by the con-

nected EEPROM being read out. During operation the

register can be altered, for example to write an EEP-

ROM which iC-MR starts with a different I/O interface.

If an EEPROM data CRC is invalid (after up to 3 read-

out trials) all registers are zeroed and the serial in-

terface is activated with SSI protocol, but pin SLO is

kept permanently high (at VDD). This state is main-

tained until the CRC veriﬁcation of renewed conﬁgu-

ration data was executed successfully (in SSI mode

register write access is permitted).

Figure 17: EEPROM read access

Two read accesses are needed to read out data from

an address on the EEPROM (for the parallel interface

and serial interface in SPI mode only). The ﬁrst read

access initiates communication with the EEPROM; at

the end of communication the read data is stored in a

temporary register on iC-MR. This temporary register

data is supplied on the next read access to an exter-

nal address. At the same time communication with the

EEPROM is again started on this access. This enables

a large area to be read out quickly, as the next readout

address can already be created to read out the tempo-

rary register.

INTCFG

Code

11

Addr. 0x18; bit 7...6

Function

(R/W)

Parallel interface

10

Serial interface with SPI protocol

Invalid value

01

00

Serial interface with BiSS/SSI protocol*

*) Switching BiSS/SSI with register NESSI

Note

Table 47: Interface selection

Without an EEPROM the pin state of SCL and SDA is

evaluated on startup; INTCFG(1) takes on the value

at pin SCL, with INTCFG(0) assuming the value at pin

SDA.

Startup without EEPROM

SCL level

SDA level

Activated interface

1

0

1

0

1

0

Parallel interface

Serial interface with SPI protocol

Invalid value

Serial interface with BiSS/SSI proto-

col

Figure 18: EEPROM write access

Table 48: Interface selection without EEPROM

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 31/44

PARALLEL I/O INTERFACE

The parallel interface enables sensor and register data the register content. The second write access writes

to be read out through pins NCS, NRD, NWR, NL, the data at the bus to the addressed register.

and D0 to D7. After a reset or when inactive the in-

terface is in read mode (data pins D(7:0) are tristate,

NCS

address transfer is expected). If the internal data bus

is busy due to an EEPROM readout after the reset,

NWR

for instance (i.e. if the BUSY bit is active in the status

byte), all read accesses are answered by the status

byte through the parallel interface.

NRD

ADDR1

DATA1

ADDR2

DATA2

D(7:0)

Notice: The parallel interface can not be simultane-

ously operational with a serial I/O interface.

Figure 20: Write process

A simultaneous low signal for NRD and NWR is not

permissible; the interface behavior is not deﬁned for

this conﬁguration.

Reading out registers

iC-MR’s parallel interface enables internal registers to

be accessed for readout. To this end the required reg-

ister address must ﬁrst be written to, after which the

data at this address can be read out.

Reading out position data

Position data can be requested through the parallel in-

terface in two different ways:

NCS

NWR

NRD

• by an implemented command

• by a low signal through pin NL.

To read out position data on an implemented com-

mand, command register CMD must be written with the

request command 0x00. Depending on the set conﬁg-

uration, singleturn, multiturn, and interpolator data is

then provided for readout. Each request command in-

creases the life counter by one.

ADDR1

DATA1

ADDR2

DATA2

D(7:0)

Figure 19: Readout process

Writing to registers

The internal registers can be written through the paral- Position data is marked as valid by bit PDV being set

lel interface. To this end the required register address in the status byte. Only after this has occurred posi-

and then the relevant data word must be written to. tion data should be read out at the relevant register

Write mode is selected by NWR = 0. The ﬁrst write ac- addresses. Here, data is read out on a normal read

cess sets the register address and has no effect on register access.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 32/44

NL

NCS

NWR

NRD

STATUS

0x60

0x00

0x60

0x62

ST

0x63

ST

D(7:0)

Request Position

Wait for PDV=1

Read Data

Figure 21: Position data output at request by command

If it is not possible to extend the NRD pulse to wait When reading out position data through pin NL,

for data validity, the status register must be continually the request is made directly on the falling edge

read out anew until pin D0 supplies a high (PDV = 1). at pin NL. While NL = low, the status and posi-

After this, the position data can be read out on a read tion data are output on consecutive read accesses

register access.

(NRD = high → low → high).

As the position data registers are read out individu-

ally following a request for position data by command, It is not necessary to write to the register addresses

no CRC is formed across the position data. The life in this operating mode, as this is only used for the fast

counter function continues to be active, however.

readout of sensor data.

NL

NCS

NRD

Status

ST

MT

LC

ERR

TMP

CRC

D(7:0)

Statusbit PDV

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

ADDR int

Wait for PDV=1

Read Data

PosData

Request

Figure 22: Position data output at request by pin NL

The status register data is output ﬁrst. During the sta- out with each low signal at NRD.

tus register readout NRD should remain low until pin

D0 (in this case, PDV) switches to high, as this indi-

cates the validity of the position data.

The various ways of outputting position data in this

operating mode are set in register FULL_CYC. If bit

On each rising edge at NRD the internal address is FULL_CYC is set (Table 49), registers 0x60-0x6D are

increased, after which the position data can be read output on each cyclic access. If this bit is disabled,

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 33/44

Data sequence shortened format (FULL_CYC = 0)

registers 0x61 and 0x67 are bypassed; only 24 bits of

singleturn and 16 bits of multiturn data are output.

Byte No.

1

2

Data

Status byte

Register

STAT(7:0)

ST(9:2)

Address

0x60

0x62

0x63

0x64

0x65

0x66

0x68

0x69

0x6A

Singleturn Lo byte

Singleturn Mid byte

Singleturn Hi byte

Multiturn Lo byte

Multiturn Mid byte

Life counter

FULL_CYC

Addr. 0x18; bit 5

Function

R/W

3

4

5

ST(17:10)

ST(25:18)

MT(7:0)

Code

0

1

24-bit ST / 16-bit MT

26-bit ST / 24-bit MT

6

7

MT(15:8)

LC(7:0)

8

9

10

11

12

Error byte

ERR(7:0)

TEMP(7:0)

Table 49: Cyclic telegram length

Temperature Lo byte

Temperature Hi byte

CRC Lo byte

TEMP(15:8) 0x6B

A CRC is formed across the output data (with the poly-

nomial x¹⁶+ x¹⁴+ x¹¹+ x¹⁰+ x⁹+ x⁷+ x⁵+ x³+ x¹+ 1

(0x14EAB), start value 0xFFFF). The check sum is re-

formed for each cyclic transmission and is only valid

for the duration of this transmission. The follow-

ing sequence applies to the shortened output format

(FULL_CYC = 0):

CRC(7:0)

CRC(15:8)

0x6C

0x6D

CRC Hi byte

Table 50: Data sequence shortened output format

If more bytes are read out in cyclic operation, a zero

is always output. In full output format (FULL_CYC = 1)

the data is output in the following order:

Data sequence complete format (FULL_CYC = 1)

Byte No.

1

2

3

4

5

6

7

Data

Status byte

Register

STAT(7:0)

ST(1:0)

Address

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

Singleturn Ext byte

Singleturn Lo byte

Singleturn Mid byte

Singleturn Hi byte

Multiturn Lo byte

Multiturn Mid byte

Multiturn Hi byte

Life counter

ST(9:2)

ST(17:10)

ST(25:18)

MT(7:0)

MT(15:8)

MT(23:16)

LC(7:0)

ERR(7:0)

TEMP(7:0)

TEMP(15:8) 0x6B

8

9

10

11

12

13

14

Error byte

Temperature Lo byte

Temperatur Hi byte

CRC Lo byte

CRC(7:0)

CRC(15:8)

0x6C

0x6D

CRC Hi byte

Table 51: Data sequence complete output format

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 34/44

SERIAL I/O INTERFACE: BiSS C

Conﬁguration

The following parameters deﬁne the serial interface in

The serial I/O interface operates in BiSS C proto- BiSS C protocol:

col and allows sensor data to be output in repeated

cycles without any termination (data channels POS

and TMP). At the same time parameters can be ex-

changed through bidirectional register communication

(data channel CD).

NESSI

Addr 0x19, bit 4

Code

Protocol

Information

0

1

SSI

BiSS C

www.biss-interface.com

Depending on the conﬁguration, the sensor data sup-

plied by iC-MR contains the cycle counter and interpo-

lation data (MT + ST) of up to 50 bits, a life counter

of up to 6 bits, two error bits (ERR and WARN), and

6 or 16 CRC bits (CRC). Another data channel can be

switched in to transmit the temperature data from the

12-bit A/D converter at a length of 16 bits. Registers

PROFILE and DEV_ID can be programmed separately

for the data channels.

Table 53: BiSS/SSI protocol selection

ENLC

Code

0

Addr. 0x19; bit 5

Function

R/W

No transmission of life counter

Transmission of 6-bit life counter

1

Table 54: Life counter enable

Single-cycle data channel: POS

Bits

Type

Label

TMPSCD

Addr. 0x19; bit 2

Function

0/12/24

24/26

1

DATA

ERROR

Multiturn data MT

Singleturn data ST

Code

0

1

No cyclic output of temperature value

Cyclic output of temperature value

Error bit nE (see ERR)

(inverted bit output)

1

ERROR

Error bit nW (see WARN)

(inverted bit output)

Table 55: Temperature data enable (BiSS)

0/6

DATA

CRC

Life counter LC

ENXCRC

Addr. 0x19; bit 3

Function

6/16

Polynomial 0x43 or 0x190D9

(inverted bit output)

Code

0

6-bit CRC with polynomial

0x43 = x⁶+ x¹+ 1

Single-cycle data channel: TMP

Bits

16

5

Type

DATA

CRC

Label

1

16-bit CRC with polynomial

Temperature data TEMP

Polynomial 0x25 = x⁵+ x²+ 1

(inverted bit output)

0x190D9 = x¹⁶+ x¹⁵+ x¹²+ x⁷+ x⁶+ x⁴+ x³+ 1

Table 56: Selecting extended CRC

Table 52: BiSS data channels

Figure 23: Example of line signals (BiSS C)

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 35/44

CRCS(15:8)

CRCS(7:0)

Code

Addr. 0x28; bit 7...0

Addr. 0x29; bit 7...0

R/W

Conﬁguration examples

Function

POS: Singleturn data

0x00

Bits

Type

Label

...

Start value for CRC calculation

24

DATA

ERROR

CRC

Singleturn value ST(23:0)

Error nE and warning nW

Polynomial 0x43

0xFF

2

Note

For ENXCRC = ’0’ only CRCS(5:0) is applied.

Table 57: CRC start value

6

Conﬁg.

NESSI = 1, ENLC = 0, TMPSCD = 0, ENXCRC = 0,

STRESO = 0x02, MTRESO = 0x7

In addition, bit ENLC enables the life counter to be

transmitted on the single-cycle data channel. The

counter data (6 bits) is sent directly after the nE/nW

bits. Register ENXCRC deﬁnes the CRC polynomial

used and the number of CRC bits transmitted. Here,

CRCS allows a free start value to be programmed for

CRC calculation. If the 6-bit CRC is chosen, only

CRCS bits 5 to 0 are used. The temperature can be

transmitted as an additional single-cycle data channel.

This can be controlled by bit TMPSCD. The timeout

is always formed adaptively and thus does not require

conﬁguration.

Table 59: Format example 1 for BiSS proﬁle BP1

POS: Single- and multiturn data

Bits

Type

Label

24

DATA

ERROR

CRC

Multiturn value MT(23:0)

Singleturn value ST(11:0) & x"000"

Error nE and warning nW

Polynomial 0x43

24

2

6

Conﬁg.

NESSI = 1, ENLC = 0, TMPSCD = 0, ENXCRC = 0,

STRESO = 0x0E, MTRESO = 0x0

Table 60: Format example 2 for BiSS proﬁle BP1

Register communication

POS: Single- and multiturn data with life counter

According to BiSS C protocol slave registers are di-

rectly addressed in a reserved address area (0x40 to

0x7F). Other memory areas are addressed dynami-

cally and in blocks. For this purpose BiSS addresses

0x00 to 0x3F target a register bank consisting of 64

bytes, whose physical storage address determines

bank selection n. iC-MR supports up to 32 memory

banks, enabling a 16-kbit EEPROM to be fully ex-

ploited. This means that there is sufﬁcient storage

space for an ID plate (EDS) and OEM data. Page

29 provides information on memory allocation and ad-

dressing through BiSS. If the internal bus is busy in

BiSS C mode (due to a CRC, conﬁguration being writ-

ten to the EEPROM, or absolute data being read out

through the ADI, for example), zeroes are sent on the

single-cycle data channel.

Bits

12

26

2

Type

Label

DATA

ERROR

DATA

CRC

Multiturn value MT(11:0)

Singleturn value ST(25:0)

Error nE and warning nW

Life counter LC

6

16

Polynomial 0x190D9

TMP: Temperature data

16

DATA

CRC

Temperature value TEMP(15:0)

Polynomial 0x25

5

Conﬁg.

NESSI = 1, ENLC = 1, TMPSCD = 1, ENXCRC = 1,

STRESO = 0x00, MTRESO = 0x3

Table 61: Format example 3

Commands

The following BiSS interface commands are imple-

mented. These commands cannot be listed in the

broadcast.

Opcode

10

Function

Readout new data via absolute data interface

CRC veriﬁcation of internal conﬁguration

11

Table 58: BiSS commands

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 36/44

SERIAL I/O INTERFACE: SSI

Conﬁguration

cesses in write form are possible in SSI mode. As in

iC-MR can transmit position data in SSI protocol, for BiSS mode, the timeout is formed adaptively and thus

which purpose the following parameters give the nec- does not require conﬁguration.

essary settings and options. In addition, register ac-

Figure 24: Example of line signals (SSI)

NESSI

Addr 0x19, bit 4

Protocol

Conﬁguration examples

Code

Information

POS: Singleturn data

Bits

Type

Label

0

1

SSI

BiSS C

13

DATA

Singleturn value ST(23:11)

www.biss-interface.com

Conﬁg.

NESSI = 0, ENLC = 0, TMPSCD = 0, ENXCRC = 0,

SSIERR = 0, SSIMODE = 00,

STRESO = 0x0D, MTRESO = 0x7

Table 62: BiSS/SSI protocol selection

Table 64: Format example 1 for 13-bit SSI

Register NESSI must be zeroed so that data can be

transmitted in SSI protocol. SSI ring mode can be acti-

vated by SSIRING. SSIMODE(1:0) sets the data length

of the serial interface in SSI protocol. Possible values

are a 13-bit SSI, a 25-bit SSI, or an extended mode,

the data length of which can be conﬁgured as in BiSS

C protocol. In 13-bit or 25-bit SSI mode the error bit

can be attached to the data by SSIERR.

POS: Single- and multiturn data

Bits

12

Type

Label

DATA

ERROR

Multiturn value MT(11:0)

Singleturn value ST(23:11)

Error nE

13

1

Conﬁg.

NESSI = 0, ENLC = 0, TMPSCD = 0, ENXCRC = 0,

SSIERR = 1, SSIMODE = 01,

STRESO = 0x0D, MTRESO = 0x3

Table 65: Format example 2 for 25-bit SSI

SSIRING

Addr. 0x18; bit 1

Function

R/W

Code

0

SSI ring mode deactivated

SSI ring mode activated

Addr. 0x18; bit 0

POS: Single- and multiturn data with life counter

1

Bits

24

26

2

Type

Label

SSIERR

R/W

DATA

ERROR

DATA

CRC

Multiturn value MT(23:0)

Singleturn value ST(25:0)

Error nE and warning nW

Life counter LC

0

Standard SSI output without error bit

Standard SSI output with error bit

Addr. 0x19; bit 1...0

1

SSIMODE

6

00

01

10

13-bit SSI protocol

16

Polynomial 0x190D9

25-bit SSI protocol

TMP: Temperature data

Extended SSI protocol (8-85 bit)

16

DATA

CRC

Temperature value TEMP(15:0)

Polynomial 0x25

5

Table 63: SSI Conﬁguration

Conﬁg.

NESSI = 0, ENLC = 1, TMPSCD = 1, ENXCRC = 1,

SSIERR = 0, SSIMODE = 10,

STRESO = 0x00, MTRESO = 0x0

Table 66: Format example 3 for extended SSI

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 37/44

SERIAL I/O INTERFACE: SPI

Register access

The third byte concludes the transmission, with which

SPI protocol can also be used for communication the register data (WRITEDATA) is written through pin

through the serial interface. Data changes at pins SLI SLI on a register write access. On a register read ac-

and SLO respectively on a falling edge at MAI and is cess the requested register data (READDATA) can be

accepted on a rising edge at MAI. If the internal data read out at pin SLO. To access the command register

bus is busy due to an EEPROM readout after the reset, the protocol can be shortened to two bytes, as the op-

for instance (i.e. if the BUSY bit is active in the status code already contains the command to be executed.

byte), all read accesses are answered by the status

Command

byte through the serial interface in SPI mode.

The protocol for the register read or write access con-

MAI

sists of a 3-byte transmission.

NCS

SLI

OPC

- - -

CYC & x60

- - -

MAI

NCS

SLI

SLO

OPC

- - -

CYC & ADR(6:0)

- - -

WRITEDATA

READDATA

Figure 26: Command register access

SLO

Figure 25: Register access

Cyclic readout

The decision is made as to whether a cyclic transmis-

sion or a register access takes place on the ﬁrst sent

CYC bit. If registers are to be accessed, a 0 is trans-

mitted.

In order to generate new position data, either

• parallel interface pin NL can be used, or

• the command register can be written to prior to cyclic

access (opcode 0x00: request for new position data).

CYC

Code

Function

The position data is read out on a read access from ad-

dress 0x60 when CYC = 1. The output data (addresses

0x60 to 0x6D) can be read out directly in sequence.

0

1

Register access

Cyclic readout

Table 67: Selecting cyclic transmission

MAI

The address is then sent as a 7-bit value. The next

transmitted byte contains the OPC transmission op-

code. This opcode comprises one bit for register read

(RD) and one bit for register write (WR) access, plus

the data for the command register (CMD).

NCS

SLI

CYC & x60

- - -

STATUS

0x60

SLO

ST(1:0)

0x61

...

CRC(7:0)

0x6C

CRC(15:8)

0x6D

- - -

ADDR int

OPC

Figure 27: Cyclic readout

Code

Function

–

RD WR CMD

00

0

1

0

1

0

0000 Request new Position data

0001 Write conﬁguration in EEPROM

0010 Readout absolute data interface

0011 Trigger software reset

0100 CRC veriﬁcation of internal conﬁguration

0101 Activate error simulation ERR bit

0110 Deactivate error simulation ERR bit

0000 Writing register access

A CRC is formed across the output data (with the poly-

nomial x¹⁶+ x¹⁴+ x¹¹+ x¹⁰+ x⁹+ x⁷+ x⁵+ x³+ x¹+ 1

(0x14EAB), start value 0xFFFF). The check sum is re-

formed for each cyclic transmission and is only valid

for the duration of this transmission.

0000 Reading register access

Table 68: Opcode of transmission

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 38/44

ABSOLUTE DATA INTERFACE (ADI)

DL_ADI

Code

0x00

0x01

...

Addr. 0x1A; bit 7...3

R/W

Through the absolute data interface the cycle counter

can be preloaded to a required value. The absolute

data interface is a BiSS master and operates on either

BiSS C or SSI protocol. Pin AMAO outputs the master

clock, with slave data read in at pin ASLI.

Function

0 bit MT / 0 bit ST

0 bit MT / 1 bit ST

...

0x0C

...

0 bit MT / 12 bit ST

...

The following registers deﬁne the use of the absolute

data interface. Bit STP_ADI controls the readin of ab-

solute data during startup. If set, and after the EEP-

ROM has been successfully read out, absolute data

is read in by the absolute data interface. Alternatively,

absolute data can be read in at a later stage by the

command register.

0x17

0x18

0x19

0x1A

0x1B

0x1C

...

0 bit MT / 23 bit ST

0 bit MT / 24 bit ST

8 bit MT / 24 bit ST

12 bit MT / 24 bit ST

16 bit MT / 24 bit ST

24 bit MT / 24 bit ST

...

0x1F

24 bit MT / 24 bit ST

STP_ADI

Addr. 0x18; bit 3

Function

R/W

Table 72: Data length absolute data interface

Code

0

1

Do not read absolute data during start-up

Read absolute data during start-up

Register SYNC_ADI sets the number of synchroniza-

tion bits used to synchronize the data on the internal

cycle counter.

Table 69: Startup with absolute data

SYNC_ADI

Addr. 0x1A; bit 2...1

Function

R/W

Code

00

Bit CYC_ADI controls the cyclic readin of absolute

data. If set, absolute data is read in every 550 µs, pro-

vided the absolute data interface is not busy. Should

the absolute data interface be busy, the reading is suit-

ably delayed. If this bit is disabled, absolute data must

be read in through the command register.

Use 0 bit for synchronisation

Use 1 bit for synchronisation

Use 2 bit for synchronisation

Use 3 bit for synchronisation

01

10

11

Table 73: Synchronisation bits absolute data interface

CYC_ADI

Addr. 0x18; bit 2

Function

R/W

The transmission protocol used for the absolute data

interface is selected by bit SSI_ADI.

Code

0

1

Do not read absolut data cyclically

Read absolute data cyclically

SSI_ADI

Addr. 0x1A; bit 0

Function

R/W

Code

Table 70: Cyclic reading of absolute data

0

1

BiSS C protocol

SSI protocol

CHK_ADI is used to check the counted value versus a

cyclically read absolute value. If the two values differ,

error bit ERR_ABS will be set.

Table 74: Protocol of absolute data interface

In order to access the sensor connected up to the

absolute data interface through the serial interface in

BiSS C protocol, bit GET_ADI permits the interface

signals to be looped through to the absolute data in-

terface. To this end the master clock received at pin

MAI is output at pin AMAO and the data read at ASLI

is used internally in place of SLI. The sensor con-

nected up to the absolute data interface is then allocat-

ing slave ID 0 in BiSS C protocol, and iC-MR is taking

slave ID 1.

CHK_ADI

Addr. 0x27; bit 5

Funktion

R/W

Code

0

1

Do not check data cyclically

Check data cyclically versus ADI reading

Table 71: Cyclic check of absolute data

Register DL_ADI deﬁnes the length of the data read in When routing signals in this manner it is not possible

at the absolute data interface. to read in the absolute data of the connected sensor

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 39/44

for internal calculation. Bit GET_ADI must ﬁrst be dis-

abled.

GET_ADI

Addr. 0x18; bit 4

Function

R/W

Code

0

1

Normal operation, no loop through of BiSS signals

BiSS signal routing altered

(readout of absolute data not possible)

Table 75: BiSS chain with absolute data interface

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 40/44

SAFETY FEATURES

CRC Veriﬁcation

Safety register

The conﬁguration check sum CRCCFG is stored in If safety register SEC_HI does not equal 0x00, NR-

registers 0x2E-0x2F. The CRC polynomial used is DOK can be used to select whether write or read/write

x¹⁶+ x¹²+ x⁵+ 1 (CRC-16), the start value is 0x0000.

protection is valid for memory area CONF - in the lat-

ter case the conﬁguration registers can then be neither

If an EEPROM is available, the check sum read out is read out nor overwritten. On read access 0x00 is out-

stored to the CRCCFG register and is used for veriﬁca- put.

tion. If no EEPROM is connected, or if the check sum In both cases bit EWKH of status byte 0x60 is disabled.

read in is incorrect, renewed conﬁguration data with Safety register SEC_HI can be reset and protection

check sum must be written and the CRC veriﬁcation deleted only if the current register key data is again

executed on command (to register 0x60).

written.

NRDOK

Addr. 0x25; bit 7

Function

R/W

If the conﬁguration is written to the EEPROM by com-

mand, the current check sum in addresses 0x2E-0x2F

is not used but the CRCCFG register is calculated

again.

Code

0

1

Only write protection active

Read and write protection active

Table 77: Selecting read/write protection

CRCCFG(15:8)

CRCCFG(7:0)

Addr. 0x2E; bit 7...0

Addr. 0x2F; bit 7...0

R/W

Code

0x0000

...

Function

SEC_HI

Addr. 0x25; bit 6...0

Function

No read/write protection active

R/W

Code

0x00

Test value generated with CRC polynomial 0x1021,

Start value is 0x0000

0xFFFF

Otherwise Read/write protection active depending on NRDOK

value

Table 76: CRC test value for conﬁguration

Table 78: Safety register for conﬁguration

Example of CRC calculation routine:

If safety register SEC_LO does not equal 0x00, write

protection is active for memory area EDS (indicated by

the disabled EWKL bit in status byte 0x60). All regis-

ters in this area can be read out but not overwritten.

Safety register SEC_LO can be reset and protection

deleted only if the current register key data is again

written.

unsigned char ucDataStream

int iCRCPoly 0x1021 ;

unsigned char ucCRC=0;

int 0;

= 0;

=

i

=

ucCRC = 0; / / s t a r t value ! ! !

for ( iReg

= 0; iReg <46; iReg ++)

{

ucDataStream

for ( i =0; i <=7; i ++)

i f ( (ucCRC & 0x80 ) != ( ucDataStream & 0x80 ) )

ucCRC = (ucCRC << 1) iCRCPoly ;

else

ucCRC = (ucCRC << 1 ) ;

ucDataStream ucDataStream << 1;

= ucGetValue ( iReg ) ;

{

^

SEC_LO

Code

Addr. 0x26; bit 5...0

Function

No write protection active

R/W

=

0x00

}

Otherwise Only write protection active

}

Table 79: Safety register for EDS memory area

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 41/44

Status and command register

ADV and error bit ERR_ABS are updated. If the pro-

Read access to the status byte provides the current cess is successful, the cycle counter is set.

system status.

Command 0x03 initiates a software reset which is also

messaged at pin NRES.

ERR and WARN indicate internal errors which are se-

lected using mask registers 0x22 and 0x23. EWKH

and EWKL signal that write protection is active for

memory areas CONF and/or EDS. The BUSY bit

shows that the internal bus is busy, such as when data

is being read out from or written to the EEPROM. Bit

ADV (absolute data valid) indicates that absolute data

has been successfully read out through the absolute

data interface (ADI); bit PDV (position data valid) sig-

nals that position data is valid. If the conﬁguration

register has been successfully CRCed and if absolute

data has been correctly read out through the absolute

data interface (ADI), the INIT bit is also set.

Command 0x04 triggers a CRC of the internal conﬁgu-

ration, during which all conﬁguration registers are read

out and veriﬁed by the check sum in registers 0x2E-

0x2F. During this process the BUSY bit in the status

byte and the ERR_KNF bit are set in the error byte.

If the process ends successfully, the ERR_KNF bit is

cancelled.

Commands 0x05 and 0x06 simulate errors for the ERR

bit in the status byte, with 0x05 setting the bit and 0x06

disabling it.

STATUS

Bit

Addr. 0x60; bit 7...0

Status message

R

CMD

Code

0x00

0x01

0x02

0x03

0x04

0x05

0x06

Addr. 0x60; bit 7...0

Function

W

INIT

Conﬁguration complete

Request new position data

ERR

Signalizes error as per mask register EMASK

Write current conﬁguration in EEPROM

Readout new data via absolute data interface

Trigger software reset

WARN

EWKH

EWKL

BUSY

ADV

Signalizes warning as per mask register WMASK

Writing memory area CONF permitted

Writing memory area EDS permitted

Internal data bus busy

CRC check of internal conﬁguration

Activate error simulation ERR bit

Deactivate error simulation ERR bit

Absolute data valid

PDV

Position data valid

Note

All bits signal active high.

Table 81: Command register

Table 80: Status byte

Error mask

On write access register 0x60 acts as a command reg-

ister.

Error byte 0x69 (Table 82) signals internal and external

errors.

ERR_EXT is activated by input pin NERR and con-

veys errors which occur in external devices. Error

bits ERR_EXT, ERR_SYN, ERR_TMP, ERR_AMP, and

ERR_RGL are stored and only cancelled if the error

byte is read accessed. This information is stored for

the parallel interface and for the serial interface in SPI

mode. The following errors are reported:

If command 0x00 is written, new position data is re-

quested. As long as this new data is not yet available,

the PDV (position data valid) bit is disabled in the sta-

tus byte.

Command 0x01 writes the current conﬁguration to the

EEPROM. If no EEPROM is connected up on startup,

this commend has no effect. The conﬁguration - up to

and including register 0x2D - and a newly generated

check sum are otherwise written to the EEPROM. For

the duration of the write process the BUSY bit in the

status byte and the ERR_KNF bit (conﬁguration er-

ror) are set in the error byte. If an error occurs, the

ERR_KNF bit is not cancelled at the end of the pro-

cess.

ERROR

Addr. 0x69; bit 7...0

Error message

R

Bit

ERR_EXT Externally signalized error *

ERR_ABS Error in readout of absolute value

ERR_IPO

Fallen below conversion time of interpolator

ERR_KNF Conﬁguration error

ERR_SYN Synchronisation error counter/interpolator *

ERR_TMP Temperature beyond thresholds *

ERR_AMP Amplitude error *

ERR_RGL Beyond control range of transmit current control *

Command 0x02 triggers a new readout of absolute

data through the absolute data interface. Should this

readout not prove successful, it is set to zero for in-

ternal calculation. At the end of the process status bit

Note

*) Stored message, reset after read access

Table 82: Error byte

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 42/44

Error bits ERR_EXT, ERR_SYN, ERR_TMP, Register EMASK deﬁnes a mask for the ERR bit in the

ERR_AMP and ERR_RGL are stored internally. status byte. If the relevant bit is set in the mask reg-

RES_ERR is used to choose which action resets the ister, the corresponding error bit in the error register is

error bit.

signaled as ERR in the status byte. In the same man-

ner, register WMASK deﬁnes a mask for the WARN bit

in the status byte.

RES_ERR

Addr. 0x27; bit 6

Function

R/W

Code

0

1

Reset by readout position data

Reset by readout error register

EMASK

Bit

Addr. 0x22; bit 7...0

Message

EM_EXT

EM_ABS

EM_IPO

EM_KNF

EM_SYN

EM_TMP

EM_AMP

EM_RGL

Externally signalized error

Table 83: Error reset

Error in readout of absolute value

Fallen below conversion time of interpolator

Conﬁguration error

Error bit ERR_AMP can be assigned with a digital ﬁlter.

The ﬁlter is implemented as an integrator with timeout.

If required a bypass can be conﬁgured (EN_FAMP).

The timeout resets the integrator cyclically (conﬁg-

urable by using TO_FAMP). The error output’s thresh-

old value is conﬁgurable and the error output is being

set at a duty cycle of a timeout period of 17, 34, 51 or

68 µs.

Synchronisation error counter/interpolator

Temperature beyond thresholds

Amplitude error

Beyond control range of transmit current control

Table 87: Mask for error ERR (Addr. 0x60, bit 6)

WMASK

Addr. 0x23; bit 7...0

Message

THR_FAMP

Code

0x0

Addr. 0x2B; bit 3...2

Function

R/W

Bit

WM_EXT

WM_ABS

WM_IPO

WM_KNF

WM_SYN

WM_TMP

Externally signalized error

Threshold at 17 µs duty cycle of timeout period

Threshold at 34 µs duty cycle of timeout period

Threshold at 51 µs duty cycle of timeout period

Threshold at 68 µs duty cycle of timeout period

Error in readout of absolute value

Fallen below conversion time of interpolator

Conﬁguration error

0x1

0x2

0x3

Synchronisation error counter/interpolator

Temperature beyond thresholds

Table 84: Amplitude error ﬁlter threshold

WM_AMP Amplitude error

WM_RGL

Beyond control range of transmit current control

TO_FAMP

Addr. 0x2B; bit 1

Function

R/W

Table 88: Mask for warning WARN (Addr. 0x60, bit 5)

Code

0

1

Timeout after 273 µs

Timeout after 546 µs

Life counter

Life counter LC counts the position data generated and

is zeroed on a reset. In normal operation, however,

zero is bypassed and cannot occur (order: 0xFE, 0xFF,

0x01, 0x02 ...).

Table 85: Amplitude error ﬁlter timeout

EN_FAMP

Addr. 0x2B; bit 0

Function

R/W

Code

0

1

Filter for amplitude error deactivated

Filter for amplitude error active

Table 86: Amplitude error ﬁltering

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 43/44

DESIGN REVIEW: Application notes

iC-MR Y1

No.

1

Function, parameter/code

Description and application notes

NEFDR, LCMODE,

CHK_ADI

These functions are not available. Mandatory programming of the corresponding

register bits is zero.

2

3

4

RES_ERR,

THR_FAMP, TO_FAMP, EN_FAMP

These functions are not available. Mandatory programming of the corresponding

register bits is zero.

PROFILE(15:0),

Addr 0x48, 0x49

These addresses are not assigned. The recommended programming value is

zero.

DEV_ID(47:0),

Addr 0x72 to 0x77

These addresses are not assigned. The recommended programming value is

zero.

Table 89: Notes on chip functions regarding iC-MR chip release Y1

iC-MR X

No.

1

Function, parameter/code

Description and application notes

None at time of printing.

Table 90: Notes on chip functions regarding iC-MR chip release X

REVISION HISTORY

Rel

Rel.Date Chapter

Modiﬁcation

Page

A1

13-11-21

Initial release

all

iC-Haus expressly reserves the right to change its products and/or speciﬁcations. An info letter gives details as to any amendments and additions made to the

relevant current speciﬁcations on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by

email.

Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

iC-Haus does not warrant the accuracy, completeness or timeliness of the speciﬁcation and does not assume liability for any errors or omissions in these

materials.

The data speciﬁed is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, ﬁtness

for a particular purpose or of any other nature are made hereunder with respect to information/speciﬁcation or the products to which information refers and no

guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of

the product.

iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade

mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.

iC-MR 13-BIT S&H SIN/COS

INTERPOLATOR WITH CONTROLLER INTERFACES

Rev A1, Page 44/44

ORDERING INFORMATION

Type

Package

Order Designation

iC-MR

48-pin QFN 7x7 mm

iC-MR QFN48

Evaluation Board

iC-MR EVAL MR1D

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH

Tel.: +49 (0) 61 35 - 92 92 - 0

Fax: +49 (0) 61 35 - 92 92 - 192

Web: http://www.ichaus.com

E-Mail: sales@ichaus.com

Am Kuemmerling 18

D-55294 Bodenheim

GERMANY

Appointed local distributors: http://www.ichaus.com/sales_partners


型号：	IC-MR
厂家：	IC-HAUS GMBH
描述：	13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES 13位S ＆H SIN / COS插补算法Controller接口
文件：	总44页 (文件大小：1160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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