IC-MSB2EVALMSB1D [ICHAUS]
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER; SIN / COS信号调理与1Vpp典型DRIVER型号: | IC-MSB2EVALMSB1D |
厂家: | IC-HAUS GMBH |
描述: | SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER |
文件: | 总29页 (文件大小:584K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 1/29
FEATURES
APPLICATIONS
♦ PGA inputs to 500 kHz for differential and single-ended sensor
signals
♦ Selectable adaptation to voltage or current signals
♦ Flexible pin assignment due to signal path multiplexers
♦ Sine/Cosine signal conditioning for offset, amplitude and
phase
♦ Programmable sensor interface
for optical and magnetic position
sensors
♦ Linear gauges and incremental
encoders
♦ Linear scales
♦ Separate index signal conditioning
♦ Short-circuit-proof and reverse polarity tolerant output drivers
(1 Vpp to 100 Ω)
♦ Stabilized output signal levels due to sensor control
♦ Signal and system monitoring with configurable alarm output
♦ Supply voltage monitoring with integrated switches for
reversed-polarity-safe systems
PACKAGES
♦ Excessive temperature protection with sensor calibration
♦ I2C multimaster interface
♦ Supply from 4.3 to 5 V, operation within -25(-40) to +100 °C
♦ Suitable for SAFETY applications
TSSOP20, TSSOP20-TP
♦ Verifyable chip release code
♦ Version iC-MSB2 with output multiplexer (not for SAFETY)
BLOCK DIAGRAM
Copyright © 2006, 2010 iC-Haus
http://www.ichaus.com
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 2/29
DESCRIPTION
iC-MSB is a signal conditioner with line drivers for compensated for and the set signal amplitude main-
sine/cosine sensors which are used to determine po- tained with absolute accuracy. At the same time the
sitions in linear and angular encoders, for example.
control circuitry monitors both whether the sensor is
functioning correctly and whether it is properly con-
Programmable instrumentation amplifiers with se- nected; signal loss due to wire breakage, short cir-
lectable gain levels permit differential or referenced cuiting, dirt or aging, for example, is recognized when
input signals; at the same time the modes of op- control thresholds are reached and indicated at alarm
eration differentiate between high and low input output ERR.
impedance. This adaptation of the iC to voltage or
current signals enables MR sensor bridges or photo- iC-MSB is protected against a reversed power supply
sensors to be directly connected up to the device.
voltage; the integrated voltage switch for loads of up
to 20 mA extends this protection to cover the overall
The integrated signal conditioning unit allows signal system. The analog output drivers are directly cable-
amplitudes and offset voltages to be calibrated accu- compatible and tolerant to false wiring; if supply volt-
rately and also any phase error between the sine and age is connected up to these pins, the device is not
cosine signals to be corrected. Separate zero signal destroyed.
conditioning settings can be made for the gain and
offset; data is then output either as an analog or a The device configuration and calibration parameters
differential square-wave signal (low/high level analo- are CRC protected and stored in an external EEP-
gous to the sine/cosine amplitude).
ROM; they are loaded automatically via the I2C in-
terface once the supply voltage has been connected
For the stabilization of the sine and cosine output sig- up.
nal levels a control signal is generated from the con-
ditioned and calibrated input signals which can power A safety-technical analysis of iC-MSB on device level
the transmitting LED of optical systems via the inte- with the inclusion of layout and internal/external cir-
grated 50 mA driver stage (output ACO). If MR sen- cuitry has been carried out together with the BGIA,
sors are connected this driver stage also powers the St. Augustin. The result proved iC-MSB’s capability
measuring bridges.
for safety oriented applications with Siemens Sinu-
merik Controls.
By tracking the sensor energy supply any signal vari-
ations and temperature and aging effects can be
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 3/29
CONTENTS
PACKAGES
4
5
SIGNAL PATH MULTIPLEXING: iC-MSBSAFETY
18
EXTENDED SIGNAL PATH MULTIPLEXING:
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
( not for safety applications )
iC-MSB2
19
21
5
SIGNAL CONDITIONING CH1, CH2
Gain Settings CH1, CH2 . . . . . . . . . . . . 21
Offset Calibration CH1, CH2 . . . . . . . . . 22
Phase Correction CH1 vs. CH2 . . . . . . . . 22
ELECTRICAL CHARACTERISTICS
PROGRAMMING
6
10
SIGNAL CONDITIONING CH0
23
SERIAL CONFIGURATION INTERFACE
(EEPROM)
13
Gain Settings CH0 . . . . . . . . . . . . . . . 23
Offset Calibration CH0 . . . . . . . . . . . . . 23
Example of CRC Calculation Routine . . . . . 13
EEPROM Selection . . . . . . . . . . . . . . 13
I2C Slave Mode (ENSL = 1) . . . . . . . . . . 14
SIGNAL LEVEL CONTROL and SIGNAL
MONITORING
24
25
BIAS SOURCE AND TEMPERATURE
ERROR MONITORING AND ALARM OUTPUT
SENSOR CALIBRATION
15
16
Error Protocol . . . . . . . . . . . . . . . . . . 25
I/O pin ERR . . . . . . . . . . . . . . . . . . . 25
OPERATING MODES
Calibration Op. Modes . . . . . . . . . . . . . 16
Special Device Test Functions . . . . . . . . 16
Signal Filter . . . . . . . . . . . . . . . . . . . 16
TEMPERATURE MONITORING
26
26
27
REVERSE POLARITY PROTECTION
TEST MODE
17 APPLICATION HINTS
Connecting MR sensor bridges for
INPUT CONFIGURATIONS
18
safety-related applications . . . . . . . . 27
Input Configurations . . . . . . . . . . . . . . 18
PLC Operation . . . . . . . . . . . . . . . . . 27
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 4/29
PACKAGES
PIN CONFIGURATION TSSOP20, TSSOP20-TP
PIN FUNCTIONS
No. Name Function
1 X1
2 X2
3 X3
4 X4
Signal Input 1 (Index +)
Signal Input 2 (Index -)
Signal Input 3
Signal Inout 4
5 VDDS Switched Supply Output
(reverse polarity proof, load to 20 mA
max.)
6 GNDS Switched Ground
(reverse polarity proof)
7 X5
8 X6
Signal Input 5
Signal Input 6
9 ACO Signal Level Controller,
high-side current source output
10 SDA Serial Configuration Interface,
data line
11 SCL
Serial Configuration Interface,
clock line
12 NC
13 PC
14 NS
15 PS
Neg. Cosine Output
Pos. Cosine Output
Neg. Sine Output
Pos. Sine Output
16 GND Ground
17 VDD +4.5 to +5.5 V Supply Voltage
18 NZ
19 PZ
Neg. Index Output
Pos. Index Output
20 ERR Error Signal (In/Out),
Test Mode Trigger Input
To improve heat dissipation the thermal pad of the TSSOP20-TP package (bottom side) should be joined
to an extended copper area which must have GNDS potential.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 5/29
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Voltage at VDD, GND, PC, NC, PS, NS,
PZ, NZ, ACO
-6
6
V
G002 V()
G003 V()
Voltage at ERR
-6
8
6
V
V
Pin-To-Pin Voltage between VDD,
GND, PC, NC, PS, NS, PZ, NZ, ACO,
ERR
G004 V()
Voltage at X1...X6, SCL, SDA
-0.3
VDDS +
0.3
V
G005 I(VDD)
G006 I()
Current in VDD
-100
-50
100
50
mA
mA
mA
Current in VDDS, GNDS
G007 I()
Current in X1...X6, SCL, SDA, ERR,
PC, NC, PS, NS, PZ, NZ
-20
20
G008 I(ACO)
G009 Vd()
G010 Ptot
Current in ACO
-100
20
2
mA
kV
ESD Susceptibility at all pins
Permissible Power Dissipation
HBM 100 pF discharged through 1.5 kΩ
TSSOP20
TSSOP20-TP
300
400
mW
mW
G011 Tj
G012 Ts
Junction Temperature
-40
-40
150
150
°C
°C
Storage Temperature Range
THERMAL DATA
Item Symbol
No.
Parameter
Operating Ambient Temperature Range
Conditions
Unit
Min. Typ. Max.
T01 Ta
iC-MSB TSSOP20, iC-MSB2 TSSOP20
iC-MSB TSSOP20-TP
-25
-40
100
115
°C
°C
T02 Rthja
T03 Rthja
Thermal Resistance Chip to Ambient TSSOP20 surface mounted to PCB
according to JEDEC 51
80
35
K/W
Thermal Resistance Chip to Ambient TSSOP20-TP surface mounted to PCB
according to JEDEC 51
K/W
All voltages are referenced to Pin GNDS unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 6/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001
VDD
Permissible Supply Voltage
Load current I(VDDS) < -10 mA
Tj = 27 °C, no load
4.3
4.5
5.5
5.5
V
V
002 I(VDD)
003 I(VDDS)
004 Vcz()hi
005 Vc()hi
Supply Current in VDD
25
50
0
mA
mA
V
Permissible Load Current VDDS
Clamp Voltage hi at all pins
-20
11
1.5
Clamp Voltage hi at inputs
SCL, SDA
Vc()hi = V() − V(VDDS), I() = 1 mA
Vc()hi = V() − V(VDDS), I() = 4 mA
I() = -4 mA
0.4
0.3
V
006 Vc()hi
007 Vc()lo
Clamp Voltage hi at inputs
X1...X6
1.2
V
V
Clamp Voltage lo at all pins
-1.2
-0.3
Signal Conditioning, Inputs X3...X6
101
Vin()sig
Permissible Input Voltage Range
RIN12(3:0) = 0x01
RIN12(3:0) = 0x09
0.75
0
VDDS
− 1.5
VDDS
V
V
102
Iin()sig
Permissible Input Current Range
RIN12(0) = 0, BIAS12 = 0
RIN12(0) = 0, BIAS12 = 1
-300
10
-10
300
µA
µA
103 Iin()
104
Input Current
RIN12(3:0) = 0x01
-10
10
µA
Rin()
Input Resistance vs. VREFin
Tj = 27 °C;
RIN12(3:0) = 0x09
RIN12(3:0) = 0x00
RIN12(3:0) = 0x02
RIN12(3:0) = 0x04
RIN12(3:0) = 0x06
16
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
24
2.1
3.0
4.2
6.0
kΩ
kΩ
kΩ
kΩ
kΩ
105 TCRin()
Temperature Coefficient Rin
0.15
%/K
106
VREFin12 Reference Voltage
RIN12(0) = 0, BIAS12 = 1
RIN12(0) = 0, BIAS12 = 0
1.35
2.25
1.5
2.5
1.65
2.75
V
V
107
G12
Selectable Gain Factors
RIN12(3:0) = 0x01, GR12 and GF12 = 0x0
RIN12(3:0) = 0x01, GR12 and GF12 = max.
2
100
RIN12(3:0) = 0x09, GR12 and GF12 = 0x0
RIN12(3:0) = 0x09, GR12 and GF12 = max.
0.5
25
108 ∆Gdiff
109 ∆Gabs
Differential Gain Accuracy
Absolute Gain Accuracy
calibration range 11 bit
-0.5
-1
0.5
1
LSB
LSB
calibration range 11 bit, guaranteed monotony
110
Vin()diff
Recommended Differential Input
Voltage
Vin()diff = V(CHPx) - V(CHNx),
RUIN12(3) = 0
10
40
500
2000
mVpp
mVpp
RUIN12(3) = 1
111 Vin()os
112
Input Offset Voltage
refered to side of input
0
20
µV
VOScal
Offset Calibration Range
referenced to the selected source (VOS12);
ORx = 00
ORx = 01
ORx = 10
ORx = 11
±100
±200
±600
±1200
%V()
%V()
%V()
%V()
113 ∆VOSdiff Differential Linearity Error of
calibration range 11 bit
-0.5
-1
0.5
1
LSB
Offset Correction
114 ∆VOSint Integral Linearity Error of Offset calibration range 11 bit
LSB
Correction
115 PHIkorr
Phase Error Calibration Range
CH1 versus CH2
±10.4
°
116 ∆PHIdiff
Differential Linearity Error of
Phase Calibration
calibration range 10 bit
-0.5
-1
0.5
1
LSB
117 ∆PHIint
Integral Linearity Error of Phase calibration range 10 bit
Calibration
LSB
119 fin()max
120 fhc()
Permissible Input Frequency
500
250
kHz
kHz
Input Amplifier Cut-off Frequency
(-3dB)
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 7/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Signal Conditioning, Inputs X1, X2
201
Vin()sig
Permissible Input Voltage Range
RIN0(3:0) = 0x01
RIN0(3:0) = 0x09
0.75
0
VDDS
− 1.5
VDDS
V
V
202
Iin()sig
Permissible Input Current Range
RIN0(0) = 0, BIAS0 = 0
RIN0(0) = 0, BIAS0 = 1
-300
10
-10
300
µA
µA
203 Iin()
Input Current
RIN0(3:0) = 0x01
-10
95
10
µA
%
V
204 Vout(X2)
205 Vin(X2)
Output Voltage at X2
BIASEX = 10, I(X2) = 0, referenced to VREFin12
100
27
105
Permissible Input Voltage at X2 BIASEX = 11
0.5
VDDS
− 2
30
206 Rin(X2)
Input Resistance at X2
BIASEX = 11, RIN0(3:0) = 0x01,
20
kΩ
RIN12(3:0) = 0x01
207
Rin()
Input Resistance vs. VREFin
Tj = 27 °C;
RIN0(3:0) = 0x09
RIN0(3:0) = 0x00
RIN0(3:0) = 0x02
RIN0(3:0) = 0x04
RIN0(3:0) = 0x06
16
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
24
2.1
3.0
4.2
6.0
kΩ
kΩ
kΩ
kΩ
kΩ
208 TCRin()
Temperature Coefficient Rin
0.15
%/K
209
VREFin0 Reference Voltage
RIN0(0) = 0, BIAS0 = 1
RIN0(0) = 0, BIAS0 = 0
1.35
2.25
1.5
2.5
1.65
2.75
V
V
210
G0
Selectable Gain Factors
RIN0(3:0) = 0x01, GR0 and GF0 = 0x0
RIN0(3:0) = 0x01, GR0 and GF0 = max.
2
100
RIN0(3:0) = 0x09, GR0 and GF0 = 0x0
RIN0(3:0) = 0x09, GR0 and GF0 = max
0.5
25
211 ∆Gdiff
212 ∆Gabs
Differential Gain Accuracy
Absolute Gain Accuracy
calibration range 5 bit
-0.5
-1
0.5
1
LSB
LSB
calibration range 5 bit, guaranteed monotony
213
Vin()diff
Recommended Differential Input
Voltage
Vin()diff = V(CHP0) - V(CHN0),
RIN0(3:0) = 0x01
10
40
500
2000
mVpp
mVpp
RIN0(3:0) = 0x09
214 Vin()os
215
Input Offset Voltage
referred to side of input
0
75
µV
VOScal
Offset Calibration Range
referenced to the selected source (REFVOS);
OR0 = 00
OR0 = 01
OR0 = 10
OR0 = 11
±100
±200
±600
±1200
%V()
%V()
%V()
%V()
216 ∆VOSdiff Differential Linearity Error of
calibration range 6 bit
-0.5
-1
0.5
1
LSB
Offset Correction
217 ∆VOSint Integral Linearity Error of Offset calibration range 6 bit
LSB
Correction
Signal Filter
301
4000
10
kHz
°
fg
Cut-off Frequency
Phase Shift
302
fin 500 kHz for sine/cosine
phi
Index Pulse Comparator Output PZ, NZ
401 Vpk()
Output Amplitude With Sensor
Tracking via ACO
EAZ = 1, ADJ(4:0) = 0x19
EAZ = 1
225
250
1
275
mV
402 SR()
Output Slew Rate
V/µs
Line Driver Outputs PS, NS, PC, NC, PZ, NZ
501
Vpk()max Permissible Output Amplitude
VDD = 4.5 V, DC level = VDD / 2,
RL = 50 Ω vs. VDD / 2
300
275
mV
mV
502 Vpk()
Output Amplitude With Sensor
Tracking via ACO
ADJ (8:0) = 0x19
CL = 250 pF
225
500
250
503 fg
Cut-off Frequency
Offset Voltage
kHz
µV
504 Vos
505 Isc()
506 Ilk()
±200
30
Short-circuit Current
Tristate Leakage Current
pin shorten to VDD or GND
tristate or reversed supply
10
-1
50
1
mA
µA
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 8/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Signal Level Controller ACO
601
Vs()hi
Saturation Voltage hi
at ACO vs. VDD
Vs() = VDD - V();
ADJ(8:0) = 0x11F, I() = -5 mA
ADJ(8:0) = 0x13F, I() = -10 mA
ADJ(8:0) = 0x15F, I() = -25 mA
ADJ(8:0) = 0x17F, I() = -50 mA
1
1
1
1
V
V
V
V
602
Isc()hi
Short-circuit Current hi in ACO
V() = 0 ... VDD - 1 V;
ADJ(8:0) = 0x11F
ADJ(8:0) = 0x13F
ADJ(8:0) = 0x15F
ADJ(8:0) = 0x17F
-10
-20
-50
-5
mA
mA
mA
mA
-10
-25
-50
-100
603 tr()
Current Rise Time in ACO
I(ACO): 0 → 90 % setpoint
1
ms
µs
604 tset()
Current Settling Time in ACO
Square control active, I(ACO): 50 → 100 %
400
setpoint
605 It()min
606 It()max
607 Vt()min
608 Vt()max
Control Range Monitoring 1:
lower limit
referenced to range ADJ(6:5)
referenced to range ADJ(6:5)
referenced to Vscq()
3
%Isc
%Isc
Control Range Monitoring 2:
upper limit
90
Signal Level Monitoring 1:
lower limit
40
%Vpp
%Vpp
Signal Level Monitoring 2:
upper limit
referenced to Vscq()
130
Test Current ERR
701 I(ERR)
Permissible Test Current
test mode activated
0
1
mA
Bias Current Source and Reference Voltages
801 IBN()
802 VPAH
Bias Current Source
MODE(3:0) = 0x01, I(NC) vs. VDDS
referenced to GND
180
45
200
50
220
55
µA
%VDD
mV
Reference Voltage VPAH
Reference Voltage V05
Reference Voltage V025
803 V05
450
500
50
550
804 V025
%V05
Power-Down-Reset
901 VDDon
Turn-on Threshold
(power-on release)
increasing voltage at VDD vs. GND
decreasing voltage at VDD vs. GND
VDDhys = VDDon − VDDoff
3.7
3.2
0.3
4
4.3
3.8
V
V
V
902 VDDoff
Turn-off Threshold
(power-down reset)
3.5
903 VDDhys
Clock Oscillator
A01 fclk()
Threshold Hysteresis
Internal Clock Frequency
MODE(3:0) = 0x0A, fclk(NS)
vs. GND, I() = 4 mA
120
160
200
0.4
kHz
V
Error Signal Input/Output, Pin ERR
B01 Vs()lo
B02
Saturation Voltage lo
Short-circuit Current lo
Isc()
vs. GND; V(ERR) ≤ VDD
4
2
mA
mA
V(ERR) > VTMon
B03 Vt()hi
B04 Vt()lo
B05 Vt()hys
B06 Ipu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
vs. GND
2
V
V
vs. GND
0.8
300
-400
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDD − 1 V, EPU = 1
EPU = 0
500
-300
500
mV
µA
kΩ
V
Input Pull-up Current
Input Pull-Up Resistor
Pull-up Voltage
-200
0.4
B07 Rpu()
B08 Vpu()
B09 VTMon
Vpu() = VDD - V(), I() = -5 µA, EPU = 1
Test Mode Activation Threshold increasing voltage at ERR
VDD +
1.5
V
B10 VTMoff
Test Mode Disabling Threshold
decreasing voltage at ERR
VDD +
0.5
V
B11 VTMhys
B12 Ilk()
Test Mode Hysteresis
Leakage Current
VTMhys = VTMon − VTMoff
tristate or reversed supply voltage
0.15
-1
0.3
-10
V
-50
µA
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 9/29
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...125 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Supply Switch and Reverse Polarity Protection VDDS, GNDS
C01
Vs()
Saturation Voltage
VDDS vs. VDD
Vs(VDDS) = VDD − V(VDDS)
I(VDDS) = -10 mA...0 mA
I(VDDS) = -20 mA...-10 mA
150
250
mV
mV
C02
Vs()
Saturation Voltage
GNDS vs. GND
Vs(GNDS) = V(GNDS) − GND
I(GNDS) = 0 mA...10 mA
150
250
mV
mV
I(GNDS) = 10 mA...20 mA
Serial Configuration Interface SCL, SDA
D01 Vs()lo
D02 Isc()
Saturation Voltage lo
Short-circuit Current lo
I() = 4 mA
400
80
2
mV
mA
V
4
D03 Vt()hi
D04 Vt()lo
D05 Vt()hys
D06 Ipu()
D07 Vpu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
0.8
300
-600
V
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDDS − 1 V
500
mV
µA
V
Input Pull-up Current
-300
-60
0.4
Input Pull-up Voltage
Vpu() = VDDS − V(), I() = -5 µA
D08
fclk(SCL) Clock Frequency at SCL
ENFAST = 0
ENFAST = 1
60
240
80
320
100
400
kHz
kHz
D09
tbusy()cfg Duration of Startup Configuration
IBN not calibated, EEPROM access without
read failure, time to outputs operational;
ENFAST = 0
40
25
55
35
ms
ms
ENFAST = 1
D10
D11
tbusy()err End Of I2C Communication;
IBN not calibrated;
Time Until I2C Slave Is Enabled V(SDA) = 0 V
4
indef.
45
12
ms
ms
ms
ms
V(SCL) = 0 V or arbitration lost
no EEPROM
CRC ERROR
135
285
95
td()
Start Of Master Activity On I2C
Protocol Error
SCL without clock signal: V(SCL) = constant;
IBN not calibrated
IBN calibrated to 200 µA
25
64
80
80
240
120
µs
µs
D12 td()i2c
Delay for I2C-Slave-Mode Enable no EEPROM, V(SDA) = 0 V
4
6.2
ms
Temperature Monitoring
E01
E02 TCs
E03
VTs
Temperature Sensor Voltage
VTs() = VDDS − V(PS), Tj = 27 °C,
600
650
-1.8
700
mV
Calibration Mode 3, no load
Temp. Co. of Temperature Sen-
sor Voltage
mV/K
VTth
Temperature Warning Activation
Threshold
VTth() = VDDS − V(NS), Tj = 27 °C,
Calibration Mode 3, no load;
CFGTA(3:0) = 0x00
260
470
310
550
360
630
mV
mV
CFGTA(3:0) = 0x0F
E04 TCth
Temp. Co. Temperature Warning
Activation Threshold
0.06
%/K
E05 Thys
Temperature Warning Hysteresis
4
4
12
12
20
20
°C
°C
E06 ∆T
Relative Shutdown Temperature ∆T = Toff − Twarn
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 10/29
PROGRAMMING
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 Signal Conditioning CH1, CH2 (X3...X6) . . Page 21
GR12:
GF1:
Gain Range CH1, CH2 (coarse)
Gain Factor CH1 (fine)
GF2:
Gain Factor CH2 (fine)
Configuration Interface . . . . . . . . . . . . . . . . . . . Page 13
ENFAST:
ENSL:
I2C Fast Mode Enable
VOS12:
VDC1:
VDC2:
OR1:
OF1:
OR2:
Offset Reference Source CH1, CH2
Intermediate Voltage CH1
Intermediate Voltage CH2
Offset Range CH1 (coarse)
Offset Factor CH1 (fine)
Offset Range CH2 (coarse)
Offset Factor CH2 (fine)
Phase Correction CH1 vs. CH2
I2C Slave Mode Enable
DEVID:
Device ID of EEPROM providing the
chip configuration data (e.g. 0x50)
CRC of chip configuration data
(address range 0x00 to 0x1E)
Chip Release
CHKSUM:
OF2:
PH12:
CHPREL:
NTRI:
Tristate Function and
Op. Mode Change
Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 23
GR0:
GF0:
VOS0:
OR0:
OF0:
Gain Range CH0 (coarse)
Gain Factor CH0 (fine)
Offset Reference Source CH0
Offset Range CH0 (coarse)
Offset Factor CH0 (fine)
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGIBN:
CFGTA:
Bias Calibration
Temperature Sensor Calibration
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 16
MODE:
ENF:
Operation Mode
Signal Filtering
Signal Level Controller . . . . . . . . . . . . . . . . . . . . Page 24
ADJ: Setup of ACO Output Function
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Seite 17
TMODE:
TMEM:
Test Mode Functions
Test Mode Memory Selection
Error Monitoring and Alarm Output . . . . . . Page 25
EMTD:
EPH:
Minimal Alarm Indication Time
Alarm Input/Output Logic
Input Configuration and
Signal Path Multiplexer . . . . . . . . . . . . . . . . . . . Page 18
INMODE:
RIN12:
EPU:
EMASKA:
Alarm Output Pull-Up Enable
Error Mask For Alarm Indication (pin
ERR)
Diff./Single-Ended Input Mode
I/V Mode and Input Resistance CH1,
CH2
Reference Voltage CH1, CH2
I/V Mode and Input Resistance CH0
Reference Voltage CH0
EMASKE:
EMASKO:
Error Mask For Protocol (EEPROM)
Error Mask For Driver Shutdown
BIAS12:
RIN0:
BIAS0:
MUXIN:
ERR1:
ERR2:
ERR3:
Error Protocol: First Error
Error Protocol: Last Error
Error Protocol: History
Input-To-Channel Assignment:
X3...X6 to CH1, CH2
INVZ:
EAZ:
MUXOUT:
BIASEX:
BYP
Index Signal Inversion
PDMODE:
Driver Activation After Cycling Power
Index Comparator Enable
Output Multiplexer (iC-MSB2 only)
Input Reference Selection
Input-to-output Feedthrough
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 11/29
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration Interface
0x00
ENFAST
DEVID(6:0)
Calibration
0x01
CFGIBN(3:0)
CFGTA(3:0)
Operation Modes
0x02 NTRI
1
0
–
MODE(3:0)
Input Configuration and Signal Path Multiplexer: iC-MSB
0x03 EAZ
Input Configuration and Signal Path Multiplexer: iC-MSB2
0
0
0
INVZ
INVZ
INMODE
MUXIN(1:0)
0x03
EAZ
MUXOUT(2:0)
INMODE
MUXIN(1:0)
Signal Conditioning CH1, CH2
0x04
0x05
0x06
GF2(4:0)
GR12(2:0)
GF1(7:0)
VDC1(4:0)
GF1(10:8)
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
VDC2(2:0)
VDC1(9:5)
OR1(0)
VDC2(9:3)
OF1(6:0)
OR2(1:0)
OR1(1)
OF2(1:0)
OF1(10:7)
OF2(9:2)
PH12(6:0)
1
OF2(10)
BIASEX(1:0)
BYP
1
0
PH12(9:7)
RIN12(3:0)
ENF
BIAS12
VOS12(1:0)
Signal Level Controller
0x0F
0x10
ADJ(0)
–
0
1
0
0
0
ADJ(8:1)
Signal Conditioning CH0
0x11
0x12
GF0(4:0)
GR0(2:0)
OF0(5:0)
VOS0(1:0)
OR0(1:0)
0x13
0
BIAS0
RIN0(3:0)
Error Monitoring and Alarm Output
0x14
0x15
0x16
0x17
0x18
–
EMASKA(6:0)
TMODE(1:0)
EMTD(2:0)
EPH
EPU
–
–
–
–
EMASKO(6:0)
EMASKE(3:0)
PDMODE
ENSL
–
–
TMEM
–
–
EMASKE(6:4)
0x19..
0x1A
not defined
0x1B..
0x1E
OEM Data
Check Sum
/ Chip Release
0x1F
EEPROM: CHKSUM(7:0)
/
ROM: CHPREL(7:0)
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 12/29
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Error Register
0x20
0x21
0x22
0x23
–
ERR1(6:0)
ERR2(5:0)
–
–
ERR3(3:0)
–
–
–
–
ERR2(6)
–
–
–
–
ERR3(6:4)
Table 4: Register layout
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 13/29
SERIAL CONFIGURATION INTERFACE (EEPROM)
The serial configuration interface consists of the two Example of CRC Calculation Routine
pins SCL and SDA and enables read and write access
to an EEPROM with I2C interface. The readout speed
can be adjusted using register bit ENFAST.
unsigned char ucDataStream
int iCRCPoly 0x11D ;
unsigned char ucCRC=0;
int 0;
= 0;
=
i
=
ENFAST
Code
0
Adr 0x00, bit 7
ucCRC = 1; / / s t a r t value ! ! !
Function
for ( iReg
= 0; iReg <31; iReg ++)
{
Regular clock rate, f(SCL) approx. 80 kHz
High clock rate, f(SCL) approx. 320 kHz
ucDataStream
for ( i =0; i <=7; i ++)
i f ( (ucCRC & 0x80 ) != ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1) iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream ucDataStream << 1;
= ucGetValue ( iReg ) ;
1
{
Notes
For in-circuit programming bus lines SCL and SDA
require pull-up resistors.
For line capacitances to 170 pF, adequate values
are:
4.7 kΩ with clock frequency 80 kHz
2 kΩ with clock frequency 320 kHz
^
=
}
}
The pull-up resistors may not be less than 1.5 kΩ.
To separate the signals a ground line between SCL
and SDA is recommended.
iC-MSB requires a supply voltage during EEPROM
programming (5 V to VDD).
EEPROM Selection
The following minimal requirements must be fulfilled:
• Operation from 3.3 to 5 V, I2C interface
Table 5: Config. Interface Clock Frequency
• Minimal 512 bit, 64x8
Once the supply has been switched on (power down
reset) the iC-MSB outputs are high impedance (tris-
tate) until a valid configuration is read out from the
EEPROM using device ID 0x50.
(address range used is 0x00 to 0x3F)
• Support of Page Write with Pages of at least 4
bytes. Otherwise error events can not be saved
to the EEPROM (EMASKE(9:0) = 0x000).
Bit errors in the 0x00 to 0x1E memory section are
pinpointed by the CRC deposited in register CHK-
SUM(7:0) (address 0x1F; the CRC polynomial used is
"1 0001 1101").
• Device ID 0x50 "1010 000", no occupation of
0x55 (A2...A0 = 0). Otherwise iC-MSB is not ac-
cessible in I2C slave mode via 0x55 (ENSL = 0).
Device recommendation: Atmel AT24C01B, 128x8
Should no valid configuration data being available (in-
correct CRC value or EEPROM missing), the readin
process is repeated; the system aborts following a
fourth faulty attempt and iC-MSB switches to I2C slave
mode.
For devices loading valid configuration data from the
EEPROM, the register bit ENSL decides for enabling
the I2C slave function.
ENSL
Code
0
Adr 0x17, bit 3
Function
Normal operation
1
I2C Slave Mode Enable (Device ID 0x55)
Table 6: Config. Interface Mode
The device ID for the EEPROM can be entered in reg-
ister DEVID(6:0) (address 0x00), from which iC-MSB
will take its configuration after exiting test mode (see
page 17). The DEVID(6:0) stored therein is then ac-
cepted.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 14/29
I2C Slave Mode (ENSL = 1)
Register
Read access in I2C slave mode (ENSL = 1)
Content
In this mode iC-MSB behaves like an I2C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MSB’s internal registers.
Address
0x00-0x18 Configuration: register addresses 0x00-0x18
0x19-0x1A Not available
0x1B-0x1E OEM data: register addresses 0x1B-0x1E
0x1F
Chip release (ROM)
For chip release verification purposes an identification
value is stored under ROM address 0x1F; a write ac-
cess to this address is not permitted.
0x20-0x23 Configuration: register addresses 0x20-0x23
0x24-0x37 Not available
0x38
Configuration: register address 0x18
0x39-0x3A Not available
CHPREL
Code
0x00
Adr 0x1F, bit 7:0 (ROM)
Chip Release
0x3B-0x3E OEM data: register addresses 0x1B-0x1E
0x3F
Chip release (ROM)
Not available
iC-MSB SAFETY v4
iC-MSB SAFETY v5
iC-MSB2 v5
0x40-0x43 Current error memory
0x44-0x7F Not available
0x04
0x05
0x25
Table 9: RAM Read Access
Table 7: Chip Release
Register
Address
0x00
Write access in I2C slave mode (ENSL = 1)
Access and conditions
NTRI
Code
0
Adr 0x02, bit 7
Changes possible, no restrictions
Function
0x01
Changes possible (wrong entries for CFGIBN can
limit functions)
Output drivers disabled
1
Setting the operating mode, output drivers active
NTRI is evaluated only during I2C slave mode.
0x02
Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits
(6:0) are not permitted.
Notes
Table 8: Tristate Function And Op. Mode Change
0x03-0x16 Changes possible, no restrictions
0x17
Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
0x18
Changes possible, no restrictions
0x19-0x1A Not available
0x1B-0x1E Changes possible, no restrictions
others
No changes permitted
Table 10: RAM Write Access
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 15/29
BIAS SOURCE AND TEMPERATURE SENSOR CALIBRATION
Bias Source Calibration
The necessary activation threshold voltage VTth(T1) is
The calibration of the bias current source in operation then calculated. The required warning temperature T2,
mode Calibration 1 (Tab. 13) is prerequisite for adher- temperature coefficients TCs and TCth (see Electrical
ence to the given electrical characteristics and also in- Characteristics, Section E) and measurement value
strumental in the determination of the chip timing (e.g. VTs(T1) are entered into this calculation:
SCL clock frequency). For setup purposes the IBN
value is measured using a 10 kΩ resistor by pin VDDS
connected to pin NC. The setpoint is 200 µA which is
equivalent to a measurement voltage of 2 V.
VTs(T1) + TCs · (T2 − T1)
VTth(T1) =
1 + TCth · (T2 − T1)
CFGIBN
Code k
0x0
Adr 0x01, bit 7:4
Example: For T2 = T1 + 100 K, VTth(T1) must be pro-
grammed to 443 mV.
31
39−k
31
39−k
IBN ∼
Code k
0x8
IBN ∼
100 %
103 %
107 %
111 %
115 %
119 %
124 %
129 %
79 %
81 %
84 %
86 %
88 %
91 %
94 %
97 %
0x1
0x9
Activation threshold voltage VTth(T1) is provided for a
high impedance measurement (10 MΩ) at output pin
NS (measurement versus VDDS) and must be set by
programming CFGTA(3:0) to the calculated value.
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
0x4
0x5
0x6
Example: Altering VTth(T1) from 310 mV (measured
with CFGTA(3:0)= 0x0) to 443 mV is equivalent to
143 %, the closest value for CFGTA is 0x9;
0x7
Table 11: Bias Current Source Calibration
CFGTA
Code k
0x0
Adr 0x01, bit 3:0
65+3k
VTth ∼
65
65+3k
65
Code k
0x8
VTth ∼
140 %
145 %
150 %
155 %
160 %
165 %
170 %
175 %
Temperature Sensor
The temperature monitor is calibrated in operating
mode Calibration Mode 3.
100 %
105 %
110 %
115 %
120 %
125 %
130 %
135 %
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
To set the required warning temperature T2 the tem-
perature sensor voltage VTs at which the warning is
generated is first determined. To this end a volt-
age ramp from VDDS towards GNDS is applied to
pin PS until pin ERR triggers an error message (for
EMASKA = 0x20 and EMTD = 0x00).
0x4
0x5
0x6
0x7
Notes
With CFGTA = 0xF Toff is 80 °C typ.,
with CFGTA = 0x0 Toff is 155 °C typ.
Example: VTs(T1) is ca. 650 mV, measured from
VDDS versus PS, with T1 = 25 °C;
Table 12: Calibration of Temperature Monitoring
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 16/29
OPERATING MODES
In order to calibrate iC-MSB, compensate for the input to the various operating modes; the line drivers and
signals and test iC-MSB the mode of operation must protection against reverse polarity facility are only ac-
be changed. The output function changes according tive in normal mode.
MODE(3:0)
BYP
Addr. 0x02; bit 3:0
Addr. 0x0D; bit 5
Code
0x00
Operating Mode
Normal operation
Calibration 1
Pin PS
PS
Pin NS
NS
Pin PC
PC
Pin NC
NC
Pin PZ
PZ
Pin NZ
NZ
Pin ERR
ERR
ERR
—
0x01
TANA0(2)
PCH1
VREFI0
NCH1
VPD
VREFI12
PCH2
—
IBN
PZI
NZI
0x02
Calibration 2
NCH2
CGUCK
NC_out
NC_out
VDC1
IPF
VDC2
V05
0x03
iC-Haus Test 1
iC-Haus Test 2
iC-Haus Test 3
VPAH
IERR
IERR
ERR
0x04
PS_out
PS_out
NS_out
NS_out
PC_out
PC_out
PZ_out
PZ_out
NZ_out
NZ_out
0x05
0x06
iC-Haus Test 4, BYP = 0
iC-Haus Test 4, BYP = 1
TANA12(0) TANA12(1) TANA12(2) TANA12(3) TANA12(4) TANA12(5) IERR
X4
X6
X3
X5
X1
X2
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Calibration 3
VTs
VTth
—
—
—
—
ERR
Saturation low
SCL, SDA and ERR low
—
—
TP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
iC-Haus Test 5
CLK6
—
—
—
—
—
—
IDDQ-Test
—
All PU/PD resistors, oscillator and supply voltage deactivated
—
—
—
—
—
—
—
Table 13: Selection of Operating Modes
Calibration Op. Modes
Signal Filter
In Calibration Mode 1 the user can measure the BIAS iC-MSB has a noise limiting signal filter to filter the con-
current (IBN), input amplifier reference potential VREFI ditioned analog signals. This can be activated using
and the analog signals from channel 0 following signal ENF.
conditioning (PCH0 and NCH0).
ENF
Code
0
Adr 0x0E, bit 7
In Calibration Mode 2 the conditioned signals from
channels 1 and 2 are output (PCH1, NCH1, PCH2
and NCH2). In addition the intermediate potentials of
the compensating circuits are also available for CH1
(VDC1) and CH2 (VDC2).
Function
Noise limiter deactivated
Noise limiter activated
1
Table 14: Signal Filtering
In Calibration Mode 3 the internal temperature moni-
toring signals are provided.
Special Device Test Functions
IDDQ-Test, Saturation Low, Saturation High, and Test
1 to 5 are test modes for iC-Haus device tests. With an
activated bypass (BYP = 1), mode iC-Haus Test 4 per-
mits the direct feedthrough of X1 - X6 input signals to
the output pins; in this instance the output impedance
is high-ohmic. Furthermore, if the input voltage divider
is selected (by RINx = 1- -1), it reduces the signal am-
plitudes to approx. 7/8.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 17/29
TEST MODE
iC-MSB switches to test mode when a voltage greater When test mode is quit with TMODE > 0, then iC-
than VTMon is applied to pin ERR (precondition: MSB again reads out its configuration from the EEP-
TMODE(0) = 1). In response iC-MSB transmits its con- ROM, accessible at the device ID filed to DEVID(6:0)
figuration settings as current-modulated data using er- of adr 0x00. In TMODE = 0x00 the EEPROM is read
ror signal I/O pin ERR either directly from the RAM completely; in all other cases only the address range
(for TMEM = 1) or after re-reading the EEPROM (for 0x00 to 0x21 is read to keep the configuration time
TMEM = 0).
for device testing short. When test mode is quit with
TMODE = 0x00 iC-MSB continues operation without
any interruption.
TMEM
Adr 0x18, bit 7
0
1
EEPROM contents
iC-MSB RAM contents
TMODE
Adr 0x15, bit 7:6
Code
Function during test
mode
Function following test
mode
Table 15: Test Mode Memory Selection
00
01
Normal operation
Normal operation
TMEM = 0:
Repeated read out of
EEPROM
Should the voltage at the ERR pin fall below
VTMoff test mode is terminated and data transmission
aborted.
Transmission of
EEPROM data, address
range 0x1B-0x7F
TMEM = 1:
Transmission of RAM
data, address range
0x3B-0x43
The clock rate for the data output is determined by
ENFAST. Two clock rates can be selected: 780 ns for
ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-
cal Characteristics, D08, for clock frequency and toler-
ances).
10
11
Normal operation
Repeated read out of
EEPROM
Transmission of
Repeated read out of
EEPROM data, address EEPROM
range 0x0-0x7F
Data is output in Manchester code via two clock pulses
per bit. To this end the lowside current source switches
between a Z state (OFF = 0 mA) and an L state (ON =
2 mA).
Table 16: Test Mode Functions
VP
U23-B
VP LM393
VP
7
8
6
5
VP
VP
C21
100nF
C22
100nF
-
The bit information lies in the direction of the current
source switch:
U22-S
AD8029
VN
U23-S
LM393
GND
7
+
4
4
Zero bit: change of state Z → L (OFF to ON)
JP4
R24
470
ERR
One bit: Change of state L → Z (ON to OFF)
max. 5V
VDD
M22
IRLML6401
C24
VP
R26
100pF
100k
R23
2K
C26
100nF
R28
51k
U22-A
U23-A
LM393
R25
2k
2
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is iden-
tical with an EEPROM access via the I2C interface).
D21
LL4148
-
M21
2N7002
6
2
3
DATA_ON
AD8029
-
3
1
NDIS
DATA_OUT
+
8
+
R21
475k
8
4
R27
100k
U21
LM285
VP
5
C25
100nF
R22
365k
VDD
Example: byte value = 1000 1010
C23
100nF
Transmission including the start bit: 1 1000 1010
In Manchester code: LZ LZZL ZLZL LZZL LZZL
dra_mq1d_error_schem
Figure 1: Example circuit for the decoding and con-
version of the current-modulated signals
to logic levels.
Decoding of the data stream:
ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ
Pause 1 1 0 0 0 1 0 1 0 Pause
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 18/29
INPUT CONFIGURATIONS
RIN12
RIN0
Code
–000
–010
–100
–110
1—1
0—1
Adr 0x0E, bit 3:0
Input Configurations
Adr 0x13, bit 3:0
All input stages are configured as instrumentation am-
plifiers and thus directly suitable for differential input
signals. Referenced input signals can be processed as
an option; in this mode input X2 acts as a reference.
Nominal Rin() Intern Rui()
I/V Mode
1.7 kΩ
2.5 kΩ
3.5 kΩ
4.9 kΩ
20 kΩ
1.6 kΩ
2.3 kΩ
3.2 kΩ
4.6 kΩ
5 kΩ
current input
current input
current input
current input
voltage input
voltage input
INMODE
Adr 0x03, bit 2
Code
0
Function
high
impedance
1 MΩ
Differential input signals
Single-ended input signals *
* Input X2 is reference for all inputs.
1
Note
Table 18: I/V Mode and Input Resistance
Table 17: Input Signal Mode
BIAS12
BIAS0
Code
0
Adr 0x0E, bit 6
Adr 0x13, bit 6
VREFin()
2.5 V)
Both current and voltage signals can be processed as
input signals, selected using RIN12(0) and RIN0(0).
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a volt-
age signal. Input resistance Rin() consists of a pad
wiring resistor and resistor Rui() which is linked to the
adjustable bias voltage source VREFin(). The follow-
ing table shows the possible selections, with Rin() giv-
ing the typical resulting input resistance (see Electri-
cal Characteristics for tolerances). The input resistor
should be set in such a way that intermediate poten-
tials VDC1 and VDC2 lie between 125 mV and 250 mV
(verifiable in Calibration Mode 2).
Type of sensor
Lowside sink current (I Mode)
Highside current source (I Mode)
1
1.5 V)
Table 19: Reference Voltage
BIASEX
Code
0-
Adr 0x0D, bit 7:6
VREFin()
internal
Signal at X2
Neg. Zero Signal (Index -), input
Ref. Voltage VREFin12, output
Ref. Voltage VREFin, input
10
internal *
external *
11
Note
*) The voltage at X2 is reference for all inputs.
In V Mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
ca. 25%. The circuitry is equivalent to the resistor
chain in I Mode; the pad wiring resistor is considerably
larger here, however.
Table 20: Input Reference Selection
Figure 2: Input instrumentation amplifier and signal conditioning
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 19/29
SIGNAL PATH MULTIPLEXING: iC-MSBSAFETY
Figure 3: Multiplexer Schematics
The signals for index channel CH0 are connected up to EAZ permits the activation of an analog comparator for
pins X1 and X2. Pins X3 to X6 are allocated to internal index channel CH0.
channels CH1 and CH2 via MUXIN. INMODE can be
INVZ
Code
0
Adr 0x03, bit 3
activated for referenced input signals; this then selects
X2 as the reference input. For output purposes INVZ
allows the index signal phase to be inverted.
PZ_out
NZ_out
NCH0o
PCH0o
PCH0o
1
NCH0o
MUXIN
Code
00
0x03, bit 1:0
Table 24: Index Signal Inversion
PCH1i
X4
NCH1i
X6
PCH2i
X3
NCH2i
X5
01
X4
X6
X5
X5
10
X4
X5
X3
X6
11
X4
X3
X5
X6
Table 21: Input Multiplexer for INMODE = 0
MUXIN
0x03, bit 1:0
PCH1i
X4
Code
-0
NCH1i
X2
PCH2i
X3
NCH2i
X2
-1
X4
X2
X5
X2
Table 22: Input Multiplexer for INMODE = 1
EAZ
Code
0
Adr 0x03, bit 7
Function
Comparator bypass
Comparator active
1
Table 23: Index Output
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 20/29
( not for safety applications )
EXTENDED SIGNAL PATH MULTIPLEXING: iC-MSB2
Figure 4: Multiplexer Schematics
The signals for index channel CH0 are connected up to EAZ permits the activation of an analog comparator for
pins X1 and X2. Pins X3 to X6 are allocated to internal index channel CH0.
channels CH1 and CH2 via MUXIN. INMODE can be
EAZ
Code
0
Adr 0x03, bit 7
activated for referenced input signals; this then selects
X2 as the reference input. For output purposes INVZ
allows the index signal phase to be inverted.
Function
Comparator bypass
Comparator active
1
MUXIN
Code
00
0x03, bit 1:0
Table 28: Index Output
PCH1i
X4
NCH1i
X6
PCH2i
X3
NCH2i
X5
MUXOUT
Code
000
Adr 0x03, bit 6:4
01
X4
X6
X5
X5
PS_Out
NS_Out
PC_Out
NC_Out
10
X4
X5
X3
X6
Channel 1
Channel 2
11
X4
X3
X5
X6
010
Channel 1
Channel 1 inverted
Channel 1 inverted
Channel 2
Channel 2 inverted
Channel 2
Table 25: Input Multiplexer for INMODE = 0
100
110
Channel 2 inverted
Channel 1
001
MUXIN
0x03, bit 1:0
PCH1i
X4
011
Channel 2
Channel 1 inverted
Channel 1
Code
-0
NCH1i
X2
PCH2i
X3
NCH2i
X2
101
Channel 2 inverted
Channel 2 inverted
111
Channel 1 inverted
-1
X4
X2
X5
X2
Table 29: Output Multiplexer
Table 26: Input Multiplexer for INMODE = 1
INVZ
Code
0
Adr 0x03, bit 3
PZ_out
PCH0o
NCH0o
NZ_out
NCH0o
PCH0o
1
Table 27: Index Signal Inversion
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 21/29
SIGNAL CONDITIONING CH1, CH2
GR12
Code
0x0
Adr 0x04, bit 2:0
The voltage signals necessary for the conditioning of
channels 1 and 2 can be measured in operation mode
Calibration 2.
Range with RIN12=0x9
Range with RIN12=0x9
0.5
1.0
1.3
1.7
2.2
2.6
3.3
4.0
2.0
0x1
4.1
0x2
5.3
Gain Settings CH1, CH2
The gain is set in four stages:
0x3
6.7
0x4
8.7
0x5
10.5
13.2
16.0
1. The sensor supply tracking is shut down and the
constant current source for the ACO output set to a
suitable output current (register ADJ; current value
close to the later operating point).
0x6
0x7
Table 30: Gain Range CH1, CH2
2. The coarse gain is selected so that the differential
signal amplitudes of ca. 1 Vpp are produced (signal Px
vs. Nx, see Figure below).
GF2
Code
0x00
0x01
...
Adr 0x04, bit 7:3
Factor
1.00
3. Using fine gain factor GF2 the CH2 signal amplitude
is then adjusted to 1 Vpp.
1.06
6.25GF2
31
0x1F
6.25
4. The CH1 signal amplitude can then be adjusted to
the CH2 signal amplitude via fine gain factor GF1.
Table 31: Fine Gain Factor CH2
GF1
Adr 0x06, bit 2:0, Adr 0x05, bit 7:0
Code
0x000
0x001
...
Factor
1.0
0.25 Vp
0.25 Vp
1 Vpp
1.0009
GF1
1984
6.25
0x7FF
6.6245
iC-MSB
Px
Table 32: Fine Gain Factor CH1
Vpeak-to-peak
R0
Vpk(Px)
Nx
Vpk(Nx)
GND
Figure 5: Definition of 1 Vpp signal. Termination R0
must be high-ohmic during all Test and
Calibration modes.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 22/29
The calibration range for the CH1/CH2 offset is depen-
Offset Calibration CH1, CH2
In order to calibrate the offset the reference source dent on the selected VOS12 source and is set using
must first be selected using VOS12. Two fixed voltages OR1 and OR2. Both sine and cosine signals are then
and two dependent sources are available for this pur- calibrated using factors OF1 and OF2. The calibration
pose. The fixed voltage sources should be selected for target is reached when the DC fraction of the differen-
external sensors which provide stable, self-regulating tial signals PCHx versus NCHx is zero.
signals.
OR1
OR2
Code
0x0
Adr 0x09, bit 0; Adr 0x08, bit 7
So that photosensors can be operated in optical en-
coders iC-MSB tracks changes in offset voltages via
the signal-dependent source VDC when used in con-
junction with the controlled sensor current source for
LED supply (pin ACO). The VDC potential automati-
cally tracks higher DC photocurrents. To this end inter-
mediate potentials VDC1 and VDC2 must be adjusted
to a minimal AC ripple using the selectable k factor (this
calibration must be repeated when the gain setting is
altered).
Adr 0x0A, bit 5:4
Range
x1
0x1
x2
0x2
x6
0x3
x12
Table 35: Offset Range CH1, CH2
OF1
Adr 0xA, bit 3:0; Adr 0x9, bit 7:1
OF2
Adr 0xC, bit 0; Adr 0xB, bit 7:0; Adr 0xA, bit 7:6
The feedback of pin voltage V(ACO) fulfills the same
task as source VDC when MR bridge sensors are sup-
plied by the controlled power supply output. In this
instance the VDC intermediate voltages do not need
adjusting.
Code
0x000
0x001
...
Factor
Code
0x400
0x401
...
Factor
0
0
0.00098
−0.00098
−0.00098 · OFx
−1
0.00098 · OFx
0x3FF
1
0x7FF
VOS12
Code
0x0
Adr 0x0E, bit 5:4
Type of source
0.05 · V(ACO)
0.5 V
Table 36: Offset Factors CH1, CH2
0x1
Phase Correction CH1 vs. CH2
0x2
0.25 V
The phase shift between CH1 and CH2 can be ad-
justed using parameter PH12. Following phase cal-
ibration other calibration parameters may have to be
adjusted again (those as amplitude compensation, in-
termediate potentials and offset voltages).
0x3
VDC (ie. VDC1, VDC2)
Table 33: Offset Reference Source CH1, CH2
VDC1
Adr 0x07, bit 4:0; Adr 0x06, bit 7:3
Adr 0x08, bit 6:0; Adr 0x07, bit 7:5
VDC = k · VPi + (1 − k) · VNi
k = 0.33
VDC2
Code
0x000
0x001
...
PH12
Code
0x000
0x001
...
Adr 0xD, bit 2:0; Adr 0xC, bit 7:1
Correction angle
+0
Code
0x200
0x201
Correction angle
−0
k = 0.33032
+0.0204
−0.0204
k = 0.33 + MP2 · 0.00032
k = 0.66
+0.0204 · PH12 ...
+10.42 0x3FF
−0.0204 · PH12
−10.42
0x3FF
0x1FF
Table 34: Intermediate Voltages CH1, CH2
Table 37: Phase Correction CH1 vs. CH2
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 23/29
SIGNAL CONDITIONING CH0
The voltage signals needed to calibrate channel 0 are Offset Calibration CH0
available in Calibration Mode 1.
To calibrate the offset the source of supply must first
be selected using VOS0 (see Offset Calibration CH1
and CH2 for further information). For the CH0 path the
Gain Settings CH0
Parallel to the conditioning process for the CH1 and dependent source VDC is identical to source VDC1.
CH2 signals the CH0 gain is set in the following stages:
VOSZ
Code
0x0
Adr 0x13, bit 5:4
1. The sensor supply tracking unit is shut down and the
constant current source for the ACO output set to the
same output current as in the compensation of CH1
and CH2 (register ADJ; current value close to the later
operating point).
Source
0.05 · V(ACO)
0.5 V
0x1
0x2
0.25 V
0x3
VDC (ie. VDC1)
Table 40: Offset Reference Source CH0
2. The coarse gain is selected so that a differential sig-
nal amplitude of ca. 1 Vpp is produced internally (sig-
nal PCHx versus NCHx).
OR0
Code
0x0
Adr 0x12, bit 1:0
Range
x1
3. GF0 then permits fine gain adjustment to 1 Vpp.
0x1
x2
GR0
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Adr 0x11, bit 2:0
0x2
x6
Range with RIN0=0x9
Range with RIN0=0x9
0x3
x12
0.5
1.0
1.3
1.7
2.2
2.6
3.3
4.0
2.0
4.1
Table 41: Offser Range CH0
5.3
6.7
OF0
Code
0x00
0x01
...
Adr 0x12, bit 7:2
8.7
Factor
Code
0x20
0x21
...
Factor
10.5
13.2
16.0
0
0
0.0322
-0.0322
-0.0322 · OFZ
-1
0.0322 · OFZ
1
0x1F
0x3F
Table 38: Gain Range CH0
Table 42: Offset Factor CH0
GF0
Code
0x00
0x01
...
Adr 0x11, bit 7:3
Factor
1.00
1.06
6.25GFZ
31
0x1F
6.25
Table 39: Fine Gain Factor CH0
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 24/29
SIGNAL LEVEL CONTROL and SIGNAL MONITORING
ADJ (6:5)
Code
00
Adr 0x10, bit 5:4
Function
Via the controlled sensor current source (pin ACO)
iC-MSB can keep the output signals for the ensuing
sine/digital converter constant regardless of tempera-
ture and aging effects by tracking the sensor supply.
5 mA - Range
10 mA - Range
25 mA - Range
50 mA - Range
01
10
11
Table 44: ACO Output Current Range (applies for con-
trol modes and constant current source)
Both the controller operating range and input signal
amplitude for the controller are monitored and can
be enabled for error messaging. A constant current
source can be selected for the ACO output when set-
ting the signal conditioning; the current range for the
highside current source is adjusted using ADJ(6:5).
ADJ (4:0)
Code
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Square control ADJ(8:7) = 00
Vpp() ca. 300 mV (60 %)
0x00
0x01
Vpp() ca. 305 mV (61 %)
77
...
Vpp() ≈ 300 mV 77−(1.25∗Code)
0x19
...
Vpp() ca. 500 mV (98 %)
...
0x1F
Vpp() ca. 600 mV (120 %)
Table 45: Vpp Setpoint For Square Control
ADJ (4:0)
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Sum control ADJ(8:7) = 01
VDC1 + VDC2 ca. 245 mV
VDC1 + VDC2 ca. 249 mV
Code
0x00
0x01
77
...
VDC1 + VDC2 ≈ 245mV 77−(1.25∗Code)
Figure 6: Signal level monitoring with square control
(example for ADJ(8:0) = 0x19; see Elec.
Char. Nos.607 and 608 regarding Vt()min
resp. Vt()max)
0x1F
VDC1 + VDC2 ca. 490 mV
Table 46: DC Setpoint For Sum Control
ADJ (4:0)
Code
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Constant current source ADJ(8:7) = 10
I(ACO) ca. 3.125% Isc(ACO)
0x00
ADJ (8:7)
Code
00
Adr 0x10, bit 7:6
0x01
I(ACO) ca. 6.25% Isc(ACO)
Function
...
I(ACO) ≈ 3.125% ∗ (Code + 1) ∗ Isc(ACO)
Sine/cosine square control
Sum control
01
0x1F
I(ACO) ca. 100% Isc(ACO)
10
Constant current source
Not permitted (device test only)
11
Notes
See Elec. Char. No. 602 for Isc(ACO)
Table 43: Controller Operating Modes
Table 47: I(ACO) With Constant Current Source
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 25/29
ERROR MONITORING AND ALARM OUTPUT
The following table gives the errors which can both I/O pin ERR
be recognized by iC-MSB and enabled either for mes- Pin ERR is operated by a current-limited open drain
saging, output shutdown or protocol in the EEPROM. output driver and has an internal pull-up which can be
Mask EMASKA stipulates that errors should be sig- shutdown. The ERR pin also acts as an input for ex-
naled at pin ERR, mask EMASKO determines whether ternal system error messaging and for switching iC-
the line driver outputs are to be shutdown or not MSB to test mode for which a voltage of greater than
(with PDMODE setting a renewed power-on) and mask VTMon must be applied. Interpretation of external
EMASKE governs the storage of error events in the system error messaging and the phase length of the
EEPROM.
message output can be set using EPH; the minimum
signaling duration for internal errors is adjusted using
EMTD(2:0).
EMASKA
EMASKO
EMASKE
Bit
Adr 0x14, bit 6:0
Adr 0x16, bit 6:0
Adr 0x18, bit 2:0; Adr 0x17, bit 7:4
Error Event
EPU
Code
0
Adr 0x17, bit 2
Function
6
Configuration error*: SDA or SCL pin error, no Ack
signal from EEPROM or invalid check sum
without internal pull-up at ERR
internal pull-up at ERR active
1
5
4
3
2
1
0
Excessive temperature warning
External system error
Table 50: Alarm Output Pull-up Enable
Level controller out of range (max. limit)
Level controller out of range (min. limit)
Signal clipping (excessive input level)
PDMODE
Adr 0x18, bit 6
Code
Function
Loss of signal (poor input level or CH1/CH2 phase
out of range)
0
1
Line driver active when no error persists
Line driver active after power-on
Note
*) The line drivers remain high impedance (tristate)
when cycling power.
Table 51: Driver Activation
Table 48: Error Event Masks
EPH
Code
0
Adr 0x15, bit 2
ERR pin function
Ext. error message
Error Protocol
with error low,
otherwise Z
with error low,
otherwise pull-up active
Out of the errors pinpointed by EMASKE both the first
(ERR1) and last error (ERR2) which occur after the
iC-MSB is turned on are stored in the EEPROM. The
EEPROM also has a memory area in which all occur-
ring errors can be stored (ERR3). Only the fact that an
error has occurred can be recorded, with no informa-
tion as to the time and frequency of that error given.
The EEPROM memory can be used to statistically
evaluate the causes of system failure, for example.
1
with error Z,
otherwise low
with error pull-up active,
otherwise low
Table 52: Alarm Input/Output Logic
EMTD
Code
0x0
Adr 0x15, bit 5:3
Indication Time
0 ms
Code
0x4
0x5
0x6
0x7
Indication Time
50 ms
0x1
12.5 ms
25 ms
62.5 ms
75 ms
0x2
ERR1
ERR2
ERR3
Bit
Adr 0x20, bit 6:0
0x3
37.5 ms
87.5 ms
Adr 0x22, bit 0; Adr 0x21, bit 7:2
Adr 0x23, bit 2:0; Adr 0x22, bit 7:4
Error Event
Table 53: Minimum Alarm Indication Time
9:0
Assignation according to EMASKE
Code
Function
0
1
No event
Registered error event
Table 49: Error Protocol
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 26/29
TEMPERATURE MONITORING
iC-MSB has an integrated temperature monitor. If the can be signaled at pin ERR or used to shut down the
temperature threshold is exceeded an excessive tem- line drivers. If temperature Toff = Twarn + ∆T is ex-
perature message is generated which is processed in ceeded the line drivers are shut down independent of
the temperature monitor block. The warning threshold EMASKO(6:0).
REVERSE POLARITY PROTECTION
The line drivers in iC-MSB are protected against re- are also reverse polarity protected: PC, NC, PS, NS,
verse polarity and short-circuiting. A defective device PZ, NZ, ERR, VDD, GND and ACO (as long as GNDS
cable or one wrongly connected cause damage neither is only loaded versus VDDS). The maximum voltage
to iC-MSB nor to the components protected against re- difference between the pins should not be greater than
verse polarity by VDDS and GNDS. The following pins 6 V, the exception here being pin ERR.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 27/29
APPLICATION HINTS
Connecting MR sensor bridges for safety-related applications
For safety-related applications iC-MSBSAFETY requires an external overvoltage protection of supply VDD (Zener
diode with fuse, for instance) and external pull-down resistors at the inputs X3 to X6 towards GNDS (of up to
100 kΩ).
F1
+5V
C1
100nF
C2
100nF
R6
R5
2.2kS 2.2kS
D1
5.6V
VP
SCL
VDDS
VDD
SCL
I2C
ERR
24xx
ERR
SDA
ACO
SDA
VN
iC-MSB
SIGNAL
LEVEL
PZ
NZ
PC
NC
PS
NS
CONTROL
RL
MR0
100S
X1
X2
+
-
INPUT ZERO
MR1
RL
100S
X3
X5
+
-
R1
R2
100kS
INPUT COS
100kS
MR2
X4
X6
+
RL
100S
-
R3
R4
INPUT SIN
100kS 100kS
GNDS
GND
0V
TVS diode array
Figure 7: Example circuit for safety-related applications with iC-MSBSAFETY
.
PLC Operation
ther the supply VDD nor the output pins, which are
There are PLCs with a remote sense supply which re- also monitored, must fall to below ground potential (pin
quire longer for the voltage regulation to settle. At the GND); otherwise the device is not configured and the
same time the PLC inputs can have high-impedance outputs remain permanently set to tristate.
resistances versus an internal, negative supply voltage
which define the input potential for open inputs.
In order to ensure that iC-MSB starts with the PLCs
In this instance iC-MSB’s reverse polarity protection mentioned above pull-up resistors can be used in the
feature can be activated as the outputs are tristate dur- encoder. Values of 100 kΩ are usually sufficient; it
ing the start phase and the resistances in the PLC de- is, however, recommended that PLC specifications be
termine the pin potential. During the start phase nei- specifically referred to here.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 28/29
iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions
in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of
merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
Rev D2, Page 29/29
ORDERING INFORMATION
Type
Package
Order Designation
iC-MSBSAFETY
TSSOP20
iC-MSB TSSOP20
TSSOP20 with thermal pad
iC-MSB TSSOP20-TP
iC-MSB EVAL MSB1D
Evaluation Board iC-MSBSAFETY
iC-MSB2
TSSOP20
iC-MSB2 TSSOP20
Evaluation Board iC-MSB2
iC-MSB2 EVAL MSB1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Tel.: +49 (61 35) 92 92-0
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明