IC41C16105S-50K [ICSI]
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE; 1M ×16 （ 16兆位）动态RAM具有快速页面模式
| 型号： | IC41C16105S-50K |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| 文件： | 总18页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC41C16105S
IC41LV16105S
1M x 16 (16-MBIT) DYNAMIC RAM
WITH ꢀAST PAGE MODE
DESCRIPTION
ꢀEATURES
The ICSI IC41C16105S and IC41LV16105S are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. <ast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IC41C16105S ideal for use in 16-, 32-bit wide data
bus systems.
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1,024 cycles/16 ms,
1,024 cycles / 128ms Self Refresh
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden, and Self Refresh
JEDEC standard pinout
Single power supply:
5V ± 10% (IC41C16105S)
3.3V ± 10% (IC41LV16105S)
These features make the IC41C16105S and IC41LV16105S
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
Byte Write and Byte Read operation via two CAS
Industrail temperature range -40oC to 85oC
The IC41C16105S and IC41LV16105S are packaged in a
42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
-50
50
13
25
20
84
-60
60
15
30
25
Unit
ns
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. ꢀast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
ns
ns
ns
104
ns
PIN CONꢀIGURATIONS
44(50)-Pin TSOP-2
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
50
49
48
47
46
45
44
43
42
41
40
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
2
2
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
3
3
4
4
5
5
6
6
PIN DESCRIPTIONS
7
7
8
A0-A9
Address Inputs
8
9
9
10
11
I/O8
I/O0-15 Data Inputs/Outputs
10
11
12
13
14
15
16
17
18
19
20
21
NC
WE
Write Enable
NC
NC
WE
RAS
NC
NC
A0
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
NC
LCAS
UCAS
OE
OE
Output Enable
LCAS
UCAS
OE
WE
RAS
NC
RAS
UCAS
LCAS
Vcc
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
A9
A9
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
GND
NC
Ground
A3
A4
VCC
GND
VCC
GND
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
1
IC41C16105S
IC41LV16105S
ꢀUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
2
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
TRUTH TABLE
ꢀunction
RAS
LCAS UCAS
WE
X
OE
X
Address tR/tC I/O
Standby
H
L
L
H
L
L
H
L
X
High-Z
Read: Word
Read: Lower Byte
H
L
ROW/COL
ROW/COL
DOUT
H
H
L
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
DIN
Write: Lower Byte (Early Write)
H
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H
®
L
L
®
H
DOUT, DIN
Hidden Refresh
Read(2)
Write(1,3)
L
®H®
L
L
L
L
L
L
H
L
L
ROW/COL
ROW/COL
DOUT
DOUT
L®H®
X
RAS-Only Refresh
CBR Refresh(4)
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H
®
L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
3
IC41C16105S
IC41LV16105S
ꢀunctional Description
Write Cycle
The IC41C16105S and IC41LV16105S is a CMOS DRAM
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 10 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter ten bits.
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
The ICS41C16105S and IC41LV16105S has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ignored.
The IC41C16105S and IC41LV16105S CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16105L and IS41LV16105L both
BYTE READ and BYTE WRITE cycle capabilities.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
4
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
1.0 to +7.0
0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
1.0 to +7.0
0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
Industrail Operation Temperature
0 to +70
40 to +85
°C
°C
TSTG
Storage Temperature
55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
2.4
2.0
VCC + 1.0
VCC + 0.3
V
V
5V
3.3V
1.0
0.3
0.8
0.8
Commercial Ambient Temperature
Industrail Ambient Temperature
0
40
70
85
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A9
Max.
Unit
CIN1
CIN2
CIO
5
7
7
p<
p<
p<
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz,
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
5
IC41C16105S
IC41LV16105S
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ꢀ VIN ꢀ Vcc
Other inputs not under test = 0V
5
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ꢀ VOUT ꢀ Vcc
5
2.4
5
µA
V
VOH
VOL
ICC1
IOH = 5.0 mA (5V)
IOH = 2.0 mA (3.3V)
0.4
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
V
RAS, LCAS, UCAS > VIH
Commerical
5V
2mA
3.3V
Extended & Idustrial 5V
3.3V
1
3
2
mA
ICC2
ICC3
Standby Current: CMOS
RAS, LCAS, UCAS > VCC 0.2V
5V
3.3V
1
0.5
mA
mA
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
160
145
ICC4
ICC5
ICC6
Operating Current:
<ast Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
90
80
mA
mA
mA
µA
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, LCAS, UCAS > VIH
tRC = tRC (min.)
-50
-60
160
145
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
160
145
ICCS
Self Refresh Current
Self Refresh mode
5V
3.3V
650
300
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each ꢀast page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Min. Max.
-60
Min. Max.
Symbol
Parameter
Units
tRC
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
84
50
30
8
50
13
2
104
60
15
ns
ns
ns
tRAC
tCAC
tAA
5
30
ns
tRAS
tRP
10K
60
40
10
9
10K
ns
ns
ns
ns
ns
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
tCAS
tCP
10K
10K
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
38
1237
0
40
14
45
ns
0
ns
ns
ns
ns
ns
8
10
0
0
8
10
40
Column-Address Hold Time
(referenced to RAS)
30
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
10
25
5
25
15
13
12
30
5
30
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
37
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
37
0
5
5
3
3
tOE
Output Enable Time(15, 16)
20
5
20
5
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
Read Command Hold Time
(referenced to RAS)(12)
0
0
tRCH
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
0
0
ns
tWCH
tWCR
Write Command Hold Time(17, 27)
8
10
50
ns
ns
Write Command Hold Time
(referenced to RAS)(17)
40
tWP
Write Command Pulse Width(17)
8
10
13
8
10
10
15
10
0
ns
ns
ns
ns
ns
ns
tWPZ
tRWL
tCWL
tWCS
tDHR
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
0
39
39
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
7
IC41C16105S
IC41LV16105S
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Min. Max.
-60
Min. Max.
Symbol
Parameter
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
15
ns
tOEH
OE Hold Time from WE during
READ-MODI<Y-WRITE cycle(18)
8
10
ns
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
0
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODI<Y-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODI<Y-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
32
47
25
ns
ns
ns
<ast Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width
50
56
5
100K
30
60
68
5
100K
35
ns
ns
ns
ns
Access Time from CAS Precharge(15)
READ-WRITE Cycle Time(24)
Data Output Hold after CAS LOW
tPRWC
tCOH
tOꢀꢀ
Output
CAS or RAS(13,15,19, 29)
Buffer
Turn-Off
Delay
from
1.6
121
tWHZ
Output Disable Delay from WE
3
10
3
10
ns
ns
tCLCH
Last CAS going LOW to <irst CAS
returning HIGH(23)
10
10
tCSR
tCHR
tORD
CAS Setup Time (CBR RE<RESH)(30, 20)
CAS Hold Time (CBR RE<RESH)(30, 21)
5
8
0
5
10
0
ns
ns
ns
OE Setup Time prior to RAS during
HIDDEN RE<RESH Cycle
tREꢀ
tT
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or <all)(2, 3)
1
16
50
1
16
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p< (Vcc = 5.0V ±10%)
One TTL Load and 50 p< (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
8
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pꢀ.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOꢀꢀ (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIꢀY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIꢀY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIꢀY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOꢀꢀ occur.
20. The first cCAS edge to transition LOW.
21. The last cCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIꢀY-WRITE cycles.
23. Last falling cCAS edge to first rising cCAS edge.
24. Last rising cCAS edge to next cycles last rising cCAS edge.
25. Last rising cCAS edge to first falling cCAS edge.
26. Each cCAS must meet minimum pulse width.
27. Last cCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
9
IC41C16105S
IC41LV16105S
READ CYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLC
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Don’t Care
Note:
1. tOꢀꢀ is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
READ WRITE CYCLE (LATE WRITE and READ-MODI<Y-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Don’t Care
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
11
IC41C16105S
IC41LV16105S
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
ADDRESS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DHR
t
DH
t
DS
Valid Data
Don’t Care
12
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
ꢀAST PAGE MODE READ CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PRWC
t
t
RSH
CAS
t
CAS
t
CAS
t
CRP
t
RCD
t
CRP
t
CP
tCP
UCAS/LCAS
ADDRESS
t
CPWD
RAL
t
AR
t
CPWD
t
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
tASC
t
ASC
t
ASR
Row
Column
Column
Column
t
RCS
WE
t
AA
t
AA
tAA
t
CAC
t
CAC
tCAC
t
OE
t
OE
tOE
OE
I/O
t
RAC
t
OED
t
OED
tOED
t
CLZ
t
CLZ
t
CLZ
OUT
OUT
OUT
Don’t Care
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
13
IC41C16105S
IC41LV16105S
ꢀAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODI<Y-WRITE Cycles)
tRASP
tRP
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tCAS
tCAH
tCRP
tRCD
tAR
tCRP
tCP
tCP
UCAS/LCAS
ADDRESS
tCPWD
tRAL
tCPWD
tRAD
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
Row
Column
Column
Column
tCWL
tRWD
tCWL
tRWL
tCWL
tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tRCS
tWP
tWP
tWP
WE
tAA
tAA
tAA
tCAC
tCAC
tCAC
tOE
tOE
tOE
OE
tOEZ
tOEZ
tOED
tOEZ
tOED
tRAC
tCLZ
tOED
tDH
tDH
tDH
tDS tCLZ
tDS
tCLZ
OUT
tDS
I/O0-I/O15
OUT
IN
IN
IN
OUT
Don’t Care
14
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
ꢀAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP
RAS
tRHCP
tRSH
tCAS
tCSH
tCAS
tPC
tCAS
tCRP
tRCD
tAR
tCRP
tCP
tCP
UCAS/LCAS
ADDRESS
tRAL
tRAD
tCAH
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
Row
Column
Column
Column
tCWL
tWCH
tCWL
tWCH
tCWL
tWCH
tWCS
tWCS
tWCS
tWP
tWP
tWP
WE
OE
tWCR
tDHR
tDS
tDS
tDS
tDH
tDH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O0-I/O15
Don’t Care
AC WAVEꢀORMS
RAS-ONLY REꢀRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
t
RP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
15
IC41C16105S
IC41LV16105S
CBR REꢀRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REꢀRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOꢀꢀ is referenced from rising edge of RAS or CAS, whichever occurs last.
16
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
IC41C16105S
IC41LV16105S
SELꢀ REꢀRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
RP
t
RASS
tRPS
V
IH
IL
RAS
V
t
CHD
t
RPC
CP
t
RPC
t
t
CSR
t
CP
V
IH
IL
UCAS/LCAS
DQ
V
VOH
OL
Open
V
Don’t Care
TIMING PARAMETERS
-50
Min. Max.
-60
Min. Max.
Symbol
Units
tCHD
tCP
8
9
10
9
ns
ns
ns
µs
ns
ns
ns
tCSR
tRASS
tRP
5
5
100
30
84
5
100
40
104
5
tRPS
tRPC
ORDERING INꢀORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No.
Package
50
IC41C16105S-50K
IC41C16105S-50T
400mil SOJ
400mil TSOP-2
60
IC41C16105S-60K
IC41C16105S-60T
400mil SOJ
400mil TSOP-2
ORDERING INꢀORMATION: 5V
Industrial Temperature Range: 40°C to 85°C
Speed (ns) Order Part No.
Package
50
IC41C16105S-50KI
IC41C16105S-50TI
400mil SOJ
400mil TSOP-2
60
IC41C16105S-60KI
IC41C16105S-60TI
400mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
17
IC41C16105S
IC41LV16105S
ORDERING INꢀORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No.
Package
50
IC41LV16105S-50K
IC41LV16105S-50T
400mil SOJ
400mil TSOP-2
60
IC41LV16105S-60K
IC41LV16105S-60T
400mil SOJ
400mil TSOP-2
ORDERING INꢀORMATION: 3.3V
Industrial Temperature Range: 40°C to 85°C
Speed (ns) Order Part No.
Package
50
IC41LV16105S-50KI
IC41LV16105S-50TI
400mil SOJ
400mil TSOP-2
60
IC41LV16105S-60KI
IC41LV16105S-60TI
400mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
ꢀax: 886-3-5783000
BRANCH OꢀꢀICE:
7ꢀ, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
ꢀAX: 886-2-26962252
http://www.icsi.com.tw
18
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
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