IC61S25632T-250TQI [ICSI]
8Mb SyncBurst Pipelined SRAM; 8MB SyncBurst流水线SRAM
| 型号： | IC61S25632T-250TQI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 8Mb SyncBurst Pipelined SRAM |
| 文件： | 总22页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Document Title
8Mb SyncBurst Pipelined SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
0B
Initial Draft
September 24,2001
August 13,2002
1.Move the FT pin for user-configurable Flow
throught or pipelineed operation, That pin can be
NC or connected to VCC for pipelined operation.
Refer to Pin configuration.
2.Revise the power supply charaetoristics at page 12
3.Resive the tKQ of 250 MHZ from 2.5ns to 3ns.
4.Move the 100 MHZ speed grade.
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
1
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb S/DCD SYNCBURST Pipelined SRAMs
FEATURES
Controls
All synchronous inputs pass through registers controlled by a
• Pipeline Mode operation
positive-edge-triggered single clock input.Bursts can be initiated
with either ADSP (Address Status Processor) or ADSC (Address
Status Cache Controller) input pins. Subsequent burst ad-
dresses can be generated internally and controlled by the ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
• Single/Dual Cycl Deselect
• User-selectable Output Drive Strength with XQ Mode
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using
MODE input
SCD and DCD Pipelined Reads
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +3.3V, +10%, –5% core power supply
• Power-down snooze mode
• 2.5V or 3.3V I/O Supply
• Snooze MODE for reduced-power standby
• T version (three chip selects)
The device is a SCD (Single Cycle Deselect) and DCD(Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input on Bump 4L.
• D version (two chip selects)
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
DESCRIPTION
ICSI's 8Mb SyncBurst Pipelined SRAMs integrate a 512k
x 18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Pipelined SRAM family employs
high-speed ,low-power CMOS designs that are fabricated
using an advanced CMOS process to provide Level 2
Cache applications supporting Pentium and PowerPC
microprocessors originally, the device now finds applica-
tion ranging from DSP main store to networking chip set
support.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
FAST ACCESS TIME
Symbol
-250
3
-200 -166 -133 Units
Pipeline tKQ
3.1
3.5
4
ns
3-1-1-1
tKC
4
5
6
7.5
300
ns
ICC1
390
360
330
mA
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
BLOCK DIAGRAM
MODE
A0
A0'
A1'
Q0
CLK
CLK
BINARY
COUNTER
Q1
ADV
A1
256Kx32; 256Kx36;
512Kx18
ADSC
ADSP
MEMORY ARRAY
18/19
16/17
18/19
D
Q
An-A0
ADDRESS
REGISTER
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQd
BYTE WRITE
REGISTERS
BWd
(x32/x36)
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BWb
(x32/x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
(T, D)CE
(T, D) CE2
4
32, 36,
or 18
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa - DQd
(T) CE
2
ENABLE
OE
REGISTER
CLK
CLK
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
Integrated Circuit Solution Inc.
3
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
119-pin PBGA (Top View)
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
A
B
C
D
E
F
VCCQ
NC
SA
CE2
SA
SA
SA
ADSP
SA
SA
SA
SA
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
ADSC
VCC
XQ
NC
SA
SA
SA
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
GND
GND
GND
GND
GND
GND
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
CE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
BWb
GND
NC
ADV
BWc
GND
GW
VCC
ZZ
GND
NC
VCC
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
K
L
GND
CLK
SCD
GND
BWd
GND
GND
GND
MODE
SA
BWa
M
N
P
R
T
GND
BWE
A1
GND
GND
A0
VCC
SA
SA
SA
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
SA
NC
ZZ
U
VCCQ
NC
NC
NC
NC
NC
VCCQ
256K x 32
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
MODE
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
SCD
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
ADSP
Synchronous Processor Address
Status
VCC
+3.3V Power Supply
GND
VCCQ
Ground
ADSC
Synchronous Controller Address
Status
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADV
BWa -BWd
BWE
GW
CE , CE2
OE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
ZZ
Snooze Enable
4
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
GND
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 32
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
DQa-DQd
MODE
SCD
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
VCC
+3.3V Power Supply
ADSP
Synchronous Processor Address
Status
GND
VCCQ
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADSC
Synchronous Controller Address
Status
ADV
BWa -BWd
BWE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
ZZ
Snooze Enable
GW
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
Integrated Circuit Solution Inc.
5
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
119-pin PBGA (Top View)
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
SA
SA
SA
ADSP
ADSC
VCC
XQ
SA
SA
SA
SA
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
CE2
NC
SA
SA
SA
SA
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
SA
GND
GND
GND
GND
GND
GND
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
SA
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
CE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
BWc
GND
ADV
BWb
GND
GW
NC
GND
BWd
GND
GND
GND
MODE
SA
VCC
NC
GND
BWa
GND
GND
GND
NC
ZZ
GND
K
L
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
CLK
SCD
BWE
A1
M
N
P
R
T
A0
VCC
SA
NC
NC
SA
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VCCQ
NC
NC
NC
NC
NC
VCCQ
256K x 36
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
MODE
SCD
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
ADSP
Synchronous Processor Address
Status
VCC
+3.3V Power Supply
GND
VCCQ
Ground
ADSC
Synchronous Controller Address
Status
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADV
BWa -BWd
BWE
GW
CE , CE2
OE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
ZZ
Snooze Enable
DQPa-DQPd Parity Data I/O
6
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
ZZ
GND
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
MODE
SCD
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
ADSP
Synchronous Processor Address
Status
VCC
+3.3V Power Supply
GND
VCCQ
Ground
ADSC
Synchronous Controller Address
Status
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADV
BWa -BWd
BWE
GW
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
ZZ
Snooze Enable
DQPa-DQPd Parity Data I/O
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
Integrated Circuit Solution Inc.
7
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
119-pin PBGA (Top View)
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
SA
CE2
SA
SA
SA
ADSP
ADSC
VCC
SA
SA
SA
SA
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA
NC
NC
VCCQ
GND
NC
NC
NC
NC
VCCQ
GND
NC
NC
SA
SA
SA
NC
DQc1
DQb2
NC
GND
GND
GND
GND
GND
GND
GND
GND
NC
DQPa
NC
XQ
CE
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
SCD
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
NC
DQb8
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCCQ
DQc4
DQc3
NC
DQb7
NC
VCCQ
DQb6
NC
OE
G
H
J
NC
DQc4
VCCQ
Nc
BWb
GND
NC
ADV
DQb5
VCC
NC
GW
VCC
XQ
VCC
DQd5
NC
VCC
VCCQ
DQa4
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
K
L
GND
GND
GND
GND
GND
MODE
SA
CLK
SCD
GND
BWa
GND
GND
GND
NC
DQd6
VCCQ
DQd8
NC
DQa3
NC
M
N
P
R
T
DQd7
NC
VCCQ
NC
BWE
A1
DQa2
NC
NC
DQPd
SA
A0
DQa1
NC
GND
VCCQ
NC
NC
NC
NC
VCC
NC
SA
NC
SA
SA
SA
ZZ
U
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCCQ
NC
NC
NC
NC
NC
VCCQ
512K x18
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
DQa-DQb
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
pins must tied to the two LSBs of the
address bus.
MODE
SCD
A2-A18
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
ADSP
Synchronous Processor Address
Status
VCC
+3.3V Power Supply
GND
VCCQ
Ground
ADSC
Synchronous Controller Address
Status
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADV
BWa -BWb
BWE
GW
CE , CE2
OE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
ZZ
Snooze Enable
DQPa-DQPb Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
8
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA
NC
NC
VCCQ
GND
NC
NC
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
SCD
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
NC
VCC
XQ
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
NC
GND
VCCQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x18
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
DQa-DQb
MODE
SCD
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18
CLK
Synchronous Address Inputs
Synchronous Clock
XQ
VCC
+3.3V Power Supply
ADSP
Synchronous Processor Address
Status
GND
VCCQ
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
ADSC
Synchronous Controller Address
Status
ZZ
Snooze Enable
ADV
BWa -BWb
BWE
GW
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
DQPa-DQPb Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
Integrated Circuit Solution Inc.
9
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Mode Pin Functions
Mode Name
Pin Name
MODE
State
Function
Linear Burst
Burst Order Control
L
H or NC
Interleaved Burst
Active
Power Down Control
Single/DualCycleDeselectControl
Output Drive Control
Note:
ZZ
SCD
XQ
L or NC
H
Standby
L
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
H or NC
L
H
There are pull-up devices on the MODE, XQ, and SCD pins and a pull down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above table.
TRUTH TABLE
Address
Used
None
Operation
CE CE2 CE2
ADSP
X
ADSC
L
ADV
X
X
X
X
X
X
X
X
L
WRITE
X
OE DQ
X High-Z
X High-Z
X High-Z
X High-Z
X High-Z
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
H
L
X
X
L
X
H
X
H
X
L
None
L
X
X
None
L
L
X
X
None
L
X
L
H
H
L
L
X
None
L
L
X
External
External
External
Next
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Q
Q
D
Q
L
L
H
H
H
H
X
L
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H High-Z
Next
L
L
Q
Next
X
L
H High-Z
Next
H
X
L
X
X
L
D
D
Q
Next
L
Current
Current
Current
Current
Current
Current
H
H
X
H
H
H
H
H
H
H High-Z
L
Q
X
H High-Z
H
X
X
X
D
D
PARTIAL TRUTH TABLE
Function
GW BWE BWa BWb BWc BWd
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
10
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
00
A1 A0
01
A1 A0
10
A1 A0
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
TBIAS
TSTG
PD
Parameter
Value
–40 to +85
–55 to +150
1.6
Unit
°C
°C
W
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
IOUT
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.5
–0.5 to VCC + 0.5
VIN
Voltage Relative to GND for
V
for Address and Control Inputs
Voltage on Vcc Supply Relatiive to GND
VCC
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
11
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
OPERATING RANGE
Range
Ambient Temperature
VCC
VCCQ
2.375–3.6V
2.375–3.6V
Commercial
Industrial
0°C to +70°C
3.3V, +10%, –5%
3.3V, +10%, –5%
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
1.7
2.4
—
Max.
—
Unit
V
VOH
VOL
VIH
VIL
Output HIGH Voltage
IOH = –2.0 mA, VCCQ = 2.5V
IOH = –4.0 mA, VCCQ = 3.3V
IOL = 2.0 mA, VCCQ = 2.5V
IOL = 8.0 mA, VCCQ = 3.3V
VCCQ = 2.5V
—
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.7
0.4
V
—
V
1.7 VCCQ+ 0.3
2.0 VCCQ + 0.3
V
VCCQ = 3.3V
V
VCCQ = 2.5V
–0.3
–0.3
–2
0.7
0.8
2
V
VCCQ = 3.3V
V
ILI
Input Leakage Current
Output Leakage Current
GND ≤ VIN ≤ VCC (1)
GND ≤ VOUT ≤ VCCQ, OE = VIH
µA
µA
ILO
–2
2
Notes:
1. The MODE, ZZ, SCD, XQ, pin has an internal pullup. and input leakage = ±10 µA .
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-250
-200
-166
-133
Parameter
Test Conditions
Device Selected,
All Inputs ≤ VIL or ≥VIH
f = 1/tKC
Symbol
ICC1
Max.
390
Max. Max. Max. Unit
AC Operating
Supply Current
Com.
Ind.
360
380
330
300 mA
410
350
320
Clock Running
COMS Standby
Device Deselected,
VCC = Max.,
Icc2
Com.
Ind.
110
130
100
120
90
85
mA
110
105 mA
All Inputs ≤ VIL or ≥VIH
f = 1/tKC
Device Deselected,
VCC = Max.,
ISB
Com.
Ind.
90
90
90
90
mA
100
100
100
100 mA
All Inputs ≤ 0.2V or ≥VCC -0.2V
f = 0
Power Dowin Mode VCC = Max
IZZ
Com.
Ind.
80
90
80
90
80
90
80
90
mA
mA
ZZ ≥VCC - 0.2V
f = 0
All input ≤ 0.2V or ≥VCC -0.2V
12
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
CAPACITANCE (1,2)
Symbol
CIN
Parameter Conditions
Input Capacitance
Max.
VIN = 0V
Unit
6
pF
pF
COUT
Input/Output Capacitance
VOUT = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
0V to 3.0V
1.5 ns
1.5V for 3.3V I/O
VCCQ/2V for 2.5V I/O
See Figures 1 and 2
AC TEST LOADS
ZO = 50Ω
317Ω /1667Ω
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Output
Buffer
50Ω
OUTPUT
351Ω /1538Ω
5 pF
1.5V for 3,3V I/O
CCQ/2V for 2.5V I/O
Including
jig and
scope
V
Figure 1
Figure 2
Integrated Circuit Solution Inc.
13
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-250
-200
-166
-133
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
4
—
3
5
—
3.1
—
—
—
—
3.1
3.1
—
3.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
3.5
—
—
—
—
3.5
3.5
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.5
—
—
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pipeline tKQ
Clock Access Time
—
—
1.0
0
—
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output High-Z
OutputEnabletoOutputValid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
1.0
0
—
—
—
—
3.1
3.1
—
3.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
0
1.5
0
—
—
—
—
4
(1,2)
tKQLZ
tKH
1.6
1.6
—
2
2.3
2.3
—
2.8
2.8
—
tKL
2
(1,2)
tKQHZ
tOEQ
—
—
0
—
—
—
4
(1,2)
tOELZ
tOEHZ
tAS
0
0
0
—
4
(1,2)
—
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
—
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
tWS
tCES
tAVS
tDS
Chip Enable Setup Time
Address Advance Setup Time
Data Setup time
tDH
Data Hold time
tAH
Address Hold Time
tSH
Address Status Hold Time
Write Hold Time
tWH
tCEH
tAVH
tZZS
Chip Enable Hold Time
Address Advance Hold Time
ZZ Setup Time
— cyc
— cyc
tZZREC
ZZ Recovery Time
2
2
2
2
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIPELINED SCD READ
CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
BW4-BW1
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Burst Read
Single Read
Unselected
Integrated Circuit Solution Inc.
15
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIPELINED DCD READ CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
BW4-BW1
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
3b
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Burst Read
Single Read
Unselected
16
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BW4-BW1
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Circuit Solution Inc.
17
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE TIMING: PIPELINED
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
t
SS
tSH
t
SS
tSH
ADV
t
AS
tAH
Addresses
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
t
WS
tWH
WR1
BW4-BW1
t
CES
tCEH
CE1 Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE3
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQX
KQHZ
t
KQ
t
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Unselected
18
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
t
SS
tSH
ADV
t
AS
tAH
Address
RD1
RD2
GW
BWE
BW4-BW1
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
t
t
OEHZ
t
OEQ
OE
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
1a
t
KQLZ
t
KQX
KQHZ
t
KQ
t
DATAIN
ZZ
t
ZZS
tZZREC
Snooze with Data Retention
Single Read
Read
Integrated Circuit Solution Inc.
19
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
IC61S25632T-250TQ
IC61S25632D-250TQ
IC61S25632D-250B
IC61S25632T-200TQ
IC61S25632D-200TQ
IC61S25632D-200B
IC61S25632T-166TQ
IC61S25632D-166TQ
IC61S25632D-166B
IC61S25632T-133TQ
IC61S25632D-133TQ
IC61S25632D-133B
Package
250 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Speed
Order Part Number
IC61S25636T-250TQ
IC61S25636D-250TQ
IC61S25636D-250B
IC61S25636T-200TQ
IC61S25636D-200TQ
IC61S25636D-200B
IC61S25636T-166TQ
IC61S25636D-166TQ
IC61S25636D-166B
IC61S25636T-133TQ
IC61S25636D-133TQ
IC61S25636D-133B
Package
250 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
20
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Speed
Order Part Number
Package
250 MHz
IC61S51218T-250TQ
IC61S51218D-250TQ
IC61S51218D-250B
IC61S51218T-200TQ
IC61S51218D-200TQ
IC61S51218D-200B
IC61S51218T-166TQ
IC61S51218D-166TQ
IC61S51218D-166B
IC61S51218T-133TQ
IC61S51218D-133TQ
IC61S51218D-133B
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Industrial Range: -40°C to 85°C
Speed
Order Part Number
IC61S25632T-250TQI
IC61S25632D-250TQI
IC61S25632D-250B
IC61S25632T-200TQI
IC61S25632D-200TQI
IC61S25632D-200B
IC61S25632T-166TQI
IC61S25632D-166TQI
IC61S25632D-166B
IC61S25632T-133TQI
IC61S25632D-133TQI
IC61S25632D-133B
Package
250 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Integrated Circuit Solution Inc.
21
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Speed
Order Part Number
Package
250 MHz
IC61S25636T-250TQI
IC61S25636D-250TQI
IC61S25636D-250B
IC61S25636T-200TQI
IC61S25636D-200TQI
IC61S25636D-200B
IC61S25636T-166TQI
IC61S25636D-166TQI
IC61S25636D-166B
IC61S25636T-133TQI
IC61S25636D-133TQI
IC61S25636D-133B
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Speed
Order Part Number
IC61S51218T-250TQI
IC61S51218D-250TQI
IC61S51218D-250B
IC61S51218T-200TQI
IC61S51218D-200TQI
IC61S51218D-200B
IC61S51218T-166TQI
IC61S51218D-166TQI
IC61S51218D-166B
IC61S51218T-133TQI
IC61S51218D-133TQI
IC61S51218D-133B
Package
250 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
200 MHz
166 MHz
133 MHz
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
22
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
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