IC62LV1024AL-70T [ICSI]
128K x 8 Ultra Low Power and Low VCC SRAM; 128K ×8的超低功耗和低VCC SRAM
| 型号： | IC62LV1024AL-70T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 128K x 8 Ultra Low Power and Low VCC SRAM |
| 文件： | 总11页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62LV1024AL
IC62LV1024ALL
Document Title
128K x 8 Ultra Low Power and Low VCC SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 13,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
1
IC62LV1024AL
IC62LV1024ALL
128K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IC62LV1024AL and IC62LV1024ALL are low power
and low Vcc,131,072-word by 8-bit CMOS static RAMs. They
arefabricatedusingICSI'shigh-performanceCMOStechnology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low power
consumption devices.
• Access times of 45, 55, and 70 ns
• Low active power: 60 mW (typical)
• Low standby power: 15 µW (typical) CMOS
standby
• Low data retention voltage: 2V (min.)
• Available in Low Power (-L) and
Ultra Low Power (-LL)
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• Single 2.7V to 3.3V power supply
TheIC62LV1024ALandIC62LV1024ALLareavailablein32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin
6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
512 X 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP
32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
48-Pin 6x8mm TF-BGA
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
1
2
3
4
5
6
CE2
CE2
WE
NC
A3
A4
A5
A6
A7
A0
I/O
A1
A2
A8
I/O
A
B
C
D
E
F
OE
5
1
WE
I/O
I/O
2
6
I/O0-I/O7
NC
GND
Vcc
Vcc
No Connection
Power
GND
Vcc
GND
Ground
I/O
7
NC
CE1
A11
NC
A16
A12
I/O
3
I/O
8
OE
A15
A13
I/O
4
G
H
A9
A10
A14
OPERATING RANGE
Range
Commercial
Ambient Temperature
VCC
2.7V to 3.3V
0°C to +70°C
Industrial
–40°C to +85°C
2.7V to 3.3V
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
3
IC62LV1024AL
IC62LV1024ALL
TRUTH TABLE
Mode
WE CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled H
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Read
Write
H
L
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
Terminal Voltage with Respect to GND
–0.5 to +3.6
–0.3 to +3.6
–40 to +85
–65 to +150
0.7
VCC
Vcc related to GND
Temperature Under Bias
StorageTemperature
Power Dissipation
V
TBIAS
TSTG
PT
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
COUT
Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
2.2
—
—
V
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
2.2
–0.3
–1
VCC + 0.3
V
0.4
1
V
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
µA
µA
ILO
Output Leakage
–1
1
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
4
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
IC62LV1024AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45L ns
-55L ns
-70L ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
Com.
Ind.
—
—
40
45
—
—
35
40
—
—
30
35
mA
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIH Ind.
—
—
0.8
1
—
—
0.8
1
—
—
0.8
1
mA
µA
VIN = VIH or VIL, CE1
≥
or CE2
≤ VIL, f = 0
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
—
—
50
75
—
—
50
75
—
—
50
75
CE1
≥
≤
VCC – 0.2V,
0.2V,
CE2
or VIN
≥ VCC – 0.2V, VIN ≤ 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV1024ALL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45LL ns
-55LL ns
-70LL ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
Com.
Ind.
—
—
40
45
—
—
35
40
—
—
30
35
mA
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIH Ind.
—
—
0.8
1
—
—
0.8
1
—
—
0.8
1
mA
µA
VIN = VIH or VIL, CE1
≥
or CE2
≤ VIL, f = 0
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
—
—
5
10
—
—
5
10
—
—
5
10
CE1
≥
≤
VCC – 0.2V,
0.2V,
CE2
or VIN
≥ VCC – 0.2V, VIN ≤ 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
5
IC62LV1024AL
IC62LV1024ALL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45
-55
-70
Symbol Parameter
Min.
45
—
10
—
—
—
0
Max.
—
Min.
55
—
10
—
—
—
5
Max.
—
Min.
70
—
10
—
—
—
5
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
45
—
55
—
70
—
tOHA
tACE1
tACE2
tDOE
45
45
20
—
55
55
25
—
70
70
35
—
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
(2)
tHZOE
0
15
—
0
20
—
0
25
—
tLZCE1(2) CE1 to Low-Z Output
tLZCE2(2) CE2 to Low-Z Output
5
7
10
10
0
5
—
7
—
—
(2)
tHZCE
CE1 or CE2 to High-Z Output
0
15
0
20
25
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0.4V to 2.2V
5 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1
AC TEST LOADS
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1.
Figure 2.
6
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
DOUT
t
AA
t
OHA
t
OHA
DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
7
IC62LV1024AL
IC62LV1024ALL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
-45
-55
-70
Symbol Parameter
Min.
45
35
35
35
0
Max.
—
Min.
55
50
50
50
0
Max.
—
Min.
70
60
60
60
0
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tSCE1
tSCE2
tAW
CE1 to Write End
—
—
—
CE2 to Write End
—
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
—
tHA
—
—
—
tSA
0
—
0
—
0
—
(4)
tPWE
tSD
WE Pulse Width
35
25
0
—
40
25
0
—
55
30
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
—
tHD
—
—
—
(2)
tHZWE
—
5
15
—
—
5
20
—
0
25
—
(2)
tLZWE
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATA-IN VALID
8
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
t
HD
t
SD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Vcc for Data Retention
TestCondition
See Data Retention Waveform
Min.
2.0
Max.
3.3
Unit
V
IDR
Data Retention Current
Vcc = 2.0V, CE1
≥
Vcc – 0.2V
Com. (-L)
Com. (-LL)
Ind. (-L)
—
—
—
—
30
5
50
10
µA
µA
µA
µA
Ind. (-LL)
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
—
ns
ns
tRC
DATA RETENTION WAVEFORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
V
V
CC
DR
3.0V
2.2V
CE1 ≥ V
- 0.2V
CC
CE1
GND
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
9
IC62LV1024AL
IC62LV1024ALL
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
V
CC
3.0V
2.2V
t
t
RDR
SDR
CE2
V
DR
CE2 ≤ 0.2V
0.4V
GND
IC62LV1024AL
IC62LV1024AL
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
45
55
70
IC62LV1024AL-45Q
IC62LV1024AL-45T
IC62LV1024AL-45H
IC62LV1024AL-45B
450milSOP
45
55
70
IC62LV1024AL-45QI
IC62LV1024AL-45TI
IC62LV1024AL-45HI
IC62LV1024AL-45BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
IC62LV1024AL-55Q
IC62LV1024AL-55T
IC62LV1024AL-55H
IC62LV1024AL-55B
450milSOP
IC62LV1024AL-55QI
IC62LV1024AL-55TI
IC62LV1024AL-55HI
IC62LV1024AL-55BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
IC62LV1024AL-70Q
IC62LV1024AL-70T
IC62LV1024AL-70H
IC62LV1024AL-70B
450milSOP
IC62LV1024AL-70QI
IC62LV1024AL-70TI
IC62LV1024AL-70HI
IC62LV1024AL-70BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
10
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
IC62LV1024ALL
IC62LV1024ALL
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
45
55
70
IC62LV1024ALL-45Q
IC62LV1024ALL-45T
IC62LV1024ALL-45H
IC62LV1024ALL-45B
450milSOP
45
55
70
IC62LV1024ALL-45QI
IC62LV1024ALL-45TI
IC62LV1024ALL-45HI
IC62LV1024ALL-45BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
IC62LV1024ALL-55Q
IC62LV1024ALL-55T
IC62LV1024ALL-55H
IC62LV1024ALL-55B
450milSOP
IC62LV1024ALL-55QI
IC62LV1024ALL-55TI
IC62LV1024ALL-55HI
IC62LV1024ALL-55BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
IC62LV1024ALL-70Q
IC62LV1024ALL-70T
IC62LV1024ALL-70H
IC62LV1024ALL-70B
450milSOP
IC62LV1024ALL-70QI
IC62LV1024ALL-70TI
IC62LV1024ALL-70HI
IC62LV1024ALL-70BI
450milSOP
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
8*20mmTSOP-1
8*13.4mmTSOP-1
6*8mmTF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
11
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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