IC80C58-40W [ICSI]
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER; CMOS单芯片8位微控制器
| 型号： | IC80C58-40W |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | CMOS SINGLE CHIP 8-BIT MICROCONTROLLER |
| 文件： | 总22页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC80C54
IC80C58
CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
FEATURES
GENERAL DESCRIPTION
The ICSI IC80C54 and IC80C58 are high-performance
microcontroller fabricated using high-density CMOS
technology. The CMOS IC80C54/58 is functionally
compatible with the industry standard 80C52/32
microcontrollers.
• 80C52 based architecture
• 16K x 8 ROM (80C54)
32K x 8 ROM (80C58)
• 256 x 8 RAM
The IC80C54/58 is designed with 16K x 8 ROM (IC80C54
)and 32Kx8 ROM (IC80C58); 256 x 8 RAM; 32
programmable I/O lines; a serial I/O port for either
multiprocessorcommunications,I/Oexpansionorfullduplex
UART; three 16-bit timer/counters; an eight-source, two-
priority-level, nested interrupt structure; and an on-chip
oscillator and clock circuit. The IC80C54/58 can be
expanded using standard TTL compatible memory.
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Lock bits (2)
• Power save modes:
– Idle and power-down
T2/P1.0
T2EX/P1.1
P1.2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
• Eight interrupt sources
3
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
P1.3
4
P1.4
5
• Maximum speed: 40 MHz @ Vcc = 5V
P1.5
6
P1.6
7
• Packages available:
– 40-pin DIP
P1.7
8
RST
9
– 44-pin PLCC
– 44-pin PQFP
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
10
11
12
13
14
15
16
17
18
19
20
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
Figure 1. IC80C54/58 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
MC003-0B
1
IC80C54
IC80C58
INDEX
6
5
4
3
2
1
44
43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
P1.5
P1.6
P1.7
7
8
9
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
RST 10
RxD/P3.0 11
NC 12
TOP VIEW
NC
TxD/P3.1 13
INT0/P3.2 14
INT1/P3.3 15
T0/P3.4 16
T1/P3.5 17
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
Figure 2. IC80C54/58 Pin Configuration: 44-pin PLCC
2
Integrated Circuit Solution Inc.
MC003-0B
IC80C54
IC80C58
44
43 42 41 40 39 38
37 36 35 34
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
33
32
31
30
29
28
27
26
25
24
23
P1.5
P1.6
P1.7
RST
1
2
3
4
RxD/P3.0
NC
5
NC
6
ALE
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
7
PSEN
8
P2.7/A15
P2.6/A14
P2.5/A13
9
10
11
12 13 14 15 16 17 18 19 20 21 22
Figure 3. IC80C54/58 Pin Configuration: 44-pin PQFP
Integrated Circuit Solution Inc.
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3
IC80C54
IC80C58
P2.0-P2.7
P0.0-P0.7
P2
DRIVERS
P0
DRIVERS
VCC
GND
ADDRESS
DECODER
& 256
ADDRESS
DECODER
& 16/32K
ROM
2 LOCK BITS
P2
LATCH
P0
LATCH
RAM ADDR
REGISTER
BYTES RAM
PROGRAM
ADDRESS
REGISTER
STACK
POINT
B
ACC
REGISTER
PROGRAM
COUNTER
PCON SCON TMOD TCON
T2CON
TL1
TH0
TH2
TL0
TL2 RCAP2H
IE IP
TH1
TMP2
TMP1
RCAP2L SBUF
INTERRUPT
SERIAL PORT
PC
INCREMENTER
ALU
AND TIMER BLOCK
PSW
BUFFER
DPTR
PSEN
TIMING
ALE
RST
EA
AND
CONTROL
P3
LATCH
P1
LATCH
PD
OSCILLATOR
P3
DRIVERS
P1
DRIVERS
XTAL1
XTAL2
P3.0-P3.7
P1.0-P1.7
Figure 4. IC80C54/58 Block Diagram
4
Integrated Circuit Solution Inc.
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IC80C54
IC80C58
Table 1. Detailed Pin Description
Symbol
PDIP
PLCC
PQFP I/O
Name and Function
ALE
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte
of the address during an access to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.
EA
31
35
29
I
External Access enable: EA must be externally held low to
enable the device to fetch code from external program memory
locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the program
counter contains an address greater than internal ROM seze.
P0.0-P0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: IIL). The Port 1
output buffers can sink/source four TTL inputs.
Port1alsoreceivesthelow-orderaddressbyteduringverification.
1
2
2
3
40
41
I
I
T2(P1.0): Timer/Counter 2 external count input.
T2EX(P1.1): Timer/Counter 2 trigger input.
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
2 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: IIL). Port 2 emits
the high order address byte during fetches from external pro-
gram memory and during accesses to external data memory
that used 16-bit addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pullups when emitting 1s. During
accesses to external data memory that use 8-bit addresses
(MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order bits and some control signals
during verification.
Integrated Circuit Solution Inc.
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IC80C54
IC80C58
Table 1. Detailed Pin Description (continued)
Symbol
PDIP
PLCC
PQFP I/O
Name and Function
P3.0-P3.7
10-17
11, 13-19
5, 7-13 I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IC80C54/58, as
listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
9
10
11
12
13
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine cycle
except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during
fetches from internal program memory.
RST
9
10
21
4
I
I
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external capaci-
tor connected to Vcc.
XTAL 1
19
15
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
XTAL 2
GND
Vcc
18
20
40
20
22
44
14
16
38
O
I
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
I
Power Supply: This is the power supply voltage for operation.
OPERATING DESCRIPTION
The detail description of the IC80C54/58 included in this description are:
• Memory Map and Registers
• The Timer/Counters
• The Serial Interface
• The Interrupt System
• Information
• Another information
The detail information desription of the IC80C54/58 refer to IC80C52/32 date sheet
6
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IC80C54
IC80C58
Table 2. Reset Values of the SFR's
OTHER INFORMATION
Reset
SFR Name
PC
Reset Value
0000H
00H
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
ACC
B
00H
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 7.
PSW
SP
00H
07H
DPTR
P0-P3
IP
0000H
FFH
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.
XX000000B
0X000000B
00H
IE
TMOD
TCON
T2CON
TH0
00H
00H
The internal reset algorithm writes 0s to all the SFRs except
the port latches, the Stack Pointer, and SBUF. The port
latches are initialized to FFH, the Stack Pointer to 07H, and
SBUF is indeterminate. Table 9 lists the SFRs and their
reset values.
00H
TL0
00H
TH1
00H
TL1
00H
TH2
00H
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
TL2
00H
RCAP2H
RCAP2L
SCON
SBUF
PCON
00H
00H
00H
Indeterminate
0XXX0000B
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IC80C54
IC80C58
Power-on Reset
Vcc
An automatic reset can be obtained when VCC goes through
a 10 µF capacitor and GND through an 8.2K resistor,
providing the Vcc rise time does not exceed 1 msec and the
oscillator start-up time does not exceed 10 msec. This
Power-on reset circuit is shown if Figure 21. The CMOS
devices do not require the 8.2K pulldown resistor, although
its presence does no harm.
+
10 F
-
Vcc
IC80C54/58
RST
When power is turned on, the circuit holds the RST pin high
for an amount of time that depends on the value of the
capacitor and the rate at which it charges. To ensure a good
reset, the RST pin must be high long enough to allow the
oscillator time to start-up (normally a few msec) plus two
machine cycles.
8.2K Ω
GND
Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.
With this circuit, reducing VCC quickly to 0 causes the RST
pin voltage to momentarily fall below 0V. However, this
voltage is internally limited and will not harm the device.
Figure 6. Power-On Reset Circuit
12 OSC. PERIODS
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
RST
INTERNAL RESET SIGNAL
SAMPLE
RST
SAMPLE
RST
ALE
PSEN
P0
INST ADDR INST ADDR
11 OSC. PERIODS
INST
ADDR
INST ADDR INST
ADDR
19 OSC. PERIODS
Figure 7. Reset Timing
8
Integrated Circuit Solution Inc.
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IC80C54
IC80C58
Power-Saving Modes of Operation
The IC80C54/58 has two power-reducing modes. Idle and
Power-down. The input through which backup power is
supplied during these operations is Vcc. Figure 23 shows
the internal circuitry which implements these features. In
the Idle mode (IDL = 1), the oscillator continues to run and
the Interrupt, Serial Port, and Timer blocks continue to be
clocked, but the clock signal is gated off to the CPU. In
Power-down (PD = 1), the oscillator is frozen. The Idle and
Power-down modes are activated by setting bits in Special
Function Register PCON.
XTAL 1
XTAL 2
OSC
PD
INTERRUPT,
SERIAL PORT,
TIMER BLOCKS
CLOCK
GEN
CPU
IDL
Idle Mode
Figure 8. Idle and Power-Down Hardware
Power-down Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode, the
internal clock signal is gated off to the CPU, but not to the
Interrupt, Timer, and Serial Port functions. The CPU status
is preserved in its entirety; the Stack Pointer, Program
Counter, Program Status Word, Accumulator, and all other
registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated.
ALE and PSEN hold at logic high levels.
An instruction that sets PCON.1 is the last instruction
executed before Power-down mode begins. In the Power-
down mode, the on-chip oscillator stops. With the clock
frozen, all functions are stopped, but the on-chip RAM and
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and PSEN
output lows.
There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
the Power-down mode is invoked, and Vcc must be restored
to its normal operating level before the Power-down mode
is terminated. The reset that terminates Power-down also
frees the oscillator. The reset should not be activated
before Vcc is restored to its normal operating level and
must be held active long enough to allow the oscillator to
restart and stabilize (normally less than 10 msec).
The flag bits GF0 and GF1 can be used to indicate whether
an interrupt occurred during normal operation or during an
Idle. For example, an instruction that activates Idle can also
set one or both flag bits. When Idle is terminated by an
interrupt, the interrupt service routine can examine the flag
bits.
The only exit from Power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.
The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 22, two or three machine cycles of program execution
may take place before the internal reset algorithm takes
control. On-chip hardware inhibits access to the internal
RAM during his time, but access to the port pins is not
inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not write to a port pin or to external data
RAM.
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IC80C54
IC80C58
Table 3. Status of the External Pins During Idle and Power-down Modes.
Mode
Idle
Memory
Internal
External
Internal
External
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
1
1
0
0
1
1
0
0
Idle
Float
Data
Address
Data
Data
Power-down
Power-down
Data
Data
Data
Float
Data
Data
Data
On-Chip Oscillators
The on-chip oscillator circuitry of the IC80C54/58 is a
single stage inverter, intended for use as a crystal-
controlled, positive reactance oscillator. In this application
the crystal is operated in its fundamental response mode
as an inductive reactance in parallel resonance with
capacitance external to the crystal (Figure 9). Examples
of how to drive the clock with external oscillator are shown
in Figure 10.
The crystal specifications and capacitance values (C1 and
C2 in Figure 9) are not critical. 20 pF to 30 pF can be used
in these positions at a 12 MHz to 24 MHz frequency with
good quality crystals. (For ranges greater than 24 MHz refer
to Figure 11.) A ceramic resonator can be used in place of
the crystal in cost-sensitive applications. When a ceramic
resonator is used, C1 and C2 are normally selected to be of
somewhat higher values. The manufacturer of the ceramic
resonator should be consulted for recommendation on the
values of these capacitors.
C2
XTAL2
XTAL1
NC
XTAL2
C1
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
GND
Figure 9. Oscillator Connections
Figure 10. External Clock Drive Configuration
10
Integrated Circuit Solution Inc.
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IC80C54
IC80C58
XTAL2
XTAL1
R
C2
C1
Figure 11. Oscillator Connections for High Speed (> 24 MHz)
Note:
When the frequency is higher than 24 MHz, please refer to Table 4 for recommended values of C1, C2, and R.
Table 4. Recommended Value for C1, C2, R
Frequency Range
3.5 MHz - 24 MHz
20 pF-30 pF
20 pF-30 pF
Not Apply
24 MHz - 40 MHz
3 pF-10 pF
C1
C2
R
3 pF-10 pF
6.2K-10K
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IC80C54
IC80C58
ROM Verification
The address of the program menory location to be read is
applied to Port 1 and pins P2.5-P2.0 (A14 is P3.4 for
IC80C58). The other pins should be held at the “Verify”
level are indicated in Figure 12. The contents of the ad-
dressed locations exits on Port 0. External pullups are re-
quired on Rort 0 for this operation. Figure 12 shows the
setup to verify the program memory.
+ 5V
A7-A0
P1
Vcc
10K x 8
A12-A8
P2.4-P2.0
1
1
1
0
0
0
RST
EA
ALE
PSEN
P2.7
P2.6
PGM
DATA
P0
XTAL1
P2.5
P3.4
A13
P14
4-6 MHz
IC80C54 : A13 - A0
IC80C58 : A14 - A0
XTAL2
GND
Figure 12. ROM Verification
12
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IC80C54
IC80C58
ROM Lock System
The ICSI 80C54/58 contains two Program Memory Locking:
Security Bit 1:
When programmed, this bit two effects on masked ROM
parts:
1) External MOVC is disable, and
2) EA pin is latch on reset.
Security Bit2:
When programmed, this bit inhibits Verify User ROM.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–2.0 to +7.0
0 to +70
–65 to +125
1.5
Unit
V
°C
°C
W
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND(2)
Temperature Under Bias(3)
Storage Temperature
Power Dissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.
0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V
which may overshoot to Vcc + 2.0V for periods less than 20 ns.
3. Operating temperature is for commercial products only defined by this specification.
OPERATING RANGE(1)
Range
Ambient Temperature
VCC
Oscillator Frequency
Commercial
Note:
0°C to +70°C
5V 10ꢀ
3.5 to 40 MHz
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
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IC80C54
IC80C58
DC CHARACTERISTICS
(Ta=0°C to 70 °C; VCC=5V+10ꢀ; VSS=0V )
Symbol
Parameter
Test conditions
Min
Max
Unit
VIL
VIL1
VIH
Input low voltage (All except EA)
Input low voltage (EA)
–0.5
–0.5
0.2Vcc – 0.1
0.2Vcc – 0.3
Vcc + 0.5
V
V
V
Input high voltage
0.2Vcc + 0.9
(All except XTAL 1, RST)
VIH1
Input high voltage (XTAL 1)
0.7Vcc
0.7Vcc
Vcc + 0.5
Vcc + 0.5
V
V
VSCH+
RST positive schmitt-trigger
threshold voltage
VSCH–
RST negative schmitt-trigger
threshold voltage
0
0.3Vcc
V
(1)
VOL
Output low voltage
(Ports 1, 2, 3)
Iol = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
—
—
0.3
0.45
1.0
V
V
V
V
V
V
V
—
VOL1(1)
VOH
Output low voltage
—
0.3
(Port 0, ALE, PSEN)
—
0.45
1.0
—
Output high voltage
IOH = –10 µA
0.9Vcc
—
(Ports 1, 2, 3, ALE, PSEN)
Vcc = 4.5V-5.5V
IOL = –25 µA
IOL = –60 µA
0.75Vcc
2.4
—
—
—
V
V
V
VOH1
Output high voltage
IOH = –80 µA
0.9Vcc
(Port 0, ALE, PSEN)
Vcc = 4.5V-5.5V
IOH = –300 µA
IOH = –800 µA
0.75Vcc
2.4
—
—
V
V
IIL
ILI
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V
—
–50
+10
–650
µA
µA
µA
Input leakage current (Port 0)
0.45V < VIN < Vcc
VIN = 2.0V
–10
—
ITL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
RRST
RST pulldown resister
50
300
KΩ
Note:
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
14
Integrated Circuit Solution Inc.
MC003-0B
IC80C54
IC80C58
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test conditions
Vcc = 5.0V
12 MHz
Min
Max
Unit
Icc
Power supply current(1)
Active mode
—
—
—
—
—
—
—
—
—
—
—
—
—
20
26
32
38
50
62
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
16 MHz
20 MHz
25 MHz
36 MHz
40 MHz
Idle mode
12 MHz
16 MHz
6
20 MHz
7.6
9
25 MHz
36 MHz
12
15
100
40 MHz
Power-down mode
VCC = 5V
Note:
1. See Figures13,14,15, and 16 for Icc test conditiions.
Vcc
Vcc
Icc
Vcc
Icc
RST
Vcc
RST
Vcc
Vcc
Vcc
P0
EA
P0
EA
NC
XTAL2
NC
XTAL2
CLOCK
SIGNAL
CLOCK
SIGNAL
XTAL1
GND
XTAL1
GND
Figure 14. Idle Mode
Figure 13. Active Mode
Vcc
Icc
RST
Vcc
Vcc
P0
EA
NC
XTAL2
XTAL1
GND
Figure 15. Power-down Mode
Integrated Circuit Solution Inc.
MC003-0B
15
IC80C54
IC80C58
t
CLCX
tCHCX
Vcc — 0.5V
0.45V
0.7Vcc
0.2Vcc — 0.1
t
CHCL
tCLCH
t
CLCL
Figure 16. Clock Signal Waveform for ICC Tests in Active and Idle Mode (tCLCH=tCHCL=5 ns)
EXTERNAL MEMORY CHARACTERISTICS
24 MHz
Clock
Min Max
40 MHz
Clock
Min Max
Variable Oscillator
(3.5 - 40 MHz)
Symbol Parameter
Min
3.5
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
Oscillator frequency
—
68
26
31
—
31
110
—
0
—
—
—
35
10
15
—
15
60
—
0
—
—
40
ALE pulse width
2tCLCL–15
tCLCL–15
tCLCL–10
—
—
Address valid to ALE low
Address hold after ALE low
ALE low to valid instr in
ALE low to PSEN low
PSEN pulse width
—
—
—
—
—
—
147
—
80
—
4tCLCL–20
—
tLLPL
tCLCL–10
3tCLCL–15
—
tPLPH
tPLIV
—
—
—
PSEN low to valid instr in
Input instr hold after PSEN
Input instr float after PSEN
Address to valid instr in
PSEN low to address float
RD pulse width
105
—
55
—
3tCLCL–20
—
tPXIX
0
tPXIZ
—
—
—
230
230
—
0
37
—
—
—
130
130
—
0
20
105
10
—
—
tCLCL–5
5tCLCL–20
10
tAVIV
188
10
—
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tWHQX
tRLAZ
tWHLH
—
—
6tCLCL–20
6tCLCL–20
—
—
WR pulse width
—
—
—
RD low to valid data in
Data hold after RD
157
—
90
—
4tCLCL–10
—
0
Data float after RD
—
—
—
78
—
—
—
45
165
190
—
2tCLCL–5
7tCLCL–10
8tCLCL–10
3tCLCL+20
—
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address to RD or WR low
Data valid to WR transition
Data hold after WR
282
323
—
—
105 145
55 95
3tCLCL–20
4tCLCL–20
tCLCL–15
tCLCL–10
—
146
26
31
—
—
—
—
0
80
10
15
—
—
—
—
0
—
—
RD low to address float
RD or WR high to ALE high
0
26
57
10 40
tCLCL–15
tCLCL+15
16
Integrated Circuit Solution Inc.
MC003-0B
IC80C54
IC80C58
EXTERNAL MEMORY CHARACTERISTICS
24 MHz
Clock
Min Max
40 MHz
Clock
Min Max
Variable Oscillator
(3.5-40 MHz)
Symbol Parameter
Min
Max
12tCLCL+10
—
Unit
ns
tXLXL
Serial port clock cycle time
490 510
290 310
12tCLCL–10
10tCLCL–10
tQVXH
Output data setup to
clock rising edge
406
73
0
—
240
40
0
—
ns
tXHQX
tXHDX
tXHDV
Output data hold after
clock rising edge
—
—
2tCLCL–10
—
—
ns
ns
ns
Input data hold after
clock rising edge
—
—
0
Clock rising edge to
input data valid
—
417
—
250
—
10tCLCL
EXTERNAL CLOCK DRIVE
Symbol
1/tCLCL
tCHCX
Parameter
Min
Max
40
—
Unit
MHz
ns
Oscillator Frequency
High time
3.5
10
10
—
tCLCX
Low time
—
ns
tCLCH
Rise time
10
10
ns
tCHCL
Fall time
—
ns
ROM VERIFICATION CHARACTERISTICS
Symbol
1/tCLCL
tAVQV
Parameter
Min
4
Max
6
Unit
Oscillator Frequency
Address to data valid
ENABLE low to data valid
Data float after ENABLE
MHz
—
—
0
40tCLCL
48tCLCL
48tCLCL
tELQV
tEHQZ
Integrated Circuit Solution Inc.
MC003-0B
17
IC80C54
IC80C58
TIMING WAVEFORMS
t
LHLL
ALE
t
LLPL
t
PLPH
PLIV
t
AVLL
t
PSEN
t
PLAZ
tPXIZ
t
LLAX
A7-A0
t
PXIX
PORT 0
INSTR IN
A7-A0
t
LLIV
AVIV
A15-A8
t
A15-A8
PORT 2
Figure 17. External Program Memory Read Cycle
ALE
t
WHLH
PSEN
t
LLDV
t
LLWL
tRLRH
RD
t
AVLL
t
RLAZ
LLAX
t
RHDZ
t
RLDV
t
t
RHDX
PORT 0
A7-A0 FROM RI OR DPL
DATA IN
A7-A0 FROM PCL
INSTR IN
t
AVWL
t
AVDV
A15-A8 FROM DPH
A15-A8 FROM PCH
PORT 2
Figure 18. External Data Memory Read Cycle
18
Integrated Circuit Solution Inc.
MC003-0B
IC80C54
IC80C58
ALE
t
WHLH
PSEN
WR
t
LLWL
tWLWH
t
AVLL
t
WHQX
t
QVWX
DATA OUT
t
LLAX
PORT 0
PORT 2
A7-A0 FROM RI OR DPL
A7-A0 FROM PCL
INSTR IN
t
AVWL
A15-A8 FROM DPH
Figure 19. External Data Memory Write Cycle
A15-A8 FROM PCH
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
DATAOUT
DATAIN
t
XHQX
t
QVXH
0
1
2
3
4
5
6
7
t
XHDX
SET TI
t
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 20. Shift Register Mode Timing Waveform
Integrated Circuit Solution Inc.
MC003-0B
19
IC80C54
IC80C58
P1.0-P1.7
ADDRESS
P2.0-P2.5[A14(P3.4)]
t
AVQV
PORT 0
P2.7
DATA OUT
t
ELQV
tEHQZ
Figure 21. ROM Verification Waveforms
t
CLCX
tCHCX
Vcc — 0.5V
0.45V
0.7Vcc
0.2Vcc — 0.1
t
CHCL
tCLCH
t
CLCL
Figure 22. External Clock Drive Waveforms
Vcc - 0.5V
0.2Vcc + 0.9V
0.2Vcc - 0.1V
0.45V
Figure 23. AC Test Point
Note:
1. AC inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”.
Timing measurements are made at VIH min for logic “1” and max for logic “0”.
20
Integrated Circuit Solution Inc.
MC003-0B
IC80C54
IC80C58
ORDERING INFORMATION
Commercial Temperature: 0°C to +70°C
Speed
Order Part Number
Package
12 MHz
IC80C54/58-12PL
IC80C54/58-12PQ
PLCC
PQFP
IC80C54/58-12W
600mil DIP
24 MHz
40 MHz
IC80C54/58-24PL
IC80C54/58-24PQ
PLCC
PQFP
IC80C54/58-24W
IC80C54/58-40PL
600mil DIP
PLCC
IC80C54/58-40PQ
IC80C54/58-40W
PQFP
600mil DIP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
MC003-0B
21
IC80C54
IC80C58
22
Integrated Circuit Solution Inc.
MC003-0B
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