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IC80LV32-24W [ICSI]

CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER; CMOS单芯片低电压8位微控制器
IC80LV32-24W
型号： IC80LV32-24W
厂家： INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述：

CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
CMOS单芯片低电压8位微控制器

微控制器
文件： 总22页 (文件大小：132K)
中文：  中文翻译
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IC80LV52  
IC80LV32  
CMOS SINGLE CHIP  
LOW VOLTAGE  
8-BIT MICROCONTROLLER  
FEATURES  
GENERAL DESCRIPTION  
The ICSI IC80LV52 and IC80LV32 are high-performance  
microcontrollers fabricated using high-density CMOS  
technology. The CMOS IC80LV52/32 is functionally  
compatible with the industry standard 8052/32  
microcontrollers.  
• 80C51 based architecture  
• 8K x 8 ROM (IC80LV52 only)  
• 256 x 8 RAM  
• Three 16-bit Timer/Counters  
• Full duplex serial channel  
• Boolean processor  
The IC80LV52/32 is designed with 8K x 8 ROM (IC80LV52  
only); 256 x 8 RAM; 32 programmable I/O lines; a serial  
I/O port for either multiprocessor communications, I/O  
expansion or full duplex UART; three 16-bit timer/counters;  
an eight-source, two-priority-level, nested interrupt  
structure; and an on-chip oscillator and clock circuit. The  
IC80LV52/32 can be expanded using standard TTL  
compatible memory.  
• Four 8-bit I/O ports, 32 I/O lines  
• Memory addressing capability  
– 64K ROM and 64K RAM  
• Program memory lock  
– Encrypted verify (32 bytes)  
– Lock bits (2)  
• Power save modes:  
– Idle and power-down  
T2/P1.0  
T2EX/P1.1  
P1.2  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
VCC  
• Eight interrupt sources  
2
P0.0/AD0  
P0.1/AD1  
P0.2/AD2  
P0.3/AD3  
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
• Most instructions execute in 0.5 µs  
• CMOS and TTL compatible  
3
P1.3  
4
• Maximum speed: 24 MHz @ Vcc = 3.3V  
P1.4  
5
• Packages available:  
– 40-pin DIP  
P1.5  
6
P1.6  
7
– 44-pin PLCC  
– 44-pin PQFP  
P1.7  
8
RST  
9
RxD/P3.0  
TxD/P3.1  
INT0/P3.2  
INT1/P3.3  
T0/P3.4  
T1/P3.5  
WR/P3.6  
RD/P3.7  
XTAL2  
XTAL1  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
ALE  
PSEN  
P2.7/A15  
P2.6/A14  
P2.5/A13  
P2.4/A12  
P2.3/A11  
P2.2/A10  
P2.1/A9  
P2.0/A8  
Figure 1. IC80LV52/32 Pin Configuration:  
40-pin DIP  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
MC006-0B  
1
IC80LV52  
IC80LV32  
INDEX  
6
5
4
3
2
1
44  
43 42 41 40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
P1.5  
P1.6  
P1.7  
7
8
9
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
RST 10  
RxD/P3.0 11  
NC 12  
TOP VIEW  
NC  
TxD/P3.1 13  
INT0/P3.2 14  
INT1/P3.3 15  
T0/P3.4 16  
T1/P3.5 17  
ALE  
PSEN  
P2.7/A15  
P2.6/A14  
P2.5/A13  
18 19 20 21 22 23 24 25 26 27 28  
Figure 2. IC80LV52/32 Pin Configuration: 44-pin PLCC  
2
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
44  
43 42 41 40 39 38  
37 36 35 34  
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
P1.5  
P1.6  
P1.7  
RST  
1
2
3
4
RxD/P3.0  
NC  
5
NC  
6
ALE  
TxD/P3.1  
INT0/P3.2  
INT1/P3.3  
T0/P3.4  
T1/P3.5  
7
PSEN  
8
P2.7/A15  
P2.6/A14  
P2.5/A13  
9
10  
11  
12 13 14 15 16 17 18 19 20 21 22  
Figure 3. IC80LV52/32 Pin Configuration: 44-pin PQFP  
Integrated Circuit Solution Inc.  
MC006-0B  
3
IC80LV52  
IC80LV32  
P2.0-P2.7  
P0.0-P0.7  
P2  
DRIVERS  
P0  
DRIVERS  
V
CC  
GND  
ADDRESS  
DECODER  
& 256  
ADDRESS 2 LOCK BITS  
DECODER  
&
&
P2  
LATCH  
P0  
LATCH  
32 BYTES  
ENCRYPTION  
RAM ADDR  
REGISTER  
BYTES RAM  
8K ROM  
PROGRAM  
ADDRESS  
REGISTER  
STACK  
POINT  
B
ACC  
REGISTER  
PROGRAM  
COUNTER  
PCON SCON TMOD TCON  
T2CON  
TL1  
TH0  
TH2  
TL0  
TL2 RCAP2H  
IE IP  
TH1  
TMP2  
TMP1  
RCAP2L SBUF  
INTERRUPT  
SERIAL PORT  
PC  
INCREMENTER  
ALU  
AND TIMER BLOCK  
PSW  
BUFFER  
DPTR  
PSEN  
TIMING  
ALE  
RST  
EA  
AND  
CONTROL  
P3  
LATCH  
P1  
LATCH  
OSCILLATOR  
P3  
DRIVERS  
P1  
DRIVERS  
XTAL1  
XTAL2  
P3.0-P3.7  
P1.0-P1.7  
Figure 4. IC80LV52/32 Block Diagram  
4
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
Table 1. Detailed Pin Description  
Symbol  
PDIP  
PLCC  
PQFP  
I/O  
Name and Function  
ALE  
30  
33  
27  
I/O  
Address Latch Enable: Output pulse for latching the low byte  
of the address during an address to the external memory. In  
normal operation, ALE is emitted at a constant rate of 1/6 the  
oscillator frequency, and can be used for external timing or  
clocking. Note that one ALE pulse is skipped during each  
access to external data memory.  
EA  
31  
35  
29  
I
External Access enable: EA must be externally held low to  
enable the device to fetch code from external program memory  
locations 0000H to FFFFH. If EA is held high, the device  
executes from internal program memory unless the program  
counter contains an address greater than 1FFFH.  
P0.0-P0.7 39-32  
43-36  
37-30  
I/O  
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port  
0 pins that have 1s written to them float and can be used as  
high-impedance inputs. Port 0 is also the multiplexed low-order  
address and data bus during accesses to external program and  
data memory. In this application, it uses strong internal pullups  
when emitting 1s.  
P1.0-P1.7  
1-8  
2-9  
40-44  
1-3  
I/O  
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal  
pullups. Port 1 pins that have 1s written to them are pulled high  
by the internal pullups and can be used as inputs. As inputs,  
Port 1 pins that are externally pulled low will source current  
because of the internal pullups. (See DC Characteristics: IIL).  
The Port 1 output buffers can sink/source four TTL inputs.  
Port 1 also receives the low-order address byte during ROM  
verification.  
1
2
2
3
40  
41  
I
I
T2(P1.0): Timer/Counter 2 external count input.  
T2EX(P1.1): Timer/Counter 2 trigger input.  
P2.0-P2.7 21-28  
24-31  
18-25  
I/O  
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal  
pullups. Port 2 pins that have 1s written to them are pulled high  
by the internal pullups and can be used as inputs. As inputs,  
Port 2 pins that are externally pulled low will source current  
because of the internal pullups. (See DC Characteristics: IIL).  
Port 2 emits the high order address byte during fetches from  
external program memory and during accesses to external  
data memory that used 16-bit addresses (MOVX @ DPTR). In  
this application, Port 2 uses strong internal pullups when  
emitting 1s. During accesses to external data memory that use  
8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents  
of the P2 Special Function Register.  
Port 2 also receives the high-order bits and some control  
signals during ROM verification.  
Integrated Circuit Solution Inc.  
MC006-0B  
5
IC80LV52  
IC80LV32  
Table 1. Detailed Pin Description (continued)  
Symbol  
PDIP  
PLCC  
PQFP  
I/O  
Name and Function  
P3.0-P3.7 10-17  
11, 13-19  
5, 7-13 I/O  
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal  
pullups. Port 3 pins that have 1s written to them are pulled high  
by the internal pullups and can be used as inputs. As inputs,  
Port 3 pins that are externally pulled low will source current  
because of the internal pullups. (See DC Characteristics: IIL).  
Port 3 also serves the special features of the IC80LV52/32, as  
listed below:  
10  
11  
12  
13  
14  
15  
16  
17  
11  
13  
14  
15  
16  
17  
18  
19  
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port.  
TxD (P3.1): Serial output port.  
INT0 (P3.2): External interrupt 0.  
INT1 (P3.3): External interrupt 1.  
T0 (P3.4): Timer 0 external input.  
T1 (P3.5): Timer 1 external input.  
WR (P3.6): External data memory write strobe.  
RD (P3.7): External data memory read strobe.  
9
10  
11  
12  
13  
PSEN  
29  
32  
26  
O
Program Store Enable: The read strobe to external program  
memory. When the device is executing code from the external  
program memory, PSEN is activated twice each machine cycle  
except that two PSEN activations are skipped during each  
access to external data memory. PSEN is not activated during  
fetches from internal program memory.  
RST  
9
10  
21  
4
I
I
Reset: A high on this pin for two machine cycles while the  
oscillator is running, resets the device. An internal MOS resistor  
to GND permits a power-on reset using only an external  
capacitor connected to Vcc.  
XTAL 1  
19  
15  
Crystal 1: Input to the inverting oscillator amplifier and input  
to the internal clock generator circuits.  
XTAL 2  
GND  
Vcc  
18  
20  
40  
20  
22  
44  
14  
16  
38  
O
I
Crystal 2: Output from the inverting oscillator amplifier.  
Ground: 0V reference.  
I
Power Supply: This is the power supply voltage for operation.  
OPERATING DESCRIPTION  
The detail description of the IC80LV52/32 included in this description are:  
• Memory Map and Registers  
• Timer/Counters  
• Serial Interface  
• Interrupt System  
• Other Information  
The detail information desription of the IC80LV52/32 refer to IC80C52/32 data sheet  
6
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
Table 2. Reset Values of the SFR's  
OTHER INFORMATION  
Reset  
SFR Name  
PC  
Reset Value  
0000H  
00H  
The reset input is the RST pin, which is the input to a  
Schmitt Trigger.  
ACC  
B
00H  
A reset is accomplished by holding the RST pin high for at  
least two machine cycles (24 oscillator periods), while the  
oscillator is running. The CPU responds by generating an  
internal reset, with the timing shown in Figure 6.  
PSW  
SP  
00H  
07H  
DPTR  
P0-P3  
IP  
0000H  
FFH  
The external reset signal is asynchronous to the internal  
clock. The RST pin is sampled during State 5 Phase 2 of  
every machine cycle. The port pins will maintain their  
current activities for 19 oscillator periods after a logic 1 has  
been sampled at the RST pin; that is, for 19 to 31 oscillator  
periods after the external reset signal has been applied to  
the RST pin.  
XX000000B  
0X000000B  
00H  
IE  
TMOD  
TCON  
T2CON  
TH0  
00H  
00H  
The internal reset algorithm writes 0s to all the SFRs  
except the port latches, the Stack Pointer, and SBUF. The  
port latches are initialized to FFH, the Stack Pointer to  
07H, and SBUF is indeterminate. Table 2 lists the SFRs  
and their reset values.  
00H  
TL0  
00H  
TH1  
00H  
TL1  
00H  
TH2  
00H  
Then internal RAM is not affected by reset. On power-up  
the RAM content is indeterminate.  
TL2  
00H  
RCAP2H  
RCAP2L  
SCON  
SBUF  
PCON  
00H  
00H  
00H  
Indeterminate  
0XXX0000B  
Integrated Circuit Solution Inc.  
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7
IC80LV52  
IC80LV32  
Power-on Reset  
An automatic reset can be obtained when VCC goes  
through a 10µF capacitor and GND through an 8.2K  
resistor, providing the VCC rise time does not exceed  
1 msec and the oscillator start-up time does not exceed  
10 msec. This power-on reset circuit is shown in Figure 5.  
The CMOS devices do not require the 8.2K pulldown  
resistor, although its presence does no harm.  
Vcc  
+
10 F  
-
Vcc  
IC80LV52/32  
When power is turned on, the circuit holds the RST pin high  
for an amount of time that depends on the value of the  
capacitor and the rate at which it charges. To ensure a  
good reset, the RST pin must be high long enough to allow  
the oscillator time to start-up (normally a few msec) plus  
two machine cycles.  
RST  
8.2K Ω  
Note that the port pins will be in a random state until the  
oscillator has start and the internal reset algorithm has  
written 1s to them.  
GND  
With this circuit, reducing VCC quickly to 0 causes the RST  
pin voltage to momentarily fall below 0V. However, this  
voltage is internally limited, and will not harm the device.  
Figure 5. Power-On Reset Circuit  
12 OSC. PERIODS  
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4  
RST  
INTERNAL RESET SIGNAL  
SAMPLE  
RST  
SAMPLE  
RST  
ALE  
PSEN  
P0  
INST ADDR INST ADDR  
11 OSC. PERIODS  
INST  
ADDR  
INST ADDR INST  
ADDR  
19 OSC. PERIODS  
Figure 6. Reset Timing  
8
Integrated Circuit Solution Inc.  
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IC80LV52  
IC80LV32  
Power-Saving Modes of Operation  
The IC80LV52/32 has two power-reducing modes. Idle  
and Power-down. The input through which backup power  
is supplied during these operations is Vcc. Figure 7 shows  
the internal circuitry which implements these features. In  
the Idle mode (IDL = 1), the oscillator continues to run and  
the Interrupt, Serial Port, and Timer blocks continue to be  
clocked, but the clock signal is gated off to the CPU. In  
Power-down (PD = 1), the oscillator is frozen. The Idle and  
Power-down modes are activated by setting bits in Special  
Function Register PCON.  
XTAL 1  
XTAL 2  
OSC  
PD  
INTERRUPT,  
SERIAL PORT,  
TIMER BLOCKS  
CLOCK  
GEN  
CPU  
IDL  
Idle Mode  
An instruction that sets PCON.0 is the last instruction  
executed before the Idle mode begins. In the Idle mode,  
the internal clock signal is gated off to the CPU, but not to  
the Interrupt, Timer, and Serial Port functions. The CPU  
status is preserved in its entirety: the Stack Pointer,  
Program Counter, Program Status Word, Accumulator,  
and all other registers maintain their data during Idle. The  
port pins hold the logical states they had at the time Idle  
was activated. ALE and PSEN hold at logic high levels.  
Figure 7. Idle and Power-Down Hardware  
Power-down Mode  
An instruction that sets PCON.1 is the last instruction  
executed before Power-down mode begins. In the Power-  
down mode, the on-chip oscillator stops. With the clock  
frozen, all functions are stopped, but the on-chip RAM and  
Special function Registers are held. The port pins output  
the values held by their respective SFRs. ALE and PSEN  
output lows.  
There are two ways to terminate the Idle. Activation of any  
enabled interrupt will cause PCON.0 to be cleared by  
hardware, terminating the Idle mode. The interrupt will be  
serviced, and following RETI the next instruction to be  
executed will be the one following the instruction that put  
the device into Idle.  
In the Power-down mode of operation, Vcc can be reduced  
to as low as 2V. However, Vcc must not be reduced before  
the Power-down mode is invoked, and Vcc must be restored  
to its normal operating level before the Power-down mode is  
terminated. The reset that terminates Power-down also  
frees the oscillator. The reset should not be activated before  
Vcc is restored to its normal operating level and must be held  
active long enough to allow the oscillator to restart and  
stabilize (normally less than 10 msec).  
The flag bits GF0 and GF1 can be used to indicate whether  
an interrupt occurred during normal operation or during an  
Idle. For example, an instruction that activates Idle can  
also set one or both flag bits. When Idle is terminated by  
an interrupt, the interrupt service routine can examine the  
flag bits.  
The only exit from power-down is a hardware reset. Reset  
redefines all the SFRs but does not change the on-chip  
RAM.  
The other way of terminating the Idle mode is with a  
hardware reset. Since the clock oscillator is still running,  
the hardware reset must be held active for only two  
machine cycles (24 oscillator periods) to complete the  
reset.  
The signal at the RST pin clears the IDL bit directly and  
asynchronously. At this time, the CPU resumes program  
execution from where it left off; that is, at the instruction  
following the one that invoked the Idle Mode. As shown in  
Figure 22, two or three machine cycles of program execution  
may take place before the internal reset algorithm takes  
control. On-chip hardware inhibits access to the internal  
RAM during his time, but access to the port pins is not  
inhibited. To eliminate the possibility of unexpected outputs  
at the port pins, the instruction following the one that  
invokes Idle should not write to a port pin or to external data  
RAM.  
Integrated Circuit Solution Inc.  
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9
IC80LV52  
IC80LV32  
Table 3. Status of the External Pins During Idle and Power-down Modes.  
Mode  
Idle  
Memory  
Internal  
External  
Internal  
External  
ALE  
PSEN  
PORT 0  
Data  
PORT 1  
Data  
PORT 2  
Data  
PORT 3  
Data  
1
1
0
0
1
1
0
0
Idle  
Float  
Data  
Address  
Data  
Data  
Power-down  
Power-down  
Data  
Data  
Data  
Float  
Data  
Data  
Data  
On-Chip Oscillators  
The crystal specifications and capacitance values (C1 and  
C2 in Figure 8) are not critical. 20 pF to 30 pF can be used  
in these positions at a12 MHz to 24 MHz frequency with  
good quality crystals. A ceramic resonator can be used in  
place of the crystal in cost-sensitive applications. When a  
ceramic resonator is used, C1 and C2 are normally selected  
to be of somewhat higher values. The manufacturer of the  
ceramic resonator should be consulted for recommendation  
on the values of these capacitors.  
The on-chip oscillator circuitry of the IC80LV52/32 is a  
single stage linear inverter, intended for use as a crystal-  
controlled, positive reactance oscillator (Figure 8). In this  
application the crystal is operated in its fundamental  
response mode as an inductive reactance in parallel  
resonance with capacitance external to the crystal (Figure  
8). Examples of how to drive the clock with external  
oscillator are shown in Figure 9.  
C2  
XTAL2  
XTAL1  
NC  
XTAL2  
C1  
EXTERNAL  
OSCILLATOR  
SIGNAL  
XTAL1  
GND  
GND  
Figure 9. External Clock Drive Configuration  
Figure 8. Oscillator Connections  
Table 4. Recommended Value for C1, C2, R  
Frequency Range  
4 MHz-24 MHz  
30 MHz-40 MHz  
C1  
C2  
R
20 pF-30 pF  
20 pF-30 pF  
Not Apply  
–
–
–
10  
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IC80LV52  
IC80LV32  
ROM Verification  
The address of the program memory location to be read is  
applied to Port 1 and pins P2.4-P2.0. The other pins  
should be held at the “Verify” level are indicated in Figure  
10. The contents of the addressed locations exits on Port  
0. External pullups are required on Port 0 for this operation.  
Figure 10 shows the setup to verify the program memory.  
+ 3.3V  
A7-A0  
P1  
Vcc  
10K x 8  
A12-A8  
P2.4-P2.0  
1
1
1
0
0
0
RST  
EA  
ALE  
PSEN  
P2.7  
P2.6  
PGM  
DATA  
P0  
XTAL1  
4-6 MHz  
XTAL2  
GND  
Figure 10. ROM Verification  
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IC80LV52  
IC80LV32  
ROM Lock System  
Encryption Array  
The program lock system, when programmed, protects  
the ROM code against software piracy. The IC80LV52/32  
has a two-level program lock system (see Table 5) and a  
32-byte encryption table. No matter what lock bit is, the  
user submits the encryption table with his or her code in  
verify ROM mode. Both the lock-bit and encryption array  
programmed by the factory.  
Within the ROM array are 32 bytes of Encryption Array that  
are initially unprogrammed (all 1's). Every time that a byte  
is addressed during verify, five address lines are used to  
select a byte of the Encryption Array.This byte is then  
exclusive-NOR'ed (XNOR) with the code byte, creating an  
Encryption verify byte. The algorithm, with the array in the  
unprogrammed state (all 1's), will return the code in its  
original, unmodified form.  
When using the encryption array, one important factor  
needs to be considered. If a code byte has the value 0FFH,  
verifying the byte will produce the encryption byte value. If  
a large block (> 32 bytes) of code is left unprogrammed, a  
verification routine will display the contents of the encryption  
array. For this reason, all unused code bytes should be  
programmed with some value other than 0FFH, and not all  
of them the same value.  
Table 5. Program Lock Bits  
LB1  
LB2  
Protection Type  
1
2
U
U
No Program Lock Features enabled. (Code verify will still be  
encrypted by the Encryption Array if Programmed)  
MOVC instructions executed from external program memory  
are diabled form fetching code bytes from internal memory,  
EA is sampled and latched on Reset.  
P
P
U
P
3
Same as 2, also ROM verify is disabled.  
12  
Integrated Circuit Solution Inc.  
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IC80LV52  
IC80LV32  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameter  
Value  
–2.0 to +7.0  
0 to +70  
–65 to +125  
1.5  
Unit  
V
°C  
°C  
W
VTERM  
TBIAS  
TSTG  
PT  
Terminal Voltage with Respect to GND(2)  
Temperature Under Bias(3)  
Storage Temperature  
Power Dissipation  
Note:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V  
for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may  
overshoot to Vcc + 2.0V for periods less than 20 ns.  
3. Operating temperature is for commercial products only defined by this specification.  
OPERATING RANGE(1)  
Range  
Ambient Temperature  
VCC  
Oscillator Frequency  
Commercial  
0°C to +70°C  
3.3V 10ꢀ  
3.5 to 24 MHz  
Note:  
1. Operating ranges define those limits between which the functionality of the device is guaranteed.  
Integrated Circuit Solution Inc.  
MC006-0B  
13  
IC80LV52  
IC80LV32  
DC CHARACTERISTICS  
(TA = 0°C to 70°C; Vcc = 3.3V 10ꢀ; GND = 0V)  
Symbol  
Parameter  
Test conditions  
Min  
Max  
Unit  
VIL  
VIL1  
VIH  
Input low voltage (All except EA)  
Input low voltage (EA)  
–0.5  
–0.5  
0.2Vcc + 0.1  
0.2Vcc + 0.1  
Vcc + 0.5  
V
V
V
Input high voltage  
0.2Vcc + 0.9  
(All except XTAL 1, RST)  
VIH1  
Input high voltage (XTAL 1)  
0.7Vcc  
0.7Vcc  
Vcc + 0.5  
Vcc + 0.5  
V
V
VSCH+  
RST positive schmitt-trigger  
threshold voltage  
VSCH–  
Vol(1)  
RST negative schmitt-trigger  
threshold voltage  
0
0.3Vcc  
0.45  
V
V
Output low voltage  
(Ports 1, 2, 3)  
IOL = 1.6 mA  
IOL = 3.2 mA  
—
VOL1(1)  
Output low voltage  
(Port 0, ALE, PSEN)  
—
0.45  
V
VOH  
Output high voltage  
(Ports 1, 2, 3, ALE, PSEN)  
IOH = –20 µA  
IOH = –800 µA  
Vcc–0.9  
Vcc–0.9  
—
—
V
V
VOH1  
Output high voltage  
(Port 0, ALE, PSEN)  
IIL  
ILI  
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V  
—
–5  
—
–50  
5
µA  
µA  
µA  
Input leakage current (Port 0)  
0.45V < VIN < Vcc  
VIN = 2.0V  
ITL  
Logical 1-to-0 transition current  
(Ports 1, 2, 3)  
–450  
RRST  
RST pulldown resister  
150  
450  
KΩ  
Note:  
1. Under steady state (non-transient) conditions, Iol must be externally limited as follows:  
Maximum IOL per port pin: 10 mA  
Maximum IOL per 8-bit port  
Port 0: 26 mA  
Ports 1, 2, 3: 15 mA  
Maximum total IOL for all output pins: 71 mA  
If IOL exceeds the test condition, VOL may exceed the related specification.  
Pins are not guaranteed to sink greater than the listed test conditions.  
14  
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test conditions  
Vcc = 3.3V  
12 MHz  
Min  
Max  
Unit  
Icc  
Power supply current(1)  
Active mode  
—
—
—
—
—
15  
24  
4
mA  
mA  
mA  
mA  
µA  
24 MHz  
Idle mode  
12 MHz  
24 MHz  
8
Power-down mode  
VCC = 3.3V  
50  
Note:  
1. See Figures 11, 12, 13, and 14 for Icc test conditiions.  
Vcc  
Vcc  
Vcc  
Icc  
Icc  
RST  
Vcc  
RST  
Vcc  
Vcc  
Vcc  
P0  
EA  
P0  
EA  
NC  
NC  
XTAL2  
XTAL2  
CLOCK  
SIGNAL  
CLOCK  
SIGNAL  
XTAL1  
GND  
XTAL1  
GND  
Figure 11. Active Mode  
Figure 12. Idle Mode  
Vcc  
Icc  
RST  
Vcc  
Vcc  
P0  
EA  
NC  
XTAL2  
XTAL1  
GND  
Figure 13. Power-down Mode  
Integrated Circuit Solution Inc.  
MC006-0B  
15  
IC80LV52  
IC80LV32  
t
CLCX  
tCHCX  
Vcc — 0.5V  
0.45V  
0.7Vcc  
0.2Vcc — 0.1  
t
CHCL  
tCLCH  
t
CLCL  
Figure 14. Clock Signal Waveform for Icc Tests in Active and Idle Modes. (tCLCH=tCHCL=5 ns)  
AC CHARACTERISTICS  
(TA = 0°C to 70°C; Vcc = 3.3V 10ꢀ; GND = 0V; Cl for Port 0, ALE and PSEN Outputs = 100 pF; Cl for other outputs = 80 pF)  
EXTERNAL MEMORY CHARACTERISTICS  
12 MHz  
Clock  
Min Max  
24 MHz  
Clock  
Min Max  
Variable Oscillator  
(3.5-24 MHz)  
Symbol Parameter  
Min  
3.5  
Max  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1/tCLCL  
tLHLL  
tAVLL  
tLLAX  
tLLIV  
Oscillator frequency  
—
152  
68  
73  
—
—
—
—
68  
26  
31  
—
—
—
24  
ALE pulse width  
2tCLCL–15  
tCLCL–15  
tCLCL–10  
—
—
Address valid to ALE low  
Address hold after ALE low  
ALE low to valid instr in  
ALE low to PSEN low  
PSEN pulse width  
—
—
—
—
—
—
313  
—
147  
—
4tCLCL–20  
—
tLLPL  
73  
235  
—
31  
110  
—
tCLCL–10  
3tCLCL–15  
—
tPLPH  
tPLIV  
—
—
—
PSEN low to valid instr in  
Input instr hold after PSEN  
Input instr float after PSEN  
Address to valid instr in  
PSEN low to address float  
RD pulse width  
230  
—
105  
—
3tCLCL–20  
—
tPXIX  
0
0
0
tPXIZ  
—
78  
—
37  
—
tCLCL–5  
5tCLCL–20  
10  
tAVIV  
—
397  
10  
—
188  
10  
—
tPLAZ  
tRLRH  
tWLWH  
tRLDV  
tRHDX  
tRHDZ  
tLLDV  
tAVDV  
tLLWL  
tAVWL  
tQVWX  
tWHQX  
tRLAZ  
tWHLH  
—
—
—
480  
480  
—
—
230  
230  
—
—
6tCLCL–20  
6tCLCL–20  
—
—
WR pulse width  
—
—
—
RD low to valid data in  
Data hold after RD  
323  
—
157  
—
4tCLCL–10  
—
0
0
0
Data float after RD  
—
162  
573  
656  
—
78  
—
2tCLCL–5  
7tCLCL–10  
8tCLCL–10  
3tCLCL+20  
—
ALE low to valid data in  
Address to valid data in  
ALE low to RD or WR low  
Address to RD or WR low  
Data valid to WR transition  
Data hold after WR  
—
—
282  
323  
—
—
—
—
230 270  
105 145  
3tCLCL–20  
4tCLCL–20  
tCLCL–15  
tCLCL–10  
—
313  
68  
73  
—
—
—
—
0
146  
26  
—
—
—
0
—
31  
—
RD low to address float  
RD or WR high to ALE high  
—
0
68  
98  
26 57  
tCLCL–15  
tCLCL+15  
16  
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
EXTERNAL MEMORY CHARACTERISTICS  
(CONTINUED)  
12 MHz  
Clock  
Min Max  
24 MHz  
Clock  
Min Max  
Variable Oscillator  
(3.5-24 MHz)  
Symbol Parameter  
Min  
Max  
12tCLCL+10  
—
Unit  
ns  
tXLXL  
Serial port clock cycle time  
990 1010  
290 310  
12tCLCL–10  
10tCLCL–10  
tQVXH  
Output data setup to  
clock rising edge  
823  
157  
0
—
240  
40  
0
—
ns  
tXHQX  
tXHDX  
tXHDV  
Output data hold after  
clock rising edge  
—
—
2tCLCL–10  
—
—
ns  
ns  
ns  
Input data hold after  
clock rising edge  
—
—
0
Clock rising edge to  
input data valid  
—
833  
—
250  
—
10tCLCL  
EXTERNAL CLOCK DRIVE  
Symbol  
1/tCLCL  
tCHCX  
wParameter  
Min  
Max  
40  
—
Unit  
MHz  
ns  
Oscillator Frequency  
High time  
3.5  
10  
10  
—
tCLCX  
Low time  
—
ns  
tCLCH  
Rise time  
10  
10  
ns  
tCHCL  
Fall time  
—
ns  
ROM VERIFICATION CHARACTERISTICS  
Symbol  
1/tCLCL  
tAVQV  
Parameter  
Min  
4
Max  
6
Unit  
Oscillator Frequency  
Address to data valid  
ENABLE low to data valid  
Data float after ENABLE  
MHz  
—
—
0
48tCLCL  
48tCLCL  
48tCLCL  
tELQV  
tEHQZ  
Integrated Circuit Solution Inc.  
MC006-0B  
17  
IC80LV52  
IC80LV32  
TIMING WAVEFORMS  
t
LHLL  
ALE  
t
LLPL  
t
PLPH  
PLIV  
t
AVLL  
t
PSEN  
t
PLAZ  
tPXIZ  
t
LLAX  
A7-A0  
t
PXIX  
PORT 0  
INSTR IN  
A7-A0  
t
LLIV  
AVIV  
A15-A8  
t
A15-A8  
PORT 2  
Figure 15. External Program Memory Read Cycle  
ALE  
t
WHLH  
PSEN  
t
LLDV  
t
LLWL  
tRLRH  
RD  
t
AVLL  
t
RLAZ  
LLAX  
t
RHDZ  
t
RLDV  
t
t
RHDX  
PORT 0  
A7-A0 FROM RI OR DPL  
DATA IN  
A7-A0 FROM PCL  
INSTR IN  
t
AVWL  
t
AVDV  
A15-A8 FROM DPH  
A15-A8 FROM PCH  
PORT 2  
Figure 16. External Data Memory Read Cycle  
18  
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
ALE  
t
WHLH  
PSEN  
WR  
t
LLWL  
tWLWH  
t
AVLL  
t
WHQX  
t
QVWX  
DATA OUT  
t
LLAX  
PORT 0  
PORT 2  
A7-A0 FROM RI OR DPL  
A7-A0 FROM PCL  
INSTR IN  
t
AVWL  
A15-A8 FROM DPH  
A15-A8 FROM PCH  
Figure 17. External Data Memory Write Cycle  
INSTRUCTION  
0
1
2
3
4
5
6
7
8
ALE  
t
XLXL  
CLOCK  
DATAOUT  
DATAIN  
t
XHQX  
t
QVXH  
0
1
2
3
4
5
6
7
t
XHDX  
SET TI  
t
XHDV  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
SET RI  
Figure 18. Shift Register Mode Timing Waveform  
Integrated Circuit Solution Inc.  
MC006-0B  
19  
IC80LV52  
IC80LV32  
t
CLCX  
tCHCX  
Vcc — 0.5V  
0.45V  
0.7Vcc  
0.2Vcc — 0.1  
t
CHCL  
tCLCH  
t
CLCL  
Figure 19. External Clock Drive Waveform  
ADDRESS  
P1.0-P1.7  
P2.0-P2.3  
t
AVQV  
PORT 0  
DATA OUT  
t
ELQV  
tEHQZ  
P2.7  
Figure 20. ROM Verification Waveforms  
Vcc - 0.5V  
0.45V  
0.2Vcc + 0.9V  
0.2Vcc - 0.1V  
Figure 21. AC Test Point  
Note:  
1. AC inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”.  
Timing measurements are made at VIH min for logic “1” and max for logic “0”.  
20  
Integrated Circuit Solution Inc.  
MC006-0B  
IC80LV52  
IC80LV32  
ORDERING INFORMATION  
COMMERCIAL TEMPERATURE: 0°C to +70°C  
Speed  
Order Part Number  
Package  
24 MHz  
IC80LV52-24PL  
IC80LV52-24PQ  
IC80LV52-24W  
PLCC  
PQFP  
600mil DIP  
24 MHz  
IC80LV32-24PL  
IC80LV32-24PQ  
IC80LV32-24W  
PLCC  
PQFP  
600mil DIP  
Integrated Circuit Solution Inc.  
HEADQUARTER:  
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,  
HSIN-CHU, TAIWAN, R.O.C.  
TEL: 886-3-5780333  
Fax: 886-3-5783000  
BRANCH OFFICE:  
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,  
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.  
TEL: 886-2-26962140  
FAX: 886-2-26962252  
http://www.icsi.com.tw  
Integrated Circuit Solution Inc.  
MC006-0B  
21  
IC80LV52  
IC80LV32  
22  
Integrated Circuit Solution Inc.  
MC006-0B  

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