ICS1523MLF [ICSI]
Video Clock Synthesizer with I2C Programmable Delay; 视频时钟合成器，带有I2C可编程延迟
| 型号： | ICS1523MLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Video Clock Synthesizer with I2C Programmable Delay |
| 文件： | 总21页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
Features
General Description
• Low Jitter
• Wide input frequency range
The ICS1523 is a low-cost, high-performance
frequency generator. It is well suited to general
purpose phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using ICS’s advanced low-voltage
CMOS mixed-mode technology, the ICS1523 is an
effective phase controlled clock synthesizer and also
supports video projectors and displays at resolutions
from VGA to beyond UXGA.
• 15.734 kHz to 100 MHz
• PECL differential outputs
• Up to 250 MHz
• SSTL_3 Single-ended clock outputs
• Up to 150 MHz
• Dynamic Phase Adjust (DPA) for all outputs
2
The ICS1523 offers clock outputs in both differential
(to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust (DPA) allows I C™ control of
• I C controlled phase adjustment
• Full clock cycle down to 1/64 of a clock
• Double-buffered control registers
• External or internal loop filter selection
• COAST input can disable charge pump
• 3.3 VDD
2
the output clock’s phase relative to the input sync
signal. A second, half speed set of outputs that can be
separately enabled allows such applications as
clocking analog-to-digital converters. The FUNC pin
provides either the regenerated input from the
phase-locked loop (PLL) divider chain output, or the
input HSYNC after being sharpened by the Schmitt
trigger. Both signals are then delayed by the DPA.
• 5 volt Tolerant Inputs
2
• Industry Standard I C-bus programming interface
2
• PLL Lock detection via I C or LOCK/REF output pin
• 24-pin 300-mil SOIC package
• Available in Pb-free packaging
The advanced PLL uses either its internal
programmable feedback divider or an external divider.
Either the internal or external loop filters is software
selectable. The COAST input pin disables the PLL’s
charge pump, causing the device to idle at the current
speed for short periods of time, such as vertical
blanking intervals.
The device is programmed by a standard I2C-bus
serial interface and is available in a 24-pin, wide
small-outline integrated circuit (SOIC) package.
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration
ICS1523 Functional Diagram
External Loop Filter (optional)
OSC
HSYNC
I2C I/F
CLK
24-pin SOIC
CLK/2
FUNC
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Figure 1-1 PLL Functional Blocks
Section 1 Operational Description
1.1 Naming Conventions
0xY = Register Index Y(hex)
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
1.2 Overview
The ICS1523 is a general purpose, high-performance,
I2C programmable clock generator. It also addresses
stringent graphics system line-locked and genlocked
applications and provides the clock signals required by
high-performance analog-to-digital converters.
Included are a phase-locked loop (PLL) with an over
500MHz voltage controlled oscillator (VCO), a Dynamic
Phase Adjust to provide (DPA) output clocks with a
programmable phase delay with respect to the input
HSYNC. This delay occurs on all PLL outputs including
the differential (PECL) and single-ended (SSTL_3)
high-speed clock outputs and the FUNC output.
1.4 Voltage Controlled Oscillator (VCO)
The ICS1523 has the ability to operate in line-locked
mode with the HSYNC input or in frequency synthesis
mode with the OSC input with a 7 bit input divider. See
Section 6, “OSC Divider and REF”
The heart of the ICS1523 is a VCO. The VCOs speed
is controlled by the voltage on the loop filter circuit. This
voltage is controlled by the charge pump (CP) and will
be further described later in this section.
1.3 Phase-Locked Loop (PLL)
1.5 Charge Pump (CP) and COAST Input
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1523 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation.
The CPen bit and COAST input pin can enable and
disable the Charge Pump as needed. See Register
0:7-6. This is for maintaining the correct speed clock
outputs in the absence of reliable HSYNC inputs and is
useful for skipping vertical blanking intervals. These
intervals can have double frequency serration pulses or
even be missing HSYNC pulses completely. The
charge pump is asynchronously disabled and
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid.
1.6 VCO Divider (VCOD)
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock. The
VCOD has no effect on the speed of the output clocks,
but it increases the VCO frequency, thereby reducing
jitter and allowing VCO operation between 100 to 500
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
MHz even if a low output frequency is required.The
output of the VCOD is the full speed output frequency
seen on the CLK pins.
1.11 OSC Input
The high-frequency OSC input pin, has a 7-bit user
programmable divider. OSC can also be selected as
the loop input, allowing the loop to operate from any
appropriate, single-ended source, typically a crystal
oscillator.
1.7 Dynamic Phase Adjust (DPA)
The VCOD output clock is then sent through the DPA
for phase adjustment relative to the input HSYNC as
well as the 12-bit internal Feedback Divider. An
external divider may alternately be used and it’s output
must be input on the EXTFB pin. The feedback divider
controls how many clocks are seen during every cycle
of the input reference.
1.12 FUNC Output
Either the conditioned HSYNC input or the loop output
(recovered HSYNC) is available at the FUNC pin, and
is aligned with the output clocks.
The DPA allows a programmable delay between the
input HSYNC to the clock and FUNC outputs, relative
to the input HSYNC signal on a sub-pixel basis. A delay
of up to one clock period is programmable: See Note 6
in Section 5, “Register Set Details” for more
information.
1.13 Logic Inputs
The ICS1523 uses Low-Voltage TTL (LVTTL) inputs
that are 5 volt tolerant such as most VESA compliant
HSYNC and VSYNC signals.
1.14 Output Drivers
1.8 Feedback Divider (FD) and FUNC
The ICS1523 also has SSTL_3 (EIA/JESD8-8) and
low-voltage PECL (Positive ECL) outputs, operating off
the 3.3 V supply voltage.
The 12-bit FD controls how many clocks are seen
between successive HSYNCs.
The number of clocks per HSYNC is FB + 8
The SSTL_3 and differential PECL output drivers drive
resistive terminations or transmission lines. At lower
clock frequencies, the SSTL_3 outputs can be
operated unterminated. See Section 9, “Output
Termination”
The FD output is a 4 CLK wide, active high signal
called FUNC. The FUNC signal is aligned with the
output clocks via the DPA and is intended to be used by
the system as a replacement for the HSYNC input,
which is of in-determinate quality and is not aligned
with the output clocks. Alternately, the post
1.15 Power-On Reset Detection (POR)
Schmitt-trigger HSYNC signal can also be DPA
delayed and then output on the FUNC pin. See 0x0:5.
The ICS1523 has automatic POR circuitry, meaning it
resets itself if the supply voltage drops below a
threshold values of approximately 1.8 V. No external
connection to a reset signal is required.
1.9 Phase Frequency Detector (PFD)
2
The PFD compares the FUNC signal to the selected
input described below and controls the filter voltage by
enabling and disabling the charge pump. The charge
pump has programmable current drive and will source
and sink current as appropriate to keep the input and
the FUNC output aligned.
1.16 I C Bus Serial Interface
The ICS1523 uses a 5 V tolerant, industry-standard
I C-bus serial interface that runs at either low speed
(100 kHz) or high speed (400 kHz). The interface uses
12 indexed registers: one write-only, eight read/write,
and three read-only registers.
2
1.10 HSYNC and REF Inputs
Two ICS1523 devices can be addressed according to
the state of the I2CADR pin. When this pin is low the
read address is 4Dh and the write address is 4Ch.
When the pin is high, the read address is 4Fh and the
write address is 4Eh. See Section 11, “Programming”.
One of the PFDs two possible inputs is HSYNC (pin 7).
HSYNC is conditioned by a high-performance
Schmitt-trigger. This preconditioned HSYNC signal,
called REF, is provided as a reference signal with a
short transition time. REF can be output on pin 14.
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Section 2 Pin Descriptions
TYPE
DESCRIPTION
COMMENTS
Notes
PIN
NO.
PIN NAME
1
2
VDDD
VSSD
SDA
POWER
POWER
IN/OUT
IN
Digital supply
Digital ground
Serial data
3.3 V to digital sections
2
3
I C-bus Data
1
1
1
1
1
2
4
SCL
Serial clock
I C-bus Clock
5
COAST
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
IN
Charge pump enable Enables\Disables the charge pump
External feedback in External feedback divider input
6
IN
7
IN
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
Clock input to PLL
8
IN
External loop filter
9
IN
External loop filter return
3.3 V for analog circuitry
Ground for analog circuitry
10
11
12
POWER
POWER
IN
Input from oscillator or other high
frequency input
1 & 2
2
2
2
13
I CADR
IN
I C address
Chip I C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
14
15
LOCK/REF SSTL_3 OUT Lock / Reference
REF (Schmitt conditioned HSYNC) or
PLL lock output
FUNC
SSTL_3 OUT Function output
Output selectable between a 4 clock
wide, active high HSYNC-like output,
and a Schmitt-trigger filtered HSYNC
16
17
18
19
20
21
22
23
24
CLK/2
CLK
SSTL_3 OUT Pixel clock/2 output
SSTL_3 OUT Pixel clock output
Output driver for half speed clock
Output driver for full speed clock
3.3 V to output drivers
VDDQ
VSSQ
CLK–
CLK+
CLK/2–
CLK/2+
IREF
POWER
POWER
Output driver supply
Output driver ground Ground for output drivers
OD OUT
Pixel clock outputs
PECL driver for full-speed clock
OD OUT
IN
Pixel clock/2 outputs
Reference current
PECL driver for half-speed clock
Reference current for PECL outputs
Note 1: These LVTTL inputs are 5 V-tolerant.
Note 2: Connect to ground if unused.
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Section 3 Functional Block Diagram
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Section 4 Register Set Summary
Reg.
Reset
Index
Name
Access
Bit Name
Bit#
Value
Description
Note
0x0
Input
R / W
CPen
0
1
Charge Pump Enable
3
Control
0=External Enable via COAST Pin, 1=Always Enabled
CP_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
1
2
3
4
5
6
7
0
0
0
0
0
1
0
COAST Pin Charge Pump Enable Polarity
0=Active High, 1=Active Low
3
External Reference Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Select
0=Internal Feedback, 1=External
FUNC Pin Output Select (DPA delayed)
0=Recovered HSYNC, 1=Input HSYNC
Enable PLL Lock/Ref Status Output
0=Disable 1=Enable
4
4
EnRef
1=Enable Ref to Lock/Ref Output
0x1
Loop
R / W
ICP0-2
0-2
0
ICP (Charge Pump Current)
1, 6
Control
Bit 2,1,0=(000 =1 uA, 001 = 2 uA, 010 = 4 uA, 011 = 8 uA,
100 = 16 uA, 101 = 32 uA, 110 = 64 uA, 111 = 128 uA
Reserved
VCOD0-1
Reserved
3
0
0
0
Reserved
4-5
6-7
VCO Divider Bit 5,4 =(00 = ÷2, 01=÷4, 10=÷8, 11=÷16)
Reserved
1, 7
0x2
0x3
FdBk Div 0
FdBk Div 1
R / W
R / W
FBD0-7
0-7
FF
Feedback Divider LSBs (Bit 7, 6, 5, 4, 3, 2, 1, 0)
Actual # of clocks = Programmed value + 8
1
1
FBD8-11
Reserved
0-3
4-7
F
0
Feedback Divider MSBs (Bit 11, 10, 9, 8)
Reserved
0x4
0x5
DPA Offset
R / W
DPA_OS0-5
0-5
0
Dynamic Phase Aligner Offset
Bit 5, 4, 3, 2, 1, 0 = (MUST be < total # of DPA elements)
8
Reserved
Fil_Sel
6
7
0
0
Reserved
Loop Filter Select (0=External, 1=Internal)
6
DPA
Control
R / W
DPA_Res0-1
Metal_Rev
0-1
2-7
3
0
DPA Resolution, Total # of delay elements
Bit 1, 0 = (00 = 16, 01 = 32, 10 = Reserved, 11 = 64)
2, 8
Metal Mask Revision Number
Note 1: Double-buffered register. Working registers are loaded during software PLL reset. See 0x8.
Note 2: Double-buffered register. Working registers are loaded during software DPA reset. See 0x8.
Notes 3~8: See Section 5, “Register Set Details”
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
4.1 Register Set Summary (continued)
Reg.
Index
Name
Access Bit Name
Bit#
Reset
Value
Description
Notes
0x6
Output
Enables
R / W
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
0
1
2
3
4
0
0
0
0
0
Output Enable for PECL CLK (Pins 20, 21)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK (Pin 17)
0=High Z, 1=Enabled
Output Enable for PECL CLK/2 (Pins 22, 23)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK/2 (Pin 16)
0=High Z, 1=Enabled)
Output Enable for STTL_3 FUNC Output (Pin15)
0=High Z, 1=Enabled
Ck2_Inv
Out_Scl
5
0
0
CLK/2 Invert (0=Not Inverted, 1= Inverted)
6-7
CLK Scaler (pin 17)
Bit 7, 6 = (00 = ÷ 1, 01 = ÷ 2, 10 = ÷ 4, 11 = ÷ 8)
See Section 5, “Register Set Details”
0x7
0x8
Osc_Div R / W
Osc_Div
0-6
0-6
7
0
1
Osc Divider modulus
See Section 6, “OSC Divider and REF”
In-Sel
Input Select
0=HSYNC Input, 1=Osc Divider
Reset
Write
DPA
PLL
0-3
4-7
x
x
Writing xAh resets DPA and loads working 0x5
Writing 5xh resets PLL and loads working 0x1- 0x3
0x10
0x11
0x12
Chip Ver Read
Chip Rev Read
Rd_Reg Read
Chip Ver
Chip Rev
0-7
0-7
17
01
Chip Version 23 Dec (17h) as in 1523
Initial value 01h. Value Increments with each all-layer change.
Reserved
Reserved
PLL_Lock
0
1
N/A
N/A
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
2-7
0
Reserved
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Note 6 - ICP - Charge Pump Current
Section 5 Register Set Details
Charge Pump Current (µA)
0x1
Register Conventions
Bit 2~0
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
Note 3- COAST - Charge Pump Enable/Disable
4
CP_Pol
CPen
8 (Typical Internal Filter Value)
Charge Pump Enabled If...
COAST (Pin 5) = 1
0x0:1~0
16
32
0 0
x 1
1 0
Always Enabled (Default)
COAST (Pin 5) = 0
64
Reserved
The COAST input can be used to disable the charge
pump during the vertical blanking interval if the input
HSYNC input changes frequency during this time. The
charge pump is asynchronously disabled and
Increasing the charge pump current makes the loop
respond faster, raising the loop bandwidth. The typical
value when using the internal loop filter is 011.
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid. This pin can be
connected to VSYNC or pulled to either rail if unused.
Note 7 - VCO Divider
VCO Divider
0x1:bit 5,4
0 0
0 1
1 0
1 1
2 (default)
Note 4 - LOCK/REF Function
4
IN_SEL
EnPLS
0x0
-
8
0x7bit 7 LOCK/REF Output
16
bit 7~6
0 0
-
-
0
This is used to keep the VCO running at faster speeds
even when the output frequency is low.
VCO speed = Output Frequency * VCO Scaler
0 1
PLL locked = 1 else 0
RESERVED
1 0
-
1 1
0
Post Schmitt trigger
HSYNC (pin 7) XOR
REF_Pol (0x0:2)
Note 8 - DPA Offset Ranges
Clock Range (MHz)
0x4
0x5
bit 1-0
# of DPA Delay
Elements (d)
bit 5-0
Max. (h)
1 1
1
F
/ (OSC _DIV +2)
OSC
Min Max
0 0
0 1
1 0
1 1
16
32
0F
1F
48
24
160
80
Note 5- CLK Output Divider
Reserved
3F
CLK Divider
0x6 bit 7,6
64
12
40
0 0
0 1
1 0
1 1
1 (default)
2
4
8
Using the DPA above 160 MHz is not recommended.
Set DPA_OS = 0 for speeds in excess of 160 MHz to
bypass the DPA.
SSTL_3 CLK Freq. = Output Freq. / CLK Divider
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
The DPA Resolution Select register (0x5:0~1) is
double-buffered. Working registers are loaded only
after a DPA software reset (0x8=xA)
While the internal loop filter works well for most
applications, ICS still recommends the implementation
of an external filter network on all designs.
For more details, See Figure 11.2
Implementing the external loop filter gives the system
engineer flexibility to add external filter functionality if
without having to alter the PCB.
Section 6 OSC Divider and REF
The ICS1523 accepts a single-ended clock on pin 12,
the OSC input. The period of this input signal becomes
the high time of the REF signal and the low time is
controlled by 0x7:0~6.
7.1 External Filter Recommendations
The resulting REF signal can be used as an input to the
PLL’s phase detector to allow the ICS1523 to
synthesize frequencies without an HSYNC input when
0x7:7=1.
ICS recommends the following as a general purpose
external loop filter:
CS = 3300 pF
RS = 6.8 kΩ
CP = 33 pF
This REF signal may also be output on the LOCK/REF
pin (14) when 0x0:6-7 = 11
Table 6-1 REF Functionality
Special considerations must be made in selecting loop
capacitors CS and CP. These recommendations can be
found at:
Parameter
Value
REF Frequency
(Input Osc Frequency) *
[(0x7: 6~0) + 2]
http://www.icst.com/appnotes/loopfilter.pdf
REF High Time
REF Low Time
Input OSC Period
Section 8 PLL Parameter Settings
[(0x7: 6~0) + 1] * Input
OSC Period
Settings for all standard VESA video modes are
provided by ICS as a starting point for the systems
engineer. These files are in human readable text files
(*.ics files) and come bundled within the ICS1523
Register Editor Tool.
Minimum OSC Divider
Maximum OSC Divider
3 (0x7:6~0 = 000001)
129 (0x7:6~0 = 111111)
RESERVED OSC Divider 0 (0x7:6~0 = 000000)
This tool directly drives the ICS1523EB Evaluation
Board and can be downloaded from:
Section 7 Loop Filter
http://www.icst.com/icscs/PartSummary.aspx?id=d28d
be26-195c-46a4-8ac7-fc756463febf&name=ICS1523&
mode=short
The ICS1523 contains an internal loop filter, but also
supports the use of an external loop filter configured as
in Figure 7-1. Selection between these two filters is
controlled by 0x4:7. The external filter is selected when
4:7=0; internal filter is selected with a 1.
Figure 7-1 External Loop Filter
Pin 8
CS
CP
RS
Pin 9
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
For the high logic level, the output transistor is off, so
the logic level is set by the ratio of R1 and R2 and the
voltage VAA. Generally, VAA will be equal to VDD.
Section 9 Output Termination
9.1 PECL Description
For logic low, the pull-down transistor turns on, pulling
the output voltage down to the low logic level.
Decoupling capacitor C1 should be a 0.01µF
high-frequency ceramic unit, and all power pins on the
ICS1523 should also be decoupled with similar
capacitors.
The ICS1523 PECL outputs consist of open-drain,
current-source, pull-down transistors. An external
resistor network permits complete flexibility of logic
levels and source impedance. This section describes
the design procedure to select the resistor values and
the pull-down current for these devices.
9.3 PECL Design Assumptions
9.2 PECL Output Structure
All referenced voltages in this application note are
positive and referenced to the GND pin of the chip.
However, negative logic levels can be generated by
level shifting, i.e. connecting the VDD pin of the device
to system ground and the GND pin to a negative
voltage.
The output stage and external circuitry are shown
below in Figure 9-1. The output devices are open-drain
pull-downs. The two output transistors switch
differentially, steering the current source
(programmable via RSET) from one output to the other.
All logic levels must be between GND and the lesser of
VAA and VDD. Then, nodal equations are written, with
resistances transformed into conductances.
Figure 9-1 PECL Termination Network
V
DD
RSET
V
CC
ICS1523
IREF (Pin 24)
CLK+ (Pin 21)
C
1
0.1µF
0.1µF
R
R
A
B
I
I
PECL
*
*
or CLK/2+ (Pin 23)
Destination
Device
R
A
PECL
CLK– (Pin 20)
R
B
or CLK/2– (Pin 22)
* Coaxial cable, microstrip, or stripline, with Z = R . Typically,
0
L
coaxial cable, microstrip, or stripline is not required if the distance
from the ICS1523 to the PECL load is short (that is, < 3 cm).
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Figure 10-1 SSTL_3 Outputs
9.4 PECL Example
VDD
Determine V and V for target device, as follows
(see also Figure 9-1):
OL
OH
330Ω
150Ω
Single
LVTTL
Load
SSTL_3 Output
ICS1523
1. Choose ZO
2. RA = (VCC * ZO) / VOH
3. RB = (ZO * RA) / (RA - ZO)
4. RSET=(16.661E-3 -(VCC/RA)+(VOL/RA)+(VOL/RB))
2.4E-6
The ICS1523s SSTL_3 output source impedance is
typically less than 60Ω. Termination impedance of
100Ω reduces output swing by less than 30% which is
more than enough to drive a single LVTTL load.
For more detailed equations regarding PECL
termination, please see the following application note
on the ICS web site at:
10.3 Using SSTL_3 Outputs with CMOS
or LVTTL Inputs
http://www.icst.com/appnotes/man09.pdf
Per EIA/JESD8-8, SSTL_3 outputs are intended to
provide a moderate voltage swing across a
low-impedance load at the end of a transmission line.
However, if an SSTL_3 output is connected directly to a
destination LVTTL-compatible input, it can provide
nearly rail-to-rail swings (from 0 to 3.3 V). The
equivalent source impedance of these outputs is
typically 30 to 50Ω. The FUNC and LOCK/REF signals
are both at the input HSYNC frequency rate. As a
result, if these signals are directly connected to a
destination LVTTL-compatible input, this direct
connection does not typically result in signal
degradation.
Section 10 SSTL_3 Outputs
The ICS1523 incorporates SSTL_3 outputs on FUNC
(pin 15), CLK/2 (pin 16), and CLK (pin 17).
10.1 Unterminated Outputs
In the ICS1523, unterminated SSTL_3 output pins
display exponential transitions similar to those of
rectangular pulses presented to RC loads. The 10 to
90% rise time is typically 1.6 ns, and the corresponding
fall time is typically 700 ps. This asymmetry and
external capacitive loading contribute to duty cycle
distortion at higher output frequencies. Typically, no
termination is required for either the LOCK/REF,
FUNC, and CLK/2 outputs. The CLK output works up to
approximately 135 MHz, and normally requires no
termination.
The CLK and CLK/2 signals operate at much higher
frequency rates. and if they are directly connected to a
destination LVTTL-compatible input, they can exhibit
distortion. For example, their waveforms can appear as
though some shunt capacitance is present across the
output load. This equivalent RC effect limits the highest
frequency at which the SSTL_3 outputs can be used.
For these applications, the PECL outputs must be used
instead.
10.2 Terminated Outputs
SSTL_3 outputs are intended to be terminated into low
impedances to reduce the effect of external circuit
capacitance. Use of transmission line techniques
enables use of longer traces between source and
driver without increasing ringing due to reflections.
Where external capacitance is minimal and substantial
ICS recommends traces less than 3 cm for all
high-frequency signals.
voltage swing is required to meet LVTTL V and V
IH
OL
requirements, the intrinsic rise and fall times of
ICS1523 SSTL_3 outputs are only slightly improved by
termination in a low impedance.
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Section 11 Programming
2
11.1 Industry-Standard I C Serial Bus: Data Format
2
Figure 11-1 ICS1523 Data Format for I C 2-Wire Serial Bus
Write Procedure for Single Register
MSB
LSB
S
0
1
0
0
1
1
X
0
A
A
A
A Stop
Device address
Register Index
Data
Read Procedure for Single Register
MSB LSB
MSB
LSB
S
0
1
0
0
1
1
X
0
A
S
0
1
0
0
1
1
X
1
A
A
Stop
Device address
Register Index
Device address
Repeat START
Data
NO Acknow ledge
Write Procedure for Multiple Registers (Note 1)
MSB LSB
S
0
1
0
0
1
1
X
0
A
A
A
A
A
A
A
Stop
Stop
Device address
Register Index
Data
Data
Data
Read Procedure for Multiple Registers (Note 1)
MSB LSB
MSB
LSB
S
0
1
0
0
1
1
X
0
A
S
0
1
0
0
1
1
X
1
A
A
Device address
Register Index
Device address
Repeat START
Data
NO Acknow ledge
Legend
All values are sent with the most-significant bit (MSB) first and least-significant bit (LSB) last.
S
= Start (SDA goes low when SCL was high, then SCL goes low too)
A = ACK = Acknowledge = 0
A = ACK = No Acknowledge = 1
X
= Bit value that equals logic state of SBADR pin.
= (Dashed Line) Multiple transactions
Bus Master drives signal to ICS1523
ICS1523 (Slave Device) drives signal to Bus Master
Note:
2
• 1 - Lower nibble of the I C register automatically increments after each successive data byte is written to
or read from the ICS1523.
2
• 2 - Upper nibble of the I C register does not automatically increment, and the software must explicitly
re-address the ICS1523. The software:
– Must NOT just index 0 and then do all the I/O as one-byte transactions.
– Must break the transactions into at least two separate bus transactions:
(1) 00 to 08 (2) 10 to 12
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11.2 Programming Flow for Modifying PLL and DPA Settings
BEGIN
Determine Horizontal Total
HTOTAL
Program Input Control Register Reg0x0
Typically = 41h
(Coast disabled, Positive edge of HSYNC, Internal Feedback,
FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin
Program Loop Control Register Reg0x1
VCO Divider 0x1:5~4 = (Maximum value where
Required Output Frequency * VCOD < 500 MHz)
Typical Charge Pump Current 0x1:2~0= 011b
Program Feedback Divider Reg0x2, Reg0x3
Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8
Program Internal Filter Reg0x4
Select Internal Filter 0x4:7 = 1
Program DPA Reg0x5
DPA Resolution 0x5 = (Value From Note 8 Table)
DPA Offset, 0x4:5~0 = 0
Program Output Control Reg0x6
Enable the desired outputs
Program OSC Divider Reg0x7
Select Desired Input Reg0x7:7
Select OSC divider value (if needed)
Decrement Charge
Full S/W Reset
Pump Current
Reg0xA = 5Ah
Reg0x1:2~0
PLL LOCKED?
LOCK Pin or
No
Read 0x12:1
Yes
Increment DPA
Correct Phase
Relationship?
No
Offset
Reg0x4
Yes
END
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Video Clock Synthesizer with I C Programmable Delay
Section 12 Timing Diagrams
Figure 12-1 DPA Operation
HSYNC
Fixed delay − See Figure 12-2 and Figure 12-3
One full speed clock period
DPA Offset when
DPA_OS [5-0] = 0
1 unit of DPA delay
DPA Offset when
DPA_OS [5-0] = 1
2 units of DPA delay
DPA Offset when
DPA_OS [5-0] = 2
1 unit of DPA delay
.
.
.
Maximum units of DPA delay
DPA Offset when
DPA_OS [5-0] = Max
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
(# of DPA Elements Available)[0x5:1-0]
Table 12-1 DPA Offset Ranges
0x4:5-0
Maximum
DPA Clock Range in MHz
Register 5
Selected #
of DPA
Elements
0F
Total # of DPA
Min
Max
1~0
Elements
00
16
48
24
12
160
80
1F
3F
01
11
32
64
40
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
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12.1 Timing for 0x0:2=0
Figure 12-2 0x0:2=0 Timing Diagram
Table 12-2 0x0:2=0 Timing Values
Symbol Parameter
Minimum Typical Maximum Units
T2
T3
T4
HSYNC High to FUNC High
(DPA Offset = 0)
T8 + T3
ns
ns
ns
HSYNC High to PECL CLK+ High
(DPA Offset = 0)
-
7
-
PECL Clock Low to SSTL_3 Clock Low
Delay
0
0.2
0.6
T5
T6
T7
T8
PECL Clock Low to FUNC High Delay
PECL Clock Low to PECL/2 High Clock
PECL Clock Low to SSTL_3 CLK/2 Delay
PECL Clock High Time
0.6
0.6
0.4
-
1.0
1.0
0.9
0.5
1.6
1.6
1.2
-
ns
ns
ns
UI
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Video Clock Synthesizer with I C Programmable Delay
12.2 Timing for 0x0:2=1
Figure 12-3 0x0:2=1 Timing Diagram
Table 12-3 0x0:2=1 Timing Values
Symbol Parameter
Minimum Typical Maximum Units
T2
T3
HSYNC Low to FUNC High Delay
T8 + T3
10
ns
ns
HSYNC Low to PECL CLK+ High Delay
(DPA Offset = 0)
-
-
T4
T5
T6
T7
T8
PECL Clock to SSTL_3 Clock Delay
PECL Clock to FUNC Delay
PECL Clock to PECL/2 Clock
PECL Clock to SSTL_3 CLK/2 Delay
PECL Clock High Time
0
0.2
1.0
1.0
0.9
0.5
0.6
1.6
1.6
1.2
-
ns
ns
ns
ns
UI
0.6
0.6
0.4
-
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Video Clock Synthesizer with I C Programmable Delay
12.3 HSYNC to REF Timing
Figure 12-4 HSYNC to REF Timing Diagram
HSYNC
Reg0:2 = 1
t0
t1
REF
HSYNC
Reg0:2 = 0
t0
t1
REF
Table 12-4 HSYNC to REF Timing Diagram
Symbol Parameter
Minimum Typical Maximum
Units
ns
T
T
HSYNC Low to REF Delay
HSYNC High to REF Delay
6
7.5
4.3
8.5
6
0
1
3.5
ns
12.4 CLK/2 Timing for Odd and Even Feedback Divider
Figure 12-5 CLK/2: Even versus Odd
FUNC
Even - Reg2:0=0
CLK/2
Odd - Reg2:0=1
CLK/2
For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2-
is the compliment of the CLK/2+ signal.
Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the
fall of FUNC, regardless of 0x2
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Video Clock Synthesizer with I C Programmable Delay
Section 13 AC/DC Operating Conditions
13.1 Absolute Maximum Ratings
Table 13-1 lists absolute maximum ratings for the ICS1523. Stresses above these ratings can cause permanent
damage to the device. These ratings, which are standard values for ICS commercially rated parts, are stress
ratings only. Functional operation of the ICS1523 at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Table 13-1 ICS1523 Absolute Maximum Ratings
Item
Rating
VDD, VDDA, VDDQ (measured to VSS)
Digital Inputs
Analog Outputs
4.3 V
VSS –0.3 V to 5.5 V
VSSA –0.3 V to VDDA +0.3 V
VSSQ –0.3 V to VDDQ +0.3 V
–65°C to +150°C
125°C
Digital Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Susceptibility*
260°C
> 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
Note: Measured with respect to VSS. During normal operations, the VDD supply voltage for the ICS1523
must remain within the recommended operating conditions.
Table 13-2 Environmental Conditions
Parameter
Min.
0
Typ.
–
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage
+3.0
+3.3
+3.6
V
Table 13-3 DC Characteristics
Parameter
Symbol
IDDD
Conditions
Min.
Max.
UNITS
mA
Digital Supply Current
Output Driver Supply Current
VDDD=3.6V
-
-
25
6
IDDQ
VDDD=3.6V
mA
No drivers enabled
Analog Supply Current
IDDA
VDDA=3.6V
-
5
mA
Table 13-4 AC Characteristics
Parameter
Symbol
Min.
Max.
Units
Notes
AC Inputs
HSYNC Input Frequency
OSC Input Frequency
PDEN Input Frequency
Internal VCO Frequency
Typical Lock Time
f
15.734
0.05
30
10,000
100
kHz
MHz
Hz
0x7:7=1
0x7:7=0
HSYNC
f
OSC
f
120
PDEN
f
100
500
MHz
ms
VCO
t
20
LOCK
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Video Clock Synthesizer with I C Programmable Delay
Parameter
Symbol
Min.
Max.
Units
Notes
Analog Input (HSYNC)
Input High Voltage
V
1.7
VSS - 0.3
2
5.5
1.1
V
V
IH
Input Low Voltage
V
IL
Digital Inputs (SDA, SCL, EXTFB, OSC, I CADDR)
Input High Voltage
Input Low Voltage
Input Hysteresis
POR Threshold
V
2
VSS - 0.3
0.2
5.5
0.8
0.6
1.8
V
V
V
V
IH
V
IL
-
-
VSS
Voltage that resets
register values
SDA Digital Output
SDA Output Low Voltage
SDA Output High Voltage
V
0.4
6.0
V
V
IOUT = 3ma
OL
V
Determined by
external Rset
resistor
OH
PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)
Output High Voltage
V
-
-
VDD
250
-
V
MHz
V
IOUT=0
OH
Maximum Output Frequency
Output Low Voltage *
F MAX
VDDD = 3.3 V
P
V
1.0
IOUT =
OL
Programmed Value
1
Duty Cycle
P
T
45
-
55
1.0
1.2
%
ns
ns
2
2
2
DC
Transition Time - Rise
Transition Time - Fall
PR
T
-
PF
SSTL_3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
Output Resistance
Maximum Output Frequency
Duty Cycle
R
-
-
80
150
55
Ω
MHz
%
1 V < V < 2 V
O
O
F MAX
VDDD = 3.3 V
s
S
T
45
-
3
3
DC
CR
Clock and FUNC
1.6
ns
Transition Time - Rise
Clock and FUNC
Transition Time - Fall
T
T
-
-
-
1.0
3.0
2.0
ns
ns
ns
3
3
3
CF
LR
LOCK/REF Transition Time -
Rise
LOCK/REF Transition Time - Fall
T
LF
Note 1- V must not fall below the level given so that the correct value for IOUT can be maintained.
OL
o
Note 2- Measured at 135MHz, 3.6 VDC, 0 C, 20 pF, with 75 Ω Termination
o
Note 3- Measured at 135MHz, 3.6 VDC, 0 C, 20 pF, Unterminated
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Table 13-5 Thermal Characteristics
Parameter
Symbol Conditions
Min.
Typ.
67
Max.
Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to
Ambient
θJA
θJA
θJA
θJC
Still Air
1 m/s air flow
3 m/s air flow
56
51
Thermal Resistance Junction to
Case
25
MDS 1523 Y
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Video Clock Synthesizer with I C Programmable Delay
Section 14 Package Dimensions
Figure 14-1 Physical Dimensions for
ICS1523
L ± .008
0.029
Typ.
0.018
5 Deg. Typ. ± 5
5 Deg. Typ.
0.047R
0.296 ± 0.005
0.328 ± 0.010
0.406 ± 0.010
0.015 x 45 Deg.
Pin 1
5 Deg Typ.
0.020
0.010
0.101 ± 0.010
0.008 ± 0.006
0.041 ± 0.003
0.092 ± 0.005
0.050
Pitch Typ.
24-pin SOIC (300 Mil Wide Body)
Section 15 Ordering Information
Part / Order Number
ICS1523M
Marking
ICS1523M
Package
24-pin SOIC
24-pin SOIC
24-pin SOIC
24-pin SOIC
Shipping Package
Tubes
Temperature
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
ICS1523MT
ICS1523M
Tape and Reel
Tubes
ICS1523MLF
ICS1523MLFT
ICS1523MLF
ICS1523MLF
Tape and Reel
Note: “LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both
accuracy and reliability, Integrated Circuit Systems, Incorporated
(ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from
its use. No other circuits, patents, or licenses are implied. This
product is intended for use in normal commercial applications. Any
other applications such as those requiring extended temperature
range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications
without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments
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