ICS1567-742 [ICSI]
Differential Output Video Dot Clock Generator; 差分输出视频点时钟发生器
| 型号： | ICS1567-742 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Differential Output Video Dot Clock Generator |
| 文件： | 总11页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS1567
Integrated
Circuit
Systems, Inc.
Differential Output Video Dot Clock Generator
Features
General Description
•
High frequency operation for extended video modes - up
to 180 MHz
Compatible with Brooktree high performance RAMDACs
a) Differential output clocks with ECL logic levels
b) Programmable divider modulus for load clock
The ICS1567 is a very high performance monolithic PLL
frequency synthesizer. Utilizing ICS’s advanced CMOS
mixed-mode technology, the ICS1567 provides a low cost
solution for high-end video clock generation, and for telecom
system clock generation.
•
c) Circuitry included for automatic reset of Brooktree
RAMDAC pipeline delay
Low cost - eliminates need for multiple ECL crystal clock
oscillators in video display systems
Strobed/Transparent frequency select options
32-user selected mask-programmable frequencies
Fast acquisition of selected frequencies, strobed or non-
strobed
The ICS1567 has differential video clock outputs (CLK and
CLK) that are compatible with industry standard video DACs
& RAMDACs. An additional clock output, LD, is provided,
whose frequency is divided down from the main clock by a
programmable divider.
•
•
•
•
Operating frequencies are selectable from a pre-programmed
(customer-defined) table. An on-chip crystal oscillatorfor gen-
erating the reference frequency is provided on the ICS1567.
•
•
Advanced PLL for low phase-jitter
Dynamic control of VCO sensitivity providing optimized
loop gain over entire frequency range
Programming of the ICS1567 is accomplished via frequency
select pins on the package. The ICS1567 has five lines plus a
STROBE pin which permits selection of 32 frequencies. Reset
ofthepipelinedelay onBrooktree RAMDACs is automatically
performed on a rising edge of the STROBE line.
•
Small footprint - 16-pin wide body (300 mil) SOIC
Applications
Pin Configuration
•
•
•
•
•
Workstations
High-resolution PC and MAC displays
8514A - TMS340X0 systems
EGA - VGA - Super VGA video
Telecom reference clock generation - suitable for Sonet,
ATM and other data rates up to 155.52Mb.
FS0
XTAL1
XTAL2
STROBE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS1
FS2
FS3
VDD
VDDO
VDDO
CLK
VSS
LD
FS4
CLK
16-Pin SOIC
ICS1567RevB090894
ICS1567
Block Diagram
LOOP
FILTER
X1
X2
CRYSTAL
OSCILL.
/ R
CHARGE
PHASE
COMP.
VCO
PRESCALER
/ A
/ M
CLK+
CLK−
DIFF.
OUTPUT
FS0
FS1
/ 2
/ 4
ROM
MUX
FS2
/ N1
FS3
MUX
FS4
LOAD
DRIVER
STROBE
Figure 1
System Schematic
1
2
3
4
5
6
7
8
16
15
14
13
FS0
FS1
FS2
FS3
XTAL
STROBE
VDD
ICS1567
12
11
10
9
10
VDDO
VSS
LOAD
FS4
CLK
CLK
C3
.1
C2
.1
C1+
22
Figure 2
2
ICS1567
Typical Output Configuration
Notes:
CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply
VLO = (V supply • 160)/(110 +160) in the example shown above.
The above values are a good starting point for RAMDAC or clock generator interface.
Figure 3
Pin Description
PIN NUMBER
PIN SYMBOL
TYPE
IN
DESCRIPTION
1
2
3
4
Frequency Select LSB.
• FS0
XTAL1
XTAL2
IN
Crystal Interface/External Oscillator Input.
Crystal Interface.
Control For Frequency Select Latch, also performs automatic
RAMDAC reset.
OUT
IN
• STROBE
5
6
7
8
--
--
VSS
VSS
LD
Device Ground (Both pins must be connected.)
Device Ground (Both pins must be connected.)
Load Output. This output is at CLK frequency divided by N1.
Frequency Select MSB.
OUT
IN
• FS4
CLK
CLK
VDDO
9
OUT
OUT
--
Clock Output Inverted.
Clock Output Non-Inverted.
Output Stage Power (Both pins must be connected).
10
11
12
13
14
15
16
--
--
VDDO
VDD
Output Stage Power (Both pins must be connected).
PLL System Power.
Frequency Select.
IN
IN
IN
• FS3
• FS2
• FS1
Frequency Select.
Frequency Select.
• = inputs with internal pull-up resistor
3
ICS1567
Circuit Description
Overview
Frequency Synthesizer Description
Refer to Figure 1 for a block diagram of the ICS1567. The
reference frequency is generated by an on-chip crystal oscilla-
tor, or the reference frequency may be applied to the ICS1567
from an external frequency source.
The ICS1567 is designed to provide the graphics system clock
signals required by industry standard RAMDACs. One of 32
pre-programmed (user-definable) frequencies may be selected
under digital control. Fully programmable feedback and ref-
erence divider capability allow virtually any frequency to be
generated, not just simple multiples of the reference frequency.
The ICS1567 uses the latest generation of frequency synthesis
techniques developed by ICS and is completely suitable for the
most demanding video applications.
The ICS1567 generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
toberatiometricallyrelatedtothe referencefrequencyprovided
to the PLL. The phase-frequency detector shown in the block
diagram drives the VCO to a frequency that will cause the two
inputs to the phase-frequency detector to be matched in fre-
quency and phase. This occurs when:
Digital Inputs
The FS0-FS4 pins and the STROBE pin are used to select the
desired operating frequency from the 32 pre-programmed fre-
quencies in the ROM table of theICS1567. The STROBE pin
also controls activation of the pipeline delay RESET function
included in the ICS1567 (see PIPELINE DELAY RESET
section for details). The FS0-FS4 and STROBE pins are each
equipped with a pull-up and will beata logic HIGH levelwhen
not connected.
F(XTAL1) • Feedback Divider
F(vco) =
Reference Divider
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly-programmed dividers). The
divider programming is one of the functions performed by the
ROM look-up table in the ICS1567. The VCO gain is also
ROM programmable which permits the ICS1567 to be opti-
mized for best performance at each frequency in the table.
Transparent Mode - When the STROBE pin is held HIGH,
the FS0 through FS4 inputs are transparent; that is, they di-
rectly access the ROM table. The synthesizer will output the
frequency programmed into the location addressed by the
FS0-FS4 pins.
The feedback divider makes use of a dual-modulus prescaler
technique that allows construction of a programmable counter
to operate at high speeds while still allowing the feedback
dividerto be programmed insteps of 1. This is animprovement
over conventional fixed prescaler architectures that typically
impose a factor-of-four penalty (or larger) in this respect.
Latched Mode - When the STROBE pin is held LOW, the
FS0-FS4 pins are ignored. The synthesizer will output the
frequency corresponding to the state of the FS0-FS4 pins when
the STROBE pin was last HIGH. Intheeventthat theICS1567
is powered-up with the STROBE pin held LOW, the synthe-
sizer willoutputthefrequencyprogrammedinto address 0(i.e.,
the one selected with FS0 through FS4 at a logic LOW level).
A post-divider may be inserted between the VCO and the CLK
and CLK outputs of the ICS1567. This is useful in generation
of lower frequencies, as the VCO has been optimized for
high-frequency operation. Different post-divider settings may
be used for each frequency in the table.
4
ICS1567
Load Clock Divider
Application Information
The ICS1567 has an additional programmable divider that is
used to generate the LOAD frequency. The modulus of this
divider may be set to 3, 4, 5, 6, 8, or 10. The design of this
divider permits the output duty factor to be 50/50, even when
an odd modulus is selected.
Power Supplies
The ICS1567has two VSS pins to reduce theeffects of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plane of the video board as close to the package
as is possible.
The selection of the modulus is done by the ROM look-up
table. A different modulus may, therefore, be selected for each
frequency address.
The ICS1567 has two VDDO pins which are the supply of +5
volt powertoalloutputstages. Again, bothVDDOpins connect
to the same point on the die. BOTH of these pins should be
connected to the power plane (or bus) using standard high-fre-
quency decoupling practice. This decoupling consists of a low
series inductance bypass capacitor, using the shortest leads
possible, mounted close to the ICS1567.
Pipeline Delay Reset Function
The ICS1567 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This se-
quence is automatically generated by the ICS1567 upon any
rising edge of the STROBE line.
The VDD pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to “track” through power supply fluctuations
without visible effects.
When the frequency select inputs (FS0-FS4) are used in a
transparent mode, simply lower and raise the STROBE line to
activate the function. When the frequency select inputs are
latched, simply load the same frequency into the ICS1567
twice.
When changing frequencies, it is advisable to allow 500uSec
after the new frequency is selected to activate the reset func-
tion. The output frequency of the synthesizer should be stable
enough at that point for the RAMDAC to correctly execute its
reset sequence.
Crystal Oscillatorand Crystal Selection
The ICS1567 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierceoscillators operate the crystal in anti-(also
called parallel-) resonant mode. See the AC Characteristics for
the effective capacitive loading to specify when ordering crys-
tals.
See Figure 4 for a diagram of the clock sequencing.
Output Stage Description
The CLK and CLK outputs are each connected to the drains of
P-Channel MOSFET devices. The source of each of these
devices is connected to VDDO. Typical on resistance of each
deviceis 15Ohms. Theseoutputs will drivethe clockandclock
of a RAMDAC device when a resistive network equivalent to
Figure 3 is utilized.
So-called series-resonant crystals may also be used with the
ICS1567. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically 0.005-0.01%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1567 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
The LD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may be
selected for a modulus of 3, 4, 5, 6, 8, or 10. Under control of
the ROM, this output may also be suppressed (logic low level)
at any frequency select address, if desired.
5
ICS1567
Application Notes (continued)
ICS1567 Interface
The ICS1567 should be located as closeas possible tothevideo
DAC or RAMDAC. Figure 3 illustrates interfacing the
ICS1567 to a RAMDAC. The differential output CLOCK
drivers are current sourcing only and are designed to drive
resistive terminations in a complementary fashion CLK and
CLK connections should follow good ECL interconnection
practice. Terminating resistors should be as close as possible to
the RAMDAC.
Bus Clock Interface
In some applications, it may be desirable to utilize the bus
clock. To do this, connect the clock through a .047uF capacitor
to XTAL1 (2) and keep the lead length of the capacitor to
XTAL1 (2) to a minimum to reduce noise susceptibility. This
input is internally biased at VDD/2. Since TTL compatible
clocks typically exhibit a VOH of 3.5V, capacitively coupling
the inputrestores noiseimmunity.TheICS1567is notsensitive
to the duty cycle of the bus clock; however, the quality of this
signal varies considerably with different motherboard designs.
As the quality of the bus clock is typically outside the control
of the graphics adapter card manufacturer, it is suggested that
this signal be buffered on the graphics adapter board. XTAL2
(3) must be left open in this configuration.
Absolute Maximum Ratings
Ambient Temeperature under bias . . . . . To . . . . . . . . . . . . . 0°C to 70°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . VDD . . . . . . . . . . . -0.5V to +7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . -0.5V to VDD + 0.5V
Output Voltage. . . . . . . . . . . . . . . . . . . . . VOUT . . . . . . . . . . -0.5V to VDD + 0.5V
Clamp Diode Current. . . . . . . . . . . . . . . . VIK & IOK . . . . . . ±30mA
Output Current per Pin. . . . . . . . . . . . . . . IOUT . . . . . . . . . . . ±50mA
Storage Temperature . . . . . . . . . . . . . . . . TS . . . . . . . . . . . . . -85°C to + 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . PD. . . . . . . . . . . . . 500mW
Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
ofanyvoltagehigherthanthemaximumratedvoltages. Forproperoperation,itis recommendedthatVIN andVOUT beconstrained
to > = VSS and < = VDD
.
Standard Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced
to VSS (OV Ground). Positive current flows into the referenced pin.
Operating Temperature range
Power supply voltage
0°C to 70°C
4.75 to 5.25 Volts
6
ICS1567
DC Characteristics
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
MIN
2.0
MAX
VDD + 0.5
0.8
UNITS
V
CONDITIONS
VIL
VSS -0.5
V
IIH
10
uA
VIN = VDD
VIN = VSS
IIL
-200
uA
LOAD OUTPUT
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
V
V
IOH = -4.0 mA
IOL = 6.0 mA
0.4
CLOCK OUTPUTS
1.2
Differential Output Voltage
(CLK-CLK)
VOD
V
See Figure 4
XTAL1 INPUT
VDD + 0.5
Input High Voltage
Input Low Voltage
Operating Current
VXH
VXL
IDD
3.75
VSS -0.5
V
V
1.25
50
8
mA
pF
pF
Outputs Unloaded
FC = 1 MHz
Input Pin Capacitance
Output Pin Capacitance
CIN
COUT
12
FC = 1 MHz
7
ICS1567
AC Characteristics
NOTES
3, 4, 9
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CLK and CLK TIMING
40
THIGH
60
0.5
2
%
%
Duty Cycle
Frequency Error
Rise Time
Tr
Tf
ns
5, 9
5, 9
1
2
ns
Fall Time
FVCO
TLOCK
20
180
MHz
uS
VCO Frequency
PLLAcquire Time
500
LD* TIMING
40
THIGH
FLOAD
Tr
60
60
2
%
MHz
ns
6
Duty Cycle
Load Frequency
Rise Time
7, 8
7, 8
Tf
2
ns
Fall Time
REFERENCE INPUT CLOCK
FXTAL
5
20
MHz
pF
Crystal Frequency
Crystal Oscillator
Loading Capacitance
XTAL1 High Time
XTAL1 Low Time
Rise Time
CPAR
20
TXHI
TXLO
Tr
8
8
ns
ns
ns
ns
2
2
10
10
2, 7
2, 7
Tf
Fall Time
DIGITAL INPUTS
1
2
3
10
10
20
ns
ns
ns
10
10
10
Frequency Select Setup Time
Frequency Select Hold Time
Strobe Pulse Width
PIPELINE DELAY RESET
4
5
6
2*TCLK
ns
ns
ns
10
10
10
Reset Activation
Reset Duration
Restart Delay
4*TCLK
-1*TCLK
+1.5*TCLK
Notes:
1. Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
2. Values for XTAL1 driven by an external clock
3. Duty Cycle for Differential Output (CLK- CLK)
4. Duty cycle measured at VOD/2 for Differential CLK Output
5. Rise and fall time between 20% and 80% of VOD
6. Duty cycle measured at 1.4V for TTL I/O
7. Rise and fall time between 0.8 and 2.0 VDC for TTL I/O
8. Output pin loading = 15 pF
9. See Figure 3.
10. See Figure 4.
8
ICS1567
3
LATCHED INPUTS:
STROBE
1
2
FS0-FS4
PIPELINE DELAY RESET:
3
3
STROBE
DIFF CLK
4
5
6
LD
Tclk
Figure 4
9
ICS1567
ICS Part
Number
ICS1567-
742
ICS1567-
Custom Pattern #1
ICS1567 Pattern Request Form
Video Clock
Frequency
(MHz)
112.000
148.000
OFF
Frequency
(MHz)
Custom patterns are also available, although a significant vol-
ume commitment and/or one-time mask charge will apply.
Contact ICS Sales for details.
Address (HEX)
0
1
2
3
4
135.000
31.500
5
6
105.500
78.000
7
86.000
8
9
108.000
120.000
128.000
93.000
112.000
148.000
135.000
89.210
105.500
112.000
25.000
45.000
64.000
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
75.000
78.000
86.000
103.000
108.000
120.000
127.000
128.000
135.000
112.000
148.000
Custom pattern #1 reference frequency = _____________
Standard pattern shown above uses 16.000 MHz as the input
reference frequency.
10
ICS1567
LEAD COUNT
DIMENSION L
16L
.404
Figure 5: 16-Pin SOIC Package
Ordering Information
ICS1567M-XXX
Example:
ICS XXXX M -XXX
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
11
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