ICS1574BEB [ICSI]
User Programmable Laser Engine Pixel Clock Generator; 用户可编程的激光引擎像素时钟发生器
| 型号： | ICS1574BEB |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | User Programmable Laser Engine Pixel Clock Generator |
| 文件： | 总12页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS1574B
Integrated
Circuit
Systems, Inc.
User Programmable Laser Engine Pixel Clock Generator
Description
Features
The ICS1574B is a very high performance monolithic phase-
locked loop (PLL) frequency synthesizer designed for laser
engine applications. Utilizing ICS’s advanced CMOS mixed-
mode technology, the ICS1574B provides a low cost solution
for high-end pixel clock generation for a variety of laser en-
gine product applications.
Supports high resolution laser graphics. PLL/VCO
•
frequency re-programmable through serial interface
port to 400 MHz; allows less than 1.5ns pixel clock
resolution.
Laser pixel clock output is synchronized with
conditioned beam detect input
•
The pixel clock output (PCLK) frequency is derived from the
main clock by a programmable resettable divider.
Ideal for laser printer, copier and FAX pixel clock
applications
•
Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider and
post-scaler.
On-chip PLL with internal loop filter
•
•
•
On-chip XTAL oscillator frequency reference
Resettable, programmable counter gives glitch-free
clock alignment
Single 5 volt power supply
•
•
•
•
Low power CMOS technology
Compact – 16-pin 0.150" skinny SOIC package
User re-programmable clock frequency supports
zoom and gray scale functions
Block Diagram
Figure 1
1574B 8/31/00
ICS1574B
Pin Configuration
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PCLKEN
XTAL1
XTAL2
DATCLK
VSS
DATA
HOLD
TEST (Connect to VSS))
VDD
VDDO
VSS
Reserved (Do Not Connect)
Reserved (Do Not Connect)
Reserved (Do Not Connect)
PCLK
(Do Not Connect) Reserved
16-Pin Skinny SOIC
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
7
PCLK
Pixel clock output.
1
PCLKEN
XTAL1
XTAL2
DATCLK
DATA
PCLK Enable (Input).
2
Quartz crystal connection 1 / external reference frequency input.
Quartz crystal connection 2.
3
4
Data Clock (Input).
16
Serial Register Data (Input).
15
HOLD
Test
HOLD (Input).
14
8, 9, 10, 11
13
Test. (Must be connected to VSS.)
Reserved. (Do Not Connect.)
Reserved
VDD
PLL system power (+5V. See application diagram).
Output stage power (+5V).
12
VDDO
VSS
5, 6
Device ground. (Both pins must be connected.)
2
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Fig-
ure 1 as the PCLK divider) that is used to generate the PCLK
clock frequency for the pixel clock output. The modulus of
this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is se-
lected. The input frequency to this divider is the output of the
PLL post-scaler described below:
The phase of the PCLK output is aligned with the internal
high frequency PLL clock (FVCO) immediately after the asser-
tion of the PCLKEN input pulse (active low if PCLKEN_POL
bit is 0 or active high if PCLKEN_POL bit is 1).
TK = K •TVCO
When PCLKEN is deasserted, the PCLK output will complete
its current cycle and remain at VDD until the next PCLKEN
pulse. The minimum time PCLKEN must be disabled
Td = LOGIC PROP.DELAY TIME
(typically 9ns with a 10pF load on PCLK)
TVCO = 1/FVCO
(TPULSE) is 1/FPCLK
.
Figure 2b
See Figure 2a for an example of PCLKEN enable (negative
polarity) vs. PCLK timing sequences.
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN
enable is described by Figure 2b and the following table:
K Values
PCLK Divider
K
2
3
4a
4b
5
3.5
3
4.5
3.5
5.5
5
6
8a
8b
10
12
16a
16b
20
Figure 2a
7
6.5
9.5
9
12
Typical values for Tr and Tf with a 10pF load on PCLK are
1ns.
3
ICS1574B
PLL Post-Scaler
back divider makes use of a dual-modulus prescaler tech-
nique that allows the programmable counters to operate at
low speed without sacrificing resolution. This is an improve-
ment over conventional fixed prescaler architectures that
typically impose a factor-of-four (or larger) penalty in this re-
spect.
A programmable post-scaler may be inserted between the
VCO and the PCLK divider of the ICS1574B. This is useful in
generating lower frequencies, as the VCO has been optimized
for high-frequency operation. The post-scaler is not affected
by the PCLKEN input.
Table 1 permits the derivation of “A” & “M” converter pro-
gramming directly from desired modulus.
The post-scaler allows the selection of:
• VCO frequency
Digital Inputs
• VCO frequency divided by 2
• VCO frequency divided by 4
• AUX-EN Test Mode
The programming of the ICS1574B is performed serially
by using the DATCLK, DATA, and HOLD pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD pin is latched at
the same time. When HOLD is low, the shift register may
be loaded without disturbing the operation of the
ICS1574B. When high, the shift register outputs are trans-
ferred to the control registers, and the new programming
information becomes active. Ordinarily, a high level
should be placed on the HOLD pin when the last data bit is
presented. See Figure 3 for the programming sequence.
PLL Synthesizer Description —
Ratiometric Mode
The ICS1574B generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference fre-
quency may be applied to the ICS1574B from an external
frequency source.
The PCLKEN input polarity may be programmed under
register control via Bit 39.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or VCO, to a fre-
quency that will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:
F(XTAL1) • Feedback Divider
F(VCO): =
Reference Divider
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency pro-
vided to the part (assuming correctly programmed dividers).
Figure 3
The VCO gain is programmable, permitting the ICS1574B to
be optimized for best performance at all operating frequen-
cies.
Output Description
The PCLK output is a high-current CMOS type drive
whose frequency is controlled by a programmable divider
that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12,
16 or 20. It may also be suppressed under register control
via Bit 46.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 392 in steps of one. Any even modulus from
392 through 784 can also be achieved by setting the “double”
bit which doubles the feedback divider modulus. The feed-
4
ICS1574B
Programming Notes
• VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Reference Oscillator
and Crystal Selection
The ICS1574B has circuitry on-board to implement a
Pierce oscillator with the addition of only one external
component, a quartz crystal. Pierce oscillators operate the
• Divider Range: For best results in normal situations
keep the reference divider modulus as short as possible
(for a frequency at the output of the reference divider in
the few hundred kHz to several MHz range). If you
need to go to a lower phase comparator reference fre-
quency (usually required for increased frequency
accuracy), that is acceptable, but jitter performance will
suffer somewhat.
crystal
in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to
specify when ordering crystals.
Series-resonant crystals may also be used with the
ICS1574B. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the
can (typically 0.025 – 0.05%).
• VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as
shown here:
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the ICS1574B
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
VCO GAIN
MAX FREQUENCY
100 MHz
4
5
6
7
200 MHz
If an external reference frequency source is to be used with
the ICS1574B, it is important that it be jitter-free. The ris-
ing and falling edges of that signal should be fast and free
of noise for best results.
300 MHz
400 MHz
• Phase Detector Gain: For most applications and divider
ranges, set P[1,0] = 10 and set P[2] = 1. Under some
circumstances, setting the P [2] bit “on” can reduce
jitter. During operation at exact multiples of the crystal
frequency, P[2] bit = 0 may provide the best jitter per-
formance.
The loop phase can be locked to either the rising or falling
edges of the XTAL1 input signals, and is controlled by
Bit 56.
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that
performs the following functions:
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1574B supports
this through a register programmable mode, AUX-EN.
When this mode is set, a register bit directly controls the
logic level of the PCLK pin. This mode is activated when
the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
1) Selects the modulus of the PCLK divider to
be four (4).
2) Sets the multiplexer to pass the reference
frequency to PCLK divider input.
These functions should allow initialization for most appli-
cations that cannot immediately provide for register
programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD sup-
ply reaches 4 volts.
5
ICS1574B
Power Supplies and Decoupling
The ICS1574B has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the PCB as close to
the package as is possible.
should have low series inductance and be mounted close to
the ICS1574B.
The VDD pin is the power supply pin for the PLL synthe-
sizer circuitry and other lower current digital functions.
We recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended appli-
cation circuitry). This will allow the PLL to “track”
through power supply fluctuations without visible effects.
See Figure 4 for typical external circuitry.
The ICS1574B has a VDDO pin which is the supply of +5
volt power to the output driver. This pin should be con-
nected to the power plane (or bus) using standard
high-frequency decoupling practice. That is, capacitors
Figure 4
6
ICS1574B
Register Mapping — ICS1574B
NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
BIT REF.
DESCRIPTION
1 – 4
PCLK[0]..PCLK[3]
Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
PCLK[3] PCLK[2] PCLK[1] PCLK[0]
MODULUS
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4(a)
4(b)
5
0
0
1
6
1
8(a)
8(b)
10
1
1
X
X
X
X
12
16(a)
16(b)
20
(X = Don't Care)
5, 6
7
Reserved
Reserved
SELXTAL
Must be set to 0.
Must be set to 1.
8
Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
9
Reserved
Reserved
Reserved
S[0]..S[1]
Must be set to 0.
10
Must be set to 1.
11, 12
13 – 14
Must be set to 0.
PLL post-scaler / test mode select bits.
S[1]
0
S[0]
0
DESCRIPTION
Post-scaler = 1. F(CLK) = F(PLL). The output of the PCLK
divider drives the PCLK output.
Post-scaler = 2. F(CLK) = F(PLL)/2. The output of the
PCLK divider drives the PCLK output.
0
1
1
1
0
1
Post-scaler = 4. F(CLK) = F(PLL)/4. The output of the
PCLK divider drives the PCLK output.
AUX-EN TEST MODE. The AUX_PCL
PCLK output.
K bit drives the
7
ICS1574B
BIT(S)
15
BIT REF.
Reserved
DESCRIPTION
Must be set to 0.
16
AUX_PCLK
Must be set to 0 except when in the AUX-EN test mode.
When in the AUX-EN test mode, this bit controls the
PCLK output.
17 – 24
25 – 27
Reserved
Must be set to 0.
V[0]..V[2]
Sets the gain of VCO
VCO GAIN
(MHz/Volt)
V[2]
V[1]
V[0]
1
1
1
1
0
0
1
1
0
1
0
1
30
45
60
80
28
Reserved
P[0]..P[1]
Must be set to 1.
29 – 30
Sets the gain of the phase detector according to this table:
P[1]
P[0]
GAIN (µA/radian)
0
0
1
1
0
1
0
1
0.05
0.15
0.5
1.5
31
32
Reserved
Must be set to 0.
P[2]
Phase detector tuning bit. Should normally be set to one.
See text.
33 – 38
M[0]..M[5]
M counter control bits. Modulus = value + 1.
39
PCLKEN_POL
When = 0, PCLK output enabled when PCLKEN input is
low. When = 1, PCLK output enabled when PCLKEN input
is high.
40
DBLFREQ
12 /14).
Doubles modulus of dual-modulus prescaler (from 6/7 to
41 – 44
A[0]..A[3]
Controls A counter. When set to zero, modulus = 7.
Otherwise, modulus = 7 for "value" underflows of the
prescaler, and modulus = 6 thereafter until M counter
underflows.
8
ICS1574B
BIT(S)
45
BIT REF.
Reserved
DESCRIPTION
Must be set to 1.
Must be set to 0.
46
PCLK_EN
Disables the PCLK divider when set to 1 regardless of
PCLKEN input state.
47, 48
Reserved
Must be set to 0.
49 – 55
R[0]..R[6]
Reference divider modulus control bits.
Modulus = value +1.
56
REF_POL
PLL locks to rising edge of XTAL1 input when
REFPOL = 1, falling edge of XTAL1 when REFPOL = 0.
9
ICS1574B
Table 1 — "A" & "M" Divider Programming
Feedback Divider Modulus Table
A[2]..A[0]- 001 010 011 100 101 110 111 000
A[2]..A[0]- 001 010 011 100 101 110 111 000
M[5]..M[0]
M[5]..M[0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
7
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
199 200 201 202 203 204 205 231
205 206 207 208 209 210 211 238
211 212 213 214 215 216 217 245
217 218 219 220 221 222 223 252
223 224 225 226 227 228 229 259
229 230 231 232 233 234 235 266
235 236 237 238 239 240 241 273
241 242 243 244 245 246 247 280
247 248 249 250 251 252 253 287
253 254 255 256 257 258 259 294
259 260 261 262 263 264 265 301
265 266 267 268 269 270 271 308
271 272 273 274 275 276 277 315
277 278 279 280 281 282 283 322
283 284 285 286 287 288 289 329
289 290 291 292 293 294 295 336
295 296 297 298 299 300 301 343
301 302 303 304 305 306 307 350
307 308 309 310 311 312 313 357
313 314 315 316 317 318 319 364
319 320 321 322 323 324 325 371
325 326 327 328 329 330 331 378
331 332 333 334 335 336 337 385
337 338 339 340 341 342 343 392
343 344 345 346 347 348 349 399
349 350 351 352 353 354 355 406
355 356 357 358 359 360 361 413
361 362 363 364 365 366 367 420
367 368 369 370 371 372 373 427
373 374 375 376 377 378 379 434
379 380 381 382 383 384 385 441
385 386 387 388 389 390 391 448
13
14
21
28
35
42
49
56
19 20
25
31 32
37 38
43 44
26
27
33 34
39 40
41
47
45
51 52
57 58
63 64
46
48
49
55
50
56
53 54
55
59
65
60
66
61 63
67 70
61 62
67 68
73 74
69
75
70
76
71 72
77 78
73
79
85
77
84
91
79
85
80
86
81 82
87 88
93 94
83 84
89 90
91 98
97 105
91 92
97 98
95
96
99 100 101 102 103 112
103 104 105 106 107 108 109 119
109 110 111 112 113 114 115 126
115 116 117 118 119 120 121 133
121 122 123 124 125 126 127 140
127 128 129 130 131 132 133 147
133 134 135 136 137 138 139 154
139 140 141 142 143 144 145 161
145 146 147 148 149 150 151 168
151 152 153 154 155 156 157 175
157 158 159 160 161 162 163 182
163 164 165 166 167 168 169 189
169 170 171 172 173 174 175 196
175 176 177 178 179 180 181 203
181 182 183 184 185 186 187 210
187 188 189 190 191 192 193 217
193 194 195 196 197 198 199 224
Notes: To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values. Follow the
row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three combinations of divider settings.
Any are acceptable for use.
The formula for the effective feedback modulus is: N =[(M +1) • 6] +A
except when A=0, then:
Under all circumstances:
N=(M +1) • 7
A ≤ M
10
ICS1574B
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) . . . . . . . . 7.0V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.5V to VDD +0.5V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . VSS – 0.5V to VDDO +0.5V
Ambient Operating Temperature . . . . . . . – 55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . – 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature . . . . . . . . . . . . . . . . 260°C
Recommended Operating Conditions
VDD, VDDO (measured to VSS) . . . . . . . . 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . 0 to +70°C
DC Electrical Characteristics
TTL-Compatible Inputs (DATCLK, DATA, HOLD, PCLKEN)
PARAMETER
Input High Voltage
SYMBOL
CONDITIONS
MIN
2.0
MAX
UNITS
V
IH
V
DD +0.5
0.8
V
V
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
V
IL
V
SS –0.5
—
I
IH
IL
V
V
IH = VDD
IL = 0.0
10
µA
µA
pF
V
I
—
200
8
C
IN
—
Hysterisis (DATCLK input)
V
HYS
VDD = 5V
.20
.60
XTAL1 Input (External Reference Frequency)
PARAMETER SYMBOL
Input High Voltage
CONDITIONS
MIN
3.75
MAX
DD +0.5
1.25
UNITS
V
XH
XL
V
V
V
Input Low Voltage
V
V
SS –0.5
PCLK
PARAMETER
SYMBOL
CONDITIONS
MIN
2.4
MAX
—
UNITS
Output High Voltage (IOH = 4.0mA)
Output Low Voltage (IOL = 8.0mA)
V
V
—
0.4
11
ICS1574B
AC Electrical Characteristics
PARAMETER
VCO Frequency
SYMBOL
MIN
40
TYP
20
MAX
400
20
UNITS
MHz
MHz
pF
F
VCO
Crystal Frequency
F
XTAL
5
Crystal Oscillator Loading Capacitance
XTAL1 High Time (when driven externally)
XTAL1 Low Time (when driven externally)
PLL Acquire Time (to within 1%)
VDD Supply Current
C
PAR
XHI
T
8
8
ns
T
XLO
ns
T
LOCK
500
15
µs
I
DD
t.b.d.
t.b.d.
mA
mA
VDDO Supply Current
I
DDO
20
Digital Inputs
DATA/HOLD ~Setup Time
DATA/HOLD ~Hold Time
10
ns
ns
ns
10
20
DATCLK Pulse Width (Thi or Tlo
)
Digital Output
PCLK output rate
FPCLOCK
130
MHz
16-Pin Skinny SOIC Package
Ordering Information
ICS1574BM / ICS1574BEB
Example:
ICS 1574B M
Package Type
M = SOIC
•
EB = Evaluation Board
Device Type
Prefix
ICS, AV = Standard Device • GSP = Genlock Device
12
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