ICS2694 [ICSI]

Motherboard Clock Generator; 主板上的时钟发生器


型号：	ICS2694
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Motherboard Clock Generator 主板上的时钟发生器时钟发生器
文件：	总8页 (文件大小：258K)
中文：	中文翻译
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ICS2694

Integrated

Circuit

Systems, Inc.

Motherboard Clock Generator

Description

Features

The ICS2694 Motherboard Clock Generator is an integrated

circuit using PLL and VCO technology to generate virtually all

the clock signals required in a PC. The use of the device can be

generalized to satisfy the timing needs of most digital systems

by reprogramming the VCO or reconfiguring the counter stages

which derive the output frequencies from the VCO’s.

•

Low cost - eliminates multiple oscillators and Count

Down Logic

Primary VCO has 16 Mask Programmable frequencies

(normally CPU clock)

Secondary VCO has 1 Mask Programmable frequency

(usually 96 MHz)

The primary VCO is customarily used to generate the CPU

clock and is so labeled on the ICS2694. Pre-programmed

frequency sets are listed on page 6. These choices were made

to match the major microprocessor families. CPUSEL (0-3)

allow the user to select the appropriate frequency for the

application.

•

Pre-programmed versions for typical PC applications

10 Outputs in addition to the primary CPU clock

Capability to reconfigure counter stages to change the

frequencies of the outputs via mask options

•

Advanced PLL design

On-chip PLL filters

Due to the filter in the phase-locked loop, the CPUCLK will

move in a linear fashion from one frequency to a newly-

selected frequency without glitches. If a fixed CPUCLK value

is desired, CPUSEL (0-3) may be hard wired to the desired

address with STROBE tied high. (It has a pull-up.) For board

test and debug, pulling OUTPUTE to Ground will tristate all

the outputs.

Very Flexible Architecture

Applications

Pin Configuration

•

CPU clock and Co-processor clock

Hard Disk and Floppy Disk clock

Keyboard clock

OUT2

OUT1

OUT0

OUT3

OUT4

OUT5

OUT6

OUT7 (CPUCLK/2)

OUT8

AVDD

XTAL2

XTAL1

Serial Port clock

Bus clock

System counting or timing functions

OUT9

CPUCLK

VSS

DVDD

STROBE

CPUSEL0

CPUSEL1

CPUSEL2

CPUSEL3

AVSS

OUTPUTE

CLKIN

24-Pin DIP or SOIC

ICS2694RevA1094

ICS2694

Pin Description

PIN NUMBER

NAME

DESCRIPTION

OUT2

OUT1

OUT0

OUT9

4mA Output.

4mA Output

4mA Output.

CPUCLK

4mA Output driven by Voltage Controlled Oscillator 1 (VC01). VC01 is controlled

by a 16 word ROM.

VSS

DVDD

STROBE

Ground for digital portion of chip.

Plus supply for digital portion of chip.

Input control for transparent latches associated with CPU (0-3) which select one of

16 values for CPUCLK. Holding STROBE high causes thelatches to be transparent.

CPUSEL0

CPUSEL1

CPUSEL2

CPUSEL3

CLKIN

LSB CPUCLK address bit.

CPUCLK address bit.

MSB CPUCLK address bit.

An alternative inputfor the referenceclock. Thecrystal oscillatoroutputand CLKIN

are gated together to generate the reference clock for the VCO’s. If CLKIN is used,

XTAL1 should be held high and XTAL2 left open. If the internal oscillator is used,

hold CLKIN high.

OUTPUTE

AVSS

XTAL1

XTAL2

Pulling this line low tristates all outputs.

Ground for analog portion of chip.

Input of internal crystal oscillator stage.

Output of internal crystal oscillator stage. This pin should have nothing connected

to it but one of the quartz crystal terminals.

AVDD

OUT8

OUT7

OUT6

OUT5

OUT4

OUT3

Positive supply for analog portion of chip.

4mA Output.

4mA Output. (Usually assigned as CPUCLK/2 for co-processor use.)

4mA Output.

ICS2694

Frequency Reference

Power Supply Conditioning

The internal reference oscillator contains all of the passive The ICS2694is amemberofthesecondgenerationofdotclock

components required. An appropriate series-resonant crystal products. By incorporating the loop filter on chip and upgrad-

should be connected between XTAL1 (1) and XTAL2 (2). In ing the VCO, the ease of application has been substantially

IBM-compatible applications, this will typically be a improved over earlierproducts. Ifa stableandnoise-free power

14.31818 MHz crystal, but fundamental mode crystals be- supply is available, noexternalcomponents arerequired. How-

tween 10 MHz and 25 MHz have been tested. Maintain short ever, in some applications it may be judicious to decouple the

lead lengths between the crystal and the ICS2694. In order to power supply as shown in Figures 1 or 2. Figure1 is the normal

optimize the quality of the quartz crystal oscillator, the input configuration for 5 volt only applications. Which of the two

switching threshold of XTAL1 is VDD/2 rather than the con- provides superior performance depends on thenoise content of

ventional 1.4V of TTL. Therefore, XTAL1 may not respond the power supplies. In general, the configuration of Figure 1 is

properly to a legal TTL signal since TTL is not required to satisfactory. Figure 2 is the more conventional if a 12 volt

exceedVDD/2. Therefore, another clock input CLKIN (pin13) analogsupply is available, although the improvedperformance

has been added to the chip which is sized to have an input comes at a cost of an extra component; however, the cost of the

switching point of 1.4V. Inside the chip, these two inputs are discretes used in Figure 1’s are less than the cost of Figure 1’s

ANDED. Therefore, when using the XTAL1 and XTAL2, discrete components.

CLKIN should be held high. (It has a pull-up.) When using

CLKIN, XTAL1 should be held high. (It does not have a Since the ICS2694 outputs a large number of high-frequency

pull-up because a pull-up would interfere with the oscillator clocks, conservative design practices are recommended. Care

bias.)

should be exercised in the board layout of supply and ground

traces, and adequate power supply decoupling capacitors con-

It is anticipated that some applications will use both clock sistent with the application should be used.

inputs, properly gated, for either board test or unique system

functions. By generating all the system clocks from one refer-

ence input, the phase and delay relationships between the

various outputs will remain relatively fixed, thereby eliminat-

ing problems arising from totally unsynchronized clocks inter-

acting in a system.

+50

DVDD

.µ1F

470

AVDD

VSS, AVSS

+120

AVDD

VSS, AVSS

R1 C2

4.7V .µ1F

22µV .µ1F

Figure 1

Figure 2

ICS2694

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . V_DD. . . . . . . . . . . . -0.5V to +7V

Input Voltage. . . . . . . . . . . . . . . . . . V_IN. . . . . . . . . . . . -0.5V to VDD +0.5V

Output Voltage . . . . . . . . . . . . . . . . VOUT. . . . . . . . . . -0.5V to VDD +0.5V

Clamp Diode Current . . . . . . . . . . . V_IK& I_OK. . . . . . . ±30mA

Output Current per Pin . . . . . . . . . . I_OUT. . . . . . . . . . . ±50mA

Operating Temperature . . . . . . . . . . T_O. . . . . . . . . . . . . 0°C to + 150°C

Storage Temperature . . . . . . . . . . . . T_S. . . . . . . . . . . . . -85°C to + 150°C

Power Dissipation. . . . . . . . . . . . . . P_D. . . . . . . . . . . . . 500mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against

damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications

of anyvoltage higherthanthe maximumrated voltages.Forproperoperation, it is recommendedthatV_INandV_OUTbeconstrained

to > = V_SSand < = V_DD

DC Characteristics (0°C to 70°C)

PARAMETER

Operating Voltage Range

Input Low Voltage

SYMBOL

V_DD

V_IL

CONDITIONS

MIN

4.0

VSS

2.0

2.4

MAX

5.5

0.8

V_DD

0.4

UNITS

V_DD= 5V

k ohm

Input High Voltage

V_IH

V_DD= 5V

Input Leakage Current

Output Low Voltage

Output High Voltage

Supply Current

Internal Pull-up Resistors

Input Pin Capacitance

Output Pin Capacitance

I_IH

V_IN= V_cc

I_OL= 4.0 mA

I_OH= 4.0 mA

V_DD= 5V, CPUCLK = 80 MHz

V_DD= 5V, V_in= 0V

F_c= 1 MHz

V_OL

V_OH

I_DD

R_UP

C_in

C_out

F_c= 1 MHz

The following inputs have pull-ups: OUTPUTE, STROBE, CPUSEL (0-3), CLKIN.

ICS2694

AC Timing Characteristics

The following notes apply to all parameters presented in this section:

1. Xtal Frequency = 14.31818 MHz

2. All units are in nanoseconds (ns).

3. Rise and fall time is between 0.8 and 2.0 VDC.

4. Output pin loading = 15pF

5. Duty cycle is measured at 1.4V.

6. Supply Voltage Range = 4.5 to 5.5 volts

7. Temperature Range = 0°C to 70°C

SYMBOL

Tpw

Tsu

Thd

PARAMETER

Strobe Pulse Width

Setup Time Data to Strobe

Hold Time Data to Strobe

MIN

STROBE TIMING

MAX

NOTES

FOUT TIMING

Rise Time

Fall Time

Frequency Error

Maximum Frequency

0.5

135

Duty Cycle 40% min. to 60% max.

at 80 MHz

MHz

Note:

Pattern -004 has rising edges of CPUCLK and CPUCLK/2 matched to ± 2 ns.

Tpw

STROBE

CPUSEL (0-3)

Tsu

Thd

ICS2694

24-Pin DIP Package

Ordering Information

ICS2694N-XXX

Example:

ICS XXXX M -XXX

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

N=DIP (Plastic)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV=Standard Device; GSP=Genlock Device

ICS2694

LEAD COUNT

DIMENSION L

14L

0.354

16L

0.404

18L

0.454

20L

0.504

24L

0.604

28L

0.704

32L

0.804

SOIC Packages

Ordering Information

ICS2694M-XXX

Example:

ICS XXXX M -XXX

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

M=SOIC

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV=Standard Device; GSP=Genlock Device

ICS2694

Another alternative for CPU CLOCK generation is the

ICS2494-244 if the additional functions of the ICS2694 are

not needed in the application.

ICS2694 Standard Patterns

32 MHz

1.846 MHz

24 MHz

6 MHz

CPUCLK

VSS

DVDD

STROBE

CPUSEL0

16 MHz

8 MHz

9.6 MHz

14.318 MHz

CPUCLK/2

1.19 MHz

AVDD

XTAL2

XTAL1

AVSS

OUTPUTE

CLKIN

ICS

Part Number

Address FS3-0

ICS2494-

244

Frequency

(MHz)

(Hex)

CPUSEL1 10

CPUSEL2 11

CPUSEL3 12

66.6

100

110

33.3

CPUSEL0-3

CPUCLK OUTPUT (Pin 5)

(Hex)

(MHz)

33.33

66.67

100

Address MS1-0

(Hex)

Frequency

(MHz)

66.6

Note: Pattern -004 has rising edges of CPUCLK and

CPUCLK/2 matched to ± 2 ns.

ICS2694 [ICSI]

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