ICS487G-25LFT [ICSI]
Quad PLL for DTV; 四PLL数字电视
| 型号： | ICS487G-25LFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Quad PLL for DTV |
| 文件： | 总6页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS487-25
Quad PLL for DTV
Description
Features
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using ICS’ patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
• Packaged in 16-pin TSSOP
• Available in Pb-free packaging
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 27 MHz
• Zero ppm frequency synthesis error
• Duty cycle of 45/55
Because there is zero ppm frequency synthesis error
on the audio clocks, the audio will remain locked to the
video.
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
VDD
3
2
S1:0
PLL1
PLL2
PLL3
ACLK
20M
48M
33.0M
X1/ICLK
X2
27 MHz
clock or
crystal
input
Crystal
Oscillator/
Clock
PLL4
3
24.576M
Buffer
External capacitors
may be required.
PDTS (all outputs and PLLs)
GND
MDS 487-25 A
1
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS487-25
Quad PLL for DTV
Pin Assignment
ACLK Output Selection Table
S1
0
S0
0
ACLK (MHz)
18.432
X1/ICLK
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDD
PDTS
GND
VDD
GND
33.0M
ACLK
0
1
16.9344
12.288
S1
1
0
1
1
18.432
48M
VDD
GND
20M
Note: When S1 and S0 are switched, all other output
clocks will remain stable throughout the transition.
24.576M
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Pin Description
Type
Input
Input
1
2
X1/ICLK
S0
Crystal connection. Connect to 27 MHz crystal or clock input.
Select pin 0. Determines ACLK output frequency per table above.
Internal pull up resistor.
3
S1
Input
Select pin 1. Determines ACLK output frequency per table above.
Internal pull up resistor.
4
5
6
7
8
9
48M
VDD
Output 48 MHz clcok output. Weak internal pull-down when tri-state.
Power Connect to +3.3 V.
GND
Power Connect to ground.
20M
Output 20 MHz clock output. Weak internal pull-down when tri-state.
Output 24.576 MHz clock output. Weak internal pull-down when tri-state.
24.576M
ACLK
Output Audio clock output. Determined by table above. Weak internal
pull-down when tri-state
10
11
12
13
14
33.0M
GND
VDD
Output 33.0 MHz clock output. Weak internal pull-down when tri-state.
Power Connect to ground.
Power Connect to +3.3 V.
GND
Power Connect to ground.
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
PDTS
Input
15
16
VDD
X2
Power Connect to +3.3 V.
Input
Connect to 27 MHz crystal or float for clock input.
MDS 487-25 A
2
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS487-25
Quad PLL for DTV
The value (in pF) of these crystal caps should equal
External Components
(C -6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS487-25 must be isolated from system power supply
noise to perform optimally.
PCB Layout Recommendations
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Series Termination Resistor
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS487-25. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS487-25. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70°C
MDS 487-25 A
3
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS487-25
Quad PLL for DTV
Item
Rating
Storage Temperature
Junction Temperature
Soldering Temperature
-65 to +150°C
125°C
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
°C
Ambient Operating Temperature
0
+70
+3.465
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
3.3
35
Max. Units
Operating Voltage
3.135
3.465
V
mA
µA
V
Supply Current
IDD
No load, PDTS=1
Power Down Current
Input High Voltage
IDDPD No load, PDTS=0
20
V
2
IH
Input Low Voltage
V
0.8
0.4
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance, inputs
Nominal Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
V
V
I
I
I
= -4 mA
= -12 mA
= 12 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
OS
I
Clock outputs
70
5
mA
pF
Ω
C
IN
Z
20
OUT
R
S1, S0, PDTS pins
Clock outputs
360
510
kΩ
kΩ
PU
R
PD
MDS 487-25 A
4
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS487-25
Quad PLL for DTV
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
f
27
1.2
1.0
50
MHz
ns
IN
Output Rise Time
t
20% to 80%, Note 1
80% to 20%, Note 1
at VDD/2, Note 1
Note 1
OR
Output Fall Time
t
ns
OF
Output Clock Duty Cycle
Absolute Clock Period Jitter
Frequency Synthesis Error
Output Enable Time
45
55
%
175
0
ps
All outputs
ppm
µs
t
t
PDTS high to output
locked to 1%
250
OE
Output Disable Time
PDTS low to tri-state
20
50
ns
OD
Audio Clock Stabilization Time
Time from a change
in S1 or S0 until
output stable within
1%
µs
Note 1: Measured with a 15 pF load.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram
16
9
487G-25
######
YYWW$$
1
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week
number that the part was assembled.
MDS 487-25 A
5
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS487-25
Quad PLL for DTV
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
Marking
487G-25 (1st line)
YYWW$$ (3rd line)
487G-25LF (1st line)
YYWW$$ (3rd line)
Shipping Packaging
Tubes
Package
Temperature
0 to +70 °C
0 to +70 °C
0 to +70 °C
0 to +70 °C
ICS487G-25
ICS487G-25T
ICS487G-25LF
ICS487G-25LFT
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
Tape and Reel
Tubes
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 487-25 A
6
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
相关型号：
©2020 ICPDF网 联系我们和版权申明